From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from gloria.sntech.de (gloria.sntech.de [185.11.138.130]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 646342F26 for ; Tue, 16 Aug 2022 09:12:10 +0000 (UTC) Received: from ip5b412258.dynamic.kabel-deutschland.de ([91.65.34.88] helo=diego.localnet) by gloria.sntech.de with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1oNscI-0002ox-1h; Tue, 16 Aug 2022 11:12:06 +0200 From: Heiko =?ISO-8859-1?Q?St=FCbner?= To: Samuel Holland , Chen-Yu Tsai , linux-sunxi@lists.linux.dev, Palmer Dabbelt , Paul Walmsley , Albert Ou , linux-riscv@lists.infradead.org, Krzysztof Kozlowski Cc: Rob Herring , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , Jernej =?utf-8?B?xaBrcmFiZWM=?= Subject: Re: [PATCH 06/12] riscv: dts: allwinner: Add the D1 SoC base devicetree Date: Tue, 16 Aug 2022 11:12:05 +0200 Message-ID: <3881930.ZaRXLXkqSa@diego> In-Reply-To: <5593349.DvuYhMxLoT@jernej-laptop> References: <20220815050815.22340-1-samuel@sholland.org> <149eee7b-a9e9-94ad-1ab2-13812b541a8c@linaro.org> <5593349.DvuYhMxLoT@jernej-laptop> Precedence: bulk X-Mailing-List: linux-sunxi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="UTF-8" Am Dienstag, 16. August 2022, 09:49:58 CEST schrieb Jernej =C5=A0krabec: > Dne torek, 16. avgust 2022 ob 09:41:45 CEST je Krzysztof Kozlowski napisa= l(a): > > On 15/08/2022 08:08, Samuel Holland wrote: > > > + > > > + de: display-engine { > > > + compatible =3D "allwinner,sun20i-d1-display-engine"; > > > + allwinner,pipelines =3D <&mixer0>, <&mixer1>; > > > + status =3D "disabled"; > > > + }; > > > + > > > + osc24M: osc24M-clk { > >=20 > > lowercase > >=20 > > > + compatible =3D "fixed-clock"; > > > + clock-frequency =3D <24000000>; > >=20 > > This is a property of the board, not SoC. >=20 > SoC needs 24 MHz oscillator for correct operation, so each and every boar= d has=20 > it. Having it here simplifies board DT files. I guess the oscillator is a separate component on each board, right? And DT obvious is meant to describe the hardware - independently from implementation-specific choices. Starting to discuss which exceptions to allow then might lead to even more exceptions. Also having to look for a board-component in the soc dtsi also is surprising if one gets to the party later on :-) . From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EE9FDC2BB41 for ; Tue, 16 Aug 2022 09:12:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=8yDb1gNCA0vnI+zPZ0oLUsXU6NNaZNN2kwNx/myxv2s=; b=ZAbq1bct8Lvir8 DAcQJH/VrPj6IpbTRTa/QN3HFgyP2F3RXqrBMz1NsfIAQ416kh7na2Q/2z+oPx7aAKUOhKG7QZwdc RqxQyNoasht/agyt1vVMH39TpMqfgwlzrWLgiB2QovIFR8U1QXQO90uGGtrInnCbH5AOxuPYlkGPz FiATa1qFokrzak0qtSKcJf0SygVGDYkuQ5T7POfjSuQt1CbS1nNoGGwNd7up0kT0h3mHt48mKR3vn o+8cU7CtGlVUrsTBRYGMv4oXRiB1SHg6zkuwU2sM1GhV67zpPhemetcb94vOoQ3wJWaK6JWS6Q5l5 EKiTqReaAy8Oi/5pu12Q==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oNscd-00HX67-7f; Tue, 16 Aug 2022 09:12:27 +0000 Received: from gloria.sntech.de ([185.11.138.130]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1oNscN-00HWwO-PP for linux-riscv@lists.infradead.org; Tue, 16 Aug 2022 09:12:13 +0000 Received: from ip5b412258.dynamic.kabel-deutschland.de ([91.65.34.88] helo=diego.localnet) by gloria.sntech.de with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1oNscI-0002ox-1h; Tue, 16 Aug 2022 11:12:06 +0200 From: Heiko =?ISO-8859-1?Q?St=FCbner?= To: Samuel Holland , Chen-Yu Tsai , linux-sunxi@lists.linux.dev, Palmer Dabbelt , Paul Walmsley , Albert Ou , linux-riscv@lists.infradead.org, Krzysztof Kozlowski Cc: Rob Herring , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , Jernej =?utf-8?B?xaBrcmFiZWM=?= Subject: Re: [PATCH 06/12] riscv: dts: allwinner: Add the D1 SoC base devicetree Date: Tue, 16 Aug 2022 11:12:05 +0200 Message-ID: <3881930.ZaRXLXkqSa@diego> In-Reply-To: <5593349.DvuYhMxLoT@jernej-laptop> References: <20220815050815.22340-1-samuel@sholland.org> <149eee7b-a9e9-94ad-1ab2-13812b541a8c@linaro.org> <5593349.DvuYhMxLoT@jernej-laptop> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220816_021211_858563_A2A22AFA X-CRM114-Status: GOOD ( 10.84 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org QW0gRGllbnN0YWcsIDE2LiBBdWd1c3QgMjAyMiwgMDk6NDk6NTggQ0VTVCBzY2hyaWViIEplcm5l aiDFoGtyYWJlYzoKPiBEbmUgdG9yZWssIDE2LiBhdmd1c3QgMjAyMiBvYiAwOTo0MTo0NSBDRVNU IGplIEtyenlzenRvZiBLb3psb3dza2kgbmFwaXNhbChhKToKPiA+IE9uIDE1LzA4LzIwMjIgMDg6 MDgsIFNhbXVlbCBIb2xsYW5kIHdyb3RlOgo+ID4gPiArCj4gPiA+ICsJZGU6IGRpc3BsYXktZW5n aW5lIHsKPiA+ID4gKwkJY29tcGF0aWJsZSA9ICJhbGx3aW5uZXIsc3VuMjBpLWQxLWRpc3BsYXkt ZW5naW5lIjsKPiA+ID4gKwkJYWxsd2lubmVyLHBpcGVsaW5lcyA9IDwmbWl4ZXIwPiwgPCZtaXhl cjE+Owo+ID4gPiArCQlzdGF0dXMgPSAiZGlzYWJsZWQiOwo+ID4gPiArCX07Cj4gPiA+ICsKPiA+ ID4gKwlvc2MyNE06IG9zYzI0TS1jbGsgewo+ID4gCj4gPiBsb3dlcmNhc2UKPiA+IAo+ID4gPiAr CQljb21wYXRpYmxlID0gImZpeGVkLWNsb2NrIjsKPiA+ID4gKwkJY2xvY2stZnJlcXVlbmN5ID0g PDI0MDAwMDAwPjsKPiA+IAo+ID4gVGhpcyBpcyBhIHByb3BlcnR5IG9mIHRoZSBib2FyZCwgbm90 IFNvQy4KPiAKPiBTb0MgbmVlZHMgMjQgTUh6IG9zY2lsbGF0b3IgZm9yIGNvcnJlY3Qgb3BlcmF0 aW9uLCBzbyBlYWNoIGFuZCBldmVyeSBib2FyZCBoYXMgCj4gaXQuIEhhdmluZyBpdCBoZXJlIHNp bXBsaWZpZXMgYm9hcmQgRFQgZmlsZXMuCgpJIGd1ZXNzIHRoZSBvc2NpbGxhdG9yIGlzIGEgc2Vw YXJhdGUgY29tcG9uZW50IG9uIGVhY2ggYm9hcmQsIHJpZ2h0PwpBbmQgRFQgb2J2aW91cyBpcyBt ZWFudCB0byBkZXNjcmliZSB0aGUgaGFyZHdhcmUgLSBpbmRlcGVuZGVudGx5IGZyb20KaW1wbGVt ZW50YXRpb24tc3BlY2lmaWMgY2hvaWNlcy4KClN0YXJ0aW5nIHRvIGRpc2N1c3Mgd2hpY2ggZXhj ZXB0aW9ucyB0byBhbGxvdyB0aGVuIG1pZ2h0IGxlYWQgdG8gZXZlbiBtb3JlCmV4Y2VwdGlvbnMu CgpBbHNvIGhhdmluZyB0byBsb29rIGZvciBhIGJvYXJkLWNvbXBvbmVudCBpbiB0aGUgc29jIGR0 c2kgYWxzbyBpcyBzdXJwcmlzaW5nCmlmIG9uZSBnZXRzIHRvIHRoZSBwYXJ0eSBsYXRlciBvbiA6 LSkgLgoKCgpfX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fXwps aW51eC1yaXNjdiBtYWlsaW5nIGxpc3QKbGludXgtcmlzY3ZAbGlzdHMuaW5mcmFkZWFkLm9yZwpo dHRwOi8vbGlzdHMuaW5mcmFkZWFkLm9yZy9tYWlsbWFuL2xpc3RpbmZvL2xpbnV4LXJpc2N2Cg==