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Thu, 9 Sep 2021 02:48:39 +0000 (GMT) Received: from smtpclient.apple (unknown [9.79.177.172]) by d06av22.portsmouth.uk.ibm.com (Postfix) with ESMTPS; Thu, 9 Sep 2021 02:48:39 +0000 (GMT) Content-Type: text/plain; charset=utf-8 Mime-Version: 1.0 (Mac OS X Mail 14.0 \(3654.120.0.1.13\)) Subject: Re: [PATCH 1/2] powerpc/perf: Expose instruction and data address registers as part of extended regs From: Athira Rajeev In-Reply-To: <87pmtjmysk.fsf@mpe.ellerman.id.au> Date: Thu, 9 Sep 2021 08:18:36 +0530 Content-Transfer-Encoding: quoted-printable Message-Id: <38CCAAE2-A157-4689-B774-43FC48883699@linux.vnet.ibm.com> References: <1624200360-1429-1-git-send-email-atrajeev@linux.vnet.ibm.com> <1624200360-1429-2-git-send-email-atrajeev@linux.vnet.ibm.com> <87pmtjmysk.fsf@mpe.ellerman.id.au> To: Michael Ellerman X-Mailer: Apple Mail (2.3654.120.0.1.13) X-TM-AS-GCONF: 00 X-Proofpoint-GUID: yt3ZJr0kOGaIrwzgQww7WuuqAwI2lvvY X-Proofpoint-ORIG-GUID: yt3ZJr0kOGaIrwzgQww7WuuqAwI2lvvY X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-09-08_10:2021-09-07, 2021-09-08 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 bulkscore=0 phishscore=0 mlxscore=0 malwarescore=0 adultscore=0 priorityscore=1501 mlxlogscore=999 clxscore=1015 suspectscore=0 spamscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2109030001 definitions=main-2109090014 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Madhavan Srinivasan , rnsastry@linux.ibm.com, kajoljain , Arnaldo Carvalho de Melo , Jiri Olsa , linuxppc-dev Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" > On 08-Sep-2021, at 10:47 AM, Michael Ellerman = wrote: >=20 > Athira Rajeev writes: >> Patch adds support to include Sampled Instruction Address Register >> (SIAR) and Sampled Data Address Register (SDAR) SPRs as part of = extended >> registers. Update the definition of PERF_REG_PMU_MASK_300/31 and >> PERF_REG_EXTENDED_MAX to include these SPR's. >>=20 >> Signed-off-by: Athira Rajeev >> --- >> arch/powerpc/include/uapi/asm/perf_regs.h | 12 +++++++----- >> arch/powerpc/perf/perf_regs.c | 4 ++++ >> 2 files changed, 11 insertions(+), 5 deletions(-) >>=20 > ... >> diff --git a/arch/powerpc/perf/perf_regs.c = b/arch/powerpc/perf/perf_regs.c >> index b931eed..51d31b6 100644 >> --- a/arch/powerpc/perf/perf_regs.c >> +++ b/arch/powerpc/perf/perf_regs.c >> @@ -90,7 +90,11 @@ static u64 get_ext_regs_value(int idx) >> return mfspr(SPRN_SIER2); >> case PERF_REG_POWERPC_SIER3: >> return mfspr(SPRN_SIER3); >> + case PERF_REG_POWERPC_SDAR: >> + return mfspr(SPRN_SDAR); >> #endif >> + case PERF_REG_POWERPC_SIAR: >> + return mfspr(SPRN_SIAR); >> default: return 0; >> } >=20 > This file is built for all powerpc configs that have PERF_EVENTS. = Which > includes CPUs that don't have SDAR or SIAR. >=20 > Don't we need checks in perf_reg_value() like we do for SIER? Hi Michael, Thanks for the review. SIER is part of PERF_REG_PMU_MASK and hence check is needed to see if = platform supports SIER. Incase of extended regs, they are part of PERF_REG_EXTENDED_MASK and = this mask is filled with supported registers while registering the PMU ( ie during = init_power9/10_pmu ). So these registers will be added only for supported platforms. The validity of extended mask is also done = in PMU common code=20 ( In kernel/events/core.c with PERF_REG_EXTENDED_MASK check ). So an = unsupported platform requesting for extended registers won=E2=80=99t get it. Thanks Athira >=20 > I guess we already got this wrong when we added the Power10 registers, > SIER2/3 etc. >=20 > cheers