From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 70971C4338F for ; Fri, 20 Aug 2021 12:10:36 +0000 (UTC) Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 2F97C60EB5 for ; Fri, 20 Aug 2021 12:10:36 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 2F97C60EB5 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=xen.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=lists.xenproject.org Received: from list by lists.xenproject.org with outflank-mailman.169501.309630 (Exim 4.92) (envelope-from ) id 1mH3Lp-0003Zv-Qq; Fri, 20 Aug 2021 12:10:21 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 169501.309630; Fri, 20 Aug 2021 12:10:21 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1mH3Lp-0003Zo-MN; Fri, 20 Aug 2021 12:10:21 +0000 Received: by outflank-mailman (input) for mailman id 169501; Fri, 20 Aug 2021 12:10:20 +0000 Received: from mail.xenproject.org ([104.130.215.37]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1mH3Lo-0003Zi-GQ for xen-devel@lists.xenproject.org; Fri, 20 Aug 2021 12:10:20 +0000 Received: from xenbits.xenproject.org ([104.239.192.120]) by mail.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1mH3Ln-0001Tx-Fp; Fri, 20 Aug 2021 12:10:19 +0000 Received: from [54.239.6.185] (helo=a483e7b01a66.ant.amazon.com) by xenbits.xenproject.org with esmtpsa (TLS1.3:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.92) (envelope-from ) id 1mH3Ln-0003dY-8v; Fri, 20 Aug 2021 12:10:19 +0000 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=xen.org; s=20200302mail; h=Content-Transfer-Encoding:Content-Type:In-Reply-To: MIME-Version:Date:Message-ID:From:References:Cc:To:Subject; bh=8Iz2i3yGNdKpmozgAmLtOqeEF1Bv45SaN//uecaTvoY=; b=wNZRpjS/QFtMTNtvtQf0p2T2qp x3UdWf7P9osMo9Irlaz/xeg3R7H3BnvuFnqJA70o5F1gWHN6sOCKCsoC60EodpQamw+jw0cYgeCZ1 /iRRZkd4AuStlT9Ln7XZyPpn/gDiPHHlXvbFCSzxPAhzdrpHwRn+FbSUBCs4JnYGeCgg=; Subject: Re: [PATCH v1 02/14] xen/pci: solve compilation error on ARM with HAS_PCI enabled To: Jan Beulich , Rahul Singh Cc: xen-devel , Bertrand Marquis , Stefano Stabellini , Volodymyr Babchuk References: <7F8FC9A8-5580-4517-BF8C-640BCE778D02@arm.com> <1abfb3cb-993d-3389-c627-6b8cf40457a4@xen.org> <09db7641-5cc8-13dd-f19b-558f7676a5a6@suse.com> From: Julien Grall Message-ID: <3957b8b7-21a6-8e70-d5ce-069eaf1ee991@xen.org> Date: Fri, 20 Aug 2021 13:10:17 +0100 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:78.0) Gecko/20100101 Thunderbird/78.13.0 MIME-Version: 1.0 In-Reply-To: <09db7641-5cc8-13dd-f19b-558f7676a5a6@suse.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-GB Content-Transfer-Encoding: 7bit Hi Jan, On 20/08/2021 12:55, Jan Beulich wrote: > On 20.08.2021 13:37, Julien Grall wrote: >> On 20/08/2021 11:30, Rahul Singh wrote: >>>> Please add a comment explaining why this just returns 0. >>> >>> Here is the comment that I will add in next version. >>> /* >>> * Return 0 as on ARM there is no pci physical irqs that required cleanup. >>> */ >> >> In this context, PIRQ means an interrupts that was routed to the guest >> and could be mapped to an event channel. We have no such concept on Arm >> (see allocate_pirq_struct()). >> >> So I would write "PIRQ event channels are not supported on Arm, so >> nothing to do". > > Does this mean ASSERT_UNREACHABLE() might be appropriate here? Unfortunately no. This is call unconditionally from pci_release_devices(). Cheers, -- Julien Grall