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References: <20190417133941.22962-1-clg@kaod.org>
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Date: Thu, 18 Apr 2019 02:07:42 -0400
From: "Andrew Jeffery" <andrew@aj.id.au>
To: "Alexander Amelkin" <a.amelkin@yadro.com>, openbmc@lists.ozlabs.org
Subject: =?UTF-8?Q?Re:_[PATCH_dev-5.0_1/4]_mtd:_spi-nor:_aspeed:_introduce_a_aspe?=
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On Thu, 18 Apr 2019, at 03:40, Alexander Amelkin wrote:
> 17.04.2019 16:39, C=C3=A9dric Le Goater wrote:
> > Signed-off-by: C=C3=A9dric Le Goater <clg@kaod.org>
> > ---
> >  drivers/mtd/spi-nor/aspeed-smc.c | 19 ++++++++++++-------
> >  1 file changed, 12 insertions(+), 7 deletions(-)
> >
> > diff --git a/drivers/mtd/spi-nor/aspeed-smc.c b/drivers/mtd/spi-nor/=
aspeed-smc.c
> > index ddf7ae78aa0a..ee3059b27c07 100644
> > --- a/drivers/mtd/spi-nor/aspeed-smc.c
> > +++ b/drivers/mtd/spi-nor/aspeed-smc.c
> > @@ -882,6 +882,17 @@ static const uint32_t aspeed_smc_hclk_divs[] =3D=
 {
> >  };
> >  #define ASPEED_SMC_HCLK_DIV(i) (aspeed_smc_hclk_divs[(i) - 1] << 8)=

> > =20
> > +static u32 aspeed_smc_default_read(struct aspeed_smc_chip *chip)
> > +{
> > +	return (chip->ctl_val[smc_read] & 0x2000) |
>=20
> C=C3=A9dric, isn't this a good time to get rid of these cached ctl_val=
 values?
>=20
> Why not read/modify/store the actual register?
>=20
> What's the profit of this caching?

Reasonable question, but I've merged the change as-is to dev-5.0 on the
basis that it helps fix read corruption on AC-cycles.

We can address this in a follow-up patch if necessary.

Cheers,

Andrew

>=20
> With best regards,
> Alexander Amelkin,
> Leading BMC Software Engineer, YADRO
> https://yadro.com
>=20
>=20
>=20
> Attachments:
> * signature.asc