From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8682AC433EF for ; Mon, 28 Mar 2022 07:18:57 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id CE22E10E615; Mon, 28 Mar 2022 07:18:56 +0000 (UTC) Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by gabe.freedesktop.org (Postfix) with ESMTPS id 476FF10E615 for ; Mon, 28 Mar 2022 07:18:55 +0000 (UTC) X-UUID: c10b793ef49a4ab4b043d96b3d782ea3-20220328 X-UUID: c10b793ef49a4ab4b043d96b3d782ea3-20220328 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1811055432; Mon, 28 Mar 2022 15:18:49 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Mon, 28 Mar 2022 15:18:47 +0800 Received: from mtksdccf07 (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 28 Mar 2022 15:18:47 +0800 Message-ID: <39a65a1d6b507803885cfe7edcdf364732b59cfa.camel@mediatek.com> Subject: Re: [PATCH v9 07/22] drm/mediatek: dpi: move dpi limits to SoC config From: Rex-BC Chen To: Guillaume Ranquet , , , , , , , , , , , , , , , , , Date: Mon, 28 Mar 2022 15:18:44 +0800 In-Reply-To: <20220327223927.20848-8-granquet@baylibre.com> References: <20220327223927.20848-1-granquet@baylibre.com> <20220327223927.20848-8-granquet@baylibre.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.28.5-0ubuntu0.18.04.2 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-MTK: N X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-fbdev@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-phy@lists.infradead.org, linux-arm-kernel@lists.infradead.org, markyacoub@google.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On Mon, 2022-03-28 at 00:39 +0200, Guillaume Ranquet wrote: > Add flexibility by moving the dpi limits to the SoC specific config > > Signed-off-by: Guillaume Ranquet > Reviewed-by: AngeloGioacchino Del Regno < > angelogioacchino.delregno@collabora.com> > --- > drivers/gpu/drm/mediatek/mtk_dpi.c | 25 ++++++++++++++++--------- > 1 file changed, 16 insertions(+), 9 deletions(-) > > diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c > b/drivers/gpu/drm/mediatek/mtk_dpi.c > index 4554e2de1430..4746eb342567 100644 > --- a/drivers/gpu/drm/mediatek/mtk_dpi.c > +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c > @@ -125,6 +125,7 @@ struct mtk_dpi_conf { > bool edge_sel_en; > const u32 *output_fmts; > u32 num_output_fmts; > + const struct mtk_dpi_yc_limit *limit; > }; > > static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, > u32 mask) > @@ -235,9 +236,10 @@ static void mtk_dpi_config_fb_size(struct > mtk_dpi *dpi, u32 width, u32 height) > mtk_dpi_mask(dpi, DPI_SIZE, height << VSIZE, VSIZE_MASK); > } > > -static void mtk_dpi_config_channel_limit(struct mtk_dpi *dpi, > - struct mtk_dpi_yc_limit > *limit) > +static void mtk_dpi_config_channel_limit(struct mtk_dpi *dpi) > { > + const struct mtk_dpi_yc_limit *limit = dpi->conf->limit; > + > mtk_dpi_mask(dpi, DPI_Y_LIMIT, limit->y_bottom << Y_LIMINT_BOT, > Y_LIMINT_BOT_MASK); > mtk_dpi_mask(dpi, DPI_Y_LIMIT, limit->y_top << Y_LIMINT_TOP, > @@ -449,7 +451,6 @@ static int mtk_dpi_power_on(struct mtk_dpi *dpi) > static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi, > struct drm_display_mode *mode) > { > - struct mtk_dpi_yc_limit limit; > struct mtk_dpi_polarities dpi_pol; > struct mtk_dpi_sync_param hsync; > struct mtk_dpi_sync_param vsync_lodd = { 0 }; > @@ -484,11 +485,6 @@ static int mtk_dpi_set_display_mode(struct > mtk_dpi *dpi, > dev_dbg(dpi->dev, "Got PLL %lu Hz, pixel clock %lu Hz\n", > pll_rate, vm.pixelclock); > > - limit.c_bottom = 0x0010; > - limit.c_top = 0x0FE0; > - limit.y_bottom = 0x0010; > - limit.y_top = 0x0FE0; > - > dpi_pol.ck_pol = MTK_DPI_POLARITY_FALLING; > dpi_pol.de_pol = MTK_DPI_POLARITY_RISING; > dpi_pol.hsync_pol = vm.flags & DISPLAY_FLAGS_HSYNC_HIGH ? > @@ -536,7 +532,7 @@ static int mtk_dpi_set_display_mode(struct > mtk_dpi *dpi, > else > mtk_dpi_config_fb_size(dpi, vm.hactive, vm.vactive); > > - mtk_dpi_config_channel_limit(dpi, &limit); > + mtk_dpi_config_channel_limit(dpi); > mtk_dpi_config_bit_num(dpi, dpi->bit_num); > mtk_dpi_config_channel_swap(dpi, dpi->channel_swap); > mtk_dpi_config_yc_map(dpi, dpi->yc_map); > @@ -790,12 +786,20 @@ static const u32 mt8183_output_fmts[] = { > MEDIA_BUS_FMT_RGB888_2X12_BE, > }; > > +static const struct mtk_dpi_yc_limit mtk_dpi_limit = { > + .c_bottom = 0x0010, > + .c_top = 0x0FE0, > + .y_bottom = 0x0010, > + .y_top = 0x0FE0, > +}; > + > static const struct mtk_dpi_conf mt8173_conf = { > .cal_factor = mt8173_calculate_factor, > .reg_h_fre_con = 0xe0, > .max_clock_khz = 300000, > .output_fmts = mt8173_output_fmts, > .num_output_fmts = ARRAY_SIZE(mt8173_output_fmts), > + .limit = &mtk_dpi_limit, > }; > > static const struct mtk_dpi_conf mt2701_conf = { > @@ -805,6 +809,7 @@ static const struct mtk_dpi_conf mt2701_conf = { > .max_clock_khz = 150000, > .output_fmts = mt8173_output_fmts, > .num_output_fmts = ARRAY_SIZE(mt8173_output_fmts), > + .limit = &mtk_dpi_limit, > }; > > static const struct mtk_dpi_conf mt8183_conf = { > @@ -813,6 +818,7 @@ static const struct mtk_dpi_conf mt8183_conf = { > .max_clock_khz = 100000, > .output_fmts = mt8183_output_fmts, > .num_output_fmts = ARRAY_SIZE(mt8183_output_fmts), > + .limit = &mtk_dpi_limit, > }; > > static const struct mtk_dpi_conf mt8192_conf = { > @@ -821,6 +827,7 @@ static const struct mtk_dpi_conf mt8192_conf = { > .max_clock_khz = 150000, > .output_fmts = mt8173_output_fmts, > .num_output_fmts = ARRAY_SIZE(mt8173_output_fmts), > + .limit = &mtk_dpi_limit, > }; > > static int mtk_dpi_probe(struct platform_device *pdev) Reviewed-by: Rex-BC Chen From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AC7F3C433F5 for ; Mon, 28 Mar 2022 07:19:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238780AbiC1HUq (ORCPT ); Mon, 28 Mar 2022 03:20:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57348 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232514AbiC1HUo (ORCPT ); Mon, 28 Mar 2022 03:20:44 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 380CF17062; Mon, 28 Mar 2022 00:18:55 -0700 (PDT) X-UUID: c10b793ef49a4ab4b043d96b3d782ea3-20220328 X-UUID: c10b793ef49a4ab4b043d96b3d782ea3-20220328 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1811055432; Mon, 28 Mar 2022 15:18:49 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Mon, 28 Mar 2022 15:18:47 +0800 Received: from mtksdccf07 (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 28 Mar 2022 15:18:47 +0800 Message-ID: <39a65a1d6b507803885cfe7edcdf364732b59cfa.camel@mediatek.com> Subject: Re: [PATCH v9 07/22] drm/mediatek: dpi: move dpi limits to SoC config From: Rex-BC Chen To: Guillaume Ranquet , , , , , , , , , , , , , , , , , CC: , , , , , , , Date: Mon, 28 Mar 2022 15:18:44 +0800 In-Reply-To: <20220327223927.20848-8-granquet@baylibre.com> References: <20220327223927.20848-1-granquet@baylibre.com> <20220327223927.20848-8-granquet@baylibre.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.28.5-0ubuntu0.18.04.2 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, 2022-03-28 at 00:39 +0200, Guillaume Ranquet wrote: > Add flexibility by moving the dpi limits to the SoC specific config > > Signed-off-by: Guillaume Ranquet > Reviewed-by: AngeloGioacchino Del Regno < > angelogioacchino.delregno@collabora.com> > --- > drivers/gpu/drm/mediatek/mtk_dpi.c | 25 ++++++++++++++++--------- > 1 file changed, 16 insertions(+), 9 deletions(-) > > diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c > b/drivers/gpu/drm/mediatek/mtk_dpi.c > index 4554e2de1430..4746eb342567 100644 > --- a/drivers/gpu/drm/mediatek/mtk_dpi.c > +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c > @@ -125,6 +125,7 @@ struct mtk_dpi_conf { > bool edge_sel_en; > const u32 *output_fmts; > u32 num_output_fmts; > + const struct mtk_dpi_yc_limit *limit; > }; > > static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, > u32 mask) > @@ -235,9 +236,10 @@ static void mtk_dpi_config_fb_size(struct > mtk_dpi *dpi, u32 width, u32 height) > mtk_dpi_mask(dpi, DPI_SIZE, height << VSIZE, VSIZE_MASK); > } > > -static void mtk_dpi_config_channel_limit(struct mtk_dpi *dpi, > - struct mtk_dpi_yc_limit > *limit) > +static void mtk_dpi_config_channel_limit(struct mtk_dpi *dpi) > { > + const struct mtk_dpi_yc_limit *limit = dpi->conf->limit; > + > mtk_dpi_mask(dpi, DPI_Y_LIMIT, limit->y_bottom << Y_LIMINT_BOT, > Y_LIMINT_BOT_MASK); > mtk_dpi_mask(dpi, DPI_Y_LIMIT, limit->y_top << Y_LIMINT_TOP, > @@ -449,7 +451,6 @@ static int mtk_dpi_power_on(struct mtk_dpi *dpi) > static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi, > struct drm_display_mode *mode) > { > - struct mtk_dpi_yc_limit limit; > struct mtk_dpi_polarities dpi_pol; > struct mtk_dpi_sync_param hsync; > struct mtk_dpi_sync_param vsync_lodd = { 0 }; > @@ -484,11 +485,6 @@ static int mtk_dpi_set_display_mode(struct > mtk_dpi *dpi, > dev_dbg(dpi->dev, "Got PLL %lu Hz, pixel clock %lu Hz\n", > pll_rate, vm.pixelclock); > > - limit.c_bottom = 0x0010; > - limit.c_top = 0x0FE0; > - limit.y_bottom = 0x0010; > - limit.y_top = 0x0FE0; > - > dpi_pol.ck_pol = MTK_DPI_POLARITY_FALLING; > dpi_pol.de_pol = MTK_DPI_POLARITY_RISING; > dpi_pol.hsync_pol = vm.flags & DISPLAY_FLAGS_HSYNC_HIGH ? > @@ -536,7 +532,7 @@ static int mtk_dpi_set_display_mode(struct > mtk_dpi *dpi, > else > mtk_dpi_config_fb_size(dpi, vm.hactive, vm.vactive); > > - mtk_dpi_config_channel_limit(dpi, &limit); > + mtk_dpi_config_channel_limit(dpi); > mtk_dpi_config_bit_num(dpi, dpi->bit_num); > mtk_dpi_config_channel_swap(dpi, dpi->channel_swap); > mtk_dpi_config_yc_map(dpi, dpi->yc_map); > @@ -790,12 +786,20 @@ static const u32 mt8183_output_fmts[] = { > MEDIA_BUS_FMT_RGB888_2X12_BE, > }; > > +static const struct mtk_dpi_yc_limit mtk_dpi_limit = { > + .c_bottom = 0x0010, > + .c_top = 0x0FE0, > + .y_bottom = 0x0010, > + .y_top = 0x0FE0, > +}; > + > static const struct mtk_dpi_conf mt8173_conf = { > .cal_factor = mt8173_calculate_factor, > .reg_h_fre_con = 0xe0, > .max_clock_khz = 300000, > .output_fmts = mt8173_output_fmts, > .num_output_fmts = ARRAY_SIZE(mt8173_output_fmts), > + .limit = &mtk_dpi_limit, > }; > > static const struct mtk_dpi_conf mt2701_conf = { > @@ -805,6 +809,7 @@ static const struct mtk_dpi_conf mt2701_conf = { > .max_clock_khz = 150000, > .output_fmts = mt8173_output_fmts, > .num_output_fmts = ARRAY_SIZE(mt8173_output_fmts), > + .limit = &mtk_dpi_limit, > }; > > static const struct mtk_dpi_conf mt8183_conf = { > @@ -813,6 +818,7 @@ static const struct mtk_dpi_conf mt8183_conf = { > .max_clock_khz = 100000, > .output_fmts = mt8183_output_fmts, > .num_output_fmts = ARRAY_SIZE(mt8183_output_fmts), > + .limit = &mtk_dpi_limit, > }; > > static const struct mtk_dpi_conf mt8192_conf = { > @@ -821,6 +827,7 @@ static const struct mtk_dpi_conf mt8192_conf = { > .max_clock_khz = 150000, > .output_fmts = mt8173_output_fmts, > .num_output_fmts = ARRAY_SIZE(mt8173_output_fmts), > + .limit = &mtk_dpi_limit, > }; > > static int mtk_dpi_probe(struct platform_device *pdev) Reviewed-by: Rex-BC Chen From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8AF52C433EF for ; Mon, 28 Mar 2022 07:20:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Date:CC:To:From:Subject:Message-ID:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=R4CoTHvxRAlTAmUscZODlgNFDTJ1T4W5bayLyDEoSgM=; b=Z4zJnXHoLXfHnG vVAg6y7eeOe7akaUGoEEYCFq+Wivu8JhfmmQ8dmJzUkWUz5uMvTNI/ADYAaLHx6YZSDHkUkbpSlMJ VoIxmds2MMrGxg+oon7l52AAzIOZ8MxVOBkXZ2xwtH2XECdQQLcVa1EvFBxT13B9bKEn8+0TJzeBj fj6gD14ky54+n4seNETOFWejWRzG6+6CgE5Dkx89vddouXUAQQnHrswoEIWa+VT00GMH5hbnl4OCr WDv3CJmsxXd6sXK3H2IcgN2u9jNSswo6R1CXKkKh7+o+i8468la/bEebEd9LnEY6lny8WucCKjrEJ hE41uE3k2tNFWYmJTa6w==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nYjfQ-007Zul-8W; Mon, 28 Mar 2022 07:19:56 +0000 Received: from mailgw02.mediatek.com ([216.200.240.185]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nYjfE-007Zrw-8O; Mon, 28 Mar 2022 07:19:45 +0000 X-UUID: 740cad0fba8f4c0481bb43884f7e45d2-20220328 X-UUID: 740cad0fba8f4c0481bb43884f7e45d2-20220328 Received: from mtkcas66.mediatek.inc [(172.29.193.44)] by mailgw02.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1425020537; Mon, 28 Mar 2022 00:19:36 -0700 Received: from mtkmbs10n1.mediatek.inc (172.21.101.34) by MTKMBS62DR.mediatek.inc (172.29.94.18) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 28 Mar 2022 00:18:49 -0700 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Mon, 28 Mar 2022 15:18:47 +0800 Received: from mtksdccf07 (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 28 Mar 2022 15:18:47 +0800 Message-ID: <39a65a1d6b507803885cfe7edcdf364732b59cfa.camel@mediatek.com> Subject: Re: [PATCH v9 07/22] drm/mediatek: dpi: move dpi limits to SoC config From: Rex-BC Chen To: Guillaume Ranquet , , , , , , , , , , , , , , , , , CC: , , , , , , , Date: Mon, 28 Mar 2022 15:18:44 +0800 In-Reply-To: <20220327223927.20848-8-granquet@baylibre.com> References: <20220327223927.20848-1-granquet@baylibre.com> <20220327223927.20848-8-granquet@baylibre.com> X-Mailer: Evolution 3.28.5-0ubuntu0.18.04.2 MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220328_001944_313490_ECBE5D32 X-CRM114-Status: GOOD ( 16.11 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org On Mon, 2022-03-28 at 00:39 +0200, Guillaume Ranquet wrote: > Add flexibility by moving the dpi limits to the SoC specific config > > Signed-off-by: Guillaume Ranquet > Reviewed-by: AngeloGioacchino Del Regno < > angelogioacchino.delregno@collabora.com> > --- > drivers/gpu/drm/mediatek/mtk_dpi.c | 25 ++++++++++++++++--------- > 1 file changed, 16 insertions(+), 9 deletions(-) > > diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c > b/drivers/gpu/drm/mediatek/mtk_dpi.c > index 4554e2de1430..4746eb342567 100644 > --- a/drivers/gpu/drm/mediatek/mtk_dpi.c > +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c > @@ -125,6 +125,7 @@ struct mtk_dpi_conf { > bool edge_sel_en; > const u32 *output_fmts; > u32 num_output_fmts; > + const struct mtk_dpi_yc_limit *limit; > }; > > static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, > u32 mask) > @@ -235,9 +236,10 @@ static void mtk_dpi_config_fb_size(struct > mtk_dpi *dpi, u32 width, u32 height) > mtk_dpi_mask(dpi, DPI_SIZE, height << VSIZE, VSIZE_MASK); > } > > -static void mtk_dpi_config_channel_limit(struct mtk_dpi *dpi, > - struct mtk_dpi_yc_limit > *limit) > +static void mtk_dpi_config_channel_limit(struct mtk_dpi *dpi) > { > + const struct mtk_dpi_yc_limit *limit = dpi->conf->limit; > + > mtk_dpi_mask(dpi, DPI_Y_LIMIT, limit->y_bottom << Y_LIMINT_BOT, > Y_LIMINT_BOT_MASK); > mtk_dpi_mask(dpi, DPI_Y_LIMIT, limit->y_top << Y_LIMINT_TOP, > @@ -449,7 +451,6 @@ static int mtk_dpi_power_on(struct mtk_dpi *dpi) > static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi, > struct drm_display_mode *mode) > { > - struct mtk_dpi_yc_limit limit; > struct mtk_dpi_polarities dpi_pol; > struct mtk_dpi_sync_param hsync; > struct mtk_dpi_sync_param vsync_lodd = { 0 }; > @@ -484,11 +485,6 @@ static int mtk_dpi_set_display_mode(struct > mtk_dpi *dpi, > dev_dbg(dpi->dev, "Got PLL %lu Hz, pixel clock %lu Hz\n", > pll_rate, vm.pixelclock); > > - limit.c_bottom = 0x0010; > - limit.c_top = 0x0FE0; > - limit.y_bottom = 0x0010; > - limit.y_top = 0x0FE0; > - > dpi_pol.ck_pol = MTK_DPI_POLARITY_FALLING; > dpi_pol.de_pol = MTK_DPI_POLARITY_RISING; > dpi_pol.hsync_pol = vm.flags & DISPLAY_FLAGS_HSYNC_HIGH ? > @@ -536,7 +532,7 @@ static int mtk_dpi_set_display_mode(struct > mtk_dpi *dpi, > else > mtk_dpi_config_fb_size(dpi, vm.hactive, vm.vactive); > > - mtk_dpi_config_channel_limit(dpi, &limit); > + mtk_dpi_config_channel_limit(dpi); > mtk_dpi_config_bit_num(dpi, dpi->bit_num); > mtk_dpi_config_channel_swap(dpi, dpi->channel_swap); > mtk_dpi_config_yc_map(dpi, dpi->yc_map); > @@ -790,12 +786,20 @@ static const u32 mt8183_output_fmts[] = { > MEDIA_BUS_FMT_RGB888_2X12_BE, > }; > > +static const struct mtk_dpi_yc_limit mtk_dpi_limit = { > + .c_bottom = 0x0010, > + .c_top = 0x0FE0, > + .y_bottom = 0x0010, > + .y_top = 0x0FE0, > +}; > + > static const struct mtk_dpi_conf mt8173_conf = { > .cal_factor = mt8173_calculate_factor, > .reg_h_fre_con = 0xe0, > .max_clock_khz = 300000, > .output_fmts = mt8173_output_fmts, > .num_output_fmts = ARRAY_SIZE(mt8173_output_fmts), > + .limit = &mtk_dpi_limit, > }; > > static const struct mtk_dpi_conf mt2701_conf = { > @@ -805,6 +809,7 @@ static const struct mtk_dpi_conf mt2701_conf = { > .max_clock_khz = 150000, > .output_fmts = mt8173_output_fmts, > .num_output_fmts = ARRAY_SIZE(mt8173_output_fmts), > + .limit = &mtk_dpi_limit, > }; > > static const struct mtk_dpi_conf mt8183_conf = { > @@ -813,6 +818,7 @@ static const struct mtk_dpi_conf mt8183_conf = { > .max_clock_khz = 100000, > .output_fmts = mt8183_output_fmts, > .num_output_fmts = ARRAY_SIZE(mt8183_output_fmts), > + .limit = &mtk_dpi_limit, > }; > > static const struct mtk_dpi_conf mt8192_conf = { > @@ -821,6 +827,7 @@ static const struct mtk_dpi_conf mt8192_conf = { > .max_clock_khz = 150000, > .output_fmts = mt8173_output_fmts, > .num_output_fmts = ARRAY_SIZE(mt8173_output_fmts), > + .limit = &mtk_dpi_limit, > }; > > static int mtk_dpi_probe(struct platform_device *pdev) Reviewed-by: Rex-BC Chen _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7443EC433EF for ; Mon, 28 Mar 2022 07:19:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Date:CC:To:From:Subject:Message-ID:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=TJHVSg3QUvHUPIyRnHFOWKkguvaoFbpSkM1hgEUQDCc=; b=NkzAXsfDXq2cIe oJ7SD34snM3Ksq0mvv3I+PbUv2tLqDOjxVxeXPIuo/YxHn9CPhDsMIAZ3EQ3qKo1qEUdXdREEL51B WijUKN61hifk7eFL0n1V0PwYEQN+VkteFDlbot6VznZiSMHA4uB/yrsK3KyuqumaBS73gzktaP0+e IR3ZZVqAucJexngMyHGu5MNW9KkLNGQlWfgmtkG6R0CpVS1PHNj1NGN+JIv5oO6+3GWPVn0T5yn7b +Rh/4pAu+I5KMEDz03vMmYXMqIUycKTmFL0xle/1vbQlwo454JegeeGznPgZNK+qoh7NL9dEbJgZ1 UqGO244BBapXNwb/8Yyg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nYjfQ-007Zv2-Vk; Mon, 28 Mar 2022 07:19:56 +0000 Received: from mailgw02.mediatek.com ([216.200.240.185]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nYjfE-007Zrw-8O; Mon, 28 Mar 2022 07:19:45 +0000 X-UUID: 740cad0fba8f4c0481bb43884f7e45d2-20220328 X-UUID: 740cad0fba8f4c0481bb43884f7e45d2-20220328 Received: from mtkcas66.mediatek.inc [(172.29.193.44)] by mailgw02.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1425020537; Mon, 28 Mar 2022 00:19:36 -0700 Received: from mtkmbs10n1.mediatek.inc (172.21.101.34) by MTKMBS62DR.mediatek.inc (172.29.94.18) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 28 Mar 2022 00:18:49 -0700 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Mon, 28 Mar 2022 15:18:47 +0800 Received: from mtksdccf07 (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 28 Mar 2022 15:18:47 +0800 Message-ID: <39a65a1d6b507803885cfe7edcdf364732b59cfa.camel@mediatek.com> Subject: Re: [PATCH v9 07/22] drm/mediatek: dpi: move dpi limits to SoC config From: Rex-BC Chen To: Guillaume Ranquet , , , , , , , , , , , , , , , , , CC: , , , , , , , Date: Mon, 28 Mar 2022 15:18:44 +0800 In-Reply-To: <20220327223927.20848-8-granquet@baylibre.com> References: <20220327223927.20848-1-granquet@baylibre.com> <20220327223927.20848-8-granquet@baylibre.com> X-Mailer: Evolution 3.28.5-0ubuntu0.18.04.2 MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220328_001944_313490_ECBE5D32 X-CRM114-Status: GOOD ( 16.11 ) X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org On Mon, 2022-03-28 at 00:39 +0200, Guillaume Ranquet wrote: > Add flexibility by moving the dpi limits to the SoC specific config > > Signed-off-by: Guillaume Ranquet > Reviewed-by: AngeloGioacchino Del Regno < > angelogioacchino.delregno@collabora.com> > --- > drivers/gpu/drm/mediatek/mtk_dpi.c | 25 ++++++++++++++++--------- > 1 file changed, 16 insertions(+), 9 deletions(-) > > diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c > b/drivers/gpu/drm/mediatek/mtk_dpi.c > index 4554e2de1430..4746eb342567 100644 > --- a/drivers/gpu/drm/mediatek/mtk_dpi.c > +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c > @@ -125,6 +125,7 @@ struct mtk_dpi_conf { > bool edge_sel_en; > const u32 *output_fmts; > u32 num_output_fmts; > + const struct mtk_dpi_yc_limit *limit; > }; > > static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, > u32 mask) > @@ -235,9 +236,10 @@ static void mtk_dpi_config_fb_size(struct > mtk_dpi *dpi, u32 width, u32 height) > mtk_dpi_mask(dpi, DPI_SIZE, height << VSIZE, VSIZE_MASK); > } > > -static void mtk_dpi_config_channel_limit(struct mtk_dpi *dpi, > - struct mtk_dpi_yc_limit > *limit) > +static void mtk_dpi_config_channel_limit(struct mtk_dpi *dpi) > { > + const struct mtk_dpi_yc_limit *limit = dpi->conf->limit; > + > mtk_dpi_mask(dpi, DPI_Y_LIMIT, limit->y_bottom << Y_LIMINT_BOT, > Y_LIMINT_BOT_MASK); > mtk_dpi_mask(dpi, DPI_Y_LIMIT, limit->y_top << Y_LIMINT_TOP, > @@ -449,7 +451,6 @@ static int mtk_dpi_power_on(struct mtk_dpi *dpi) > static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi, > struct drm_display_mode *mode) > { > - struct mtk_dpi_yc_limit limit; > struct mtk_dpi_polarities dpi_pol; > struct mtk_dpi_sync_param hsync; > struct mtk_dpi_sync_param vsync_lodd = { 0 }; > @@ -484,11 +485,6 @@ static int mtk_dpi_set_display_mode(struct > mtk_dpi *dpi, > dev_dbg(dpi->dev, "Got PLL %lu Hz, pixel clock %lu Hz\n", > pll_rate, vm.pixelclock); > > - limit.c_bottom = 0x0010; > - limit.c_top = 0x0FE0; > - limit.y_bottom = 0x0010; > - limit.y_top = 0x0FE0; > - > dpi_pol.ck_pol = MTK_DPI_POLARITY_FALLING; > dpi_pol.de_pol = MTK_DPI_POLARITY_RISING; > dpi_pol.hsync_pol = vm.flags & DISPLAY_FLAGS_HSYNC_HIGH ? > @@ -536,7 +532,7 @@ static int mtk_dpi_set_display_mode(struct > mtk_dpi *dpi, > else > mtk_dpi_config_fb_size(dpi, vm.hactive, vm.vactive); > > - mtk_dpi_config_channel_limit(dpi, &limit); > + mtk_dpi_config_channel_limit(dpi); > mtk_dpi_config_bit_num(dpi, dpi->bit_num); > mtk_dpi_config_channel_swap(dpi, dpi->channel_swap); > mtk_dpi_config_yc_map(dpi, dpi->yc_map); > @@ -790,12 +786,20 @@ static const u32 mt8183_output_fmts[] = { > MEDIA_BUS_FMT_RGB888_2X12_BE, > }; > > +static const struct mtk_dpi_yc_limit mtk_dpi_limit = { > + .c_bottom = 0x0010, > + .c_top = 0x0FE0, > + .y_bottom = 0x0010, > + .y_top = 0x0FE0, > +}; > + > static const struct mtk_dpi_conf mt8173_conf = { > .cal_factor = mt8173_calculate_factor, > .reg_h_fre_con = 0xe0, > .max_clock_khz = 300000, > .output_fmts = mt8173_output_fmts, > .num_output_fmts = ARRAY_SIZE(mt8173_output_fmts), > + .limit = &mtk_dpi_limit, > }; > > static const struct mtk_dpi_conf mt2701_conf = { > @@ -805,6 +809,7 @@ static const struct mtk_dpi_conf mt2701_conf = { > .max_clock_khz = 150000, > .output_fmts = mt8173_output_fmts, > .num_output_fmts = ARRAY_SIZE(mt8173_output_fmts), > + .limit = &mtk_dpi_limit, > }; > > static const struct mtk_dpi_conf mt8183_conf = { > @@ -813,6 +818,7 @@ static const struct mtk_dpi_conf mt8183_conf = { > .max_clock_khz = 100000, > .output_fmts = mt8183_output_fmts, > .num_output_fmts = ARRAY_SIZE(mt8183_output_fmts), > + .limit = &mtk_dpi_limit, > }; > > static const struct mtk_dpi_conf mt8192_conf = { > @@ -821,6 +827,7 @@ static const struct mtk_dpi_conf mt8192_conf = { > .max_clock_khz = 150000, > .output_fmts = mt8173_output_fmts, > .num_output_fmts = ARRAY_SIZE(mt8173_output_fmts), > + .limit = &mtk_dpi_limit, > }; > > static int mtk_dpi_probe(struct platform_device *pdev) Reviewed-by: Rex-BC Chen -- linux-phy mailing list linux-phy@lists.infradead.org https://lists.infradead.org/mailman/listinfo/linux-phy From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id F136AC4332F for ; Mon, 28 Mar 2022 07:20:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Date:CC:To:From:Subject:Message-ID:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=rzSBnE4fNB25WAo15zl6OgWkj50KNufVx+G+vVDX7xc=; b=ZeC6q0b2n/jvGQ NF56hgQv2oPXodzHpWBEpTOWvk7TVzujYx1qiHCxBrRIJXjx5XiE949DBGlbuXtgE7ZL3ydg52gzl O9v7LDf+1cJlGaPMIpOEmYRacRZRsGiZtzze1TcG+G14Xgx9e0TkcGLI1DsaXSNy+/+9iY3ylvqi+ MiIVQfm0eXi7ddXgby4kDTWto3It/7mW81nb3DISa67s7xqSnAeAof/qvc86qQjuGmmFOT5GPamc8 JSaphleiVqk9zg1CN7wID9GFeBwpCau+MY0zfb4b8H1d5oTxNaz5UoFeoSQff4wUWpNbX0Xwd3TQE 1CCpeHdDA/wEfsBV5fdw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nYjfI-007Zt3-04; Mon, 28 Mar 2022 07:19:48 +0000 Received: from mailgw02.mediatek.com ([216.200.240.185]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nYjfE-007Zrw-8O; Mon, 28 Mar 2022 07:19:45 +0000 X-UUID: 740cad0fba8f4c0481bb43884f7e45d2-20220328 X-UUID: 740cad0fba8f4c0481bb43884f7e45d2-20220328 Received: from mtkcas66.mediatek.inc [(172.29.193.44)] by mailgw02.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1425020537; Mon, 28 Mar 2022 00:19:36 -0700 Received: from mtkmbs10n1.mediatek.inc (172.21.101.34) by MTKMBS62DR.mediatek.inc (172.29.94.18) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 28 Mar 2022 00:18:49 -0700 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Mon, 28 Mar 2022 15:18:47 +0800 Received: from mtksdccf07 (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 28 Mar 2022 15:18:47 +0800 Message-ID: <39a65a1d6b507803885cfe7edcdf364732b59cfa.camel@mediatek.com> Subject: Re: [PATCH v9 07/22] drm/mediatek: dpi: move dpi limits to SoC config From: Rex-BC Chen To: Guillaume Ranquet , , , , , , , , , , , , , , , , , CC: , , , , , , , Date: Mon, 28 Mar 2022 15:18:44 +0800 In-Reply-To: <20220327223927.20848-8-granquet@baylibre.com> References: <20220327223927.20848-1-granquet@baylibre.com> <20220327223927.20848-8-granquet@baylibre.com> X-Mailer: Evolution 3.28.5-0ubuntu0.18.04.2 MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220328_001944_313490_ECBE5D32 X-CRM114-Status: GOOD ( 16.11 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, 2022-03-28 at 00:39 +0200, Guillaume Ranquet wrote: > Add flexibility by moving the dpi limits to the SoC specific config > > Signed-off-by: Guillaume Ranquet > Reviewed-by: AngeloGioacchino Del Regno < > angelogioacchino.delregno@collabora.com> > --- > drivers/gpu/drm/mediatek/mtk_dpi.c | 25 ++++++++++++++++--------- > 1 file changed, 16 insertions(+), 9 deletions(-) > > diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c > b/drivers/gpu/drm/mediatek/mtk_dpi.c > index 4554e2de1430..4746eb342567 100644 > --- a/drivers/gpu/drm/mediatek/mtk_dpi.c > +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c > @@ -125,6 +125,7 @@ struct mtk_dpi_conf { > bool edge_sel_en; > const u32 *output_fmts; > u32 num_output_fmts; > + const struct mtk_dpi_yc_limit *limit; > }; > > static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, > u32 mask) > @@ -235,9 +236,10 @@ static void mtk_dpi_config_fb_size(struct > mtk_dpi *dpi, u32 width, u32 height) > mtk_dpi_mask(dpi, DPI_SIZE, height << VSIZE, VSIZE_MASK); > } > > -static void mtk_dpi_config_channel_limit(struct mtk_dpi *dpi, > - struct mtk_dpi_yc_limit > *limit) > +static void mtk_dpi_config_channel_limit(struct mtk_dpi *dpi) > { > + const struct mtk_dpi_yc_limit *limit = dpi->conf->limit; > + > mtk_dpi_mask(dpi, DPI_Y_LIMIT, limit->y_bottom << Y_LIMINT_BOT, > Y_LIMINT_BOT_MASK); > mtk_dpi_mask(dpi, DPI_Y_LIMIT, limit->y_top << Y_LIMINT_TOP, > @@ -449,7 +451,6 @@ static int mtk_dpi_power_on(struct mtk_dpi *dpi) > static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi, > struct drm_display_mode *mode) > { > - struct mtk_dpi_yc_limit limit; > struct mtk_dpi_polarities dpi_pol; > struct mtk_dpi_sync_param hsync; > struct mtk_dpi_sync_param vsync_lodd = { 0 }; > @@ -484,11 +485,6 @@ static int mtk_dpi_set_display_mode(struct > mtk_dpi *dpi, > dev_dbg(dpi->dev, "Got PLL %lu Hz, pixel clock %lu Hz\n", > pll_rate, vm.pixelclock); > > - limit.c_bottom = 0x0010; > - limit.c_top = 0x0FE0; > - limit.y_bottom = 0x0010; > - limit.y_top = 0x0FE0; > - > dpi_pol.ck_pol = MTK_DPI_POLARITY_FALLING; > dpi_pol.de_pol = MTK_DPI_POLARITY_RISING; > dpi_pol.hsync_pol = vm.flags & DISPLAY_FLAGS_HSYNC_HIGH ? > @@ -536,7 +532,7 @@ static int mtk_dpi_set_display_mode(struct > mtk_dpi *dpi, > else > mtk_dpi_config_fb_size(dpi, vm.hactive, vm.vactive); > > - mtk_dpi_config_channel_limit(dpi, &limit); > + mtk_dpi_config_channel_limit(dpi); > mtk_dpi_config_bit_num(dpi, dpi->bit_num); > mtk_dpi_config_channel_swap(dpi, dpi->channel_swap); > mtk_dpi_config_yc_map(dpi, dpi->yc_map); > @@ -790,12 +786,20 @@ static const u32 mt8183_output_fmts[] = { > MEDIA_BUS_FMT_RGB888_2X12_BE, > }; > > +static const struct mtk_dpi_yc_limit mtk_dpi_limit = { > + .c_bottom = 0x0010, > + .c_top = 0x0FE0, > + .y_bottom = 0x0010, > + .y_top = 0x0FE0, > +}; > + > static const struct mtk_dpi_conf mt8173_conf = { > .cal_factor = mt8173_calculate_factor, > .reg_h_fre_con = 0xe0, > .max_clock_khz = 300000, > .output_fmts = mt8173_output_fmts, > .num_output_fmts = ARRAY_SIZE(mt8173_output_fmts), > + .limit = &mtk_dpi_limit, > }; > > static const struct mtk_dpi_conf mt2701_conf = { > @@ -805,6 +809,7 @@ static const struct mtk_dpi_conf mt2701_conf = { > .max_clock_khz = 150000, > .output_fmts = mt8173_output_fmts, > .num_output_fmts = ARRAY_SIZE(mt8173_output_fmts), > + .limit = &mtk_dpi_limit, > }; > > static const struct mtk_dpi_conf mt8183_conf = { > @@ -813,6 +818,7 @@ static const struct mtk_dpi_conf mt8183_conf = { > .max_clock_khz = 100000, > .output_fmts = mt8183_output_fmts, > .num_output_fmts = ARRAY_SIZE(mt8183_output_fmts), > + .limit = &mtk_dpi_limit, > }; > > static const struct mtk_dpi_conf mt8192_conf = { > @@ -821,6 +827,7 @@ static const struct mtk_dpi_conf mt8192_conf = { > .max_clock_khz = 150000, > .output_fmts = mt8173_output_fmts, > .num_output_fmts = ARRAY_SIZE(mt8173_output_fmts), > + .limit = &mtk_dpi_limit, > }; > > static int mtk_dpi_probe(struct platform_device *pdev) Reviewed-by: Rex-BC Chen _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel