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From: Richard Henderson <rth@twiddle.net>
To: Stafford Horne <shorne@gmail.com>
Cc: Jia Liu <proljc@gmail.com>,
	qemu-devel@nongnu.org, openrisc@lists.librecores.org
Subject: Re: [Qemu-devel] [PATCH] target-openrisc: Fix exception handling status registers
Date: Wed, 25 Jan 2017 09:27:29 -0800	[thread overview]
Message-ID: <39f927aa-26fe-0e43-7c6b-efe1b70bc5fa@twiddle.net> (raw)
In-Reply-To: <20170125123430.GG7836@lianli.shorne-pla.net>

On 01/25/2017 04:34 AM, Stafford Horne wrote:
> Hmm, I just tried your qemu branch and mine:
> 
>   git@github.com:stffrdhrn/qemu.git or1k-fix-sigill
> 
> Both of them were able to boot fine.
> 
> The opencores,or1200-rtlsvn481 cpu node is in the or1ksim device tree
> definition.  Are you sure your kernel config has this in it?
> 
>   CONFIG_OPENRISC_BUILTIN_DTB="or1ksim"
> 
> Could you send your kernel config?
> 
> I have attached mine, just in case.  For next-20170124

Curious.  The entire diff between our configs is just

--- ../or-config        2017-01-24 09:14:51.918059107 -0800
+++ .config     2017-01-25 09:18:14.153999754 -0800
@@ -18,7 +18,7 @@
 #
 CONFIG_BROKEN_ON_SMP=y
 CONFIG_INIT_ENV_ARG_LIMIT=32
-CONFIG_CROSS_COMPILE="or1k-linux-musl-"
+CONFIG_CROSS_COMPILE="or1k-musl-linux-"
 # CONFIG_COMPILE_TEST is not set
 CONFIG_LOCALVERSION=""
 CONFIG_LOCALVERSION_AUTO=y

So you're saying you *do* get serial port output?

Perhaps you can just send me your kernel...


r~

WARNING: multiple messages have this Message-ID (diff)
From: Richard Henderson <rth@twiddle.net>
To: openrisc@lists.librecores.org
Subject: [OpenRISC] [Qemu-devel] [PATCH] target-openrisc: Fix exception handling status registers
Date: Wed, 25 Jan 2017 09:27:29 -0800	[thread overview]
Message-ID: <39f927aa-26fe-0e43-7c6b-efe1b70bc5fa@twiddle.net> (raw)
In-Reply-To: <20170125123430.GG7836@lianli.shorne-pla.net>

On 01/25/2017 04:34 AM, Stafford Horne wrote:
> Hmm, I just tried your qemu branch and mine:
> 
>   git at github.com:stffrdhrn/qemu.git or1k-fix-sigill
> 
> Both of them were able to boot fine.
> 
> The opencores,or1200-rtlsvn481 cpu node is in the or1ksim device tree
> definition.  Are you sure your kernel config has this in it?
> 
>   CONFIG_OPENRISC_BUILTIN_DTB="or1ksim"
> 
> Could you send your kernel config?
> 
> I have attached mine, just in case.  For next-20170124

Curious.  The entire diff between our configs is just

--- ../or-config        2017-01-24 09:14:51.918059107 -0800
+++ .config     2017-01-25 09:18:14.153999754 -0800
@@ -18,7 +18,7 @@
 #
 CONFIG_BROKEN_ON_SMP=y
 CONFIG_INIT_ENV_ARG_LIMIT=32
-CONFIG_CROSS_COMPILE="or1k-linux-musl-"
+CONFIG_CROSS_COMPILE="or1k-musl-linux-"
 # CONFIG_COMPILE_TEST is not set
 CONFIG_LOCALVERSION=""
 CONFIG_LOCALVERSION_AUTO=y

So you're saying you *do* get serial port output?

Perhaps you can just send me your kernel...


r~

  reply	other threads:[~2017-01-25 17:27 UTC|newest]

Thread overview: 45+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-01-13 21:57 [OpenRISC] [PATCH] target-openrisc: Fix exception handling status registers Stafford Horne
2017-01-13 22:02 ` Stafford Horne
2017-01-14  4:29   ` Jia Liu
2017-01-14  8:04     ` [Qemu-devel] " Stafford Horne
2017-01-14  8:04       ` [OpenRISC] " Stafford Horne
2017-01-20 16:39       ` [Qemu-devel] " Stafford Horne
2017-01-20 16:39         ` [OpenRISC] " Stafford Horne
2017-01-23 18:08         ` [Qemu-devel] " Richard Henderson
2017-01-23 18:08           ` [OpenRISC] " Richard Henderson
2017-01-24 10:26           ` Stafford Horne
2017-01-24 10:26             ` [OpenRISC] " Stafford Horne
2017-01-24 18:32             ` Richard Henderson
2017-01-24 18:32               ` [OpenRISC] " Richard Henderson
2017-01-25 12:34               ` Stafford Horne
2017-01-25 12:34                 ` [OpenRISC] " Stafford Horne
2017-01-25 17:27                 ` Richard Henderson [this message]
2017-01-25 17:27                   ` Richard Henderson
2017-01-26 13:12                   ` Stafford Horne
2017-01-26 13:12                     ` [OpenRISC] " Stafford Horne
2017-01-26 17:26                     ` Richard Henderson
2017-01-26 17:26                       ` [OpenRISC] " Richard Henderson
2017-01-26 22:01                       ` Stafford Horne
2017-01-26 22:01                         ` [OpenRISC] " Stafford Horne
2017-02-01 10:04                       ` Stafford Horne
2017-02-01 10:04                         ` [OpenRISC] " Stafford Horne
2017-02-01 18:15                         ` Richard Henderson
2017-02-01 18:15                           ` [OpenRISC] " Richard Henderson
2017-02-02 14:34                           ` Stafford Horne
2017-02-02 14:34                             ` [OpenRISC] " Stafford Horne
2017-02-03 15:14                             ` Stafford Horne
2017-02-03 15:14                               ` [OpenRISC] " Stafford Horne
2017-02-07  2:36                               ` Richard Henderson
2017-02-07  2:36                                 ` [OpenRISC] " Richard Henderson
2017-02-06 20:44                             ` Richard Henderson
2017-02-07  0:31                               ` Stafford Horne
2017-02-07  5:48                                 ` Richard Henderson
2017-02-07  5:53                         ` Richard Henderson
2017-02-07  5:53                           ` [OpenRISC] " Richard Henderson
2017-02-08 14:01                           ` Stafford Horne
2017-02-08 14:01                             ` [OpenRISC] " Stafford Horne
2017-02-08 16:38                             ` Stafford Horne
2017-02-08 16:38                               ` [OpenRISC] " Stafford Horne
2017-02-08 20:38                             ` Richard Henderson
2017-02-08 20:38                               ` [OpenRISC] " Richard Henderson
2017-01-13 22:00 Stafford Horne

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