Re: mips32_flush_cache routine corrupts CP0_STATUS with gcc-2.96

From: Carsten Langgaard <carstenl@mips.com>
To: "Gleb O. Raiko" <raiko@niisi.msk.ru>
Cc: Ralf Baechle <ralf@oss.sgi.com>,
	Jon Burgess <Jon_Burgess@eur.3com.com>,
	linux-mips@oss.sgi.com
Subject: Re: mips32_flush_cache routine corrupts CP0_STATUS with gcc-2.96
Date: Thu, 11 Jul 2002 11:18:59 +0200	[thread overview]
Message-ID: <3D2D4D83.B2694DF1@mips.com> (raw)
In-Reply-To: 3D2D465C.FA06D50A@niisi.msk.ru

"Gleb O. Raiko" wrote:

> Ralf Baechle wrote:
> >
> > On Wed, Jul 10, 2002 at 03:16:21PM +0100, Jon Burgess wrote:
> >
> > > This may be caused by the cache routines running from the a cached kseg0, it
> > > looks like it can be fixed by making sure that the are always called via
> > > KSEG1ADDR(fn) which looks like it could be done with a bit of fiddling of the
> > > setup_cache_funcs code. I have included a patch below which starts this, but I
> > > haven't caught all combinations of how the routines are called.
> >
> > While that could be done it's not a good idea; running code in KSEG1 is
> > very slow.
> >
>
> Unfortunately, it's required by manuals for some processors. As I know,
> IDT HW manuals clearly state cache flush routines must operate from
> uncached code and must access uncached data only. Examples are R30x1 CPU
> series.

Yes, that's true.
But that code belongs in the R30xx specific cache routines, not in the MIPS32 cache
routines.

>
> Regards,
> Gleb.

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