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spf=pass smtp.mailfrom=arm.com; dmarc=pass action=none header.from=arm.com; dkim=pass header.d=arm.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=armh.onmicrosoft.com; s=selector2-armh-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=UkXB6+yAzqlmMcIig7zwuWmEpB7pxu6engCf19nVC9Y=; b=50ysvvDuqLlYJDWHzE46oA9cwSRVTWebmKt6kQjrCSuixX5wItLIOnO//leRr9YN4K00LKHJJGYFMh6p7hHYVqRTeYii7cg01ci2Uw7z5NmaGa4bKRSJ0S/rDcPU3hbHmMxU/GLsxY2ESng/wi6ePdji4SEKBnpY5eb96fAnNH0= From: Rahul Singh To: Julien Grall CC: Stefano Stabellini , "lucmiccio@gmail.com" , xen-devel , Bertrand Marquis , Volodymyr Babchuk Subject: Re: [PATCH] xen/arm: fix gnttab_need_iommu_mapping Thread-Topic: [PATCH] xen/arm: fix gnttab_need_iommu_mapping Thread-Index: AQHW/CCVIBhvrRIcEE2wSNDNMu6y5KpOkgeAgAABdICAAAIFgA== Date: Mon, 8 Feb 2021 18:19:04 +0000 Message-ID: <3EEEACBE-2028-4DE9-A3BD-053FF82CFC75@arm.com> References: <7e963696-a21f-4c79-5f35-a342982bee86@xen.org> In-Reply-To: <7e963696-a21f-4c79-5f35-a342982bee86@xen.org> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: Authentication-Results-Original: xen.org; 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X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Feb 2021 18:19:12.8746 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 74da05d7-245f-40de-de3a-08d8cc5e0973 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[63.35.35.123];Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: VE1EUR03FT016.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM8PR08MB6323 Hello Julien, > On 8 Feb 2021, at 6:11 pm, Julien Grall wrote: >=20 >=20 >=20 > On 08/02/2021 18:06, Rahul Singh wrote: >>> On 6 Feb 2021, at 12:38 am, Stefano Stabellini = wrote: >>>=20 >>> Commit 91d4eca7add broke gnttab_need_iommu_mapping on ARM. >>> The offending chunk is: >>>=20 >>> #define gnttab_need_iommu_mapping(d) \ >>> - (is_domain_direct_mapped(d) && need_iommu(d)) >>> + (is_domain_direct_mapped(d) && need_iommu_pt_sync(d)) >>>=20 >>> On ARM we need gnttab_need_iommu_mapping to be true for dom0 when it is >>> directly mapped, like the old check did, but the new check is always >>> false. >>>=20 >>> In fact, need_iommu_pt_sync is defined as dom_iommu(d)->need_sync and >>> need_sync is set as: >>>=20 >>> if ( !is_hardware_domain(d) || iommu_hwdom_strict ) >>> hd->need_sync =3D !iommu_use_hap_pt(d); >>>=20 >>> iommu_hwdom_strict is actually supposed to be ignored on ARM, see the >>> definition in docs/misc/xen-command-line.pandoc: >>>=20 >>> This option is hardwired to true for x86 PVH dom0's (as RAM belongin= g to >>> other domains in the system don't live in a compatible address space= ), and >>> is ignored for ARM. >>>=20 >>> But aside from that, the issue is that iommu_use_hap_pt(d) is true, >>> hence, hd->need_sync is false, and gnttab_need_iommu_mapping(d) is fals= e >>> too. >>>=20 >>> As a consequence, when using PV network from a domU on a system where >>> IOMMU is on from Dom0, I get: >>>=20 >>> (XEN) smmu: /smmu@fd800000: Unhandled context fault: fsr=3D0x402, iova= =3D0x8424cb148, fsynr=3D0xb0001, cb=3D0 >>> [ 68.290307] macb ff0e0000.ethernet eth0: DMA bus error: HRESP not OK >> I also observed the IOMMU fault when DOMU guest is created and great tab= le is used when IOMMU is enabled. I fixed the error in different way but I = am not sure if you also observing the same error. I submitted the patch to = pci-passthrough integration branch. Please have a look once if that make se= nse. >=20 > I belive this is the same error as Stefano has observed. However, your pa= tch will unfortunately not work if you have a system with a mix of protecte= d and non-protected DMA-capable devices. Yes you are right thats what I though when I fixed the error but then I tho= ught in different direction if IOMMU is enabled system wise every device sh= ould be protected by IOMMU. My understanding might be wrong. Regards, Rahul > Cheers, >=20 > --=20 > Julien Grall