diff for duplicates of <3a0db6052d58eb440ea29772fc7ad2502a1dfa3b.1543131714.git.mesihkilinc@gmail.com>
diff --git a/a/1.txt b/N1/1.txt
index 93ba6d8..115cf0c 100644
--- a/a/1.txt
+++ b/N1/1.txt
@@ -2,7 +2,7 @@ F1C100s is one product with the suniv die, which has a 32MiB co-packaged
DDR1 DRAM chip. As we have the support for suniv pin controller and CCU now, add a
initial DTSI for it.
-Signed-off-by: Mesih Kilinc <mesihkilinc-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
+Signed-off-by: Mesih Kilinc <mesihkilinc@gmail.com>
---
arch/arm/boot/dts/suniv-f1c100s.dtsi | 147 +++++++++++++++++++++++++++++++++++
1 file changed, 147 insertions(+)
@@ -16,8 +16,8 @@ index 0000000..11bc999
@@ -0,0 +1,147 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR X11)
+/*
-+ * Copyright 2018 Icenowy Zheng <icenowy-h8G6r0blFSE@public.gmane.org>
-+ * Copyright 2018 Mesih Kilinc <mesihkilinc-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
++ * Copyright 2018 Icenowy Zheng <icenowy@aosc.io>
++ * Copyright 2018 Mesih Kilinc <mesihkilinc@gmail.com>
+ */
+
+#include <dt-bindings/clock/suniv-ccu-f1c100s.h>
diff --git a/a/content_digest b/N1/content_digest
index a9c832d..c6e404a 100644
--- a/a/content_digest
+++ b/N1/content_digest
@@ -2,10 +2,7 @@
"ref\0cover.1543131714.git.mesihkilinc\@gmail.com\0"
]
[
- "ref\0cover.1543131714.git.mesihkilinc-Re5JQEeQqe8AvxtiuMwx3w\@public.gmane.org\0"
-]
-[
- "From\0Mesih Kilinc <mesihkilinc-Re5JQEeQqe8AvxtiuMwx3w\@public.gmane.org>\0"
+ "From\0Mesih Kilinc <mesihkilinc\@gmail.com>\0"
]
[
"Subject\0[RFC PATCH v4 16/17] ARM: dts: suniv: add initial DTSI file for F1C100s\0"
@@ -14,24 +11,24 @@
"Date\0Sun, 25 Nov 2018 10:43:19 +0300\0"
]
[
- "To\0devicetree-u79uwXL29TY76Z2rM5mHXA\@public.gmane.org",
- " linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r\@public.gmane.org",
- " linux-kernel-u79uwXL29TY76Z2rM5mHXA\@public.gmane.org",
- " linux-clk-u79uwXL29TY76Z2rM5mHXA\@public.gmane.org",
- " linux-gpio-u79uwXL29TY76Z2rM5mHXA\@public.gmane.org",
- " linux-sunxi-/JYPxA39Uh5TLH3MbocFFw\@public.gmane.org\0"
+ "To\0devicetree\@vger.kernel.org",
+ " linux-arm-kernel\@lists.infradead.org",
+ " linux-kernel\@vger.kernel.org",
+ " linux-clk\@vger.kernel.org",
+ " linux-gpio\@vger.kernel.org",
+ " linux-sunxi\@googlegroups.com\0"
]
[
- "Cc\0Mesih Kilinc <mesihkilinc-Re5JQEeQqe8AvxtiuMwx3w\@public.gmane.org>",
- " Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8\@public.gmane.org>",
- " Chen-Yu Tsai <wens-jdAy2FN1RRM\@public.gmane.org>",
- " Russell King <linux-I+IVW8TIWO2tmTQ+vhA3Yw\@public.gmane.org>",
- " Daniel Lezcano <daniel.lezcano-QSEj5FYQhm4dnm+yROfE0A\@public.gmane.org>",
- " Marc Zyngier <marc.zyngier-5wv7dgnIgG8\@public.gmane.org>",
- " Linus Walleij <linus.walleij-QSEj5FYQhm4dnm+yROfE0A\@public.gmane.org>",
- " Icenowy Zheng <icenowy-h8G6r0blFSE\@public.gmane.org>",
- " Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A\@public.gmane.org>",
- " Julian Calaby <julian.calaby-Re5JQEeQqe8AvxtiuMwx3w\@public.gmane.org>\0"
+ "Cc\0Mesih Kilinc <mesihkilinc\@gmail.com>",
+ " Maxime Ripard <maxime.ripard\@free-electrons.com>",
+ " Chen-Yu Tsai <wens\@csie.org>",
+ " Russell King <linux\@armlinux.org.uk>",
+ " Daniel Lezcano <daniel.lezcano\@linaro.org>",
+ " Marc Zyngier <marc.zyngier\@arm.com>",
+ " Linus Walleij <linus.walleij\@linaro.org>",
+ " Icenowy Zheng <icenowy\@aosc.io>",
+ " Rob Herring <robh+dt\@kernel.org>",
+ " Julian Calaby <julian.calaby\@gmail.com>\0"
]
[
"\0000:1\0"
@@ -44,7 +41,7 @@
"DDR1 DRAM chip. As we have the support for suniv pin controller and CCU now, add a\n",
"initial DTSI for it.\n",
"\n",
- "Signed-off-by: Mesih Kilinc <mesihkilinc-Re5JQEeQqe8AvxtiuMwx3w\@public.gmane.org>\n",
+ "Signed-off-by: Mesih Kilinc <mesihkilinc\@gmail.com>\n",
"---\n",
" arch/arm/boot/dts/suniv-f1c100s.dtsi | 147 +++++++++++++++++++++++++++++++++++\n",
" 1 file changed, 147 insertions(+)\n",
@@ -58,8 +55,8 @@
"\@\@ -0,0 +1,147 \@\@\n",
"+// SPDX-License-Identifier: (GPL-2.0+ OR X11)\n",
"+/*\n",
- "+ * Copyright 2018 Icenowy Zheng <icenowy-h8G6r0blFSE\@public.gmane.org>\n",
- "+ * Copyright 2018 Mesih Kilinc <mesihkilinc-Re5JQEeQqe8AvxtiuMwx3w\@public.gmane.org>\n",
+ "+ * Copyright 2018 Icenowy Zheng <icenowy\@aosc.io>\n",
+ "+ * Copyright 2018 Mesih Kilinc <mesihkilinc\@gmail.com>\n",
"+ */\n",
"+\n",
"+#include <dt-bindings/clock/suniv-ccu-f1c100s.h>\n",
@@ -207,4 +204,4 @@
"2.7.4"
]
-ff3f0af5ec1fbf3332e7ade6729f6769835874a02235485e31ea28f36e586883
+ae3cb46359e13b3e9244a87805911ba42b2062448eacfaf8fac427f1c46906bb
diff --git a/a/1.txt b/N2/1.txt
index 93ba6d8..e2100cb 100644
--- a/a/1.txt
+++ b/N2/1.txt
@@ -2,7 +2,7 @@ F1C100s is one product with the suniv die, which has a 32MiB co-packaged
DDR1 DRAM chip. As we have the support for suniv pin controller and CCU now, add a
initial DTSI for it.
-Signed-off-by: Mesih Kilinc <mesihkilinc-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
+Signed-off-by: Mesih Kilinc <mesihkilinc@gmail.com>
---
arch/arm/boot/dts/suniv-f1c100s.dtsi | 147 +++++++++++++++++++++++++++++++++++
1 file changed, 147 insertions(+)
@@ -16,8 +16,8 @@ index 0000000..11bc999
@@ -0,0 +1,147 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR X11)
+/*
-+ * Copyright 2018 Icenowy Zheng <icenowy-h8G6r0blFSE@public.gmane.org>
-+ * Copyright 2018 Mesih Kilinc <mesihkilinc-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
++ * Copyright 2018 Icenowy Zheng <icenowy@aosc.io>
++ * Copyright 2018 Mesih Kilinc <mesihkilinc@gmail.com>
+ */
+
+#include <dt-bindings/clock/suniv-ccu-f1c100s.h>
@@ -57,7 +57,7 @@ index 0000000..11bc999
+ #size-cells = <1>;
+ ranges;
+
-+ sram-controller@1c00000 {
++ sram-controller at 1c00000 {
+ compatible = "allwinner,suniv-f1c100s-system-control",
+ "allwinner,sun4i-a10-system-control";
+ reg = <0x01c00000 0x30>;
@@ -65,14 +65,14 @@ index 0000000..11bc999
+ #size-cells = <1>;
+ ranges;
+
-+ sram_d: sram@10000 {
++ sram_d: sram at 10000 {
+ compatible = "mmio-sram";
+ reg = <0x00010000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x00010000 0x1000>;
+
-+ otg_sram: sram-section@0 {
++ otg_sram: sram-section at 0 {
+ compatible = "allwinner,suniv-f1c100s-sram-d",
+ "allwinner,sun4i-a10-sram-d";
+ reg = <0x0000 0x1000>;
@@ -81,7 +81,7 @@ index 0000000..11bc999
+ };
+ };
+
-+ ccu: clock@1c20000 {
++ ccu: clock at 1c20000 {
+ compatible = "allwinner,suniv-f1c100s-ccu";
+ reg = <0x01c20000 0x400>;
+ clocks = <&osc24M>, <&osc32k>;
@@ -90,14 +90,14 @@ index 0000000..11bc999
+ #reset-cells = <1>;
+ };
+
-+ intc: interrupt-controller@1c20400 {
++ intc: interrupt-controller at 1c20400 {
+ compatible = "allwinner,suniv-f1c100s-ic";
+ reg = <0x01c20400 0x400>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
-+ pio: pinctrl@1c20800 {
++ pio: pinctrl at 1c20800 {
+ compatible = "allwinner,suniv-f1c100s-pinctrl";
+ reg = <0x01c20800 0x400>;
+ interrupts = <38>, <39>, <40>;
@@ -114,20 +114,20 @@ index 0000000..11bc999
+ };
+ };
+
-+ timer@1c20c00 {
++ timer at 1c20c00 {
+ compatible = "allwinner,suniv-f1c100s-timer";
+ reg = <0x01c20c00 0x90>;
+ interrupts = <13>;
+ clocks = <&osc24M>;
+ };
+
-+ wdt: watchdog@1c20ca0 {
++ wdt: watchdog at 1c20ca0 {
+ compatible = "allwinner,suniv-f1c100s-wdt",
+ "allwinner,sun4i-a10-wdt";
+ reg = <0x01c20ca0 0x20>;
+ };
+
-+ uart0: serial@1c25000 {
++ uart0: serial at 1c25000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c25000 0x400>;
+ interrupts = <1>;
@@ -138,7 +138,7 @@ index 0000000..11bc999
+ status = "disabled";
+ };
+
-+ uart1: serial@1c25400 {
++ uart1: serial at 1c25400 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c25400 0x400>;
+ interrupts = <2>;
@@ -149,7 +149,7 @@ index 0000000..11bc999
+ status = "disabled";
+ };
+
-+ uart2: serial@1c25800 {
++ uart2: serial at 1c25800 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c25800 0x400>;
+ interrupts = <3>;
diff --git a/a/content_digest b/N2/content_digest
index a9c832d..8bf61f7 100644
--- a/a/content_digest
+++ b/N2/content_digest
@@ -2,10 +2,7 @@
"ref\0cover.1543131714.git.mesihkilinc\@gmail.com\0"
]
[
- "ref\0cover.1543131714.git.mesihkilinc-Re5JQEeQqe8AvxtiuMwx3w\@public.gmane.org\0"
-]
-[
- "From\0Mesih Kilinc <mesihkilinc-Re5JQEeQqe8AvxtiuMwx3w\@public.gmane.org>\0"
+ "From\0mesihkilinc\@gmail.com (Mesih Kilinc)\0"
]
[
"Subject\0[RFC PATCH v4 16/17] ARM: dts: suniv: add initial DTSI file for F1C100s\0"
@@ -14,24 +11,7 @@
"Date\0Sun, 25 Nov 2018 10:43:19 +0300\0"
]
[
- "To\0devicetree-u79uwXL29TY76Z2rM5mHXA\@public.gmane.org",
- " linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r\@public.gmane.org",
- " linux-kernel-u79uwXL29TY76Z2rM5mHXA\@public.gmane.org",
- " linux-clk-u79uwXL29TY76Z2rM5mHXA\@public.gmane.org",
- " linux-gpio-u79uwXL29TY76Z2rM5mHXA\@public.gmane.org",
- " linux-sunxi-/JYPxA39Uh5TLH3MbocFFw\@public.gmane.org\0"
-]
-[
- "Cc\0Mesih Kilinc <mesihkilinc-Re5JQEeQqe8AvxtiuMwx3w\@public.gmane.org>",
- " Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8\@public.gmane.org>",
- " Chen-Yu Tsai <wens-jdAy2FN1RRM\@public.gmane.org>",
- " Russell King <linux-I+IVW8TIWO2tmTQ+vhA3Yw\@public.gmane.org>",
- " Daniel Lezcano <daniel.lezcano-QSEj5FYQhm4dnm+yROfE0A\@public.gmane.org>",
- " Marc Zyngier <marc.zyngier-5wv7dgnIgG8\@public.gmane.org>",
- " Linus Walleij <linus.walleij-QSEj5FYQhm4dnm+yROfE0A\@public.gmane.org>",
- " Icenowy Zheng <icenowy-h8G6r0blFSE\@public.gmane.org>",
- " Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A\@public.gmane.org>",
- " Julian Calaby <julian.calaby-Re5JQEeQqe8AvxtiuMwx3w\@public.gmane.org>\0"
+ "To\0linux-arm-kernel\@lists.infradead.org\0"
]
[
"\0000:1\0"
@@ -44,7 +24,7 @@
"DDR1 DRAM chip. As we have the support for suniv pin controller and CCU now, add a\n",
"initial DTSI for it.\n",
"\n",
- "Signed-off-by: Mesih Kilinc <mesihkilinc-Re5JQEeQqe8AvxtiuMwx3w\@public.gmane.org>\n",
+ "Signed-off-by: Mesih Kilinc <mesihkilinc\@gmail.com>\n",
"---\n",
" arch/arm/boot/dts/suniv-f1c100s.dtsi | 147 +++++++++++++++++++++++++++++++++++\n",
" 1 file changed, 147 insertions(+)\n",
@@ -58,8 +38,8 @@
"\@\@ -0,0 +1,147 \@\@\n",
"+// SPDX-License-Identifier: (GPL-2.0+ OR X11)\n",
"+/*\n",
- "+ * Copyright 2018 Icenowy Zheng <icenowy-h8G6r0blFSE\@public.gmane.org>\n",
- "+ * Copyright 2018 Mesih Kilinc <mesihkilinc-Re5JQEeQqe8AvxtiuMwx3w\@public.gmane.org>\n",
+ "+ * Copyright 2018 Icenowy Zheng <icenowy\@aosc.io>\n",
+ "+ * Copyright 2018 Mesih Kilinc <mesihkilinc\@gmail.com>\n",
"+ */\n",
"+\n",
"+#include <dt-bindings/clock/suniv-ccu-f1c100s.h>\n",
@@ -99,7 +79,7 @@
"+\t\t#size-cells = <1>;\n",
"+\t\tranges;\n",
"+\n",
- "+\t\tsram-controller\@1c00000 {\n",
+ "+\t\tsram-controller at 1c00000 {\n",
"+\t\t\tcompatible = \"allwinner,suniv-f1c100s-system-control\",\n",
"+\t\t\t\t \"allwinner,sun4i-a10-system-control\";\n",
"+\t\t\treg = <0x01c00000 0x30>;\n",
@@ -107,14 +87,14 @@
"+\t\t\t#size-cells = <1>;\n",
"+\t\t\tranges;\n",
"+\n",
- "+\t\t\tsram_d: sram\@10000 {\n",
+ "+\t\t\tsram_d: sram at 10000 {\n",
"+\t\t\t\tcompatible = \"mmio-sram\";\n",
"+\t\t\t\treg = <0x00010000 0x1000>;\n",
"+\t\t\t\t#address-cells = <1>;\n",
"+\t\t\t\t#size-cells = <1>;\n",
"+\t\t\t\tranges = <0 0x00010000 0x1000>;\n",
"+\n",
- "+\t\t\t\totg_sram: sram-section\@0 {\n",
+ "+\t\t\t\totg_sram: sram-section at 0 {\n",
"+\t\t\t\t\tcompatible = \"allwinner,suniv-f1c100s-sram-d\",\n",
"+\t\t\t\t\t\t \"allwinner,sun4i-a10-sram-d\";\n",
"+\t\t\t\t\treg = <0x0000 0x1000>;\n",
@@ -123,7 +103,7 @@
"+\t\t\t};\n",
"+\t\t};\n",
"+\n",
- "+\t\tccu: clock\@1c20000 {\n",
+ "+\t\tccu: clock at 1c20000 {\n",
"+\t\t\tcompatible = \"allwinner,suniv-f1c100s-ccu\";\n",
"+\t\t\treg = <0x01c20000 0x400>;\n",
"+\t\t\tclocks = <&osc24M>, <&osc32k>;\n",
@@ -132,14 +112,14 @@
"+\t\t\t#reset-cells = <1>;\n",
"+\t\t};\n",
"+\n",
- "+\t\tintc: interrupt-controller\@1c20400 {\n",
+ "+\t\tintc: interrupt-controller at 1c20400 {\n",
"+\t\t\tcompatible = \"allwinner,suniv-f1c100s-ic\";\n",
"+\t\t\treg = <0x01c20400 0x400>;\n",
"+\t\t\tinterrupt-controller;\n",
"+\t\t\t#interrupt-cells = <1>;\n",
"+\t\t};\n",
"+\n",
- "+\t\tpio: pinctrl\@1c20800 {\n",
+ "+\t\tpio: pinctrl at 1c20800 {\n",
"+\t\t\tcompatible = \"allwinner,suniv-f1c100s-pinctrl\";\n",
"+\t\t\treg = <0x01c20800 0x400>;\n",
"+\t\t\tinterrupts = <38>, <39>, <40>;\n",
@@ -156,20 +136,20 @@
"+\t\t\t};\n",
"+\t\t};\n",
"+\n",
- "+\t\ttimer\@1c20c00 {\n",
+ "+\t\ttimer at 1c20c00 {\n",
"+\t\t\tcompatible = \"allwinner,suniv-f1c100s-timer\";\n",
"+\t\t\treg = <0x01c20c00 0x90>;\n",
"+\t\t\tinterrupts = <13>;\n",
"+\t\t\tclocks = <&osc24M>;\n",
"+\t\t};\n",
"+\n",
- "+\t\twdt: watchdog\@1c20ca0 {\n",
+ "+\t\twdt: watchdog at 1c20ca0 {\n",
"+\t\t\tcompatible = \"allwinner,suniv-f1c100s-wdt\",\n",
"+\t\t\t\t \"allwinner,sun4i-a10-wdt\";\n",
"+\t\t\treg = <0x01c20ca0 0x20>;\n",
"+\t\t};\n",
"+\n",
- "+\t\tuart0: serial\@1c25000 {\n",
+ "+\t\tuart0: serial at 1c25000 {\n",
"+\t\t\tcompatible = \"snps,dw-apb-uart\";\n",
"+\t\t\treg = <0x01c25000 0x400>;\n",
"+\t\t\tinterrupts = <1>;\n",
@@ -180,7 +160,7 @@
"+\t\t\tstatus = \"disabled\";\n",
"+\t\t};\n",
"+\n",
- "+\t\tuart1: serial\@1c25400 {\n",
+ "+\t\tuart1: serial at 1c25400 {\n",
"+\t\t\tcompatible = \"snps,dw-apb-uart\";\n",
"+\t\t\treg = <0x01c25400 0x400>;\n",
"+\t\t\tinterrupts = <2>;\n",
@@ -191,7 +171,7 @@
"+\t\t\tstatus = \"disabled\";\n",
"+\t\t};\n",
"+\n",
- "+\t\tuart2: serial\@1c25800 {\n",
+ "+\t\tuart2: serial at 1c25800 {\n",
"+\t\t\tcompatible = \"snps,dw-apb-uart\";\n",
"+\t\t\treg = <0x01c25800 0x400>;\n",
"+\t\t\tinterrupts = <3>;\n",
@@ -207,4 +187,4 @@
"2.7.4"
]
-ff3f0af5ec1fbf3332e7ade6729f6769835874a02235485e31ea28f36e586883
+a345f1e8f76c4dacebe2d8663a69c222cd740463dcef0e996370c8044f9b446e
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