From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.2 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 515FEC2BD09 for ; Wed, 4 Dec 2019 15:56:02 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 27751206DB for ; Wed, 4 Dec 2019 15:56:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728354AbfLDP4B (ORCPT ); Wed, 4 Dec 2019 10:56:01 -0500 Received: from foss.arm.com ([217.140.110.172]:57720 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727828AbfLDP4B (ORCPT ); Wed, 4 Dec 2019 10:56:01 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 1BC9E31B; Wed, 4 Dec 2019 07:56:00 -0800 (PST) Received: from [10.1.196.37] (e121345-lin.cambridge.arm.com [10.1.196.37]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id A0FE53F52E; Wed, 4 Dec 2019 07:55:58 -0800 (PST) Subject: Re: [PATCH v2 1/8] dt-bindings: arm-smmu: Add Adreno GPU variant To: Jordan Crouse , iommu@lists.linux-foundation.org Cc: will@kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Herring , Mark Rutland , Joerg Roedel References: <1574465484-7115-1-git-send-email-jcrouse@codeaurora.org> <0101016e95751c0b-33c9379b-6b8c-43b1-8785-e5e1b6f084f1-000000@us-west-2.amazonses.com> From: Robin Murphy Message-ID: <3a283a7c-df75-a30a-1bcb-74e631f06a71@arm.com> Date: Wed, 4 Dec 2019 15:55:57 +0000 User-Agent: Mozilla/5.0 (X11; Linux aarch64; rv:60.0) Gecko/20100101 Thunderbird/60.9.0 MIME-Version: 1.0 In-Reply-To: <0101016e95751c0b-33c9379b-6b8c-43b1-8785-e5e1b6f084f1-000000@us-west-2.amazonses.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-GB Content-Transfer-Encoding: 7bit Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On 22/11/2019 11:31 pm, Jordan Crouse wrote: > Add a compatible string to identify SMMUs that are attached > to Adreno GPU devices that wish to support split pagetables. A software policy decision is not, in itself, a good justification for a DT property. Is the GPU SMMU fundamentally different in hardware* from the other SMMU(s) in any given SoC? (* where "hardware" may encompass hypervisor shenanigans) > Signed-off-by: Jordan Crouse > --- > > Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml > index 6515dbe..db9f826 100644 > --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml > +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml > @@ -31,6 +31,12 @@ properties: > - qcom,sdm845-smmu-v2 > - const: qcom,smmu-v2 > > + - description: Qcom Adreno GPU SMMU iplementing split pagetables > + items: > + - enum: > + - qcom,adreno-smmu-v2 > + - const: qcom,smmu-v2 Given that we already have per-SoC compatibles for Qcom SMMUs in general, this seems suspiciously vague. Robin. > + > - description: Qcom SoCs implementing "arm,mmu-500" > items: > - enum: > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.2 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3CC45C2BD09 for ; Wed, 4 Dec 2019 15:56:06 +0000 (UTC) Received: from silver.osuosl.org (smtp3.osuosl.org [140.211.166.136]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 079C3206DB for ; Wed, 4 Dec 2019 15:56:05 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 079C3206DB Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=iommu-bounces@lists.linux-foundation.org Received: from localhost (localhost [127.0.0.1]) by silver.osuosl.org (Postfix) with ESMTP id C3F37203A8; Wed, 4 Dec 2019 15:56:05 +0000 (UTC) X-Virus-Scanned: amavisd-new at osuosl.org Received: from silver.osuosl.org ([127.0.0.1]) by localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id OiYK+hcOeQnM; Wed, 4 Dec 2019 15:56:04 +0000 (UTC) Received: from lists.linuxfoundation.org (lf-lists.osuosl.org [140.211.9.56]) by silver.osuosl.org (Postfix) with ESMTP id 9E715230F6; Wed, 4 Dec 2019 15:56:04 +0000 (UTC) Received: from lf-lists.osuosl.org (localhost [127.0.0.1]) by lists.linuxfoundation.org (Postfix) with ESMTP id 9122AC18DD; Wed, 4 Dec 2019 15:56:04 +0000 (UTC) Received: from silver.osuosl.org (smtp3.osuosl.org [140.211.166.136]) by lists.linuxfoundation.org (Postfix) with ESMTP id 41ED3C077D for ; Wed, 4 Dec 2019 15:56:02 +0000 (UTC) Received: from localhost (localhost [127.0.0.1]) by silver.osuosl.org (Postfix) with ESMTP id 3CF5722FF0 for ; Wed, 4 Dec 2019 15:56:02 +0000 (UTC) X-Virus-Scanned: amavisd-new at osuosl.org Received: from silver.osuosl.org ([127.0.0.1]) by localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id jecm3yggH7Xz for ; Wed, 4 Dec 2019 15:56:01 +0000 (UTC) X-Greylist: domain auto-whitelisted by SQLgrey-1.7.6 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by silver.osuosl.org (Postfix) with ESMTP id 0EDD2203A8 for ; Wed, 4 Dec 2019 15:56:00 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 1BC9E31B; Wed, 4 Dec 2019 07:56:00 -0800 (PST) Received: from [10.1.196.37] (e121345-lin.cambridge.arm.com [10.1.196.37]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id A0FE53F52E; Wed, 4 Dec 2019 07:55:58 -0800 (PST) Subject: Re: [PATCH v2 1/8] dt-bindings: arm-smmu: Add Adreno GPU variant To: Jordan Crouse , iommu@lists.linux-foundation.org References: <1574465484-7115-1-git-send-email-jcrouse@codeaurora.org> <0101016e95751c0b-33c9379b-6b8c-43b1-8785-e5e1b6f084f1-000000@us-west-2.amazonses.com> From: Robin Murphy Message-ID: <3a283a7c-df75-a30a-1bcb-74e631f06a71@arm.com> Date: Wed, 4 Dec 2019 15:55:57 +0000 User-Agent: Mozilla/5.0 (X11; Linux aarch64; rv:60.0) Gecko/20100101 Thunderbird/60.9.0 MIME-Version: 1.0 In-Reply-To: <0101016e95751c0b-33c9379b-6b8c-43b1-8785-e5e1b6f084f1-000000@us-west-2.amazonses.com> Content-Language: en-GB Cc: Mark Rutland , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Herring , will@kernel.org, linux-arm-kernel@lists.infradead.org X-BeenThere: iommu@lists.linux-foundation.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Development issues for Linux IOMMU support List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Errors-To: iommu-bounces@lists.linux-foundation.org Sender: "iommu" On 22/11/2019 11:31 pm, Jordan Crouse wrote: > Add a compatible string to identify SMMUs that are attached > to Adreno GPU devices that wish to support split pagetables. A software policy decision is not, in itself, a good justification for a DT property. Is the GPU SMMU fundamentally different in hardware* from the other SMMU(s) in any given SoC? (* where "hardware" may encompass hypervisor shenanigans) > Signed-off-by: Jordan Crouse > --- > > Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml > index 6515dbe..db9f826 100644 > --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml > +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml > @@ -31,6 +31,12 @@ properties: > - qcom,sdm845-smmu-v2 > - const: qcom,smmu-v2 > > + - description: Qcom Adreno GPU SMMU iplementing split pagetables > + items: > + - enum: > + - qcom,adreno-smmu-v2 > + - const: qcom,smmu-v2 Given that we already have per-SoC compatibles for Qcom SMMUs in general, this seems suspiciously vague. Robin. > + > - description: Qcom SoCs implementing "arm,mmu-500" > items: > - enum: > _______________________________________________ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.2 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8D0B8C43603 for ; Wed, 4 Dec 2019 15:56:07 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 5B2CB206DB for ; Wed, 4 Dec 2019 15:56:07 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="t6+cZTIz" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 5B2CB206DB Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender:Content-Type: Content-Transfer-Encoding:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:Date:Message-ID:From: References:To:Subject:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=o0t8kSW6e5zvK4PcyvSzd6Ju9w5UURIdKLnwP+5+Bhg=; b=t6+cZTIzdvUd2PRyjN4fd9zbl uNlZddvOtpzzqX2cMTirfuX30AwzG8mcny6aW7IMWQtIaG7hhgyewqj1KI9kwnWvHnHTV1vDABNh6 PjKgsuqAmsLpK3UIPWXR7fpH/7ilBD7xxfF0AKVRp93WYlUJrIbywSKJTrHJOto13cKS73nnsxbf2 LBjPBm5A+PYcU8O+7eoLd3ypk46IXRcmDsHKBg1kTn65u1WFz7T2lrClRERgDA42iGw27fUFEpbPR /VAKVGtLQYnruVQb9XAP5fwhmOdAiDCy4ix4+QZRitpVwXLw6LAvl3VQrWnUHhOPWt95n0TvWPj/3 wm1aU9gwQ==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1icX0Z-0006hX-00; Wed, 04 Dec 2019 15:56:07 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1icX0V-0006go-IZ for linux-arm-kernel@lists.infradead.org; Wed, 04 Dec 2019 15:56:04 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 1BC9E31B; Wed, 4 Dec 2019 07:56:00 -0800 (PST) Received: from [10.1.196.37] (e121345-lin.cambridge.arm.com [10.1.196.37]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id A0FE53F52E; Wed, 4 Dec 2019 07:55:58 -0800 (PST) Subject: Re: [PATCH v2 1/8] dt-bindings: arm-smmu: Add Adreno GPU variant To: Jordan Crouse , iommu@lists.linux-foundation.org References: <1574465484-7115-1-git-send-email-jcrouse@codeaurora.org> <0101016e95751c0b-33c9379b-6b8c-43b1-8785-e5e1b6f084f1-000000@us-west-2.amazonses.com> From: Robin Murphy Message-ID: <3a283a7c-df75-a30a-1bcb-74e631f06a71@arm.com> Date: Wed, 4 Dec 2019 15:55:57 +0000 User-Agent: Mozilla/5.0 (X11; Linux aarch64; rv:60.0) Gecko/20100101 Thunderbird/60.9.0 MIME-Version: 1.0 In-Reply-To: <0101016e95751c0b-33c9379b-6b8c-43b1-8785-e5e1b6f084f1-000000@us-west-2.amazonses.com> Content-Language: en-GB X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191204_075603_656831_CBEC3E72 X-CRM114-Status: GOOD ( 15.06 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, Joerg Roedel , linux-kernel@vger.kernel.org, Rob Herring , will@kernel.org, linux-arm-kernel@lists.infradead.org Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 22/11/2019 11:31 pm, Jordan Crouse wrote: > Add a compatible string to identify SMMUs that are attached > to Adreno GPU devices that wish to support split pagetables. A software policy decision is not, in itself, a good justification for a DT property. Is the GPU SMMU fundamentally different in hardware* from the other SMMU(s) in any given SoC? (* where "hardware" may encompass hypervisor shenanigans) > Signed-off-by: Jordan Crouse > --- > > Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml > index 6515dbe..db9f826 100644 > --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml > +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml > @@ -31,6 +31,12 @@ properties: > - qcom,sdm845-smmu-v2 > - const: qcom,smmu-v2 > > + - description: Qcom Adreno GPU SMMU iplementing split pagetables > + items: > + - enum: > + - qcom,adreno-smmu-v2 > + - const: qcom,smmu-v2 Given that we already have per-SoC compatibles for Qcom SMMUs in general, this seems suspiciously vague. Robin. > + > - description: Qcom SoCs implementing "arm,mmu-500" > items: > - enum: > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel