From: "Souza, Jose" <jose.souza@intel.com>
To: "ville.syrjala@linux.intel.com" <ville.syrjala@linux.intel.com>
Cc: "intel-gfx@lists.freedesktop.org"
<intel-gfx@lists.freedesktop.org>,
"De Marchi, Lucas" <lucas.demarchi@intel.com>,
"Pandiyan, Dhinakaran" <dhinakaran.pandiyan@intel.com>
Subject: Re: [Intel-gfx] [PATCH 2/2] drm/i915/dgfx: Do not write in removed FBC fence registers
Date: Tue, 4 Feb 2020 02:06:23 +0000 [thread overview]
Message-ID: <3ab6b8071f4af31d0c6059748c6b5c54bfabd587.camel@intel.com> (raw)
In-Reply-To: <20200129114257.GR13686@intel.com>
On Wed, 2020-01-29 at 13:42 +0200, Ville Syrjälä wrote:
> On Tue, Jan 28, 2020 at 03:52:41PM -0800, José Roberto de Souza
> wrote:
> > From: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> >
> > dgfx platforms do not support CPU fence and FBC host tracking so
> > lets avoid write to removed registers.
> >
> > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > Cc: Matt Roper <matthew.d.roper@intel.com>
> > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> > Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com
> > >
> > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_fbc.c | 7 ++++++-
> > 1 file changed, 6 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
> > b/drivers/gpu/drm/i915/display/intel_fbc.c
> > index 1f0d24a1dec1..12900b8ce28e 100644
> > --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> > +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> > @@ -314,7 +314,12 @@ static void gen7_fbc_activate(struct
> > drm_i915_private *dev_priv)
> > break;
> > }
> >
> > - if (params->fence_id >= 0) {
> > + if (IS_DGFX(dev_priv)) {
> > + /*
> > + * dGFX GPUs don't have apperture or fences and only
> > rely on FBC
> > + * render nuke to track frontbuffer modifications
> > + */
> > + } else if (params->fence_id >= 0) {
> > dpfc_ctl |= IVB_DPFC_CTL_FENCE_EN;
> > intel_de_write(dev_priv, SNB_DPFC_CTL_SA,
> > SNB_CPU_FENCE_ENABLE | params-
> > >fence_id);
>
> if (fence) {
> do stuff
> } else if (num_fences) {
> do other stuff
> }
Did not get what you want here.
It is covering all cases:
- DGFX that don't have the registers
- Setting the registers when fence_id >= 0
- Clearing the register when fences_id == -1
>
> > --
> > 2.25.0
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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next prev parent reply other threads:[~2020-02-04 2:06 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-01-28 23:52 [Intel-gfx] [PATCH 1/2] drm/i915/display/fbc: Make fences a nice-to-have for GEN9+ José Roberto de Souza
2020-01-28 23:52 ` [Intel-gfx] [PATCH 2/2] drm/i915/dgfx: Do not write in removed FBC fence registers José Roberto de Souza
2020-01-29 11:42 ` Ville Syrjälä
2020-02-04 2:06 ` Souza, Jose [this message]
2020-02-04 13:47 ` Ville Syrjälä
2020-01-29 3:19 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915/display/fbc: Make fences a nice-to-have for GEN9+ Patchwork
2020-01-29 11:44 ` [Intel-gfx] [PATCH 1/2] " Ville Syrjälä
2020-01-29 11:58 ` Ville Syrjälä
2020-02-04 1:42 ` Souza, Jose
2020-01-30 2:44 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915/display/fbc: Make fences a nice-to-have for GEN9+ (rev2) Patchwork
2020-02-04 20:58 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/display/fbc: Make fences a nice-to-have for GEN9+ (rev3) Patchwork
2020-02-06 20:29 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
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