From: Richard Henderson <richard.henderson@linaro.org>
To: LIU Zhiwei <zhiwei_liu@c-sky.com>, qemu-devel@nongnu.org
Subject: Re: [PATCH 0/5] tcg: Add 32-bit vector operations
Date: Fri, 25 Jun 2021 20:53:50 -0700 [thread overview]
Message-ID: <3b2d25af-1c32-716d-1d43-73d007d963ba@linaro.org> (raw)
In-Reply-To: <20210624105023.3852-1-zhiwei_liu@c-sky.com>
On 6/24/21 3:50 AM, LIU Zhiwei wrote:
> This patch set is split from RISC-V Packed extension where needs
> some i32 vector operations, accorind to Richard Henderson's suggestion.
>
> The original implementation is on
> https://www.mail-archive.com/qemu-devel@nongnu.org/msg814538.html.
>
> LIU Zhiwei (5):
> tcg: Add tcg_gen_vec_add{sub}16_i32
> tcg: Add tcg_gen_vec_add{sub}8_i32
> tcg: Add tcg_gen_vec_shl{shr}{sar}16i_i32
> tcg: Add tcg_gen_vec_shl{shr}{sar}8i_i32
> tcg: Implement tcg_gen_vec_add{sub}32_tl
>
> include/tcg/tcg-op-gvec.h | 43 ++++++++++++++
> tcg/tcg-op-gvec.c | 122 ++++++++++++++++++++++++++++++++++++++
> 2 files changed, 165 insertions(+)
>
Queued to tcg-next, thanks.
r~
prev parent reply other threads:[~2021-06-26 3:54 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-24 10:50 [PATCH 0/5] tcg: Add 32-bit vector operations LIU Zhiwei
2021-06-24 10:50 ` [PATCH 1/5] tcg: Add tcg_gen_vec_add{sub}16_i32 LIU Zhiwei
2021-06-24 10:50 ` [PATCH 2/5] tcg: Add tcg_gen_vec_add{sub}8_i32 LIU Zhiwei
2021-06-24 10:50 ` [PATCH 3/5] tcg: Add tcg_gen_vec_shl{shr}{sar}16i_i32 LIU Zhiwei
2021-06-24 10:50 ` [PATCH 4/5] tcg: Add tcg_gen_vec_shl{shr}{sar}8i_i32 LIU Zhiwei
2021-06-24 10:50 ` [PATCH 5/5] tcg: Implement tcg_gen_vec_add{sub}32_tl LIU Zhiwei
2021-06-26 3:53 ` Richard Henderson [this message]
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