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[83.51.162.1]) by smtp.gmail.com with ESMTPSA id y77sm4730301wmd.36.2020.07.03.15.27.43 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 03 Jul 2020 15:27:44 -0700 (PDT) Subject: Re: [PATCH v3 05/12] hw/arm: Add NPCM730 and NPCM750 SoC models To: Havard Skinnemoen References: <20200626235519.591734-1-hskinnemoen@google.com> <20200626235519.591734-6-hskinnemoen@google.com> <001d2d27-dfe2-b03b-9996-ca69ba81a542@amsat.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <3b35fff3-6b4c-42ef-5a3a-0f67eb055fb2@amsat.org> Date: Sat, 4 Jul 2020 00:27:43 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.5.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::442; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x442.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: 0 X-Spam_score: 0.0 X-Spam_bar: / X-Spam_report: (0.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=1, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , QEMU Developers , Joel Stanley , CS20 KFTing , qemu-arm , =?UTF-8?Q?C=c3=a9dric_Le_Goate?= =?UTF-8?Q?r?= , IS20 Avi Fishman Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 7/3/20 10:56 PM, Havard Skinnemoen wrote: > On Fri, Jul 3, 2020 at 6:32 AM Philippe Mathieu-Daudé wrote: >> >> On 6/27/20 1:55 AM, Havard Skinnemoen wrote: >>> +/* >>> + * This covers the whole MMIO space. We'll use this to catch any MMIO accesses >>> + * that aren't handled by any device. >>> + */ >>> +#define NPCM7XX_MMIO_BA (0x80000000) >>> +#define NPCM7XX_MMIO_SZ (0x7FFD0000) >> >> Could be 0x80000000 since UNIMP_DEVICE is created with low >> priority. > > Good point, I'll do that. > >>> + /* I/O space -- unimplemented unless overridden below. */ >>> + create_unimplemented_device("npcm7xx.io", NPCM7XX_MMIO_BA, NPCM7XX_MMIO_SZ); >> >> Note by doing that you won't get transaction failures when accessing >> unassigned regions. This not incorrect, but a bit overkill (this covers >> almost 2GiB...). > > A lot of that 2GiB space is used by six 128 MiB flash memory > apertures. But there are some holes that probably should generate > transaction failures instead of a default response. See commit 529fc5fd3e ("hw/arm: Add the STM32F4xx SoC") for the recommended verbose way. > > Would it be OK if I send a patch to tighten up the unimplemented space > once a few more of the peripherals have been implemented? Fine by me, this is not a blocker. Joel reviewed your patch anyway, I trust him :) Regards, Phil.