* [PATCH for-6.2 01/43] hw/core: Make do_unaligned_access available to user-only
2021-07-29 0:46 [PATCH for-6.2 00/43] Unaligned accesses for user-only Richard Henderson
@ 2021-07-29 0:46 ` Richard Henderson
2021-07-29 6:14 ` Philippe Mathieu-Daudé
` (2 more replies)
2021-07-29 0:46 ` [PATCH for-6.2 02/43] target/alpha: Implement do_unaligned_access for user-only Richard Henderson
` (43 subsequent siblings)
44 siblings, 3 replies; 102+ messages in thread
From: Richard Henderson @ 2021-07-29 0:46 UTC (permalink / raw)
To: qemu-devel
We shouldn't be ignoring SIGBUS for user-only.
Move our existing TCGCPUOps hook out from CONFIG_SOFTMMU.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/hw/core/tcg-cpu-ops.h | 14 +++++++-------
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h
index eab27d0c03..513d6bfe72 100644
--- a/include/hw/core/tcg-cpu-ops.h
+++ b/include/hw/core/tcg-cpu-ops.h
@@ -60,6 +60,13 @@ struct TCGCPUOps {
/** @debug_excp_handler: Callback for handling debug exceptions */
void (*debug_excp_handler)(CPUState *cpu);
+ /**
+ * @do_unaligned_access: Callback for unaligned access handling
+ */
+ void (*do_unaligned_access)(CPUState *cpu, vaddr addr,
+ MMUAccessType access_type,
+ int mmu_idx, uintptr_t retaddr);
+
#ifdef NEED_CPU_H
#ifdef CONFIG_SOFTMMU
/**
@@ -70,13 +77,6 @@ struct TCGCPUOps {
unsigned size, MMUAccessType access_type,
int mmu_idx, MemTxAttrs attrs,
MemTxResult response, uintptr_t retaddr);
- /**
- * @do_unaligned_access: Callback for unaligned access handling
- */
- void (*do_unaligned_access)(CPUState *cpu, vaddr addr,
- MMUAccessType access_type,
- int mmu_idx, uintptr_t retaddr);
-
/**
* @adjust_watchpoint_address: hack for cpu_check_watchpoint used by ARM
*/
--
2.25.1
^ permalink raw reply related [flat|nested] 102+ messages in thread* Re: [PATCH for-6.2 01/43] hw/core: Make do_unaligned_access available to user-only
2021-07-29 0:46 ` [PATCH for-6.2 01/43] hw/core: Make do_unaligned_access available to user-only Richard Henderson
@ 2021-07-29 6:14 ` Philippe Mathieu-Daudé
2021-07-29 6:19 ` Philippe Mathieu-Daudé
2021-07-29 13:05 ` Peter Maydell
2 siblings, 0 replies; 102+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-07-29 6:14 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
On 7/29/21 2:46 AM, Richard Henderson wrote:
> We shouldn't be ignoring SIGBUS for user-only.
> Move our existing TCGCPUOps hook out from CONFIG_SOFTMMU.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> include/hw/core/tcg-cpu-ops.h | 14 +++++++-------
> 1 file changed, 7 insertions(+), 7 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
^ permalink raw reply [flat|nested] 102+ messages in thread
* Re: [PATCH for-6.2 01/43] hw/core: Make do_unaligned_access available to user-only
2021-07-29 0:46 ` [PATCH for-6.2 01/43] hw/core: Make do_unaligned_access available to user-only Richard Henderson
2021-07-29 6:14 ` Philippe Mathieu-Daudé
@ 2021-07-29 6:19 ` Philippe Mathieu-Daudé
2021-07-29 17:51 ` Richard Henderson
2021-07-29 13:05 ` Peter Maydell
2 siblings, 1 reply; 102+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-07-29 6:19 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
On 7/29/21 2:46 AM, Richard Henderson wrote:
> We shouldn't be ignoring SIGBUS for user-only.
> Move our existing TCGCPUOps hook out from CONFIG_SOFTMMU.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> include/hw/core/tcg-cpu-ops.h | 14 +++++++-------
> 1 file changed, 7 insertions(+), 7 deletions(-)
>
> diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h
> index eab27d0c03..513d6bfe72 100644
> --- a/include/hw/core/tcg-cpu-ops.h
> +++ b/include/hw/core/tcg-cpu-ops.h
> @@ -60,6 +60,13 @@ struct TCGCPUOps {
> /** @debug_excp_handler: Callback for handling debug exceptions */
> void (*debug_excp_handler)(CPUState *cpu);
>
> + /**
> + * @do_unaligned_access: Callback for unaligned access handling
> + */
> + void (*do_unaligned_access)(CPUState *cpu, vaddr addr,
> + MMUAccessType access_type,
> + int mmu_idx, uintptr_t retaddr);
Shouldn't it be QEMU_NORETURN?
^ permalink raw reply [flat|nested] 102+ messages in thread* Re: [PATCH for-6.2 01/43] hw/core: Make do_unaligned_access available to user-only
2021-07-29 6:19 ` Philippe Mathieu-Daudé
@ 2021-07-29 17:51 ` Richard Henderson
0 siblings, 0 replies; 102+ messages in thread
From: Richard Henderson @ 2021-07-29 17:51 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
On 7/28/21 8:19 PM, Philippe Mathieu-Daudé wrote:
> On 7/29/21 2:46 AM, Richard Henderson wrote:
>> We shouldn't be ignoring SIGBUS for user-only.
>> Move our existing TCGCPUOps hook out from CONFIG_SOFTMMU.
>>
>> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
>> ---
>> include/hw/core/tcg-cpu-ops.h | 14 +++++++-------
>> 1 file changed, 7 insertions(+), 7 deletions(-)
>>
>> diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h
>> index eab27d0c03..513d6bfe72 100644
>> --- a/include/hw/core/tcg-cpu-ops.h
>> +++ b/include/hw/core/tcg-cpu-ops.h
>> @@ -60,6 +60,13 @@ struct TCGCPUOps {
>> /** @debug_excp_handler: Callback for handling debug exceptions */
>> void (*debug_excp_handler)(CPUState *cpu);
>>
>> + /**
>> + * @do_unaligned_access: Callback for unaligned access handling
>> + */
>> + void (*do_unaligned_access)(CPUState *cpu, vaddr addr,
>> + MMUAccessType access_type,
>> + int mmu_idx, uintptr_t retaddr);
>
> Shouldn't it be QEMU_NORETURN?
>
I think in system mode we're allowed to return, letting the unaligned access continue.
But I'm not sure about that, and it may not even be used.
r~
^ permalink raw reply [flat|nested] 102+ messages in thread
* Re: [PATCH for-6.2 01/43] hw/core: Make do_unaligned_access available to user-only
2021-07-29 0:46 ` [PATCH for-6.2 01/43] hw/core: Make do_unaligned_access available to user-only Richard Henderson
2021-07-29 6:14 ` Philippe Mathieu-Daudé
2021-07-29 6:19 ` Philippe Mathieu-Daudé
@ 2021-07-29 13:05 ` Peter Maydell
2 siblings, 0 replies; 102+ messages in thread
From: Peter Maydell @ 2021-07-29 13:05 UTC (permalink / raw)
To: Richard Henderson; +Cc: QEMU Developers
On Thu, 29 Jul 2021 at 01:50, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> We shouldn't be ignoring SIGBUS for user-only.
> Move our existing TCGCPUOps hook out from CONFIG_SOFTMMU.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
thanks
-- PMM
^ permalink raw reply [flat|nested] 102+ messages in thread
* [PATCH for-6.2 02/43] target/alpha: Implement do_unaligned_access for user-only
2021-07-29 0:46 [PATCH for-6.2 00/43] Unaligned accesses for user-only Richard Henderson
2021-07-29 0:46 ` [PATCH for-6.2 01/43] hw/core: Make do_unaligned_access available to user-only Richard Henderson
@ 2021-07-29 0:46 ` Richard Henderson
2021-07-29 13:05 ` Peter Maydell
2021-07-29 0:46 ` [PATCH for-6.2 03/43] target/arm: " Richard Henderson
` (42 subsequent siblings)
44 siblings, 1 reply; 102+ messages in thread
From: Richard Henderson @ 2021-07-29 0:46 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/alpha/cpu.c | 2 +-
target/alpha/mem_helper.c | 8 +++-----
2 files changed, 4 insertions(+), 6 deletions(-)
diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c
index 4871ad0c0a..cb7e5261bd 100644
--- a/target/alpha/cpu.c
+++ b/target/alpha/cpu.c
@@ -220,11 +220,11 @@ static const struct TCGCPUOps alpha_tcg_ops = {
.initialize = alpha_translate_init,
.cpu_exec_interrupt = alpha_cpu_exec_interrupt,
.tlb_fill = alpha_cpu_tlb_fill,
+ .do_unaligned_access = alpha_cpu_do_unaligned_access,
#ifndef CONFIG_USER_ONLY
.do_interrupt = alpha_cpu_do_interrupt,
.do_transaction_failed = alpha_cpu_do_transaction_failed,
- .do_unaligned_access = alpha_cpu_do_unaligned_access,
#endif /* !CONFIG_USER_ONLY */
};
diff --git a/target/alpha/mem_helper.c b/target/alpha/mem_helper.c
index 75e72bc337..e3cf98b270 100644
--- a/target/alpha/mem_helper.c
+++ b/target/alpha/mem_helper.c
@@ -23,30 +23,28 @@
#include "exec/exec-all.h"
#include "exec/cpu_ldst.h"
-/* Softmmu support */
-#ifndef CONFIG_USER_ONLY
void alpha_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
MMUAccessType access_type,
int mmu_idx, uintptr_t retaddr)
{
AlphaCPU *cpu = ALPHA_CPU(cs);
CPUAlphaState *env = &cpu->env;
- uint64_t pc;
uint32_t insn;
cpu_restore_state(cs, retaddr, true);
- pc = env->pc;
- insn = cpu_ldl_code(env, pc);
+ insn = cpu_ldl_code(env, env->pc);
env->trap_arg0 = addr;
env->trap_arg1 = insn >> 26; /* opcode */
env->trap_arg2 = (insn >> 21) & 31; /* dest regno */
+
cs->exception_index = EXCP_UNALIGN;
env->error_code = 0;
cpu_loop_exit(cs);
}
+#ifndef CONFIG_USER_ONLY
void alpha_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
vaddr addr, unsigned size,
MMUAccessType access_type,
--
2.25.1
^ permalink raw reply related [flat|nested] 102+ messages in thread* Re: [PATCH for-6.2 02/43] target/alpha: Implement do_unaligned_access for user-only
2021-07-29 0:46 ` [PATCH for-6.2 02/43] target/alpha: Implement do_unaligned_access for user-only Richard Henderson
@ 2021-07-29 13:05 ` Peter Maydell
0 siblings, 0 replies; 102+ messages in thread
From: Peter Maydell @ 2021-07-29 13:05 UTC (permalink / raw)
To: Richard Henderson; +Cc: QEMU Developers
On Thu, 29 Jul 2021 at 01:50, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/alpha/cpu.c | 2 +-
> target/alpha/mem_helper.c | 8 +++-----
> 2 files changed, 4 insertions(+), 6 deletions(-)
>
> diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c
> index 4871ad0c0a..cb7e5261bd 100644
> --- a/target/alpha/cpu.c
> +++ b/target/alpha/cpu.c
> @@ -220,11 +220,11 @@ static const struct TCGCPUOps alpha_tcg_ops = {
> .initialize = alpha_translate_init,
> .cpu_exec_interrupt = alpha_cpu_exec_interrupt,
> .tlb_fill = alpha_cpu_tlb_fill,
> + .do_unaligned_access = alpha_cpu_do_unaligned_access,
>
> #ifndef CONFIG_USER_ONLY
> .do_interrupt = alpha_cpu_do_interrupt,
> .do_transaction_failed = alpha_cpu_do_transaction_failed,
> - .do_unaligned_access = alpha_cpu_do_unaligned_access,
> #endif /* !CONFIG_USER_ONLY */
> };
>
> diff --git a/target/alpha/mem_helper.c b/target/alpha/mem_helper.c
> index 75e72bc337..e3cf98b270 100644
> --- a/target/alpha/mem_helper.c
> +++ b/target/alpha/mem_helper.c
> @@ -23,30 +23,28 @@
> #include "exec/exec-all.h"
> #include "exec/cpu_ldst.h"
>
> -/* Softmmu support */
> -#ifndef CONFIG_USER_ONLY
> void alpha_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
> MMUAccessType access_type,
> int mmu_idx, uintptr_t retaddr)
> {
> AlphaCPU *cpu = ALPHA_CPU(cs);
> CPUAlphaState *env = &cpu->env;
> - uint64_t pc;
> uint32_t insn;
>
> cpu_restore_state(cs, retaddr, true);
>
> - pc = env->pc;
> - insn = cpu_ldl_code(env, pc);
> + insn = cpu_ldl_code(env, env->pc);
>
> env->trap_arg0 = addr;
> env->trap_arg1 = insn >> 26; /* opcode */
> env->trap_arg2 = (insn >> 21) & 31; /* dest regno */
> +
> cs->exception_index = EXCP_UNALIGN;
> env->error_code = 0;
> cpu_loop_exit(cs);
> }
The code changes here seem unnecessary ?
Anyway
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
thanks
-- PMM
^ permalink raw reply [flat|nested] 102+ messages in thread
* [PATCH for-6.2 03/43] target/arm: Implement do_unaligned_access for user-only
2021-07-29 0:46 [PATCH for-6.2 00/43] Unaligned accesses for user-only Richard Henderson
2021-07-29 0:46 ` [PATCH for-6.2 01/43] hw/core: Make do_unaligned_access available to user-only Richard Henderson
2021-07-29 0:46 ` [PATCH for-6.2 02/43] target/alpha: Implement do_unaligned_access for user-only Richard Henderson
@ 2021-07-29 0:46 ` Richard Henderson
2021-07-29 13:14 ` Peter Maydell
2021-07-29 0:46 ` [PATCH for-6.2 04/43] target/hppa: " Richard Henderson
` (41 subsequent siblings)
44 siblings, 1 reply; 102+ messages in thread
From: Richard Henderson @ 2021-07-29 0:46 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm
Cc: qemu-arm@nongnu.org
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
linux-user/aarch64/cpu_loop.c | 4 ++++
linux-user/arm/cpu_loop.c | 43 +++++++++++++++++++++++++++--------
target/arm/cpu.c | 2 +-
target/arm/cpu_tcg.c | 2 +-
4 files changed, 40 insertions(+), 11 deletions(-)
diff --git a/linux-user/aarch64/cpu_loop.c b/linux-user/aarch64/cpu_loop.c
index ee72a1c20f..998831f87f 100644
--- a/linux-user/aarch64/cpu_loop.c
+++ b/linux-user/aarch64/cpu_loop.c
@@ -137,6 +137,10 @@ void cpu_loop(CPUARMState *env)
case 0x11: /* Synchronous Tag Check Fault */
info.si_code = TARGET_SEGV_MTESERR;
break;
+ case 0x21: /* Alignment fault */
+ info.si_signo = TARGET_SIGBUS;
+ info.si_code = TARGET_BUS_ADRALN;
+ break;
default:
g_assert_not_reached();
}
diff --git a/linux-user/arm/cpu_loop.c b/linux-user/arm/cpu_loop.c
index 69632d15be..da7da6a0c1 100644
--- a/linux-user/arm/cpu_loop.c
+++ b/linux-user/arm/cpu_loop.c
@@ -23,6 +23,7 @@
#include "elf.h"
#include "cpu_loop-common.h"
#include "semihosting/common-semi.h"
+#include "target/arm/syndrome.h"
#define get_user_code_u32(x, gaddr, env) \
({ abi_long __r = get_user_u32((x), (gaddr)); \
@@ -286,9 +287,8 @@ void cpu_loop(CPUARMState *env)
{
CPUState *cs = env_cpu(env);
int trapnr;
- unsigned int n, insn;
+ unsigned int n, insn, ec, fsc;
target_siginfo_t info;
- uint32_t addr;
abi_ulong ret;
for(;;) {
@@ -437,15 +437,40 @@ void cpu_loop(CPUARMState *env)
break;
case EXCP_PREFETCH_ABORT:
case EXCP_DATA_ABORT:
- addr = env->exception.vaddress;
- {
- info.si_signo = TARGET_SIGSEGV;
- info.si_errno = 0;
- /* XXX: check env->error_code */
+ info.si_signo = TARGET_SIGSEGV;
+ info.si_errno = 0;
+ info._sifields._sigfault._addr = env->exception.vaddress;
+ /*
+ * We should only arrive here with EC in {DATAABORT, INSNABORT},
+ * and short-form FSC, which then tells us to look at the FSR.
+ * ??? arm_cpu_reset never sets TTBCR_EAE, so we always get
+ * short-form FSC.
+ */
+ ec = syn_get_ec(env->exception.syndrome);
+ assert(ec == EC_DATAABORT || ec == EC_INSNABORT);
+ fsc = extract32(env->exception.syndrome, 0, 6);
+ assert(fsc == 0x3f);
+ switch (env->exception.fsr & 0x1f) {
+ case 0x1: /* Alignment */
+ info.si_signo = TARGET_SIGBUS;
+ info.si_code = TARGET_BUS_ADRALN;
+ break;
+ case 0x3: /* Access flag fault, level 1 */
+ case 0x6: /* Access flag fault, level 2 */
+ case 0x9: /* Domain fault, level 1 */
+ case 0xb: /* Domain fault, level 2 */
+ case 0xd: /* Permision fault, level 1 */
+ case 0xf: /* Permision fault, level 2 */
+ info.si_code = TARGET_SEGV_ACCERR;
+ break;
+ case 0x5: /* Translation fault, level 1 */
+ case 0x7: /* Translation fault, level 2 */
info.si_code = TARGET_SEGV_MAPERR;
- info._sifields._sigfault._addr = addr;
- queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
+ break;
+ default:
+ g_assert_not_reached();
}
+ queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
break;
case EXCP_DEBUG:
case EXCP_BKPT:
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 2866dd7658..de0d968d76 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -1987,11 +1987,11 @@ static const struct TCGCPUOps arm_tcg_ops = {
.cpu_exec_interrupt = arm_cpu_exec_interrupt,
.tlb_fill = arm_cpu_tlb_fill,
.debug_excp_handler = arm_debug_excp_handler,
+ .do_unaligned_access = arm_cpu_do_unaligned_access,
#if !defined(CONFIG_USER_ONLY)
.do_interrupt = arm_cpu_do_interrupt,
.do_transaction_failed = arm_cpu_do_transaction_failed,
- .do_unaligned_access = arm_cpu_do_unaligned_access,
.adjust_watchpoint_address = arm_adjust_watchpoint_address,
.debug_check_watchpoint = arm_debug_check_watchpoint,
.debug_check_breakpoint = arm_debug_check_breakpoint,
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
index ed444bf436..1b91fdc890 100644
--- a/target/arm/cpu_tcg.c
+++ b/target/arm/cpu_tcg.c
@@ -904,11 +904,11 @@ static const struct TCGCPUOps arm_v7m_tcg_ops = {
.cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt,
.tlb_fill = arm_cpu_tlb_fill,
.debug_excp_handler = arm_debug_excp_handler,
+ .do_unaligned_access = arm_cpu_do_unaligned_access,
#if !defined(CONFIG_USER_ONLY)
.do_interrupt = arm_v7m_cpu_do_interrupt,
.do_transaction_failed = arm_cpu_do_transaction_failed,
- .do_unaligned_access = arm_cpu_do_unaligned_access,
.adjust_watchpoint_address = arm_adjust_watchpoint_address,
.debug_check_watchpoint = arm_debug_check_watchpoint,
.debug_check_breakpoint = arm_debug_check_breakpoint,
--
2.25.1
^ permalink raw reply related [flat|nested] 102+ messages in thread* Re: [PATCH for-6.2 03/43] target/arm: Implement do_unaligned_access for user-only
2021-07-29 0:46 ` [PATCH for-6.2 03/43] target/arm: " Richard Henderson
@ 2021-07-29 13:14 ` Peter Maydell
2021-07-29 18:51 ` Richard Henderson
0 siblings, 1 reply; 102+ messages in thread
From: Peter Maydell @ 2021-07-29 13:14 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-arm, QEMU Developers
On Thu, 29 Jul 2021 at 01:47, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Cc: qemu-arm@nongnu.org
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> linux-user/aarch64/cpu_loop.c | 4 ++++
> linux-user/arm/cpu_loop.c | 43 +++++++++++++++++++++++++++--------
> target/arm/cpu.c | 2 +-
> target/arm/cpu_tcg.c | 2 +-
> 4 files changed, 40 insertions(+), 11 deletions(-)
>
> diff --git a/linux-user/aarch64/cpu_loop.c b/linux-user/aarch64/cpu_loop.c
> index ee72a1c20f..998831f87f 100644
> --- a/linux-user/aarch64/cpu_loop.c
> +++ b/linux-user/aarch64/cpu_loop.c
> @@ -137,6 +137,10 @@ void cpu_loop(CPUARMState *env)
> case 0x11: /* Synchronous Tag Check Fault */
> info.si_code = TARGET_SEGV_MTESERR;
> break;
> + case 0x21: /* Alignment fault */
> + info.si_signo = TARGET_SIGBUS;
> + info.si_code = TARGET_BUS_ADRALN;
> + break;
> default:
> g_assert_not_reached();
> }
> diff --git a/linux-user/arm/cpu_loop.c b/linux-user/arm/cpu_loop.c
> index 69632d15be..da7da6a0c1 100644
> --- a/linux-user/arm/cpu_loop.c
> +++ b/linux-user/arm/cpu_loop.c
> @@ -23,6 +23,7 @@
> #include "elf.h"
> #include "cpu_loop-common.h"
> #include "semihosting/common-semi.h"
> +#include "target/arm/syndrome.h"
Not a huge fan of linux-user files pulling in target/arm headers, but
I guess we do it already in aarch64/cpu_loop.c. (Though that is afaict
the only other place ATM...)
>
> #define get_user_code_u32(x, gaddr, env) \
> ({ abi_long __r = get_user_u32((x), (gaddr)); \
> @@ -286,9 +287,8 @@ void cpu_loop(CPUARMState *env)
> {
> CPUState *cs = env_cpu(env);
> int trapnr;
> - unsigned int n, insn;
> + unsigned int n, insn, ec, fsc;
> target_siginfo_t info;
> - uint32_t addr;
> abi_ulong ret;
>
> for(;;) {
> @@ -437,15 +437,40 @@ void cpu_loop(CPUARMState *env)
> break;
> case EXCP_PREFETCH_ABORT:
> case EXCP_DATA_ABORT:
> - addr = env->exception.vaddress;
> - {
> - info.si_signo = TARGET_SIGSEGV;
> - info.si_errno = 0;
> - /* XXX: check env->error_code */
> + info.si_signo = TARGET_SIGSEGV;
> + info.si_errno = 0;
> + info._sifields._sigfault._addr = env->exception.vaddress;
> + /*
> + * We should only arrive here with EC in {DATAABORT, INSNABORT},
> + * and short-form FSC, which then tells us to look at the FSR.
> + * ??? arm_cpu_reset never sets TTBCR_EAE, so we always get
> + * short-form FSC.
> + */
> + ec = syn_get_ec(env->exception.syndrome);
> + assert(ec == EC_DATAABORT || ec == EC_INSNABORT);
> + fsc = extract32(env->exception.syndrome, 0, 6);
> + assert(fsc == 0x3f);
> + switch (env->exception.fsr & 0x1f) {
> + case 0x1: /* Alignment */
> + info.si_signo = TARGET_SIGBUS;
> + info.si_code = TARGET_BUS_ADRALN;
> + break;
> + case 0x3: /* Access flag fault, level 1 */
> + case 0x6: /* Access flag fault, level 2 */
> + case 0x9: /* Domain fault, level 1 */
> + case 0xb: /* Domain fault, level 2 */
> + case 0xd: /* Permision fault, level 1 */
> + case 0xf: /* Permision fault, level 2 */
> + info.si_code = TARGET_SEGV_ACCERR;
> + break;
> + case 0x5: /* Translation fault, level 1 */
> + case 0x7: /* Translation fault, level 2 */
> info.si_code = TARGET_SEGV_MAPERR;
> - info._sifields._sigfault._addr = addr;
> - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
> + break;
> + default:
> + g_assert_not_reached();
> }
> + queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
> break;
It's slightly sad that we start off with a nicely symbolic
ArmMMUFaultInfo type enum value, carefully encode it into a
numeric value and then have to switch on the numeric value here,
but I can see why we end up this way...
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
thanks
-- PMM
^ permalink raw reply [flat|nested] 102+ messages in thread* Re: [PATCH for-6.2 03/43] target/arm: Implement do_unaligned_access for user-only
2021-07-29 13:14 ` Peter Maydell
@ 2021-07-29 18:51 ` Richard Henderson
0 siblings, 0 replies; 102+ messages in thread
From: Richard Henderson @ 2021-07-29 18:51 UTC (permalink / raw)
To: Peter Maydell; +Cc: qemu-arm, QEMU Developers
On 7/29/21 3:14 AM, Peter Maydell wrote:
> On Thu, 29 Jul 2021 at 01:47, Richard Henderson
> <richard.henderson@linaro.org> wrote:
>>
>> Cc: qemu-arm@nongnu.org
>> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
>> ---
>> linux-user/aarch64/cpu_loop.c | 4 ++++
>> linux-user/arm/cpu_loop.c | 43 +++++++++++++++++++++++++++--------
>> target/arm/cpu.c | 2 +-
>> target/arm/cpu_tcg.c | 2 +-
>> 4 files changed, 40 insertions(+), 11 deletions(-)
>>
>> diff --git a/linux-user/aarch64/cpu_loop.c b/linux-user/aarch64/cpu_loop.c
>> index ee72a1c20f..998831f87f 100644
>> --- a/linux-user/aarch64/cpu_loop.c
>> +++ b/linux-user/aarch64/cpu_loop.c
>> @@ -137,6 +137,10 @@ void cpu_loop(CPUARMState *env)
>> case 0x11: /* Synchronous Tag Check Fault */
>> info.si_code = TARGET_SEGV_MTESERR;
>> break;
>> + case 0x21: /* Alignment fault */
>> + info.si_signo = TARGET_SIGBUS;
>> + info.si_code = TARGET_BUS_ADRALN;
>> + break;
>> default:
>> g_assert_not_reached();
>> }
>> diff --git a/linux-user/arm/cpu_loop.c b/linux-user/arm/cpu_loop.c
>> index 69632d15be..da7da6a0c1 100644
>> --- a/linux-user/arm/cpu_loop.c
>> +++ b/linux-user/arm/cpu_loop.c
>> @@ -23,6 +23,7 @@
>> #include "elf.h"
>> #include "cpu_loop-common.h"
>> #include "semihosting/common-semi.h"
>> +#include "target/arm/syndrome.h"
>
> Not a huge fan of linux-user files pulling in target/arm headers, but
> I guess we do it already in aarch64/cpu_loop.c. (Though that is afaict
> the only other place ATM...)
>
>>
>> #define get_user_code_u32(x, gaddr, env) \
>> ({ abi_long __r = get_user_u32((x), (gaddr)); \
>> @@ -286,9 +287,8 @@ void cpu_loop(CPUARMState *env)
>> {
>> CPUState *cs = env_cpu(env);
>> int trapnr;
>> - unsigned int n, insn;
>> + unsigned int n, insn, ec, fsc;
>> target_siginfo_t info;
>> - uint32_t addr;
>> abi_ulong ret;
>>
>> for(;;) {
>> @@ -437,15 +437,40 @@ void cpu_loop(CPUARMState *env)
>> break;
>> case EXCP_PREFETCH_ABORT:
>> case EXCP_DATA_ABORT:
>> - addr = env->exception.vaddress;
>> - {
>> - info.si_signo = TARGET_SIGSEGV;
>> - info.si_errno = 0;
>> - /* XXX: check env->error_code */
>> + info.si_signo = TARGET_SIGSEGV;
>> + info.si_errno = 0;
>> + info._sifields._sigfault._addr = env->exception.vaddress;
>> + /*
>> + * We should only arrive here with EC in {DATAABORT, INSNABORT},
>> + * and short-form FSC, which then tells us to look at the FSR.
>> + * ??? arm_cpu_reset never sets TTBCR_EAE, so we always get
>> + * short-form FSC.
>> + */
>> + ec = syn_get_ec(env->exception.syndrome);
>> + assert(ec == EC_DATAABORT || ec == EC_INSNABORT);
>> + fsc = extract32(env->exception.syndrome, 0, 6);
>> + assert(fsc == 0x3f);
>> + switch (env->exception.fsr & 0x1f) {
>> + case 0x1: /* Alignment */
>> + info.si_signo = TARGET_SIGBUS;
>> + info.si_code = TARGET_BUS_ADRALN;
>> + break;
>> + case 0x3: /* Access flag fault, level 1 */
>> + case 0x6: /* Access flag fault, level 2 */
>> + case 0x9: /* Domain fault, level 1 */
>> + case 0xb: /* Domain fault, level 2 */
>> + case 0xd: /* Permision fault, level 1 */
>> + case 0xf: /* Permision fault, level 2 */
>> + info.si_code = TARGET_SEGV_ACCERR;
>> + break;
>> + case 0x5: /* Translation fault, level 1 */
>> + case 0x7: /* Translation fault, level 2 */
>> info.si_code = TARGET_SEGV_MAPERR;
>> - info._sifields._sigfault._addr = addr;
>> - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
>> + break;
>> + default:
>> + g_assert_not_reached();
>> }
>> + queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
>> break;
>
> It's slightly sad that we start off with a nicely symbolic
> ArmMMUFaultInfo type enum value, carefully encode it into a
> numeric value and then have to switch on the numeric value here,
> but I can see why we end up this way...
We don't have to leave it that way.
We could move the ARMMMUFaultInfo out of internals.h, create special user-only copies of
arm_cpu_tlb_fill and arm_cpu_do_unaligned_access, create a new function to raise the MTE
exception, and place the proper enumeraor into env->error_code instead of the hw syndrome.
What we have seemed cleaner on the target/arm/ side at the time.
r~
^ permalink raw reply [flat|nested] 102+ messages in thread
* [PATCH for-6.2 04/43] target/hppa: Implement do_unaligned_access for user-only
2021-07-29 0:46 [PATCH for-6.2 00/43] Unaligned accesses for user-only Richard Henderson
` (2 preceding siblings ...)
2021-07-29 0:46 ` [PATCH for-6.2 03/43] target/arm: " Richard Henderson
@ 2021-07-29 0:46 ` Richard Henderson
2021-07-29 13:15 ` Peter Maydell
2021-07-29 0:46 ` [PATCH for-6.2 05/43] target/microblaze: " Richard Henderson
` (40 subsequent siblings)
44 siblings, 1 reply; 102+ messages in thread
From: Richard Henderson @ 2021-07-29 0:46 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
linux-user/hppa/cpu_loop.c | 2 +-
target/hppa/cpu.c | 8 +++++---
2 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/linux-user/hppa/cpu_loop.c b/linux-user/hppa/cpu_loop.c
index 82d8183821..5ce30fec8b 100644
--- a/linux-user/hppa/cpu_loop.c
+++ b/linux-user/hppa/cpu_loop.c
@@ -161,7 +161,7 @@ void cpu_loop(CPUHPPAState *env)
case EXCP_UNALIGN:
info.si_signo = TARGET_SIGBUS;
info.si_errno = 0;
- info.si_code = 0;
+ info.si_code = TARGET_BUS_ADRALN;
info._sifields._sigfault._addr = env->cr[CR_IOR];
queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
break;
diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c
index 2eace4ee12..55c0d81046 100644
--- a/target/hppa/cpu.c
+++ b/target/hppa/cpu.c
@@ -71,7 +71,6 @@ static void hppa_cpu_disas_set_info(CPUState *cs, disassemble_info *info)
info->print_insn = print_insn_hppa;
}
-#ifndef CONFIG_USER_ONLY
static void hppa_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
MMUAccessType access_type,
int mmu_idx, uintptr_t retaddr)
@@ -80,15 +79,18 @@ static void hppa_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
CPUHPPAState *env = &cpu->env;
cs->exception_index = EXCP_UNALIGN;
+#ifdef CONFIG_USER_ONLY
+ env->cr[CR_IOR] = addr;
+#else
if (env->psw & PSW_Q) {
/* ??? Needs tweaking for hppa64. */
env->cr[CR_IOR] = addr;
env->cr[CR_ISR] = addr >> 32;
}
+#endif
cpu_loop_exit_restore(cs, retaddr);
}
-#endif /* CONFIG_USER_ONLY */
static void hppa_cpu_realizefn(DeviceState *dev, Error **errp)
{
@@ -146,10 +148,10 @@ static const struct TCGCPUOps hppa_tcg_ops = {
.synchronize_from_tb = hppa_cpu_synchronize_from_tb,
.cpu_exec_interrupt = hppa_cpu_exec_interrupt,
.tlb_fill = hppa_cpu_tlb_fill,
+ .do_unaligned_access = hppa_cpu_do_unaligned_access,
#ifndef CONFIG_USER_ONLY
.do_interrupt = hppa_cpu_do_interrupt,
- .do_unaligned_access = hppa_cpu_do_unaligned_access,
#endif /* !CONFIG_USER_ONLY */
};
--
2.25.1
^ permalink raw reply related [flat|nested] 102+ messages in thread* Re: [PATCH for-6.2 04/43] target/hppa: Implement do_unaligned_access for user-only
2021-07-29 0:46 ` [PATCH for-6.2 04/43] target/hppa: " Richard Henderson
@ 2021-07-29 13:15 ` Peter Maydell
2021-07-29 17:55 ` Richard Henderson
0 siblings, 1 reply; 102+ messages in thread
From: Peter Maydell @ 2021-07-29 13:15 UTC (permalink / raw)
To: Richard Henderson; +Cc: QEMU Developers
On Thu, 29 Jul 2021 at 01:57, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> linux-user/hppa/cpu_loop.c | 2 +-
> target/hppa/cpu.c | 8 +++++---
> 2 files changed, 6 insertions(+), 4 deletions(-)
>
> diff --git a/linux-user/hppa/cpu_loop.c b/linux-user/hppa/cpu_loop.c
> index 82d8183821..5ce30fec8b 100644
> --- a/linux-user/hppa/cpu_loop.c
> +++ b/linux-user/hppa/cpu_loop.c
> @@ -161,7 +161,7 @@ void cpu_loop(CPUHPPAState *env)
> case EXCP_UNALIGN:
> info.si_signo = TARGET_SIGBUS;
> info.si_errno = 0;
> - info.si_code = 0;
> + info.si_code = TARGET_BUS_ADRALN;
> info._sifields._sigfault._addr = env->cr[CR_IOR];
> queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
> break;
> diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c
> index 2eace4ee12..55c0d81046 100644
> --- a/target/hppa/cpu.c
> +++ b/target/hppa/cpu.c
> @@ -71,7 +71,6 @@ static void hppa_cpu_disas_set_info(CPUState *cs, disassemble_info *info)
> info->print_insn = print_insn_hppa;
> }
>
> -#ifndef CONFIG_USER_ONLY
> static void hppa_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
> MMUAccessType access_type,
> int mmu_idx, uintptr_t retaddr)
> @@ -80,15 +79,18 @@ static void hppa_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
> CPUHPPAState *env = &cpu->env;
>
> cs->exception_index = EXCP_UNALIGN;
> +#ifdef CONFIG_USER_ONLY
> + env->cr[CR_IOR] = addr;
Do we not need the top 32 bits of the address, which the softmmu
version is recording in CR_ISR ?
> +#else
> if (env->psw & PSW_Q) {
> /* ??? Needs tweaking for hppa64. */
> env->cr[CR_IOR] = addr;
> env->cr[CR_ISR] = addr >> 32;
> }
> +#endif
>
> cpu_loop_exit_restore(cs, retaddr);
> }
> -#endif /* CONFIG_USER_ONLY */
-- PMM
^ permalink raw reply [flat|nested] 102+ messages in thread* Re: [PATCH for-6.2 04/43] target/hppa: Implement do_unaligned_access for user-only
2021-07-29 13:15 ` Peter Maydell
@ 2021-07-29 17:55 ` Richard Henderson
0 siblings, 0 replies; 102+ messages in thread
From: Richard Henderson @ 2021-07-29 17:55 UTC (permalink / raw)
To: Peter Maydell; +Cc: QEMU Developers
On 7/29/21 3:15 AM, Peter Maydell wrote:
> On Thu, 29 Jul 2021 at 01:57, Richard Henderson
> <richard.henderson@linaro.org> wrote:
>>
>> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
>> ---
>> linux-user/hppa/cpu_loop.c | 2 +-
>> target/hppa/cpu.c | 8 +++++---
>> 2 files changed, 6 insertions(+), 4 deletions(-)
>>
>> diff --git a/linux-user/hppa/cpu_loop.c b/linux-user/hppa/cpu_loop.c
>> index 82d8183821..5ce30fec8b 100644
>> --- a/linux-user/hppa/cpu_loop.c
>> +++ b/linux-user/hppa/cpu_loop.c
>> @@ -161,7 +161,7 @@ void cpu_loop(CPUHPPAState *env)
>> case EXCP_UNALIGN:
>> info.si_signo = TARGET_SIGBUS;
>> info.si_errno = 0;
>> - info.si_code = 0;
>> + info.si_code = TARGET_BUS_ADRALN;
>> info._sifields._sigfault._addr = env->cr[CR_IOR];
>> queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
>> break;
>> diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c
>> index 2eace4ee12..55c0d81046 100644
>> --- a/target/hppa/cpu.c
>> +++ b/target/hppa/cpu.c
>> @@ -71,7 +71,6 @@ static void hppa_cpu_disas_set_info(CPUState *cs, disassemble_info *info)
>> info->print_insn = print_insn_hppa;
>> }
>>
>> -#ifndef CONFIG_USER_ONLY
>> static void hppa_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
>> MMUAccessType access_type,
>> int mmu_idx, uintptr_t retaddr)
>> @@ -80,15 +79,18 @@ static void hppa_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
>> CPUHPPAState *env = &cpu->env;
>>
>> cs->exception_index = EXCP_UNALIGN;
>> +#ifdef CONFIG_USER_ONLY
>> + env->cr[CR_IOR] = addr;
>
> Do we not need the top 32 bits of the address, which the softmmu
> version is recording in CR_ISR ?
No. That's the "space" number, which for Linux user is always 0.
In system mode we use 64-bit addresses to make sure we can represent that; in user-only,
we use 32-bit addresses.
r~
>> +#else
>> if (env->psw & PSW_Q) {
>> /* ??? Needs tweaking for hppa64. */
>> env->cr[CR_IOR] = addr;
>> env->cr[CR_ISR] = addr >> 32;
>> }
>> +#endif
>>
>> cpu_loop_exit_restore(cs, retaddr);
>> }
>> -#endif /* CONFIG_USER_ONLY */
>
> -- PMM
>
^ permalink raw reply [flat|nested] 102+ messages in thread
* [PATCH for-6.2 05/43] target/microblaze: Implement do_unaligned_access for user-only
2021-07-29 0:46 [PATCH for-6.2 00/43] Unaligned accesses for user-only Richard Henderson
` (3 preceding siblings ...)
2021-07-29 0:46 ` [PATCH for-6.2 04/43] target/hppa: " Richard Henderson
@ 2021-07-29 0:46 ` Richard Henderson
2021-07-29 8:26 ` Philippe Mathieu-Daudé
2021-07-29 13:26 ` Peter Maydell
2021-07-29 0:46 ` [PATCH for-6.2 06/43] target/mips: " Richard Henderson
` (39 subsequent siblings)
44 siblings, 2 replies; 102+ messages in thread
From: Richard Henderson @ 2021-07-29 0:46 UTC (permalink / raw)
To: qemu-devel; +Cc: Edgar E . Iglesias
Cc: Edgar E. Iglesias <edgar.iglesias@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/microblaze/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
index 72d8f2a0da..cbec062ed7 100644
--- a/target/microblaze/cpu.c
+++ b/target/microblaze/cpu.c
@@ -367,11 +367,11 @@ static const struct TCGCPUOps mb_tcg_ops = {
.synchronize_from_tb = mb_cpu_synchronize_from_tb,
.cpu_exec_interrupt = mb_cpu_exec_interrupt,
.tlb_fill = mb_cpu_tlb_fill,
+ .do_unaligned_access = mb_cpu_do_unaligned_access,
#ifndef CONFIG_USER_ONLY
.do_interrupt = mb_cpu_do_interrupt,
.do_transaction_failed = mb_cpu_transaction_failed,
- .do_unaligned_access = mb_cpu_do_unaligned_access,
#endif /* !CONFIG_USER_ONLY */
};
--
2.25.1
^ permalink raw reply related [flat|nested] 102+ messages in thread* Re: [PATCH for-6.2 05/43] target/microblaze: Implement do_unaligned_access for user-only
2021-07-29 0:46 ` [PATCH for-6.2 05/43] target/microblaze: " Richard Henderson
@ 2021-07-29 8:26 ` Philippe Mathieu-Daudé
2021-07-29 13:26 ` Peter Maydell
1 sibling, 0 replies; 102+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-07-29 8:26 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: Edgar E . Iglesias
On 7/29/21 2:46 AM, Richard Henderson wrote:
> Cc: Edgar E. Iglesias <edgar.iglesias@gmail.com>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/microblaze/cpu.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
^ permalink raw reply [flat|nested] 102+ messages in thread
* Re: [PATCH for-6.2 05/43] target/microblaze: Implement do_unaligned_access for user-only
2021-07-29 0:46 ` [PATCH for-6.2 05/43] target/microblaze: " Richard Henderson
2021-07-29 8:26 ` Philippe Mathieu-Daudé
@ 2021-07-29 13:26 ` Peter Maydell
2021-07-29 18:00 ` Richard Henderson
1 sibling, 1 reply; 102+ messages in thread
From: Peter Maydell @ 2021-07-29 13:26 UTC (permalink / raw)
To: Richard Henderson; +Cc: Edgar E . Iglesias, QEMU Developers
On Thu, 29 Jul 2021 at 01:54, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Cc: Edgar E. Iglesias <edgar.iglesias@gmail.com>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/microblaze/cpu.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
> index 72d8f2a0da..cbec062ed7 100644
> --- a/target/microblaze/cpu.c
> +++ b/target/microblaze/cpu.c
> @@ -367,11 +367,11 @@ static const struct TCGCPUOps mb_tcg_ops = {
> .synchronize_from_tb = mb_cpu_synchronize_from_tb,
> .cpu_exec_interrupt = mb_cpu_exec_interrupt,
> .tlb_fill = mb_cpu_tlb_fill,
> + .do_unaligned_access = mb_cpu_do_unaligned_access,
>
> #ifndef CONFIG_USER_ONLY
> .do_interrupt = mb_cpu_do_interrupt,
> .do_transaction_failed = mb_cpu_transaction_failed,
> - .do_unaligned_access = mb_cpu_do_unaligned_access,
> #endif /* !CONFIG_USER_ONLY */
> };
If I'm reading the kernel sources correctly, for Microblaze it always
fixes up unaligned accesses, so for our linux-user code we want
"ignore unaligned access errors" rather than reporting them up
to cpu-loop.c, I think ?
-- PMM
^ permalink raw reply [flat|nested] 102+ messages in thread* Re: [PATCH for-6.2 05/43] target/microblaze: Implement do_unaligned_access for user-only
2021-07-29 13:26 ` Peter Maydell
@ 2021-07-29 18:00 ` Richard Henderson
2021-07-29 18:44 ` Edgar E. Iglesias
0 siblings, 1 reply; 102+ messages in thread
From: Richard Henderson @ 2021-07-29 18:00 UTC (permalink / raw)
To: Peter Maydell; +Cc: Edgar E . Iglesias, QEMU Developers
On 7/29/21 3:26 AM, Peter Maydell wrote:
> On Thu, 29 Jul 2021 at 01:54, Richard Henderson
> <richard.henderson@linaro.org> wrote:
>>
>> Cc: Edgar E. Iglesias <edgar.iglesias@gmail.com>
>> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
>> ---
>> target/microblaze/cpu.c | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
>> index 72d8f2a0da..cbec062ed7 100644
>> --- a/target/microblaze/cpu.c
>> +++ b/target/microblaze/cpu.c
>> @@ -367,11 +367,11 @@ static const struct TCGCPUOps mb_tcg_ops = {
>> .synchronize_from_tb = mb_cpu_synchronize_from_tb,
>> .cpu_exec_interrupt = mb_cpu_exec_interrupt,
>> .tlb_fill = mb_cpu_tlb_fill,
>> + .do_unaligned_access = mb_cpu_do_unaligned_access,
>>
>> #ifndef CONFIG_USER_ONLY
>> .do_interrupt = mb_cpu_do_interrupt,
>> .do_transaction_failed = mb_cpu_transaction_failed,
>> - .do_unaligned_access = mb_cpu_do_unaligned_access,
>> #endif /* !CONFIG_USER_ONLY */
>> };
>
> If I'm reading the kernel sources correctly, for Microblaze it always
> fixes up unaligned accesses, so for our linux-user code we want
> "ignore unaligned access errors" rather than reporting them up
> to cpu-loop.c, I think ?
Ah, in that case we should not be setting MO_ALIGN for some -cpu xxx, I think? Or does
the MSR_EE bit cover that? Anyway, it looked reachable at first glance.
r~
^ permalink raw reply [flat|nested] 102+ messages in thread* Re: [PATCH for-6.2 05/43] target/microblaze: Implement do_unaligned_access for user-only
2021-07-29 18:00 ` Richard Henderson
@ 2021-07-29 18:44 ` Edgar E. Iglesias
0 siblings, 0 replies; 102+ messages in thread
From: Edgar E. Iglesias @ 2021-07-29 18:44 UTC (permalink / raw)
To: Richard Henderson; +Cc: Peter Maydell, QEMU Developers
On Thu, Jul 29, 2021 at 08:00:50AM -1000, Richard Henderson wrote:
> On 7/29/21 3:26 AM, Peter Maydell wrote:
> > On Thu, 29 Jul 2021 at 01:54, Richard Henderson
> > <richard.henderson@linaro.org> wrote:
> > >
> > > Cc: Edgar E. Iglesias <edgar.iglesias@gmail.com>
> > > Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> > > ---
> > > target/microblaze/cpu.c | 2 +-
> > > 1 file changed, 1 insertion(+), 1 deletion(-)
> > >
> > > diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
> > > index 72d8f2a0da..cbec062ed7 100644
> > > --- a/target/microblaze/cpu.c
> > > +++ b/target/microblaze/cpu.c
> > > @@ -367,11 +367,11 @@ static const struct TCGCPUOps mb_tcg_ops = {
> > > .synchronize_from_tb = mb_cpu_synchronize_from_tb,
> > > .cpu_exec_interrupt = mb_cpu_exec_interrupt,
> > > .tlb_fill = mb_cpu_tlb_fill,
> > > + .do_unaligned_access = mb_cpu_do_unaligned_access,
> > >
> > > #ifndef CONFIG_USER_ONLY
> > > .do_interrupt = mb_cpu_do_interrupt,
> > > .do_transaction_failed = mb_cpu_transaction_failed,
> > > - .do_unaligned_access = mb_cpu_do_unaligned_access,
> > > #endif /* !CONFIG_USER_ONLY */
> > > };
> >
> > If I'm reading the kernel sources correctly, for Microblaze it always
> > fixes up unaligned accesses, so for our linux-user code we want
> > "ignore unaligned access errors" rather than reporting them up
> > to cpu-loop.c, I think ?
Yes, I think so.
>
> Ah, in that case we should not be setting MO_ALIGN for some -cpu xxx, I
> think? Or does the MSR_EE bit cover that? Anyway, it looked reachable at
> first glance.
Hmm yeah, perhaps we shouldn't be setting MO_ALIGN for linux-user...
Best regards,
Edgar
^ permalink raw reply [flat|nested] 102+ messages in thread
* [PATCH for-6.2 06/43] target/mips: Implement do_unaligned_access for user-only
2021-07-29 0:46 [PATCH for-6.2 00/43] Unaligned accesses for user-only Richard Henderson
` (4 preceding siblings ...)
2021-07-29 0:46 ` [PATCH for-6.2 05/43] target/microblaze: " Richard Henderson
@ 2021-07-29 0:46 ` Richard Henderson
2021-07-29 0:46 ` [PATCH for-6.2 07/43] target/ppc: Set fault address in ppc_cpu_do_unaligned_access Richard Henderson
` (38 subsequent siblings)
44 siblings, 0 replies; 102+ messages in thread
From: Richard Henderson @ 2021-07-29 0:46 UTC (permalink / raw)
To: qemu-devel; +Cc: Philippe Mathieu-Daudé
Cc: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
linux-user/mips/cpu_loop.c | 20 ++++++++++++++++----
target/mips/cpu.c | 2 +-
target/mips/tcg/op_helper.c | 3 +--
target/mips/tcg/user/tlb_helper.c | 23 +++++++++++------------
4 files changed, 29 insertions(+), 19 deletions(-)
diff --git a/linux-user/mips/cpu_loop.c b/linux-user/mips/cpu_loop.c
index 9d813ece4e..51f4eb65a6 100644
--- a/linux-user/mips/cpu_loop.c
+++ b/linux-user/mips/cpu_loop.c
@@ -158,12 +158,24 @@ done_syscall:
break;
case EXCP_TLBL:
case EXCP_TLBS:
- case EXCP_AdEL:
- case EXCP_AdES:
info.si_signo = TARGET_SIGSEGV;
info.si_errno = 0;
- /* XXX: check env->error_code */
- info.si_code = TARGET_SEGV_MAPERR;
+ info.si_code = (env->error_code & EXCP_TLB_NOMATCH
+ ? TARGET_SEGV_MAPERR : TARGET_SEGV_ACCERR);
+ info._sifields._sigfault._addr = env->CP0_BadVAddr;
+ queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
+ break;
+ case EXCP_AdEL:
+ case EXCP_AdES:
+ /*
+ * Note that on real hw AdE is also raised for access to a
+ * kernel address from user mode instead of a TLB error.
+ * For simplicity, we do not distinguish this in the user
+ * version of mips_cpu_tlb_fill so only unaligned comes here.
+ */
+ info.si_signo = TARGET_SIGBUS;
+ info.si_errno = 0;
+ info.si_code = TARGET_BUS_ADRALN;
info._sifields._sigfault._addr = env->CP0_BadVAddr;
queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
break;
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index d426918291..a1658af910 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -541,11 +541,11 @@ static const struct TCGCPUOps mips_tcg_ops = {
.synchronize_from_tb = mips_cpu_synchronize_from_tb,
.cpu_exec_interrupt = mips_cpu_exec_interrupt,
.tlb_fill = mips_cpu_tlb_fill,
+ .do_unaligned_access = mips_cpu_do_unaligned_access,
#if !defined(CONFIG_USER_ONLY)
.do_interrupt = mips_cpu_do_interrupt,
.do_transaction_failed = mips_cpu_do_transaction_failed,
- .do_unaligned_access = mips_cpu_do_unaligned_access,
.io_recompile_replay_branch = mips_io_recompile_replay_branch,
#endif /* !CONFIG_USER_ONLY */
};
diff --git a/target/mips/tcg/op_helper.c b/target/mips/tcg/op_helper.c
index fafbf1faca..0b874823e4 100644
--- a/target/mips/tcg/op_helper.c
+++ b/target/mips/tcg/op_helper.c
@@ -375,8 +375,6 @@ void helper_pmon(CPUMIPSState *env, int function)
}
}
-#if !defined(CONFIG_USER_ONLY)
-
void mips_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
MMUAccessType access_type,
int mmu_idx, uintptr_t retaddr)
@@ -402,6 +400,7 @@ void mips_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
do_raise_exception_err(env, excp, error_code, retaddr);
}
+#if !defined(CONFIG_USER_ONLY)
void mips_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
vaddr addr, unsigned size,
MMUAccessType access_type,
diff --git a/target/mips/tcg/user/tlb_helper.c b/target/mips/tcg/user/tlb_helper.c
index b835144b82..61a99356e9 100644
--- a/target/mips/tcg/user/tlb_helper.c
+++ b/target/mips/tcg/user/tlb_helper.c
@@ -26,24 +26,23 @@ static void raise_mmu_exception(CPUMIPSState *env, target_ulong address,
MMUAccessType access_type)
{
CPUState *cs = env_cpu(env);
+ int error_code = 0;
+ int flags;
- env->error_code = 0;
if (access_type == MMU_INST_FETCH) {
- env->error_code |= EXCP_INST_NOTAVAIL;
+ error_code |= EXCP_INST_NOTAVAIL;
}
- /* Reference to kernel address from user mode or supervisor mode */
- /* Reference to supervisor address from user mode */
- if (access_type == MMU_DATA_STORE) {
- cs->exception_index = EXCP_AdES;
- } else {
- cs->exception_index = EXCP_AdEL;
+ flags = page_get_flags(address);
+ if (!(flags & PAGE_VALID)) {
+ error_code |= EXCP_TLB_NOMATCH;
}
- /* Raise exception */
- if (!(env->hflags & MIPS_HFLAG_DM)) {
- env->CP0_BadVAddr = address;
- }
+ cs->exception_index = (access_type == MMU_DATA_STORE
+ ? EXCP_TLBS : EXCP_TLBL);
+
+ env->error_code = error_code;
+ env->CP0_BadVAddr = address;
}
bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
--
2.25.1
^ permalink raw reply related [flat|nested] 102+ messages in thread* [PATCH for-6.2 07/43] target/ppc: Set fault address in ppc_cpu_do_unaligned_access
2021-07-29 0:46 [PATCH for-6.2 00/43] Unaligned accesses for user-only Richard Henderson
` (5 preceding siblings ...)
2021-07-29 0:46 ` [PATCH for-6.2 06/43] target/mips: " Richard Henderson
@ 2021-07-29 0:46 ` Richard Henderson
2021-07-29 13:44 ` Peter Maydell
2021-07-30 16:58 ` Cédric Le Goater
2021-07-29 0:46 ` [PATCH for-6.2 08/43] target/ppc: Implement do_unaligned_access for user-only Richard Henderson
` (37 subsequent siblings)
44 siblings, 2 replies; 102+ messages in thread
From: Richard Henderson @ 2021-07-29 0:46 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-ppc
We ought to have been recording the virtual address for reporting
to the guest trap handler.
Cc: qemu-ppc@nongnu.org
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/ppc/excp_helper.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index a79a0ed465..0b2c6de442 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -1503,6 +1503,8 @@ void ppc_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr,
CPUPPCState *env = cs->env_ptr;
uint32_t insn;
+ env->spr[SPR_DAR] = vaddr;
+
/* Restore state and reload the insn we executed, for filling in DSISR. */
cpu_restore_state(cs, retaddr, true);
insn = cpu_ldl_code(env, env->nip);
--
2.25.1
^ permalink raw reply related [flat|nested] 102+ messages in thread* Re: [PATCH for-6.2 07/43] target/ppc: Set fault address in ppc_cpu_do_unaligned_access
2021-07-29 0:46 ` [PATCH for-6.2 07/43] target/ppc: Set fault address in ppc_cpu_do_unaligned_access Richard Henderson
@ 2021-07-29 13:44 ` Peter Maydell
2021-07-29 18:05 ` Richard Henderson
2021-07-30 16:58 ` Cédric Le Goater
1 sibling, 1 reply; 102+ messages in thread
From: Peter Maydell @ 2021-07-29 13:44 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-ppc, QEMU Developers
On Thu, 29 Jul 2021 at 01:51, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> We ought to have been recording the virtual address for reporting
> to the guest trap handler.
>
> Cc: qemu-ppc@nongnu.org
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/ppc/excp_helper.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
> index a79a0ed465..0b2c6de442 100644
> --- a/target/ppc/excp_helper.c
> +++ b/target/ppc/excp_helper.c
> @@ -1503,6 +1503,8 @@ void ppc_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr,
> CPUPPCState *env = cs->env_ptr;
> uint32_t insn;
>
> + env->spr[SPR_DAR] = vaddr;
> +
Is this the right SPR for all PPC variants? For instance the
kernel's code in arch/powerpc/kernel/exceptions-64e.S looks
in SPRN_DEAR, which is our SPR_BOOKE_DEAR or SPR_40x_DEAR.
-- PMM
^ permalink raw reply [flat|nested] 102+ messages in thread
* Re: [PATCH for-6.2 07/43] target/ppc: Set fault address in ppc_cpu_do_unaligned_access
2021-07-29 13:44 ` Peter Maydell
@ 2021-07-29 18:05 ` Richard Henderson
2021-07-30 17:13 ` Cédric Le Goater
0 siblings, 1 reply; 102+ messages in thread
From: Richard Henderson @ 2021-07-29 18:05 UTC (permalink / raw)
To: Peter Maydell; +Cc: qemu-ppc, QEMU Developers
On 7/29/21 3:44 AM, Peter Maydell wrote:
> On Thu, 29 Jul 2021 at 01:51, Richard Henderson
> <richard.henderson@linaro.org> wrote:
>>
>> We ought to have been recording the virtual address for reporting
>> to the guest trap handler.
>>
>> Cc: qemu-ppc@nongnu.org
>> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
>> ---
>> target/ppc/excp_helper.c | 2 ++
>> 1 file changed, 2 insertions(+)
>>
>> diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
>> index a79a0ed465..0b2c6de442 100644
>> --- a/target/ppc/excp_helper.c
>> +++ b/target/ppc/excp_helper.c
>> @@ -1503,6 +1503,8 @@ void ppc_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr,
>> CPUPPCState *env = cs->env_ptr;
>> uint32_t insn;
>>
>> + env->spr[SPR_DAR] = vaddr;
>> +
>
> Is this the right SPR for all PPC variants? For instance the
> kernel's code in arch/powerpc/kernel/exceptions-64e.S looks
> in SPRN_DEAR, which is our SPR_BOOKE_DEAR or SPR_40x_DEAR.
I have no idea. I glanced through a handful of the mmu's, and looked at the current BookS
docs, but that's certainly not all.
I'll note that if we do need to set different regs for different mmus, we'll probably want
to standardize on this one for user-only, like we did for the user-only copy of
ppc_cpu_tlb_fill.
r~
^ permalink raw reply [flat|nested] 102+ messages in thread
* Re: [PATCH for-6.2 07/43] target/ppc: Set fault address in ppc_cpu_do_unaligned_access
2021-07-29 18:05 ` Richard Henderson
@ 2021-07-30 17:13 ` Cédric Le Goater
2021-07-30 17:23 ` Cédric Le Goater
0 siblings, 1 reply; 102+ messages in thread
From: Cédric Le Goater @ 2021-07-30 17:13 UTC (permalink / raw)
To: Richard Henderson, Peter Maydell; +Cc: qemu-ppc, QEMU Developers
On 7/29/21 8:05 PM, Richard Henderson wrote:
> On 7/29/21 3:44 AM, Peter Maydell wrote:
>> On Thu, 29 Jul 2021 at 01:51, Richard Henderson
>> <richard.henderson@linaro.org> wrote:
>>>
>>> We ought to have been recording the virtual address for reporting
>>> to the guest trap handler.
>>>
>>> Cc: qemu-ppc@nongnu.org
>>> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
>>> ---
>>> target/ppc/excp_helper.c | 2 ++
>>> 1 file changed, 2 insertions(+)
>>>
>>> diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
>>> index a79a0ed465..0b2c6de442 100644
>>> --- a/target/ppc/excp_helper.c
>>> +++ b/target/ppc/excp_helper.c
>>> @@ -1503,6 +1503,8 @@ void ppc_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr,
>>> CPUPPCState *env = cs->env_ptr;
>>> uint32_t insn;
>>>
>>> + env->spr[SPR_DAR] = vaddr;
>>> +
>>
>> Is this the right SPR for all PPC variants? For instance the
>> kernel's code in arch/powerpc/kernel/exceptions-64e.S looks
>> in SPRN_DEAR, which is our SPR_BOOKE_DEAR or SPR_40x_DEAR.
Indeed :/
> I have no idea. I glanced through a handful of the mmu's, and looked at the current BookS docs, but that's certainly not all.
I took a look at some more and for instance, e300 uses DAR and e500, 405, 476 use DEAR.
DAR should be consistent over the server processors.
C.
>
> I'll note that if we do need to set different regs for different mmus, we'll probably want to standardize on this one for user-only, like we did for the user-only copy of ppc_cpu_tlb_fill.
>
>
> r~
>
^ permalink raw reply [flat|nested] 102+ messages in thread
* Re: [PATCH for-6.2 07/43] target/ppc: Set fault address in ppc_cpu_do_unaligned_access
2021-07-30 17:13 ` Cédric Le Goater
@ 2021-07-30 17:23 ` Cédric Le Goater
0 siblings, 0 replies; 102+ messages in thread
From: Cédric Le Goater @ 2021-07-30 17:23 UTC (permalink / raw)
To: Richard Henderson, Peter Maydell; +Cc: qemu-ppc, QEMU Developers
On 7/30/21 7:13 PM, Cédric Le Goater wrote:
> On 7/29/21 8:05 PM, Richard Henderson wrote:
>> On 7/29/21 3:44 AM, Peter Maydell wrote:
>>> On Thu, 29 Jul 2021 at 01:51, Richard Henderson
>>> <richard.henderson@linaro.org> wrote:
>>>>
>>>> We ought to have been recording the virtual address for reporting
>>>> to the guest trap handler.
>>>>
>>>> Cc: qemu-ppc@nongnu.org
>>>> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
>>>> ---
>>>> target/ppc/excp_helper.c | 2 ++
>>>> 1 file changed, 2 insertions(+)
>>>>
>>>> diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
>>>> index a79a0ed465..0b2c6de442 100644
>>>> --- a/target/ppc/excp_helper.c
>>>> +++ b/target/ppc/excp_helper.c
>>>> @@ -1503,6 +1503,8 @@ void ppc_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr,
>>>> CPUPPCState *env = cs->env_ptr;
>>>> uint32_t insn;
>>>>
>>>> + env->spr[SPR_DAR] = vaddr;
>>>> +
>>>
>>> Is this the right SPR for all PPC variants? For instance the
>>> kernel's code in arch/powerpc/kernel/exceptions-64e.S looks
>>> in SPRN_DEAR, which is our SPR_BOOKE_DEAR or SPR_40x_DEAR.
>
> Indeed :/
>
>> I have no idea. I glanced through a handful of the mmu's, and looked at the current BookS docs, but that's certainly not all.
>
> I took a look at some more and for instance, e300 uses DAR and e500, 405, 476 use DEAR.
>
> DAR should be consistent over the server processors.
and is_book3s_arch2x(env) is a good way to test.
Thanks,
C.
^ permalink raw reply [flat|nested] 102+ messages in thread
* Re: [PATCH for-6.2 07/43] target/ppc: Set fault address in ppc_cpu_do_unaligned_access
2021-07-29 0:46 ` [PATCH for-6.2 07/43] target/ppc: Set fault address in ppc_cpu_do_unaligned_access Richard Henderson
2021-07-29 13:44 ` Peter Maydell
@ 2021-07-30 16:58 ` Cédric Le Goater
1 sibling, 0 replies; 102+ messages in thread
From: Cédric Le Goater @ 2021-07-30 16:58 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: qemu-ppc
On 7/29/21 2:46 AM, Richard Henderson wrote:
> We ought to have been recording the virtual address for reporting
> to the guest trap handler.
>
> Cc: qemu-ppc@nongnu.org
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
> ---
> target/ppc/excp_helper.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
> index a79a0ed465..0b2c6de442 100644
> --- a/target/ppc/excp_helper.c
> +++ b/target/ppc/excp_helper.c
> @@ -1503,6 +1503,8 @@ void ppc_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr,
> CPUPPCState *env = cs->env_ptr;
> uint32_t insn;
>
> + env->spr[SPR_DAR] = vaddr;
> +
> /* Restore state and reload the insn we executed, for filling in DSISR. */
> cpu_restore_state(cs, retaddr, true);
> insn = cpu_ldl_code(env, env->nip);
>
^ permalink raw reply [flat|nested] 102+ messages in thread
* [PATCH for-6.2 08/43] target/ppc: Implement do_unaligned_access for user-only
2021-07-29 0:46 [PATCH for-6.2 00/43] Unaligned accesses for user-only Richard Henderson
` (6 preceding siblings ...)
2021-07-29 0:46 ` [PATCH for-6.2 07/43] target/ppc: Set fault address in ppc_cpu_do_unaligned_access Richard Henderson
@ 2021-07-29 0:46 ` Richard Henderson
2021-07-29 0:46 ` [PATCH for-6.2 09/43] target/riscv: " Richard Henderson
` (36 subsequent siblings)
44 siblings, 0 replies; 102+ messages in thread
From: Richard Henderson @ 2021-07-29 0:46 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-ppc
Cc: qemu-ppc@nongnu.org
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
linux-user/ppc/cpu_loop.c | 2 +-
target/ppc/cpu_init.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/linux-user/ppc/cpu_loop.c b/linux-user/ppc/cpu_loop.c
index fa91ea0eed..d72d30248b 100644
--- a/linux-user/ppc/cpu_loop.c
+++ b/linux-user/ppc/cpu_loop.c
@@ -165,7 +165,7 @@ void cpu_loop(CPUPPCState *env)
info.si_signo = TARGET_SIGBUS;
info.si_errno = 0;
info.si_code = TARGET_BUS_ADRALN;
- info._sifields._sigfault._addr = env->nip;
+ info._sifields._sigfault._addr = env->spr[SPR_DAR];
queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
break;
case POWERPC_EXCP_PROGRAM: /* Program exception */
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 505a0ed6ac..84fb6bbb83 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -9014,12 +9014,12 @@ static const struct TCGCPUOps ppc_tcg_ops = {
.initialize = ppc_translate_init,
.cpu_exec_interrupt = ppc_cpu_exec_interrupt,
.tlb_fill = ppc_cpu_tlb_fill,
+ .do_unaligned_access = ppc_cpu_do_unaligned_access,
#ifndef CONFIG_USER_ONLY
.do_interrupt = ppc_cpu_do_interrupt,
.cpu_exec_enter = ppc_cpu_exec_enter,
.cpu_exec_exit = ppc_cpu_exec_exit,
- .do_unaligned_access = ppc_cpu_do_unaligned_access,
#endif /* !CONFIG_USER_ONLY */
};
#endif /* CONFIG_TCG */
--
2.25.1
^ permalink raw reply related [flat|nested] 102+ messages in thread* [PATCH for-6.2 09/43] target/riscv: Implement do_unaligned_access for user-only
2021-07-29 0:46 [PATCH for-6.2 00/43] Unaligned accesses for user-only Richard Henderson
` (7 preceding siblings ...)
2021-07-29 0:46 ` [PATCH for-6.2 08/43] target/ppc: Implement do_unaligned_access for user-only Richard Henderson
@ 2021-07-29 0:46 ` Richard Henderson
2021-07-30 6:13 ` Alistair Francis
2021-07-29 0:46 ` [PATCH for-6.2 10/43] target/s390x: " Richard Henderson
` (35 subsequent siblings)
44 siblings, 1 reply; 102+ messages in thread
From: Richard Henderson @ 2021-07-29 0:46 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-riscv
Cc: qemu-riscv@nongnu.org
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
linux-user/riscv/cpu_loop.c | 7 +++++++
target/riscv/cpu.c | 2 +-
target/riscv/cpu_helper.c | 8 +++++++-
3 files changed, 15 insertions(+), 2 deletions(-)
diff --git a/linux-user/riscv/cpu_loop.c b/linux-user/riscv/cpu_loop.c
index 74a9628dc9..0428140d86 100644
--- a/linux-user/riscv/cpu_loop.c
+++ b/linux-user/riscv/cpu_loop.c
@@ -92,6 +92,13 @@ void cpu_loop(CPURISCVState *env)
sigcode = TARGET_SEGV_MAPERR;
sigaddr = env->badaddr;
break;
+ case RISCV_EXCP_INST_ADDR_MIS:
+ case RISCV_EXCP_LOAD_ADDR_MIS:
+ case RISCV_EXCP_STORE_AMO_ADDR_MIS:
+ signum = TARGET_SIGBUS;
+ sigcode = TARGET_BUS_ADRALN;
+ sigaddr = env->badaddr;
+ break;
case RISCV_EXCP_SEMIHOST:
env->gpr[xA0] = do_common_semihosting(cs);
env->pc += 4;
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 991a6bb760..591d17e62d 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -644,11 +644,11 @@ static const struct TCGCPUOps riscv_tcg_ops = {
.synchronize_from_tb = riscv_cpu_synchronize_from_tb,
.cpu_exec_interrupt = riscv_cpu_exec_interrupt,
.tlb_fill = riscv_cpu_tlb_fill,
+ .do_unaligned_access = riscv_cpu_do_unaligned_access,
#ifndef CONFIG_USER_ONLY
.do_interrupt = riscv_cpu_do_interrupt,
.do_transaction_failed = riscv_cpu_do_transaction_failed,
- .do_unaligned_access = riscv_cpu_do_unaligned_access,
#endif /* !CONFIG_USER_ONLY */
};
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 968cb8046f..a440b2834f 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -727,6 +727,7 @@ void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
riscv_cpu_two_stage_lookup(mmu_idx);
riscv_raise_exception(&cpu->env, cs->exception_index, retaddr);
}
+#endif /* !CONFIG_USER_ONLY */
void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
MMUAccessType access_type, int mmu_idx,
@@ -734,6 +735,7 @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
{
RISCVCPU *cpu = RISCV_CPU(cs);
CPURISCVState *env = &cpu->env;
+
switch (access_type) {
case MMU_INST_FETCH:
cs->exception_index = RISCV_EXCP_INST_ADDR_MIS;
@@ -748,11 +750,15 @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
g_assert_not_reached();
}
env->badaddr = addr;
+
+#ifdef CONFIG_USER_ONLY
+ cpu_loop_exit_restore(cs, retaddr);
+#else
env->two_stage_lookup = riscv_cpu_virt_enabled(env) ||
riscv_cpu_two_stage_lookup(mmu_idx);
riscv_raise_exception(env, cs->exception_index, retaddr);
+#endif
}
-#endif /* !CONFIG_USER_ONLY */
bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
MMUAccessType access_type, int mmu_idx,
--
2.25.1
^ permalink raw reply related [flat|nested] 102+ messages in thread* Re: [PATCH for-6.2 09/43] target/riscv: Implement do_unaligned_access for user-only
2021-07-29 0:46 ` [PATCH for-6.2 09/43] target/riscv: " Richard Henderson
@ 2021-07-30 6:13 ` Alistair Francis
0 siblings, 0 replies; 102+ messages in thread
From: Alistair Francis @ 2021-07-30 6:13 UTC (permalink / raw)
To: Richard Henderson; +Cc: open list:RISC-V, qemu-devel@nongnu.org Developers
On Thu, Jul 29, 2021 at 10:55 AM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Cc: qemu-riscv@nongnu.org
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> linux-user/riscv/cpu_loop.c | 7 +++++++
> target/riscv/cpu.c | 2 +-
> target/riscv/cpu_helper.c | 8 +++++++-
> 3 files changed, 15 insertions(+), 2 deletions(-)
>
> diff --git a/linux-user/riscv/cpu_loop.c b/linux-user/riscv/cpu_loop.c
> index 74a9628dc9..0428140d86 100644
> --- a/linux-user/riscv/cpu_loop.c
> +++ b/linux-user/riscv/cpu_loop.c
> @@ -92,6 +92,13 @@ void cpu_loop(CPURISCVState *env)
> sigcode = TARGET_SEGV_MAPERR;
> sigaddr = env->badaddr;
> break;
> + case RISCV_EXCP_INST_ADDR_MIS:
> + case RISCV_EXCP_LOAD_ADDR_MIS:
> + case RISCV_EXCP_STORE_AMO_ADDR_MIS:
> + signum = TARGET_SIGBUS;
> + sigcode = TARGET_BUS_ADRALN;
> + sigaddr = env->badaddr;
> + break;
> case RISCV_EXCP_SEMIHOST:
> env->gpr[xA0] = do_common_semihosting(cs);
> env->pc += 4;
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 991a6bb760..591d17e62d 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -644,11 +644,11 @@ static const struct TCGCPUOps riscv_tcg_ops = {
> .synchronize_from_tb = riscv_cpu_synchronize_from_tb,
> .cpu_exec_interrupt = riscv_cpu_exec_interrupt,
> .tlb_fill = riscv_cpu_tlb_fill,
> + .do_unaligned_access = riscv_cpu_do_unaligned_access,
>
> #ifndef CONFIG_USER_ONLY
> .do_interrupt = riscv_cpu_do_interrupt,
> .do_transaction_failed = riscv_cpu_do_transaction_failed,
> - .do_unaligned_access = riscv_cpu_do_unaligned_access,
> #endif /* !CONFIG_USER_ONLY */
> };
>
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index 968cb8046f..a440b2834f 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -727,6 +727,7 @@ void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
> riscv_cpu_two_stage_lookup(mmu_idx);
> riscv_raise_exception(&cpu->env, cs->exception_index, retaddr);
> }
> +#endif /* !CONFIG_USER_ONLY */
>
> void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
> MMUAccessType access_type, int mmu_idx,
> @@ -734,6 +735,7 @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
> {
> RISCVCPU *cpu = RISCV_CPU(cs);
> CPURISCVState *env = &cpu->env;
> +
> switch (access_type) {
> case MMU_INST_FETCH:
> cs->exception_index = RISCV_EXCP_INST_ADDR_MIS;
> @@ -748,11 +750,15 @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
> g_assert_not_reached();
> }
> env->badaddr = addr;
> +
> +#ifdef CONFIG_USER_ONLY
> + cpu_loop_exit_restore(cs, retaddr);
> +#else
> env->two_stage_lookup = riscv_cpu_virt_enabled(env) ||
> riscv_cpu_two_stage_lookup(mmu_idx);
> riscv_raise_exception(env, cs->exception_index, retaddr);
> +#endif
> }
> -#endif /* !CONFIG_USER_ONLY */
>
> bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
> MMUAccessType access_type, int mmu_idx,
> --
> 2.25.1
>
>
^ permalink raw reply [flat|nested] 102+ messages in thread* Re: [PATCH for-6.2 09/43] target/riscv: Implement do_unaligned_access for user-only
@ 2021-07-30 6:13 ` Alistair Francis
0 siblings, 0 replies; 102+ messages in thread
From: Alistair Francis @ 2021-07-30 6:13 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel@nongnu.org Developers, open list:RISC-V
On Thu, Jul 29, 2021 at 10:55 AM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Cc: qemu-riscv@nongnu.org
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> linux-user/riscv/cpu_loop.c | 7 +++++++
> target/riscv/cpu.c | 2 +-
> target/riscv/cpu_helper.c | 8 +++++++-
> 3 files changed, 15 insertions(+), 2 deletions(-)
>
> diff --git a/linux-user/riscv/cpu_loop.c b/linux-user/riscv/cpu_loop.c
> index 74a9628dc9..0428140d86 100644
> --- a/linux-user/riscv/cpu_loop.c
> +++ b/linux-user/riscv/cpu_loop.c
> @@ -92,6 +92,13 @@ void cpu_loop(CPURISCVState *env)
> sigcode = TARGET_SEGV_MAPERR;
> sigaddr = env->badaddr;
> break;
> + case RISCV_EXCP_INST_ADDR_MIS:
> + case RISCV_EXCP_LOAD_ADDR_MIS:
> + case RISCV_EXCP_STORE_AMO_ADDR_MIS:
> + signum = TARGET_SIGBUS;
> + sigcode = TARGET_BUS_ADRALN;
> + sigaddr = env->badaddr;
> + break;
> case RISCV_EXCP_SEMIHOST:
> env->gpr[xA0] = do_common_semihosting(cs);
> env->pc += 4;
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 991a6bb760..591d17e62d 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -644,11 +644,11 @@ static const struct TCGCPUOps riscv_tcg_ops = {
> .synchronize_from_tb = riscv_cpu_synchronize_from_tb,
> .cpu_exec_interrupt = riscv_cpu_exec_interrupt,
> .tlb_fill = riscv_cpu_tlb_fill,
> + .do_unaligned_access = riscv_cpu_do_unaligned_access,
>
> #ifndef CONFIG_USER_ONLY
> .do_interrupt = riscv_cpu_do_interrupt,
> .do_transaction_failed = riscv_cpu_do_transaction_failed,
> - .do_unaligned_access = riscv_cpu_do_unaligned_access,
> #endif /* !CONFIG_USER_ONLY */
> };
>
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index 968cb8046f..a440b2834f 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -727,6 +727,7 @@ void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
> riscv_cpu_two_stage_lookup(mmu_idx);
> riscv_raise_exception(&cpu->env, cs->exception_index, retaddr);
> }
> +#endif /* !CONFIG_USER_ONLY */
>
> void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
> MMUAccessType access_type, int mmu_idx,
> @@ -734,6 +735,7 @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
> {
> RISCVCPU *cpu = RISCV_CPU(cs);
> CPURISCVState *env = &cpu->env;
> +
> switch (access_type) {
> case MMU_INST_FETCH:
> cs->exception_index = RISCV_EXCP_INST_ADDR_MIS;
> @@ -748,11 +750,15 @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
> g_assert_not_reached();
> }
> env->badaddr = addr;
> +
> +#ifdef CONFIG_USER_ONLY
> + cpu_loop_exit_restore(cs, retaddr);
> +#else
> env->two_stage_lookup = riscv_cpu_virt_enabled(env) ||
> riscv_cpu_two_stage_lookup(mmu_idx);
> riscv_raise_exception(env, cs->exception_index, retaddr);
> +#endif
> }
> -#endif /* !CONFIG_USER_ONLY */
>
> bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
> MMUAccessType access_type, int mmu_idx,
> --
> 2.25.1
>
>
^ permalink raw reply [flat|nested] 102+ messages in thread
* [PATCH for-6.2 10/43] target/s390x: Implement do_unaligned_access for user-only
2021-07-29 0:46 [PATCH for-6.2 00/43] Unaligned accesses for user-only Richard Henderson
` (8 preceding siblings ...)
2021-07-29 0:46 ` [PATCH for-6.2 09/43] target/riscv: " Richard Henderson
@ 2021-07-29 0:46 ` Richard Henderson
2021-07-29 8:03 ` David Hildenbrand
2021-07-29 0:46 ` [PATCH for-6.2 11/43] target/sh4: Set fault address in superh_cpu_do_unaligned_access Richard Henderson
` (34 subsequent siblings)
44 siblings, 1 reply; 102+ messages in thread
From: Richard Henderson @ 2021-07-29 0:46 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-s390x
Cc: qemu-s390x@nongnu.org
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/s390x/cpu.c | 2 +-
target/s390x/tcg/excp_helper.c | 28 +++++++++++++++-------------
2 files changed, 16 insertions(+), 14 deletions(-)
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
index 7b7b05f1d3..9d8cfb37cd 100644
--- a/target/s390x/cpu.c
+++ b/target/s390x/cpu.c
@@ -267,12 +267,12 @@ static void s390_cpu_reset_full(DeviceState *dev)
static const struct TCGCPUOps s390_tcg_ops = {
.initialize = s390x_translate_init,
.tlb_fill = s390_cpu_tlb_fill,
+ .do_unaligned_access = s390x_cpu_do_unaligned_access,
#if !defined(CONFIG_USER_ONLY)
.cpu_exec_interrupt = s390_cpu_exec_interrupt,
.do_interrupt = s390_cpu_do_interrupt,
.debug_excp_handler = s390x_cpu_debug_excp_handler,
- .do_unaligned_access = s390x_cpu_do_unaligned_access,
#endif /* !CONFIG_USER_ONLY */
};
#endif /* CONFIG_TCG */
diff --git a/target/s390x/tcg/excp_helper.c b/target/s390x/tcg/excp_helper.c
index a61917d04f..9cbe160f66 100644
--- a/target/s390x/tcg/excp_helper.c
+++ b/target/s390x/tcg/excp_helper.c
@@ -82,6 +82,21 @@ void HELPER(data_exception)(CPUS390XState *env, uint32_t dxc)
tcg_s390_data_exception(env, dxc, GETPC());
}
+/*
+ * Unaligned accesses are only diagnosed with MO_ALIGN. At the moment,
+ * this is only for the atomic operations, for which we want to raise a
+ * specification exception.
+ */
+void s390x_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
+ MMUAccessType access_type,
+ int mmu_idx, uintptr_t retaddr)
+{
+ S390CPU *cpu = S390_CPU(cs);
+ CPUS390XState *env = &cpu->env;
+
+ tcg_s390_program_interrupt(env, PGM_SPECIFICATION, retaddr);
+}
+
#if defined(CONFIG_USER_ONLY)
void s390_cpu_do_interrupt(CPUState *cs)
@@ -602,19 +617,6 @@ void s390x_cpu_debug_excp_handler(CPUState *cs)
}
}
-/* Unaligned accesses are only diagnosed with MO_ALIGN. At the moment,
- this is only for the atomic operations, for which we want to raise a
- specification exception. */
-void s390x_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
- MMUAccessType access_type,
- int mmu_idx, uintptr_t retaddr)
-{
- S390CPU *cpu = S390_CPU(cs);
- CPUS390XState *env = &cpu->env;
-
- tcg_s390_program_interrupt(env, PGM_SPECIFICATION, retaddr);
-}
-
static void QEMU_NORETURN monitor_event(CPUS390XState *env,
uint64_t monitor_code,
uint8_t monitor_class, uintptr_t ra)
--
2.25.1
^ permalink raw reply related [flat|nested] 102+ messages in thread* Re: [PATCH for-6.2 10/43] target/s390x: Implement do_unaligned_access for user-only
2021-07-29 0:46 ` [PATCH for-6.2 10/43] target/s390x: " Richard Henderson
@ 2021-07-29 8:03 ` David Hildenbrand
0 siblings, 0 replies; 102+ messages in thread
From: David Hildenbrand @ 2021-07-29 8:03 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: qemu-s390x
On 29.07.21 02:46, Richard Henderson wrote:
> Cc: qemu-s390x@nongnu.org
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/s390x/cpu.c | 2 +-
> target/s390x/tcg/excp_helper.c | 28 +++++++++++++++-------------
> 2 files changed, 16 insertions(+), 14 deletions(-)
>
> diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
> index 7b7b05f1d3..9d8cfb37cd 100644
> --- a/target/s390x/cpu.c
> +++ b/target/s390x/cpu.c
> @@ -267,12 +267,12 @@ static void s390_cpu_reset_full(DeviceState *dev)
> static const struct TCGCPUOps s390_tcg_ops = {
> .initialize = s390x_translate_init,
> .tlb_fill = s390_cpu_tlb_fill,
> + .do_unaligned_access = s390x_cpu_do_unaligned_access,
>
> #if !defined(CONFIG_USER_ONLY)
> .cpu_exec_interrupt = s390_cpu_exec_interrupt,
> .do_interrupt = s390_cpu_do_interrupt,
> .debug_excp_handler = s390x_cpu_debug_excp_handler,
> - .do_unaligned_access = s390x_cpu_do_unaligned_access,
> #endif /* !CONFIG_USER_ONLY */
> };
> #endif /* CONFIG_TCG */
> diff --git a/target/s390x/tcg/excp_helper.c b/target/s390x/tcg/excp_helper.c
> index a61917d04f..9cbe160f66 100644
> --- a/target/s390x/tcg/excp_helper.c
> +++ b/target/s390x/tcg/excp_helper.c
> @@ -82,6 +82,21 @@ void HELPER(data_exception)(CPUS390XState *env, uint32_t dxc)
> tcg_s390_data_exception(env, dxc, GETPC());
> }
>
> +/*
> + * Unaligned accesses are only diagnosed with MO_ALIGN. At the moment,
> + * this is only for the atomic operations, for which we want to raise a
> + * specification exception.
> + */
> +void s390x_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
> + MMUAccessType access_type,
> + int mmu_idx, uintptr_t retaddr)
> +{
> + S390CPU *cpu = S390_CPU(cs);
> + CPUS390XState *env = &cpu->env;
> +
> + tcg_s390_program_interrupt(env, PGM_SPECIFICATION, retaddr);
> +}
> +
> #if defined(CONFIG_USER_ONLY)
>
> void s390_cpu_do_interrupt(CPUState *cs)
> @@ -602,19 +617,6 @@ void s390x_cpu_debug_excp_handler(CPUState *cs)
> }
> }
>
> -/* Unaligned accesses are only diagnosed with MO_ALIGN. At the moment,
> - this is only for the atomic operations, for which we want to raise a
> - specification exception. */
> -void s390x_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
> - MMUAccessType access_type,
> - int mmu_idx, uintptr_t retaddr)
> -{
> - S390CPU *cpu = S390_CPU(cs);
> - CPUS390XState *env = &cpu->env;
> -
> - tcg_s390_program_interrupt(env, PGM_SPECIFICATION, retaddr);
> -}
> -
> static void QEMU_NORETURN monitor_event(CPUS390XState *env,
> uint64_t monitor_code,
> uint8_t monitor_class, uintptr_t ra)
>
Reviewed-by: David Hildenbrand <david@redhat.com>
--
Thanks,
David / dhildenb
^ permalink raw reply [flat|nested] 102+ messages in thread
* [PATCH for-6.2 11/43] target/sh4: Set fault address in superh_cpu_do_unaligned_access
2021-07-29 0:46 [PATCH for-6.2 00/43] Unaligned accesses for user-only Richard Henderson
` (9 preceding siblings ...)
2021-07-29 0:46 ` [PATCH for-6.2 10/43] target/s390x: " Richard Henderson
@ 2021-07-29 0:46 ` Richard Henderson
2021-07-29 6:15 ` Philippe Mathieu-Daudé
2021-07-29 0:46 ` [PATCH for-6.2 12/43] target/sh4: Implement do_unaligned_access for user-only Richard Henderson
` (33 subsequent siblings)
44 siblings, 1 reply; 102+ messages in thread
From: Richard Henderson @ 2021-07-29 0:46 UTC (permalink / raw)
To: qemu-devel; +Cc: Yoshinori Sato
We ought to have been recording the virtual address for reporting
to the guest trap handler.
Cc: Yoshinori Sato <ysato@users.sourceforge.jp>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/sh4/op_helper.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/target/sh4/op_helper.c b/target/sh4/op_helper.c
index c0cbb95382..d6d70c339f 100644
--- a/target/sh4/op_helper.c
+++ b/target/sh4/op_helper.c
@@ -29,6 +29,9 @@ void superh_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
MMUAccessType access_type,
int mmu_idx, uintptr_t retaddr)
{
+ CPUSH4State *env = cs->env_ptr;
+
+ env->tea = addr;
switch (access_type) {
case MMU_INST_FETCH:
case MMU_DATA_LOAD:
@@ -37,6 +40,8 @@ void superh_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
case MMU_DATA_STORE:
cs->exception_index = 0x100;
break;
+ default:
+ g_assert_not_reached();
}
cpu_loop_exit_restore(cs, retaddr);
}
--
2.25.1
^ permalink raw reply related [flat|nested] 102+ messages in thread* [PATCH for-6.2 12/43] target/sh4: Implement do_unaligned_access for user-only
2021-07-29 0:46 [PATCH for-6.2 00/43] Unaligned accesses for user-only Richard Henderson
` (10 preceding siblings ...)
2021-07-29 0:46 ` [PATCH for-6.2 11/43] target/sh4: Set fault address in superh_cpu_do_unaligned_access Richard Henderson
@ 2021-07-29 0:46 ` Richard Henderson
2021-07-29 13:52 ` Peter Maydell
2021-07-29 0:46 ` [PATCH for-6.2 13/43] target/sparc: Remove DEBUG_UNALIGNED Richard Henderson
` (32 subsequent siblings)
44 siblings, 1 reply; 102+ messages in thread
From: Richard Henderson @ 2021-07-29 0:46 UTC (permalink / raw)
To: qemu-devel; +Cc: Yoshinori Sato
Cc: Yoshinori Sato <ysato@users.sourceforge.jp>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
linux-user/sh4/cpu_loop.c | 8 ++++++++
target/sh4/cpu.c | 2 +-
target/sh4/op_helper.c | 3 ---
3 files changed, 9 insertions(+), 4 deletions(-)
diff --git a/linux-user/sh4/cpu_loop.c b/linux-user/sh4/cpu_loop.c
index 222ed1c670..21d97250a8 100644
--- a/linux-user/sh4/cpu_loop.c
+++ b/linux-user/sh4/cpu_loop.c
@@ -71,6 +71,14 @@ void cpu_loop(CPUSH4State *env)
info._sifields._sigfault._addr = env->tea;
queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
break;
+ case 0xe0:
+ case 0x100:
+ info.si_signo = TARGET_SIGBUS;
+ info.si_errno = 0;
+ info.si_code = TARGET_BUS_ADRALN;
+ info._sifields._sigfault._addr = env->tea;
+ queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
+ break;
case EXCP_ATOMIC:
cpu_exec_step_atomic(cs);
arch_interrupt = false;
diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c
index 8326922942..b60234cd31 100644
--- a/target/sh4/cpu.c
+++ b/target/sh4/cpu.c
@@ -238,10 +238,10 @@ static const struct TCGCPUOps superh_tcg_ops = {
.synchronize_from_tb = superh_cpu_synchronize_from_tb,
.cpu_exec_interrupt = superh_cpu_exec_interrupt,
.tlb_fill = superh_cpu_tlb_fill,
+ .do_unaligned_access = superh_cpu_do_unaligned_access,
#ifndef CONFIG_USER_ONLY
.do_interrupt = superh_cpu_do_interrupt,
- .do_unaligned_access = superh_cpu_do_unaligned_access,
.io_recompile_replay_branch = superh_io_recompile_replay_branch,
#endif /* !CONFIG_USER_ONLY */
};
diff --git a/target/sh4/op_helper.c b/target/sh4/op_helper.c
index d6d70c339f..b46fc1bf11 100644
--- a/target/sh4/op_helper.c
+++ b/target/sh4/op_helper.c
@@ -23,7 +23,6 @@
#include "exec/cpu_ldst.h"
#include "fpu/softfloat.h"
-#ifndef CONFIG_USER_ONLY
void superh_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
MMUAccessType access_type,
@@ -46,8 +45,6 @@ void superh_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
cpu_loop_exit_restore(cs, retaddr);
}
-#endif
-
void helper_ldtlb(CPUSH4State *env)
{
#ifdef CONFIG_USER_ONLY
--
2.25.1
^ permalink raw reply related [flat|nested] 102+ messages in thread* Re: [PATCH for-6.2 12/43] target/sh4: Implement do_unaligned_access for user-only
2021-07-29 0:46 ` [PATCH for-6.2 12/43] target/sh4: Implement do_unaligned_access for user-only Richard Henderson
@ 2021-07-29 13:52 ` Peter Maydell
2021-07-30 0:01 ` Richard Henderson
2021-07-30 20:54 ` Rob Landley
0 siblings, 2 replies; 102+ messages in thread
From: Peter Maydell @ 2021-07-29 13:52 UTC (permalink / raw)
To: Richard Henderson; +Cc: QEMU Developers, Yoshinori Sato
On Thu, 29 Jul 2021 at 02:01, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Cc: Yoshinori Sato <ysato@users.sourceforge.jp>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> linux-user/sh4/cpu_loop.c | 8 ++++++++
> target/sh4/cpu.c | 2 +-
> target/sh4/op_helper.c | 3 ---
> 3 files changed, 9 insertions(+), 4 deletions(-)
>
> diff --git a/linux-user/sh4/cpu_loop.c b/linux-user/sh4/cpu_loop.c
> index 222ed1c670..21d97250a8 100644
> --- a/linux-user/sh4/cpu_loop.c
> +++ b/linux-user/sh4/cpu_loop.c
> @@ -71,6 +71,14 @@ void cpu_loop(CPUSH4State *env)
> info._sifields._sigfault._addr = env->tea;
> queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
> break;
> + case 0xe0:
> + case 0x100:
> + info.si_signo = TARGET_SIGBUS;
> + info.si_errno = 0;
> + info.si_code = TARGET_BUS_ADRALN;
> + info._sifields._sigfault._addr = env->tea;
> + queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
> + break;
sh4 kernel default for unaligned accesses seems to be "warn and fixup",
not SIGBUS, unless the user changes that by writing to /proc/cpu/alignment
or the process changes it via prctl().
-- PMM
^ permalink raw reply [flat|nested] 102+ messages in thread
* Re: [PATCH for-6.2 12/43] target/sh4: Implement do_unaligned_access for user-only
2021-07-29 13:52 ` Peter Maydell
@ 2021-07-30 0:01 ` Richard Henderson
2021-07-30 20:54 ` Rob Landley
1 sibling, 0 replies; 102+ messages in thread
From: Richard Henderson @ 2021-07-30 0:01 UTC (permalink / raw)
To: Peter Maydell; +Cc: QEMU Developers, Yoshinori Sato, Linux-sh list
On 7/29/21 3:52 AM, Peter Maydell wrote:
> sh4 kernel default for unaligned accesses seems to be "warn and fixup",
> not SIGBUS, unless the user changes that by writing to /proc/cpu/alignment
> or the process changes it via prctl().
We will still need this for load-locked/store-conditional (MOVLI/MOVCO).
It appears that the sh4 kernel fails to decode these properly, and will do something ugly,
like interpreting MOVLI as a multiple-store instead of a load.
There are also other instructions that the kernel does not attempt to handle, such as MAC.
I suppose we could begin with turning off TARGET_ALIGNED_ONLY for sh4-linux-user, then
re-enabling MO_ALIGN for the atomics (at least).
r~
^ permalink raw reply [flat|nested] 102+ messages in thread
* Re: [PATCH for-6.2 12/43] target/sh4: Implement do_unaligned_access for user-only
2021-07-29 13:52 ` Peter Maydell
2021-07-30 0:01 ` Richard Henderson
@ 2021-07-30 20:54 ` Rob Landley
1 sibling, 0 replies; 102+ messages in thread
From: Rob Landley @ 2021-07-30 20:54 UTC (permalink / raw)
To: Peter Maydell, Richard Henderson, D. Jeff Dionne, Rich Felker
Cc: QEMU Developers, Yoshinori Sato
On 7/29/21 8:52 AM, Peter Maydell wrote:
> On Thu, 29 Jul 2021 at 02:01, Richard Henderson
> <richard.henderson@linaro.org> wrote:
>>
>> Cc: Yoshinori Sato <ysato@users.sourceforge.jp>
>> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
>> ---
>> linux-user/sh4/cpu_loop.c | 8 ++++++++
>> target/sh4/cpu.c | 2 +-
>> target/sh4/op_helper.c | 3 ---
>> 3 files changed, 9 insertions(+), 4 deletions(-)
>>
>> diff --git a/linux-user/sh4/cpu_loop.c b/linux-user/sh4/cpu_loop.c
>> index 222ed1c670..21d97250a8 100644
>> --- a/linux-user/sh4/cpu_loop.c
>> +++ b/linux-user/sh4/cpu_loop.c
>> @@ -71,6 +71,14 @@ void cpu_loop(CPUSH4State *env)
>> info._sifields._sigfault._addr = env->tea;
>> queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
>> break;
>> + case 0xe0:
>> + case 0x100:
>> + info.si_signo = TARGET_SIGBUS;
>> + info.si_errno = 0;
>> + info.si_code = TARGET_BUS_ADRALN;
>> + info._sifields._sigfault._addr = env->tea;
>> + queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
>> + break;
>
> sh4 kernel default for unaligned accesses seems to be "warn and fixup",
> not SIGBUS, unless the user changes that by writing to /proc/cpu/alignment
> or the process changes it via prctl().
It's still good to know, qemu-sh4 runs j-core binaries but that target doesn't
have unaligned interrupts yet. (I think it just masks off the bottom 2 bits to
do the next lowest aligned access? It's an sh2 variant and the plumbing to let
interrupts restart multi-clock instructions is only in the j32 branch so far, so
the j2 and ice40 targets don't generate interrupts for it. Todo item, in the
meantime we need to clean unaligned access out of application code so faulting
on it is good.)
> -- PMM
Thanks,
Rob
^ permalink raw reply [flat|nested] 102+ messages in thread
* [PATCH for-6.2 13/43] target/sparc: Remove DEBUG_UNALIGNED
2021-07-29 0:46 [PATCH for-6.2 00/43] Unaligned accesses for user-only Richard Henderson
` (11 preceding siblings ...)
2021-07-29 0:46 ` [PATCH for-6.2 12/43] target/sh4: Implement do_unaligned_access for user-only Richard Henderson
@ 2021-07-29 0:46 ` Richard Henderson
2021-07-29 6:16 ` Philippe Mathieu-Daudé
2021-07-29 0:46 ` [PATCH for-6.2 14/43] target/sparc: Set fault address in sparc_cpu_do_unaligned_access Richard Henderson
` (31 subsequent siblings)
44 siblings, 1 reply; 102+ messages in thread
From: Richard Henderson @ 2021-07-29 0:46 UTC (permalink / raw)
To: qemu-devel; +Cc: Mark Cave-Ayland
The printf should have been qemu_log_mask, the parameters
themselves no longer compile, and because this is placed
before unwinding the PC is actively wrong.
We get better (and correct) logging on the other side of
raising the exception, in sparc_cpu_do_interrupt.
Cc: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/sparc/ldst_helper.c | 9 ---------
1 file changed, 9 deletions(-)
diff --git a/target/sparc/ldst_helper.c b/target/sparc/ldst_helper.c
index 22327d7d72..974afea041 100644
--- a/target/sparc/ldst_helper.c
+++ b/target/sparc/ldst_helper.c
@@ -27,7 +27,6 @@
//#define DEBUG_MMU
//#define DEBUG_MXCC
-//#define DEBUG_UNALIGNED
//#define DEBUG_UNASSIGNED
//#define DEBUG_ASI
//#define DEBUG_CACHE_CONTROL
@@ -364,10 +363,6 @@ static void do_check_align(CPUSPARCState *env, target_ulong addr,
uint32_t align, uintptr_t ra)
{
if (addr & align) {
-#ifdef DEBUG_UNALIGNED
- printf("Unaligned access to 0x" TARGET_FMT_lx " from 0x" TARGET_FMT_lx
- "\n", addr, env->pc);
-#endif
cpu_raise_exception_ra(env, TT_UNALIGNED, ra);
}
}
@@ -1968,10 +1963,6 @@ void QEMU_NORETURN sparc_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
SPARCCPU *cpu = SPARC_CPU(cs);
CPUSPARCState *env = &cpu->env;
-#ifdef DEBUG_UNALIGNED
- printf("Unaligned access to 0x" TARGET_FMT_lx " from 0x" TARGET_FMT_lx
- "\n", addr, env->pc);
-#endif
cpu_raise_exception_ra(env, TT_UNALIGNED, retaddr);
}
#endif
--
2.25.1
^ permalink raw reply related [flat|nested] 102+ messages in thread* Re: [PATCH for-6.2 13/43] target/sparc: Remove DEBUG_UNALIGNED
2021-07-29 0:46 ` [PATCH for-6.2 13/43] target/sparc: Remove DEBUG_UNALIGNED Richard Henderson
@ 2021-07-29 6:16 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 102+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-07-29 6:16 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: Mark Cave-Ayland
On 7/29/21 2:46 AM, Richard Henderson wrote:
> The printf should have been qemu_log_mask, the parameters
> themselves no longer compile, and because this is placed
> before unwinding the PC is actively wrong.
>
> We get better (and correct) logging on the other side of
> raising the exception, in sparc_cpu_do_interrupt.
>
> Cc: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/sparc/ldst_helper.c | 9 ---------
> 1 file changed, 9 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
^ permalink raw reply [flat|nested] 102+ messages in thread
* [PATCH for-6.2 14/43] target/sparc: Set fault address in sparc_cpu_do_unaligned_access
2021-07-29 0:46 [PATCH for-6.2 00/43] Unaligned accesses for user-only Richard Henderson
` (12 preceding siblings ...)
2021-07-29 0:46 ` [PATCH for-6.2 13/43] target/sparc: Remove DEBUG_UNALIGNED Richard Henderson
@ 2021-07-29 0:46 ` Richard Henderson
2021-07-29 14:51 ` Peter Maydell
2021-07-29 0:46 ` [PATCH for-6.2 15/43] target/sparc: Implement do_unaligned_access for user-only Richard Henderson
` (30 subsequent siblings)
44 siblings, 1 reply; 102+ messages in thread
From: Richard Henderson @ 2021-07-29 0:46 UTC (permalink / raw)
To: qemu-devel; +Cc: Mark Cave-Ayland
We ought to have been recording the virtual address for reporting
to the guest trap handler. Mirror the SFSR FIXME from the sparc64
version of get_physical_address_data.
Cc: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/sparc/ldst_helper.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/target/sparc/ldst_helper.c b/target/sparc/ldst_helper.c
index 974afea041..7367b48c8b 100644
--- a/target/sparc/ldst_helper.c
+++ b/target/sparc/ldst_helper.c
@@ -1963,6 +1963,14 @@ void QEMU_NORETURN sparc_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
SPARCCPU *cpu = SPARC_CPU(cs);
CPUSPARCState *env = &cpu->env;
+#ifdef TARGET_SPARC64
+ /* FIXME: ASI field in SFSR must be set */
+ env->dmmu.sfsr = SFSR_VALID_BIT; /* Fault status register */
+ env->dmmu.sfar = addr; /* Fault address register */
+#else
+ env->mmuregs[4] = addr;
+#endif
+
cpu_raise_exception_ra(env, TT_UNALIGNED, retaddr);
}
#endif
--
2.25.1
^ permalink raw reply related [flat|nested] 102+ messages in thread* Re: [PATCH for-6.2 14/43] target/sparc: Set fault address in sparc_cpu_do_unaligned_access
2021-07-29 0:46 ` [PATCH for-6.2 14/43] target/sparc: Set fault address in sparc_cpu_do_unaligned_access Richard Henderson
@ 2021-07-29 14:51 ` Peter Maydell
2021-08-01 15:56 ` Mark Cave-Ayland
0 siblings, 1 reply; 102+ messages in thread
From: Peter Maydell @ 2021-07-29 14:51 UTC (permalink / raw)
To: Richard Henderson; +Cc: Mark Cave-Ayland, QEMU Developers
On Thu, 29 Jul 2021 at 02:01, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> We ought to have been recording the virtual address for reporting
> to the guest trap handler. Mirror the SFSR FIXME from the sparc64
> version of get_physical_address_data.
>
> Cc: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/sparc/ldst_helper.c | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/target/sparc/ldst_helper.c b/target/sparc/ldst_helper.c
> index 974afea041..7367b48c8b 100644
> --- a/target/sparc/ldst_helper.c
> +++ b/target/sparc/ldst_helper.c
> @@ -1963,6 +1963,14 @@ void QEMU_NORETURN sparc_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
> SPARCCPU *cpu = SPARC_CPU(cs);
> CPUSPARCState *env = &cpu->env;
>
> +#ifdef TARGET_SPARC64
> + /* FIXME: ASI field in SFSR must be set */
> + env->dmmu.sfsr = SFSR_VALID_BIT; /* Fault status register */
> + env->dmmu.sfar = addr; /* Fault address register */
> +#else
> + env->mmuregs[4] = addr;
> +#endif
> +
> cpu_raise_exception_ra(env, TT_UNALIGNED, retaddr);
> }
> #endif
The architecture manual seems to be gratuitously opaque about
whether and where the fault address for an alignment fault gets
recorded, but Linux at least for 64-bit seems to pull it out of the
sfar, so I guess that's right.
We probably ought to have the "if SFSR_VALID_BIT already set,
set the OW bit". MMUAccessType and mmu_idx give us enough to
set the CT bits and the WRITE bit in the same way we do at
the start of get_physical_address_data().
-- PMM
^ permalink raw reply [flat|nested] 102+ messages in thread
* Re: [PATCH for-6.2 14/43] target/sparc: Set fault address in sparc_cpu_do_unaligned_access
2021-07-29 14:51 ` Peter Maydell
@ 2021-08-01 15:56 ` Mark Cave-Ayland
2021-08-01 15:59 ` Peter Maydell
0 siblings, 1 reply; 102+ messages in thread
From: Mark Cave-Ayland @ 2021-08-01 15:56 UTC (permalink / raw)
To: Peter Maydell, Richard Henderson; +Cc: QEMU Developers
On 29/07/2021 15:51, Peter Maydell wrote:
> On Thu, 29 Jul 2021 at 02:01, Richard Henderson
> <richard.henderson@linaro.org> wrote:
>>
>> We ought to have been recording the virtual address for reporting
>> to the guest trap handler. Mirror the SFSR FIXME from the sparc64
>> version of get_physical_address_data.
>>
>> Cc: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
>> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
>> ---
>> target/sparc/ldst_helper.c | 8 ++++++++
>> 1 file changed, 8 insertions(+)
>>
>> diff --git a/target/sparc/ldst_helper.c b/target/sparc/ldst_helper.c
>> index 974afea041..7367b48c8b 100644
>> --- a/target/sparc/ldst_helper.c
>> +++ b/target/sparc/ldst_helper.c
>> @@ -1963,6 +1963,14 @@ void QEMU_NORETURN sparc_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
>> SPARCCPU *cpu = SPARC_CPU(cs);
>> CPUSPARCState *env = &cpu->env;
>>
>> +#ifdef TARGET_SPARC64
>> + /* FIXME: ASI field in SFSR must be set */
>> + env->dmmu.sfsr = SFSR_VALID_BIT; /* Fault status register */
>> + env->dmmu.sfar = addr; /* Fault address register */
>> +#else
>> + env->mmuregs[4] = addr;
>> +#endif
>> +
>> cpu_raise_exception_ra(env, TT_UNALIGNED, retaddr);
>> }
>> #endif
>
> The architecture manual seems to be gratuitously opaque about
> whether and where the fault address for an alignment fault gets
> recorded, but Linux at least for 64-bit seems to pull it out of the
> sfar, so I guess that's right.
Yeah, this part is actually contained within the UltraSPARC II specification - it can
be found in section 6.4 "MMU-Related Faults and Traps" table 6-3 which indicates that
for *_mem_address_not_aligned traps the D-SFSR and SFAR registers within the MMU are
updated.
> We probably ought to have the "if SFSR_VALID_BIT already set,
> set the OW bit". MMUAccessType and mmu_idx give us enough to
> set the CT bits and the WRITE bit in the same way we do at
> the start of get_physical_address_data().
This sounds correct too from reading over section 6.9.4 "I-/D-MMU Synchronous Fault
Status Registers (SFSR)". I'm going to be fairly busy with $DAYJOB for the next
couple of weeks so it's going to be a little while before I can take a look at this
in more detail.
ATB,
Mark.
^ permalink raw reply [flat|nested] 102+ messages in thread
* Re: [PATCH for-6.2 14/43] target/sparc: Set fault address in sparc_cpu_do_unaligned_access
2021-08-01 15:56 ` Mark Cave-Ayland
@ 2021-08-01 15:59 ` Peter Maydell
2021-08-01 16:13 ` Mark Cave-Ayland
0 siblings, 1 reply; 102+ messages in thread
From: Peter Maydell @ 2021-08-01 15:59 UTC (permalink / raw)
To: Mark Cave-Ayland; +Cc: Richard Henderson, QEMU Developers
On Sun, 1 Aug 2021 at 16:56, Mark Cave-Ayland
<mark.cave-ayland@ilande.co.uk> wrote:
>
> On 29/07/2021 15:51, Peter Maydell wrote:
>
> > On Thu, 29 Jul 2021 at 02:01, Richard Henderson
> > <richard.henderson@linaro.org> wrote:
> >>
> >> We ought to have been recording the virtual address for reporting
> >> to the guest trap handler. Mirror the SFSR FIXME from the sparc64
> >> version of get_physical_address_data.
> >>
> >> Cc: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
> >> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> >> ---
> >> target/sparc/ldst_helper.c | 8 ++++++++
> >> 1 file changed, 8 insertions(+)
> >>
> >> diff --git a/target/sparc/ldst_helper.c b/target/sparc/ldst_helper.c
> >> index 974afea041..7367b48c8b 100644
> >> --- a/target/sparc/ldst_helper.c
> >> +++ b/target/sparc/ldst_helper.c
> >> @@ -1963,6 +1963,14 @@ void QEMU_NORETURN sparc_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
> >> SPARCCPU *cpu = SPARC_CPU(cs);
> >> CPUSPARCState *env = &cpu->env;
> >>
> >> +#ifdef TARGET_SPARC64
> >> + /* FIXME: ASI field in SFSR must be set */
> >> + env->dmmu.sfsr = SFSR_VALID_BIT; /* Fault status register */
> >> + env->dmmu.sfar = addr; /* Fault address register */
> >> +#else
> >> + env->mmuregs[4] = addr;
> >> +#endif
> >> +
> >> cpu_raise_exception_ra(env, TT_UNALIGNED, retaddr);
> >> }
> >> #endif
> >
> > The architecture manual seems to be gratuitously opaque about
> > whether and where the fault address for an alignment fault gets
> > recorded, but Linux at least for 64-bit seems to pull it out of the
> > sfar, so I guess that's right.
>
> Yeah, this part is actually contained within the UltraSPARC II specification - it can
> be found in section 6.4 "MMU-Related Faults and Traps" table 6-3 which indicates that
> for *_mem_address_not_aligned traps the D-SFSR and SFAR registers within the MMU are
> updated.
Do you know what 32-bit CPUs do? The Linux kernel sources don't help
here because they don't bother to report the fault address...
thanks
-- PMM
^ permalink raw reply [flat|nested] 102+ messages in thread
* Re: [PATCH for-6.2 14/43] target/sparc: Set fault address in sparc_cpu_do_unaligned_access
2021-08-01 15:59 ` Peter Maydell
@ 2021-08-01 16:13 ` Mark Cave-Ayland
0 siblings, 0 replies; 102+ messages in thread
From: Mark Cave-Ayland @ 2021-08-01 16:13 UTC (permalink / raw)
To: Peter Maydell; +Cc: Richard Henderson, QEMU Developers
On 01/08/2021 16:59, Peter Maydell wrote:
> On Sun, 1 Aug 2021 at 16:56, Mark Cave-Ayland
> <mark.cave-ayland@ilande.co.uk> wrote:
>>
>> On 29/07/2021 15:51, Peter Maydell wrote:
>>
>>> On Thu, 29 Jul 2021 at 02:01, Richard Henderson
>>> <richard.henderson@linaro.org> wrote:
>>>>
>>>> We ought to have been recording the virtual address for reporting
>>>> to the guest trap handler. Mirror the SFSR FIXME from the sparc64
>>>> version of get_physical_address_data.
>>>>
>>>> Cc: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
>>>> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
>>>> ---
>>>> target/sparc/ldst_helper.c | 8 ++++++++
>>>> 1 file changed, 8 insertions(+)
>>>>
>>>> diff --git a/target/sparc/ldst_helper.c b/target/sparc/ldst_helper.c
>>>> index 974afea041..7367b48c8b 100644
>>>> --- a/target/sparc/ldst_helper.c
>>>> +++ b/target/sparc/ldst_helper.c
>>>> @@ -1963,6 +1963,14 @@ void QEMU_NORETURN sparc_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
>>>> SPARCCPU *cpu = SPARC_CPU(cs);
>>>> CPUSPARCState *env = &cpu->env;
>>>>
>>>> +#ifdef TARGET_SPARC64
>>>> + /* FIXME: ASI field in SFSR must be set */
>>>> + env->dmmu.sfsr = SFSR_VALID_BIT; /* Fault status register */
>>>> + env->dmmu.sfar = addr; /* Fault address register */
>>>> +#else
>>>> + env->mmuregs[4] = addr;
>>>> +#endif
>>>> +
>>>> cpu_raise_exception_ra(env, TT_UNALIGNED, retaddr);
>>>> }
>>>> #endif
>>>
>>> The architecture manual seems to be gratuitously opaque about
>>> whether and where the fault address for an alignment fault gets
>>> recorded, but Linux at least for 64-bit seems to pull it out of the
>>> sfar, so I guess that's right.
>>
>> Yeah, this part is actually contained within the UltraSPARC II specification - it can
>> be found in section 6.4 "MMU-Related Faults and Traps" table 6-3 which indicates that
>> for *_mem_address_not_aligned traps the D-SFSR and SFAR registers within the MMU are
>> updated.
>
> Do you know what 32-bit CPUs do? The Linux kernel sources don't help
> here because they don't bother to report the fault address...
The SFSR and SFAR for the 32-bit sun4m machines is described in the Sun4m
Architecture manual section 4.4 "Synchronous Fault Registers". Unaligned access
behaviour isn't explicitly mentioned AFAICS but fault type 1 is "Invalid Address
Error" which seems like a possibility.
ATB,
Mark.
^ permalink raw reply [flat|nested] 102+ messages in thread
* [PATCH for-6.2 15/43] target/sparc: Implement do_unaligned_access for user-only
2021-07-29 0:46 [PATCH for-6.2 00/43] Unaligned accesses for user-only Richard Henderson
` (13 preceding siblings ...)
2021-07-29 0:46 ` [PATCH for-6.2 14/43] target/sparc: Set fault address in sparc_cpu_do_unaligned_access Richard Henderson
@ 2021-07-29 0:46 ` Richard Henderson
2021-07-29 9:40 ` Philippe Mathieu-Daudé
2021-07-29 0:46 ` [PATCH for-6.2 16/43] target/xtensa: " Richard Henderson
` (29 subsequent siblings)
44 siblings, 1 reply; 102+ messages in thread
From: Richard Henderson @ 2021-07-29 0:46 UTC (permalink / raw)
To: qemu-devel; +Cc: Mark Cave-Ayland
Cc: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
linux-user/sparc/cpu_loop.c | 11 +++++++++++
target/sparc/cpu.c | 2 +-
target/sparc/ldst_helper.c | 2 --
3 files changed, 12 insertions(+), 3 deletions(-)
diff --git a/linux-user/sparc/cpu_loop.c b/linux-user/sparc/cpu_loop.c
index 02532f198d..612e77807e 100644
--- a/linux-user/sparc/cpu_loop.c
+++ b/linux-user/sparc/cpu_loop.c
@@ -272,6 +272,17 @@ void cpu_loop (CPUSPARCState *env)
queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
}
break;
+ case TT_UNALIGNED:
+ info.si_signo = TARGET_SIGBUS;
+ info.si_errno = 0;
+ info.si_code = TARGET_BUS_ADRALN;
+#ifdef TARGET_SPARC64
+ info._sifields._sigfault._addr = env->dmmu.sfar;
+#else
+ info._sifields._sigfault._addr = env->mmuregs[4];
+#endif
+ queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
+ break;
case EXCP_DEBUG:
info.si_signo = TARGET_SIGTRAP;
info.si_errno = 0;
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
index da6b30ec74..d33d41e837 100644
--- a/target/sparc/cpu.c
+++ b/target/sparc/cpu.c
@@ -865,11 +865,11 @@ static const struct TCGCPUOps sparc_tcg_ops = {
.synchronize_from_tb = sparc_cpu_synchronize_from_tb,
.cpu_exec_interrupt = sparc_cpu_exec_interrupt,
.tlb_fill = sparc_cpu_tlb_fill,
+ .do_unaligned_access = sparc_cpu_do_unaligned_access,
#ifndef CONFIG_USER_ONLY
.do_interrupt = sparc_cpu_do_interrupt,
.do_transaction_failed = sparc_cpu_do_transaction_failed,
- .do_unaligned_access = sparc_cpu_do_unaligned_access,
#endif /* !CONFIG_USER_ONLY */
};
#endif /* CONFIG_TCG */
diff --git a/target/sparc/ldst_helper.c b/target/sparc/ldst_helper.c
index 7367b48c8b..69b812e68c 100644
--- a/target/sparc/ldst_helper.c
+++ b/target/sparc/ldst_helper.c
@@ -1954,7 +1954,6 @@ void sparc_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
}
#endif
-#if !defined(CONFIG_USER_ONLY)
void QEMU_NORETURN sparc_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
MMUAccessType access_type,
int mmu_idx,
@@ -1973,4 +1972,3 @@ void QEMU_NORETURN sparc_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
cpu_raise_exception_ra(env, TT_UNALIGNED, retaddr);
}
-#endif
--
2.25.1
^ permalink raw reply related [flat|nested] 102+ messages in thread* Re: [PATCH for-6.2 15/43] target/sparc: Implement do_unaligned_access for user-only
2021-07-29 0:46 ` [PATCH for-6.2 15/43] target/sparc: Implement do_unaligned_access for user-only Richard Henderson
@ 2021-07-29 9:40 ` Philippe Mathieu-Daudé
2021-07-29 18:20 ` Richard Henderson
0 siblings, 1 reply; 102+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-07-29 9:40 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: Alex Bennée, Mark Cave-Ayland
On 7/29/21 2:46 AM, Richard Henderson wrote:
> Cc: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> linux-user/sparc/cpu_loop.c | 11 +++++++++++
> target/sparc/cpu.c | 2 +-
> target/sparc/ldst_helper.c | 2 --
> 3 files changed, 12 insertions(+), 3 deletions(-)
>
> diff --git a/linux-user/sparc/cpu_loop.c b/linux-user/sparc/cpu_loop.c
> index 02532f198d..612e77807e 100644
> --- a/linux-user/sparc/cpu_loop.c
> +++ b/linux-user/sparc/cpu_loop.c
> @@ -272,6 +272,17 @@ void cpu_loop (CPUSPARCState *env)
> queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
> }
> break;
> + case TT_UNALIGNED:
> + info.si_signo = TARGET_SIGBUS;
> + info.si_errno = 0;
> + info.si_code = TARGET_BUS_ADRALN;
> +#ifdef TARGET_SPARC64
> + info._sifields._sigfault._addr = env->dmmu.sfar;
> +#else
> + info._sifields._sigfault._addr = env->mmuregs[4];
> +#endif
> + queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
> + break;
> case EXCP_DEBUG:
> info.si_signo = TARGET_SIGTRAP;
> info.si_errno = 0;
> diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
> index da6b30ec74..d33d41e837 100644
> --- a/target/sparc/cpu.c
> +++ b/target/sparc/cpu.c
> @@ -865,11 +865,11 @@ static const struct TCGCPUOps sparc_tcg_ops = {
> .synchronize_from_tb = sparc_cpu_synchronize_from_tb,
> .cpu_exec_interrupt = sparc_cpu_exec_interrupt,
> .tlb_fill = sparc_cpu_tlb_fill,
> + .do_unaligned_access = sparc_cpu_do_unaligned_access,
>
> #ifndef CONFIG_USER_ONLY
> .do_interrupt = sparc_cpu_do_interrupt,
> .do_transaction_failed = sparc_cpu_do_transaction_failed,
> - .do_unaligned_access = sparc_cpu_do_unaligned_access,
> #endif /* !CONFIG_USER_ONLY */
> };
> #endif /* CONFIG_TCG */
> diff --git a/target/sparc/ldst_helper.c b/target/sparc/ldst_helper.c
> index 7367b48c8b..69b812e68c 100644
> --- a/target/sparc/ldst_helper.c
> +++ b/target/sparc/ldst_helper.c
> @@ -1954,7 +1954,6 @@ void sparc_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
> }
> #endif
>
> -#if !defined(CONFIG_USER_ONLY)
> void QEMU_NORETURN sparc_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
> MMUAccessType access_type,
> int mmu_idx,
> @@ -1973,4 +1972,3 @@ void QEMU_NORETURN sparc_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
>
> cpu_raise_exception_ra(env, TT_UNALIGNED, retaddr);
> }
> -#endif
>
Somewhere around this patch I get:
SKIPPED signals on sparc64 because BROKEN awaiting sigframe clean-ups
and vdso support
TEST test-mmap (default) on sparc64
timeout: the monitored command dumped core
Bus error
make[2]: *** [tests/tcg/multiarch/Makefile.target:49: run-test-mmap]
Error 135
make[1]: *** [tests/tcg/Makefile.qemu:102: run-guest-tests] Error 2
make: *** [tests/Makefile.include:63: run-tcg-tests-sparc64-linux-user]
Error 2
^ permalink raw reply [flat|nested] 102+ messages in thread* Re: [PATCH for-6.2 15/43] target/sparc: Implement do_unaligned_access for user-only
2021-07-29 9:40 ` Philippe Mathieu-Daudé
@ 2021-07-29 18:20 ` Richard Henderson
0 siblings, 0 replies; 102+ messages in thread
From: Richard Henderson @ 2021-07-29 18:20 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Alex Bennée, Mark Cave-Ayland
On 7/28/21 11:40 PM, Philippe Mathieu-Daudé wrote:
> On 7/29/21 2:46 AM, Richard Henderson wrote:
>> Cc: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
>> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
>> ---
>> linux-user/sparc/cpu_loop.c | 11 +++++++++++
>> target/sparc/cpu.c | 2 +-
>> target/sparc/ldst_helper.c | 2 --
>> 3 files changed, 12 insertions(+), 3 deletions(-)
>>
>> diff --git a/linux-user/sparc/cpu_loop.c b/linux-user/sparc/cpu_loop.c
>> index 02532f198d..612e77807e 100644
>> --- a/linux-user/sparc/cpu_loop.c
>> +++ b/linux-user/sparc/cpu_loop.c
>> @@ -272,6 +272,17 @@ void cpu_loop (CPUSPARCState *env)
>> queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
>> }
>> break;
>> + case TT_UNALIGNED:
>> + info.si_signo = TARGET_SIGBUS;
>> + info.si_errno = 0;
>> + info.si_code = TARGET_BUS_ADRALN;
>> +#ifdef TARGET_SPARC64
>> + info._sifields._sigfault._addr = env->dmmu.sfar;
>> +#else
>> + info._sifields._sigfault._addr = env->mmuregs[4];
>> +#endif
>> + queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
>> + break;
>> case EXCP_DEBUG:
>> info.si_signo = TARGET_SIGTRAP;
>> info.si_errno = 0;
>> diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
>> index da6b30ec74..d33d41e837 100644
>> --- a/target/sparc/cpu.c
>> +++ b/target/sparc/cpu.c
>> @@ -865,11 +865,11 @@ static const struct TCGCPUOps sparc_tcg_ops = {
>> .synchronize_from_tb = sparc_cpu_synchronize_from_tb,
>> .cpu_exec_interrupt = sparc_cpu_exec_interrupt,
>> .tlb_fill = sparc_cpu_tlb_fill,
>> + .do_unaligned_access = sparc_cpu_do_unaligned_access,
>>
>> #ifndef CONFIG_USER_ONLY
>> .do_interrupt = sparc_cpu_do_interrupt,
>> .do_transaction_failed = sparc_cpu_do_transaction_failed,
>> - .do_unaligned_access = sparc_cpu_do_unaligned_access,
>> #endif /* !CONFIG_USER_ONLY */
>> };
>> #endif /* CONFIG_TCG */
>> diff --git a/target/sparc/ldst_helper.c b/target/sparc/ldst_helper.c
>> index 7367b48c8b..69b812e68c 100644
>> --- a/target/sparc/ldst_helper.c
>> +++ b/target/sparc/ldst_helper.c
>> @@ -1954,7 +1954,6 @@ void sparc_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
>> }
>> #endif
>>
>> -#if !defined(CONFIG_USER_ONLY)
>> void QEMU_NORETURN sparc_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
>> MMUAccessType access_type,
>> int mmu_idx,
>> @@ -1973,4 +1972,3 @@ void QEMU_NORETURN sparc_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
>>
>> cpu_raise_exception_ra(env, TT_UNALIGNED, retaddr);
>> }
>> -#endif
>>
>
> Somewhere around this patch I get:
>
> SKIPPED signals on sparc64 because BROKEN awaiting sigframe clean-ups
> and vdso support
> TEST test-mmap (default) on sparc64
> timeout: the monitored command dumped core
> Bus error
> make[2]: *** [tests/tcg/multiarch/Makefile.target:49: run-test-mmap]
> Error 135
> make[1]: *** [tests/tcg/Makefile.qemu:102: run-guest-tests] Error 2
> make: *** [tests/Makefile.include:63: run-tcg-tests-sparc64-linux-user]
That's really surprising, since the do_unaligned_access hook is not yet used? Oh, but
then target/sparc/ does some of its own manual TT_UNALIGNED exceptions for some ASI
access. I'll have a look, but you should have been seeing a different assert for that case.
r~
^ permalink raw reply [flat|nested] 102+ messages in thread
* [PATCH for-6.2 16/43] target/xtensa: Implement do_unaligned_access for user-only
2021-07-29 0:46 [PATCH for-6.2 00/43] Unaligned accesses for user-only Richard Henderson
` (14 preceding siblings ...)
2021-07-29 0:46 ` [PATCH for-6.2 15/43] target/sparc: Implement do_unaligned_access for user-only Richard Henderson
@ 2021-07-29 0:46 ` Richard Henderson
2021-07-29 8:10 ` Philippe Mathieu-Daudé
2021-07-29 14:55 ` Peter Maydell
2021-07-29 0:46 ` [PATCH for-6.2 17/43] accel/tcg: Report unaligned atomics " Richard Henderson
` (28 subsequent siblings)
44 siblings, 2 replies; 102+ messages in thread
From: Richard Henderson @ 2021-07-29 0:46 UTC (permalink / raw)
To: qemu-devel; +Cc: Max Filippov
Cc: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/xtensa/cpu.c | 2 +-
target/xtensa/helper.c | 30 +++++++++++++++---------------
2 files changed, 16 insertions(+), 16 deletions(-)
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
index 58ec3a0862..41816d91f6 100644
--- a/target/xtensa/cpu.c
+++ b/target/xtensa/cpu.c
@@ -195,11 +195,11 @@ static const struct TCGCPUOps xtensa_tcg_ops = {
.cpu_exec_interrupt = xtensa_cpu_exec_interrupt,
.tlb_fill = xtensa_cpu_tlb_fill,
.debug_excp_handler = xtensa_breakpoint_handler,
+ .do_unaligned_access = xtensa_cpu_do_unaligned_access,
#ifndef CONFIG_USER_ONLY
.do_interrupt = xtensa_cpu_do_interrupt,
.do_transaction_failed = xtensa_cpu_do_transaction_failed,
- .do_unaligned_access = xtensa_cpu_do_unaligned_access,
#endif /* !CONFIG_USER_ONLY */
};
diff --git a/target/xtensa/helper.c b/target/xtensa/helper.c
index f18ab383fd..a5296399c5 100644
--- a/target/xtensa/helper.c
+++ b/target/xtensa/helper.c
@@ -242,6 +242,21 @@ void xtensa_cpu_list(void)
}
}
+void xtensa_cpu_do_unaligned_access(CPUState *cs,
+ vaddr addr, MMUAccessType access_type,
+ int mmu_idx, uintptr_t retaddr)
+{
+ XtensaCPU *cpu = XTENSA_CPU(cs);
+ CPUXtensaState *env = &cpu->env;
+
+ assert(xtensa_option_enabled(env->config,
+ XTENSA_OPTION_UNALIGNED_EXCEPTION));
+ cpu_restore_state(CPU(cpu), retaddr, true);
+ HELPER(exception_cause_vaddr)(env,
+ env->pc, LOAD_STORE_ALIGNMENT_CAUSE,
+ addr);
+}
+
#ifdef CONFIG_USER_ONLY
bool xtensa_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
@@ -263,21 +278,6 @@ bool xtensa_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
#else /* !CONFIG_USER_ONLY */
-void xtensa_cpu_do_unaligned_access(CPUState *cs,
- vaddr addr, MMUAccessType access_type,
- int mmu_idx, uintptr_t retaddr)
-{
- XtensaCPU *cpu = XTENSA_CPU(cs);
- CPUXtensaState *env = &cpu->env;
-
- assert(xtensa_option_enabled(env->config,
- XTENSA_OPTION_UNALIGNED_EXCEPTION));
- cpu_restore_state(CPU(cpu), retaddr, true);
- HELPER(exception_cause_vaddr)(env,
- env->pc, LOAD_STORE_ALIGNMENT_CAUSE,
- addr);
-}
-
bool xtensa_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
MMUAccessType access_type, int mmu_idx,
bool probe, uintptr_t retaddr)
--
2.25.1
^ permalink raw reply related [flat|nested] 102+ messages in thread* Re: [PATCH for-6.2 16/43] target/xtensa: Implement do_unaligned_access for user-only
2021-07-29 0:46 ` [PATCH for-6.2 16/43] target/xtensa: " Richard Henderson
@ 2021-07-29 8:10 ` Philippe Mathieu-Daudé
2021-07-29 14:55 ` Peter Maydell
1 sibling, 0 replies; 102+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-07-29 8:10 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: Max Filippov
On 7/29/21 2:46 AM, Richard Henderson wrote:
> Cc: Max Filippov <jcmvbkbc@gmail.com>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/xtensa/cpu.c | 2 +-
> target/xtensa/helper.c | 30 +++++++++++++++---------------
> 2 files changed, 16 insertions(+), 16 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
^ permalink raw reply [flat|nested] 102+ messages in thread
* Re: [PATCH for-6.2 16/43] target/xtensa: Implement do_unaligned_access for user-only
2021-07-29 0:46 ` [PATCH for-6.2 16/43] target/xtensa: " Richard Henderson
2021-07-29 8:10 ` Philippe Mathieu-Daudé
@ 2021-07-29 14:55 ` Peter Maydell
2021-07-29 18:22 ` Richard Henderson
1 sibling, 1 reply; 102+ messages in thread
From: Peter Maydell @ 2021-07-29 14:55 UTC (permalink / raw)
To: Richard Henderson; +Cc: Max Filippov, QEMU Developers
On Thu, 29 Jul 2021 at 02:03, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Cc: Max Filippov <jcmvbkbc@gmail.com>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/xtensa/cpu.c | 2 +-
> target/xtensa/helper.c | 30 +++++++++++++++---------------
> 2 files changed, 16 insertions(+), 16 deletions(-)
The xtensa kernel has a CONFIG_XTENSA_UNALIGNED_USER option to
make the kernel silently fix up unaligned userspace accesses,
and most of the defconfigs for xtensa set it to 'y'.
-- PMM
^ permalink raw reply [flat|nested] 102+ messages in thread
* Re: [PATCH for-6.2 16/43] target/xtensa: Implement do_unaligned_access for user-only
2021-07-29 14:55 ` Peter Maydell
@ 2021-07-29 18:22 ` Richard Henderson
0 siblings, 0 replies; 102+ messages in thread
From: Richard Henderson @ 2021-07-29 18:22 UTC (permalink / raw)
To: Peter Maydell; +Cc: Max Filippov, QEMU Developers
On 7/29/21 4:55 AM, Peter Maydell wrote:
> On Thu, 29 Jul 2021 at 02:03, Richard Henderson
> <richard.henderson@linaro.org> wrote:
>>
>> Cc: Max Filippov <jcmvbkbc@gmail.com>
>> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
>> ---
>> target/xtensa/cpu.c | 2 +-
>> target/xtensa/helper.c | 30 +++++++++++++++---------------
>> 2 files changed, 16 insertions(+), 16 deletions(-)
>
> The xtensa kernel has a CONFIG_XTENSA_UNALIGNED_USER option to
> make the kernel silently fix up unaligned userspace accesses,
> and most of the defconfigs for xtensa set it to 'y'.
I believe the load/store-exclusive instructions should still fault.
r~
^ permalink raw reply [flat|nested] 102+ messages in thread
* [PATCH for-6.2 17/43] accel/tcg: Report unaligned atomics for user-only
2021-07-29 0:46 [PATCH for-6.2 00/43] Unaligned accesses for user-only Richard Henderson
` (15 preceding siblings ...)
2021-07-29 0:46 ` [PATCH for-6.2 16/43] target/xtensa: " Richard Henderson
@ 2021-07-29 0:46 ` Richard Henderson
2021-07-29 15:02 ` Peter Maydell
2021-07-29 0:46 ` [PATCH for-6.2 18/43] accel/tcg: Drop signness in tracing in cputlb.c Richard Henderson
` (27 subsequent siblings)
44 siblings, 1 reply; 102+ messages in thread
From: Richard Henderson @ 2021-07-29 0:46 UTC (permalink / raw)
To: qemu-devel
Use the newly exposed do_unaligned_access hook from atomic_mmu_lookup,
which has access to complete alignment info from the TCGMemOpIdx arg.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
accel/tcg/user-exec.c | 23 ++++++++++++++++++++++-
1 file changed, 22 insertions(+), 1 deletion(-)
diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
index 90d1a2d327..dd77e90789 100644
--- a/accel/tcg/user-exec.c
+++ b/accel/tcg/user-exec.c
@@ -852,6 +852,16 @@ int cpu_signal_handler(int host_signum, void *pinfo,
/* The softmmu versions of these helpers are in cputlb.c. */
+static void cpu_unaligned_access(CPUState *cpu, vaddr addr,
+ MMUAccessType access_type,
+ int mmu_idx, uintptr_t ra)
+{
+ CPUClass *cc = CPU_GET_CLASS(cpu);
+
+ cc->tcg_ops->do_unaligned_access(cpu, addr, access_type, mmu_idx, ra);
+ g_assert_not_reached();
+}
+
uint32_t cpu_ldub_data(CPUArchState *env, abi_ptr ptr)
{
uint32_t ret;
@@ -1230,11 +1240,22 @@ static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr,
TCGMemOpIdx oi, int size, int prot,
uintptr_t retaddr)
{
+ MemOp mop = get_memop(oi);
+ int a_bits = get_alignment_bits(mop);
+ void *ret;
+
+ /* Enforce guest required alignment. */
+ if (unlikely(addr & ((1 << a_bits) - 1))) {
+ MMUAccessType t = prot == PAGE_READ ? MMU_DATA_LOAD : MMU_DATA_STORE;
+ cpu_unaligned_access(env_cpu(env), addr, t, get_mmuidx(oi), retaddr);
+ }
+
/* Enforce qemu required alignment. */
if (unlikely(addr & (size - 1))) {
cpu_loop_exit_atomic(env_cpu(env), retaddr);
}
- void *ret = g2h(env_cpu(env), addr);
+
+ ret = g2h(env_cpu(env), addr);
set_helper_retaddr(retaddr);
return ret;
}
--
2.25.1
^ permalink raw reply related [flat|nested] 102+ messages in thread* Re: [PATCH for-6.2 17/43] accel/tcg: Report unaligned atomics for user-only
2021-07-29 0:46 ` [PATCH for-6.2 17/43] accel/tcg: Report unaligned atomics " Richard Henderson
@ 2021-07-29 15:02 ` Peter Maydell
2021-07-29 19:55 ` Philippe Mathieu-Daudé
0 siblings, 1 reply; 102+ messages in thread
From: Peter Maydell @ 2021-07-29 15:02 UTC (permalink / raw)
To: Richard Henderson; +Cc: QEMU Developers
On Thu, 29 Jul 2021 at 02:09, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Use the newly exposed do_unaligned_access hook from atomic_mmu_lookup,
> which has access to complete alignment info from the TCGMemOpIdx arg.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> accel/tcg/user-exec.c | 23 ++++++++++++++++++++++-
> 1 file changed, 22 insertions(+), 1 deletion(-)
>
> diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
> index 90d1a2d327..dd77e90789 100644
> --- a/accel/tcg/user-exec.c
> +++ b/accel/tcg/user-exec.c
> @@ -852,6 +852,16 @@ int cpu_signal_handler(int host_signum, void *pinfo,
>
> /* The softmmu versions of these helpers are in cputlb.c. */
>
> +static void cpu_unaligned_access(CPUState *cpu, vaddr addr,
> + MMUAccessType access_type,
> + int mmu_idx, uintptr_t ra)
> +{
> + CPUClass *cc = CPU_GET_CLASS(cpu);
> +
> + cc->tcg_ops->do_unaligned_access(cpu, addr, access_type, mmu_idx, ra);
> + g_assert_not_reached();
> +}
The softmmu version doesn't g_assert_not_reached(), I think
perhaps with the intent that a CPU implementation could
in some cases return without raising an exception to
mean "continue with the unaligned access". We should decide
whether we want the API to permit that, or else consistently
have both softmmu and useronly versions be marked noreturn
and with an assert, and we should document whichever we choose.
-- PMM
^ permalink raw reply [flat|nested] 102+ messages in thread* Re: [PATCH for-6.2 17/43] accel/tcg: Report unaligned atomics for user-only
2021-07-29 15:02 ` Peter Maydell
@ 2021-07-29 19:55 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 102+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-07-29 19:55 UTC (permalink / raw)
To: Peter Maydell, Richard Henderson; +Cc: QEMU Developers
On 7/29/21 5:02 PM, Peter Maydell wrote:
> On Thu, 29 Jul 2021 at 02:09, Richard Henderson
> <richard.henderson@linaro.org> wrote:
>>
>> Use the newly exposed do_unaligned_access hook from atomic_mmu_lookup,
>> which has access to complete alignment info from the TCGMemOpIdx arg.
>>
>> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
>> ---
>> accel/tcg/user-exec.c | 23 ++++++++++++++++++++++-
>> 1 file changed, 22 insertions(+), 1 deletion(-)
>>
>> diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
>> index 90d1a2d327..dd77e90789 100644
>> --- a/accel/tcg/user-exec.c
>> +++ b/accel/tcg/user-exec.c
>> @@ -852,6 +852,16 @@ int cpu_signal_handler(int host_signum, void *pinfo,
>>
>> /* The softmmu versions of these helpers are in cputlb.c. */
>>
>> +static void cpu_unaligned_access(CPUState *cpu, vaddr addr,
>> + MMUAccessType access_type,
>> + int mmu_idx, uintptr_t ra)
>> +{
>> + CPUClass *cc = CPU_GET_CLASS(cpu);
>> +
>> + cc->tcg_ops->do_unaligned_access(cpu, addr, access_type, mmu_idx, ra);
>> + g_assert_not_reached();
>> +}
>
> The softmmu version doesn't g_assert_not_reached(), I think
> perhaps with the intent that a CPU implementation could
> in some cases return without raising an exception to
> mean "continue with the unaligned access". We should decide
> whether we want the API to permit that, or else consistently
> have both softmmu and useronly versions be marked noreturn
> and with an assert, and we should document whichever we choose.
Agreed. I'd rather use noreturn, which exposed these bugs:
- "target/xtensa: clean up unaligned access"
https://lists.gnu.org/archive/html/qemu-devel/2021-05/msg05890.html
- "target/nios2: Mark raise_exception() as noreturn"
https://lists.gnu.org/archive/html/qemu-devel/2021-07/msg07001.html
^ permalink raw reply [flat|nested] 102+ messages in thread
* [PATCH for-6.2 18/43] accel/tcg: Drop signness in tracing in cputlb.c
2021-07-29 0:46 [PATCH for-6.2 00/43] Unaligned accesses for user-only Richard Henderson
` (16 preceding siblings ...)
2021-07-29 0:46 ` [PATCH for-6.2 17/43] accel/tcg: Report unaligned atomics " Richard Henderson
@ 2021-07-29 0:46 ` Richard Henderson
2021-07-29 0:46 ` [PATCH for-6.2 19/43] tcg: Expand MO_SIZE to 3 bits Richard Henderson
` (26 subsequent siblings)
44 siblings, 0 replies; 102+ messages in thread
From: Richard Henderson @ 2021-07-29 0:46 UTC (permalink / raw)
To: qemu-devel
We are already inconsistent about whether or not
MO_SIGN is set in trace_mem_get_info. Dropping it
entirely allows some simplification.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
accel/tcg/cputlb.c | 10 +++-------
accel/tcg/user-exec.c | 45 ++++++-------------------------------------
2 files changed, 9 insertions(+), 46 deletions(-)
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index b1e5471f94..0a1fdbefdd 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -2119,7 +2119,6 @@ static inline uint64_t cpu_load_helper(CPUArchState *env, abi_ptr addr,
meminfo = trace_mem_get_info(op, mmu_idx, false);
trace_guest_mem_before_exec(env_cpu(env), addr, meminfo);
- op &= ~MO_SIGN;
oi = make_memop_idx(op, mmu_idx);
ret = full_load(env, addr, oi, retaddr);
@@ -2137,8 +2136,7 @@ uint32_t cpu_ldub_mmuidx_ra(CPUArchState *env, abi_ptr addr,
int cpu_ldsb_mmuidx_ra(CPUArchState *env, abi_ptr addr,
int mmu_idx, uintptr_t ra)
{
- return (int8_t)cpu_load_helper(env, addr, mmu_idx, ra, MO_SB,
- full_ldub_mmu);
+ return (int8_t)cpu_ldub_mmuidx_ra(env, addr, mmu_idx, ra);
}
uint32_t cpu_lduw_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
@@ -2150,8 +2148,7 @@ uint32_t cpu_lduw_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
int cpu_ldsw_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
int mmu_idx, uintptr_t ra)
{
- return (int16_t)cpu_load_helper(env, addr, mmu_idx, ra, MO_BESW,
- full_be_lduw_mmu);
+ return (int16_t)cpu_lduw_be_mmuidx_ra(env, addr, mmu_idx, ra);
}
uint32_t cpu_ldl_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
@@ -2175,8 +2172,7 @@ uint32_t cpu_lduw_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
int cpu_ldsw_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
int mmu_idx, uintptr_t ra)
{
- return (int16_t)cpu_load_helper(env, addr, mmu_idx, ra, MO_LESW,
- full_le_lduw_mmu);
+ return (int16_t)cpu_lduw_le_mmuidx_ra(env, addr, mmu_idx, ra);
}
uint32_t cpu_ldl_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
index dd77e90789..f17b75e0aa 100644
--- a/accel/tcg/user-exec.c
+++ b/accel/tcg/user-exec.c
@@ -875,13 +875,7 @@ uint32_t cpu_ldub_data(CPUArchState *env, abi_ptr ptr)
int cpu_ldsb_data(CPUArchState *env, abi_ptr ptr)
{
- int ret;
- uint16_t meminfo = trace_mem_get_info(MO_SB, MMU_USER_IDX, false);
-
- trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
- ret = ldsb_p(g2h(env_cpu(env), ptr));
- qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
- return ret;
+ return (int8_t)cpu_ldub_data(env, ptr);
}
uint32_t cpu_lduw_be_data(CPUArchState *env, abi_ptr ptr)
@@ -897,13 +891,7 @@ uint32_t cpu_lduw_be_data(CPUArchState *env, abi_ptr ptr)
int cpu_ldsw_be_data(CPUArchState *env, abi_ptr ptr)
{
- int ret;
- uint16_t meminfo = trace_mem_get_info(MO_BESW, MMU_USER_IDX, false);
-
- trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
- ret = ldsw_be_p(g2h(env_cpu(env), ptr));
- qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
- return ret;
+ return (int16_t)cpu_lduw_be_data(env, ptr);
}
uint32_t cpu_ldl_be_data(CPUArchState *env, abi_ptr ptr)
@@ -941,13 +929,7 @@ uint32_t cpu_lduw_le_data(CPUArchState *env, abi_ptr ptr)
int cpu_ldsw_le_data(CPUArchState *env, abi_ptr ptr)
{
- int ret;
- uint16_t meminfo = trace_mem_get_info(MO_LESW, MMU_USER_IDX, false);
-
- trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
- ret = ldsw_le_p(g2h(env_cpu(env), ptr));
- qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
- return ret;
+ return (int16_t)cpu_lduw_le_data(env, ptr);
}
uint32_t cpu_ldl_le_data(CPUArchState *env, abi_ptr ptr)
@@ -984,12 +966,7 @@ uint32_t cpu_ldub_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr)
int cpu_ldsb_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr)
{
- int ret;
-
- set_helper_retaddr(retaddr);
- ret = cpu_ldsb_data(env, ptr);
- clear_helper_retaddr();
- return ret;
+ return (int8_t)cpu_ldub_data_ra(env, ptr, retaddr);
}
uint32_t cpu_lduw_be_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr)
@@ -1004,12 +981,7 @@ uint32_t cpu_lduw_be_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr)
int cpu_ldsw_be_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr)
{
- int ret;
-
- set_helper_retaddr(retaddr);
- ret = cpu_ldsw_be_data(env, ptr);
- clear_helper_retaddr();
- return ret;
+ return (int16_t)cpu_lduw_be_data_ra(env, ptr, retaddr);
}
uint32_t cpu_ldl_be_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr)
@@ -1044,12 +1016,7 @@ uint32_t cpu_lduw_le_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr)
int cpu_ldsw_le_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr)
{
- int ret;
-
- set_helper_retaddr(retaddr);
- ret = cpu_ldsw_le_data(env, ptr);
- clear_helper_retaddr();
- return ret;
+ return (int16_t)cpu_lduw_le_data_ra(env, ptr, retaddr);
}
uint32_t cpu_ldl_le_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr)
--
2.25.1
^ permalink raw reply related [flat|nested] 102+ messages in thread* [PATCH for-6.2 19/43] tcg: Expand MO_SIZE to 3 bits
2021-07-29 0:46 [PATCH for-6.2 00/43] Unaligned accesses for user-only Richard Henderson
` (17 preceding siblings ...)
2021-07-29 0:46 ` [PATCH for-6.2 18/43] accel/tcg: Drop signness in tracing in cputlb.c Richard Henderson
@ 2021-07-29 0:46 ` Richard Henderson
2021-07-29 6:23 ` Philippe Mathieu-Daudé
2021-07-29 0:46 ` [PATCH for-6.2 20/43] tcg: Rename TCGMemOpIdx to MemOpIdx Richard Henderson
` (25 subsequent siblings)
44 siblings, 1 reply; 102+ messages in thread
From: Richard Henderson @ 2021-07-29 0:46 UTC (permalink / raw)
To: qemu-devel
We have lacked expressive support for memory sizes larger
than 64-bits for a while. Fixing that requires adjustment
to several points where we used this for array indexing,
and two places that develop -Wswitch warnings after the change.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/exec/memop.h | 14 +++++++++-----
target/arm/translate-a64.c | 2 +-
tcg/tcg-op.c | 13 ++++++++-----
target/s390x/tcg/translate_vx.c.inc | 2 +-
tcg/aarch64/tcg-target.c.inc | 4 ++--
tcg/arm/tcg-target.c.inc | 4 ++--
tcg/i386/tcg-target.c.inc | 4 ++--
tcg/mips/tcg-target.c.inc | 4 ++--
tcg/ppc/tcg-target.c.inc | 8 ++++----
tcg/riscv/tcg-target.c.inc | 4 ++--
tcg/s390/tcg-target.c.inc | 4 ++--
tcg/sparc/tcg-target.c.inc | 16 ++++++++--------
12 files changed, 43 insertions(+), 36 deletions(-)
diff --git a/include/exec/memop.h b/include/exec/memop.h
index 529d07b02d..04264ffd6b 100644
--- a/include/exec/memop.h
+++ b/include/exec/memop.h
@@ -19,11 +19,15 @@ typedef enum MemOp {
MO_16 = 1,
MO_32 = 2,
MO_64 = 3,
- MO_SIZE = 3, /* Mask for the above. */
+ MO_128 = 4,
+ MO_256 = 5,
+ MO_512 = 6,
+ MO_1024 = 7,
+ MO_SIZE = 0x07, /* Mask for the above. */
- MO_SIGN = 4, /* Sign-extended, otherwise zero-extended. */
+ MO_SIGN = 0x08, /* Sign-extended, otherwise zero-extended. */
- MO_BSWAP = 8, /* Host reverse endian. */
+ MO_BSWAP = 0x10, /* Host reverse endian. */
#ifdef HOST_WORDS_BIGENDIAN
MO_LE = MO_BSWAP,
MO_BE = 0,
@@ -59,8 +63,8 @@ typedef enum MemOp {
* - an alignment to a specified size, which may be more or less than
* the access size (MO_ALIGN_x where 'x' is a size in bytes);
*/
- MO_ASHIFT = 4,
- MO_AMASK = 7 << MO_ASHIFT,
+ MO_ASHIFT = 5,
+ MO_AMASK = 0x7 << MO_ASHIFT,
#ifdef NEED_CPU_H
#ifdef TARGET_ALIGNED_ONLY
MO_ALIGN = 0,
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 422e2ac0c9..247c9672be 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -1045,7 +1045,7 @@ static void read_vec_element(DisasContext *s, TCGv_i64 tcg_dest, int srcidx,
int element, MemOp memop)
{
int vect_off = vec_reg_offset(s, srcidx, element, memop & MO_SIZE);
- switch (memop) {
+ switch ((unsigned)memop) {
case MO_8:
tcg_gen_ld8u_i64(tcg_dest, cpu_env, vect_off);
break;
diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c
index c754396575..e01f68f44d 100644
--- a/tcg/tcg-op.c
+++ b/tcg/tcg-op.c
@@ -2780,10 +2780,13 @@ static inline MemOp tcg_canonicalize_memop(MemOp op, bool is64, bool st)
}
break;
case MO_64:
- if (!is64) {
- tcg_abort();
+ if (is64) {
+ op &= ~MO_SIGN;
+ break;
}
- break;
+ /* fall through */
+ default:
+ g_assert_not_reached();
}
if (st) {
op &= ~MO_SIGN;
@@ -3095,7 +3098,7 @@ typedef void (*gen_atomic_op_i64)(TCGv_i64, TCGv_env, TCGv,
# define WITH_ATOMIC64(X)
#endif
-static void * const table_cmpxchg[16] = {
+static void * const table_cmpxchg[(MO_SIZE | MO_BSWAP) + 1] = {
[MO_8] = gen_helper_atomic_cmpxchgb,
[MO_16 | MO_LE] = gen_helper_atomic_cmpxchgw_le,
[MO_16 | MO_BE] = gen_helper_atomic_cmpxchgw_be,
@@ -3297,7 +3300,7 @@ static void do_atomic_op_i64(TCGv_i64 ret, TCGv addr, TCGv_i64 val,
}
#define GEN_ATOMIC_HELPER(NAME, OP, NEW) \
-static void * const table_##NAME[16] = { \
+static void * const table_##NAME[(MO_SIZE | MO_BSWAP) + 1] = { \
[MO_8] = gen_helper_atomic_##NAME##b, \
[MO_16 | MO_LE] = gen_helper_atomic_##NAME##w_le, \
[MO_16 | MO_BE] = gen_helper_atomic_##NAME##w_be, \
diff --git a/target/s390x/tcg/translate_vx.c.inc b/target/s390x/tcg/translate_vx.c.inc
index 0afa46e463..28bf5a23b6 100644
--- a/target/s390x/tcg/translate_vx.c.inc
+++ b/target/s390x/tcg/translate_vx.c.inc
@@ -67,7 +67,7 @@ static void read_vec_element_i64(TCGv_i64 dst, uint8_t reg, uint8_t enr,
{
const int offs = vec_reg_offset(reg, enr, memop & MO_SIZE);
- switch (memop) {
+ switch ((unsigned)memop) {
case ES_8:
tcg_gen_ld8u_i64(dst, cpu_env, offs);
break;
diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc
index 5924977b42..6f43c048a5 100644
--- a/tcg/aarch64/tcg-target.c.inc
+++ b/tcg/aarch64/tcg-target.c.inc
@@ -1547,7 +1547,7 @@ static void tcg_out_cltz(TCGContext *s, TCGType ext, TCGReg d,
/* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr,
* TCGMemOpIdx oi, uintptr_t ra)
*/
-static void * const qemu_ld_helpers[4] = {
+static void * const qemu_ld_helpers[MO_SIZE + 1] = {
[MO_8] = helper_ret_ldub_mmu,
#ifdef HOST_WORDS_BIGENDIAN
[MO_16] = helper_be_lduw_mmu,
@@ -1564,7 +1564,7 @@ static void * const qemu_ld_helpers[4] = {
* uintxx_t val, TCGMemOpIdx oi,
* uintptr_t ra)
*/
-static void * const qemu_st_helpers[4] = {
+static void * const qemu_st_helpers[MO_SIZE + 1] = {
[MO_8] = helper_ret_stb_mmu,
#ifdef HOST_WORDS_BIGENDIAN
[MO_16] = helper_be_stw_mmu,
diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
index 007ceee68e..8939b2c2da 100644
--- a/tcg/arm/tcg-target.c.inc
+++ b/tcg/arm/tcg-target.c.inc
@@ -1393,7 +1393,7 @@ static void tcg_out_vldst(TCGContext *s, ARMInsn insn,
/* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr,
* int mmu_idx, uintptr_t ra)
*/
-static void * const qemu_ld_helpers[8] = {
+static void * const qemu_ld_helpers[MO_SSIZE + 1] = {
[MO_UB] = helper_ret_ldub_mmu,
[MO_SB] = helper_ret_ldsb_mmu,
#ifdef HOST_WORDS_BIGENDIAN
@@ -1414,7 +1414,7 @@ static void * const qemu_ld_helpers[8] = {
/* helper signature: helper_ret_st_mmu(CPUState *env, target_ulong addr,
* uintxx_t val, int mmu_idx, uintptr_t ra)
*/
-static void * const qemu_st_helpers[4] = {
+static void * const qemu_st_helpers[MO_SIZE + 1] = {
[MO_8] = helper_ret_stb_mmu,
#ifdef HOST_WORDS_BIGENDIAN
[MO_16] = helper_be_stw_mmu,
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
index 98d924b91a..5fd4e4392f 100644
--- a/tcg/i386/tcg-target.c.inc
+++ b/tcg/i386/tcg-target.c.inc
@@ -1610,7 +1610,7 @@ static void tcg_out_nopn(TCGContext *s, int n)
/* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr,
* int mmu_idx, uintptr_t ra)
*/
-static void * const qemu_ld_helpers[16] = {
+static void * const qemu_ld_helpers[(MO_SIZE | MO_BSWAP) + 1] = {
[MO_UB] = helper_ret_ldub_mmu,
[MO_LEUW] = helper_le_lduw_mmu,
[MO_LEUL] = helper_le_ldul_mmu,
@@ -1623,7 +1623,7 @@ static void * const qemu_ld_helpers[16] = {
/* helper signature: helper_ret_st_mmu(CPUState *env, target_ulong addr,
* uintxx_t val, int mmu_idx, uintptr_t ra)
*/
-static void * const qemu_st_helpers[16] = {
+static void * const qemu_st_helpers[(MO_SIZE | MO_BSWAP) + 1] = {
[MO_UB] = helper_ret_stb_mmu,
[MO_LEUW] = helper_le_stw_mmu,
[MO_LEUL] = helper_le_stl_mmu,
diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc
index bf0eb84e2d..cc279205d6 100644
--- a/tcg/mips/tcg-target.c.inc
+++ b/tcg/mips/tcg-target.c.inc
@@ -1037,7 +1037,7 @@ static void tcg_out_call(TCGContext *s, const tcg_insn_unit *arg)
#if defined(CONFIG_SOFTMMU)
#include "../tcg-ldst.c.inc"
-static void * const qemu_ld_helpers[16] = {
+static void * const qemu_ld_helpers[(MO_SSIZE | MO_BSWAP) + 1] = {
[MO_UB] = helper_ret_ldub_mmu,
[MO_SB] = helper_ret_ldsb_mmu,
[MO_LEUW] = helper_le_lduw_mmu,
@@ -1054,7 +1054,7 @@ static void * const qemu_ld_helpers[16] = {
#endif
};
-static void * const qemu_st_helpers[16] = {
+static void * const qemu_st_helpers[(MO_SIZE | MO_BSWAP) + 1] = {
[MO_UB] = helper_ret_stb_mmu,
[MO_LEUW] = helper_le_stw_mmu,
[MO_LEUL] = helper_le_stl_mmu,
diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
index e0f4665213..3fef2aa6b2 100644
--- a/tcg/ppc/tcg-target.c.inc
+++ b/tcg/ppc/tcg-target.c.inc
@@ -1916,7 +1916,7 @@ static void tcg_out_call(TCGContext *s, const tcg_insn_unit *target)
#endif
}
-static const uint32_t qemu_ldx_opc[16] = {
+static const uint32_t qemu_ldx_opc[(MO_SSIZE + MO_BSWAP) + 1] = {
[MO_UB] = LBZX,
[MO_UW] = LHZX,
[MO_UL] = LWZX,
@@ -1929,7 +1929,7 @@ static const uint32_t qemu_ldx_opc[16] = {
[MO_BSWAP | MO_Q] = LDBRX,
};
-static const uint32_t qemu_stx_opc[16] = {
+static const uint32_t qemu_stx_opc[(MO_SIZE + MO_BSWAP) + 1] = {
[MO_UB] = STBX,
[MO_UW] = STHX,
[MO_UL] = STWX,
@@ -1950,7 +1950,7 @@ static const uint32_t qemu_exts_opc[4] = {
/* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr,
* int mmu_idx, uintptr_t ra)
*/
-static void * const qemu_ld_helpers[16] = {
+static void * const qemu_ld_helpers[(MO_SIZE | MO_BSWAP) + 1] = {
[MO_UB] = helper_ret_ldub_mmu,
[MO_LEUW] = helper_le_lduw_mmu,
[MO_LEUL] = helper_le_ldul_mmu,
@@ -1963,7 +1963,7 @@ static void * const qemu_ld_helpers[16] = {
/* helper signature: helper_st_mmu(CPUState *env, target_ulong addr,
* uintxx_t val, int mmu_idx, uintptr_t ra)
*/
-static void * const qemu_st_helpers[16] = {
+static void * const qemu_st_helpers[(MO_SIZE | MO_BSWAP) + 1] = {
[MO_UB] = helper_ret_stb_mmu,
[MO_LEUW] = helper_le_stw_mmu,
[MO_LEUL] = helper_le_stl_mmu,
diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
index c16f96b401..6264e58b3a 100644
--- a/tcg/riscv/tcg-target.c.inc
+++ b/tcg/riscv/tcg-target.c.inc
@@ -852,7 +852,7 @@ static void tcg_out_mb(TCGContext *s, TCGArg a0)
/* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr,
* TCGMemOpIdx oi, uintptr_t ra)
*/
-static void * const qemu_ld_helpers[8] = {
+static void * const qemu_ld_helpers[MO_SSIZE + 1] = {
[MO_UB] = helper_ret_ldub_mmu,
[MO_SB] = helper_ret_ldsb_mmu,
#ifdef HOST_WORDS_BIGENDIAN
@@ -878,7 +878,7 @@ static void * const qemu_ld_helpers[8] = {
* uintxx_t val, TCGMemOpIdx oi,
* uintptr_t ra)
*/
-static void * const qemu_st_helpers[4] = {
+static void * const qemu_st_helpers[MO_SIZE + 1] = {
[MO_8] = helper_ret_stb_mmu,
#ifdef HOST_WORDS_BIGENDIAN
[MO_16] = helper_be_stw_mmu,
diff --git a/tcg/s390/tcg-target.c.inc b/tcg/s390/tcg-target.c.inc
index b82cf19f09..67a2ba5ff3 100644
--- a/tcg/s390/tcg-target.c.inc
+++ b/tcg/s390/tcg-target.c.inc
@@ -350,7 +350,7 @@ static const uint8_t tcg_cond_to_ltr_cond[] = {
};
#ifdef CONFIG_SOFTMMU
-static void * const qemu_ld_helpers[16] = {
+static void * const qemu_ld_helpers[(MO_SSIZE | MO_BSWAP) + 1] = {
[MO_UB] = helper_ret_ldub_mmu,
[MO_SB] = helper_ret_ldsb_mmu,
[MO_LEUW] = helper_le_lduw_mmu,
@@ -365,7 +365,7 @@ static void * const qemu_ld_helpers[16] = {
[MO_BEQ] = helper_be_ldq_mmu,
};
-static void * const qemu_st_helpers[16] = {
+static void * const qemu_st_helpers[(MO_SIZE | MO_BSWAP) + 1] = {
[MO_UB] = helper_ret_stb_mmu,
[MO_LEUW] = helper_le_stw_mmu,
[MO_LEUL] = helper_le_stl_mmu,
diff --git a/tcg/sparc/tcg-target.c.inc b/tcg/sparc/tcg-target.c.inc
index 688827968b..b9bce29282 100644
--- a/tcg/sparc/tcg-target.c.inc
+++ b/tcg/sparc/tcg-target.c.inc
@@ -847,8 +847,8 @@ static void tcg_out_mb(TCGContext *s, TCGArg a0)
}
#ifdef CONFIG_SOFTMMU
-static const tcg_insn_unit *qemu_ld_trampoline[16];
-static const tcg_insn_unit *qemu_st_trampoline[16];
+static const tcg_insn_unit *qemu_ld_trampoline[(MO_SSIZE | MO_BSWAP) + 1];
+static const tcg_insn_unit *qemu_st_trampoline[(MO_SIZE | MO_BSWAP) + 1];
static void emit_extend(TCGContext *s, TCGReg r, int op)
{
@@ -875,7 +875,7 @@ static void emit_extend(TCGContext *s, TCGReg r, int op)
static void build_trampolines(TCGContext *s)
{
- static void * const qemu_ld_helpers[16] = {
+ static void * const qemu_ld_helpers[] = {
[MO_UB] = helper_ret_ldub_mmu,
[MO_SB] = helper_ret_ldsb_mmu,
[MO_LEUW] = helper_le_lduw_mmu,
@@ -887,7 +887,7 @@ static void build_trampolines(TCGContext *s)
[MO_BEUL] = helper_be_ldul_mmu,
[MO_BEQ] = helper_be_ldq_mmu,
};
- static void * const qemu_st_helpers[16] = {
+ static void * const qemu_st_helpers[] = {
[MO_UB] = helper_ret_stb_mmu,
[MO_LEUW] = helper_le_stw_mmu,
[MO_LEUL] = helper_le_stl_mmu,
@@ -900,7 +900,7 @@ static void build_trampolines(TCGContext *s)
int i;
TCGReg ra;
- for (i = 0; i < 16; ++i) {
+ for (i = 0; i < ARRAY_SIZE(qemu_ld_helpers); ++i) {
if (qemu_ld_helpers[i] == NULL) {
continue;
}
@@ -928,7 +928,7 @@ static void build_trampolines(TCGContext *s)
tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_O7, ra);
}
- for (i = 0; i < 16; ++i) {
+ for (i = 0; i < ARRAY_SIZE(qemu_st_helpers); ++i) {
if (qemu_st_helpers[i] == NULL) {
continue;
}
@@ -1110,7 +1110,7 @@ static TCGReg tcg_out_tlb_load(TCGContext *s, TCGReg addr, int mem_index,
}
#endif /* CONFIG_SOFTMMU */
-static const int qemu_ld_opc[16] = {
+static const int qemu_ld_opc[(MO_SSIZE | MO_BSWAP) + 1] = {
[MO_UB] = LDUB,
[MO_SB] = LDSB,
@@ -1127,7 +1127,7 @@ static const int qemu_ld_opc[16] = {
[MO_LEQ] = LDX_LE,
};
-static const int qemu_st_opc[16] = {
+static const int qemu_st_opc[(MO_SIZE | MO_BSWAP) + 1] = {
[MO_UB] = STB,
[MO_BEUW] = STH,
--
2.25.1
^ permalink raw reply related [flat|nested] 102+ messages in thread* Re: [PATCH for-6.2 19/43] tcg: Expand MO_SIZE to 3 bits
2021-07-29 0:46 ` [PATCH for-6.2 19/43] tcg: Expand MO_SIZE to 3 bits Richard Henderson
@ 2021-07-29 6:23 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 102+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-07-29 6:23 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
On 7/29/21 2:46 AM, Richard Henderson wrote:
> We have lacked expressive support for memory sizes larger
> than 64-bits for a while. Fixing that requires adjustment
> to several points where we used this for array indexing,
> and two places that develop -Wswitch warnings after the change.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> include/exec/memop.h | 14 +++++++++-----
> target/arm/translate-a64.c | 2 +-
> tcg/tcg-op.c | 13 ++++++++-----
> target/s390x/tcg/translate_vx.c.inc | 2 +-
> tcg/aarch64/tcg-target.c.inc | 4 ++--
> tcg/arm/tcg-target.c.inc | 4 ++--
> tcg/i386/tcg-target.c.inc | 4 ++--
> tcg/mips/tcg-target.c.inc | 4 ++--
> tcg/ppc/tcg-target.c.inc | 8 ++++----
> tcg/riscv/tcg-target.c.inc | 4 ++--
> tcg/s390/tcg-target.c.inc | 4 ++--
> tcg/sparc/tcg-target.c.inc | 16 ++++++++--------
> 12 files changed, 43 insertions(+), 36 deletions(-)
Nice cleanup.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
^ permalink raw reply [flat|nested] 102+ messages in thread
* [PATCH for-6.2 20/43] tcg: Rename TCGMemOpIdx to MemOpIdx
2021-07-29 0:46 [PATCH for-6.2 00/43] Unaligned accesses for user-only Richard Henderson
` (18 preceding siblings ...)
2021-07-29 0:46 ` [PATCH for-6.2 19/43] tcg: Expand MO_SIZE to 3 bits Richard Henderson
@ 2021-07-29 0:46 ` Richard Henderson
2021-07-29 6:27 ` Philippe Mathieu-Daudé
2021-07-29 0:46 ` [PATCH for-6.2 21/43] tcg: Split out MemOpIdx to exec/memopidx.h Richard Henderson
` (24 subsequent siblings)
44 siblings, 1 reply; 102+ messages in thread
From: Richard Henderson @ 2021-07-29 0:46 UTC (permalink / raw)
To: qemu-devel
We're about to move this out of tcg.h, so rename it
as we did when moving MemOp.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
accel/tcg/atomic_template.h | 24 +++++------
include/tcg/tcg.h | 74 ++++++++++++++++-----------------
accel/tcg/cputlb.c | 78 +++++++++++++++++------------------
accel/tcg/user-exec.c | 2 +-
target/arm/helper-a64.c | 16 +++----
target/arm/m_helper.c | 2 +-
target/i386/tcg/mem_helper.c | 4 +-
target/m68k/op_helper.c | 2 +-
target/mips/tcg/msa_helper.c | 6 +--
target/s390x/tcg/mem_helper.c | 20 ++++-----
target/sparc/ldst_helper.c | 2 +-
tcg/optimize.c | 2 +-
tcg/tcg-op.c | 12 +++---
tcg/tcg.c | 2 +-
tcg/tci.c | 14 +++----
accel/tcg/atomic_common.c.inc | 6 +--
tcg/aarch64/tcg-target.c.inc | 14 +++----
tcg/arm/tcg-target.c.inc | 10 ++---
tcg/i386/tcg-target.c.inc | 10 ++---
tcg/mips/tcg-target.c.inc | 12 +++---
tcg/ppc/tcg-target.c.inc | 10 ++---
tcg/riscv/tcg-target.c.inc | 16 +++----
tcg/s390/tcg-target.c.inc | 10 ++---
tcg/sparc/tcg-target.c.inc | 4 +-
tcg/tcg-ldst.c.inc | 2 +-
25 files changed, 177 insertions(+), 177 deletions(-)
diff --git a/accel/tcg/atomic_template.h b/accel/tcg/atomic_template.h
index d89af4cc1e..4427fab6df 100644
--- a/accel/tcg/atomic_template.h
+++ b/accel/tcg/atomic_template.h
@@ -72,7 +72,7 @@
ABI_TYPE ATOMIC_NAME(cmpxchg)(CPUArchState *env, target_ulong addr,
ABI_TYPE cmpv, ABI_TYPE newv,
- TCGMemOpIdx oi, uintptr_t retaddr)
+ MemOpIdx oi, uintptr_t retaddr)
{
DATA_TYPE *haddr = atomic_mmu_lookup(env, addr, oi, DATA_SIZE,
PAGE_READ | PAGE_WRITE, retaddr);
@@ -92,7 +92,7 @@ ABI_TYPE ATOMIC_NAME(cmpxchg)(CPUArchState *env, target_ulong addr,
#if DATA_SIZE >= 16
#if HAVE_ATOMIC128
ABI_TYPE ATOMIC_NAME(ld)(CPUArchState *env, target_ulong addr,
- TCGMemOpIdx oi, uintptr_t retaddr)
+ MemOpIdx oi, uintptr_t retaddr)
{
DATA_TYPE *haddr = atomic_mmu_lookup(env, addr, oi, DATA_SIZE,
PAGE_READ, retaddr);
@@ -106,7 +106,7 @@ ABI_TYPE ATOMIC_NAME(ld)(CPUArchState *env, target_ulong addr,
}
void ATOMIC_NAME(st)(CPUArchState *env, target_ulong addr, ABI_TYPE val,
- TCGMemOpIdx oi, uintptr_t retaddr)
+ MemOpIdx oi, uintptr_t retaddr)
{
DATA_TYPE *haddr = atomic_mmu_lookup(env, addr, oi, DATA_SIZE,
PAGE_WRITE, retaddr);
@@ -119,7 +119,7 @@ void ATOMIC_NAME(st)(CPUArchState *env, target_ulong addr, ABI_TYPE val,
#endif
#else
ABI_TYPE ATOMIC_NAME(xchg)(CPUArchState *env, target_ulong addr, ABI_TYPE val,
- TCGMemOpIdx oi, uintptr_t retaddr)
+ MemOpIdx oi, uintptr_t retaddr)
{
DATA_TYPE *haddr = atomic_mmu_lookup(env, addr, oi, DATA_SIZE,
PAGE_READ | PAGE_WRITE, retaddr);
@@ -134,7 +134,7 @@ ABI_TYPE ATOMIC_NAME(xchg)(CPUArchState *env, target_ulong addr, ABI_TYPE val,
#define GEN_ATOMIC_HELPER(X) \
ABI_TYPE ATOMIC_NAME(X)(CPUArchState *env, target_ulong addr, \
- ABI_TYPE val, TCGMemOpIdx oi, uintptr_t retaddr) \
+ ABI_TYPE val, MemOpIdx oi, uintptr_t retaddr) \
{ \
DATA_TYPE *haddr = atomic_mmu_lookup(env, addr, oi, DATA_SIZE, \
PAGE_READ | PAGE_WRITE, retaddr); \
@@ -167,7 +167,7 @@ GEN_ATOMIC_HELPER(xor_fetch)
*/
#define GEN_ATOMIC_HELPER_FN(X, FN, XDATA_TYPE, RET) \
ABI_TYPE ATOMIC_NAME(X)(CPUArchState *env, target_ulong addr, \
- ABI_TYPE xval, TCGMemOpIdx oi, uintptr_t retaddr) \
+ ABI_TYPE xval, MemOpIdx oi, uintptr_t retaddr) \
{ \
XDATA_TYPE *haddr = atomic_mmu_lookup(env, addr, oi, DATA_SIZE, \
PAGE_READ | PAGE_WRITE, retaddr); \
@@ -211,7 +211,7 @@ GEN_ATOMIC_HELPER_FN(umax_fetch, MAX, DATA_TYPE, new)
ABI_TYPE ATOMIC_NAME(cmpxchg)(CPUArchState *env, target_ulong addr,
ABI_TYPE cmpv, ABI_TYPE newv,
- TCGMemOpIdx oi, uintptr_t retaddr)
+ MemOpIdx oi, uintptr_t retaddr)
{
DATA_TYPE *haddr = atomic_mmu_lookup(env, addr, oi, DATA_SIZE,
PAGE_READ | PAGE_WRITE, retaddr);
@@ -231,7 +231,7 @@ ABI_TYPE ATOMIC_NAME(cmpxchg)(CPUArchState *env, target_ulong addr,
#if DATA_SIZE >= 16
#if HAVE_ATOMIC128
ABI_TYPE ATOMIC_NAME(ld)(CPUArchState *env, target_ulong addr,
- TCGMemOpIdx oi, uintptr_t retaddr)
+ MemOpIdx oi, uintptr_t retaddr)
{
DATA_TYPE *haddr = atomic_mmu_lookup(env, addr, oi, DATA_SIZE,
PAGE_READ, retaddr);
@@ -245,7 +245,7 @@ ABI_TYPE ATOMIC_NAME(ld)(CPUArchState *env, target_ulong addr,
}
void ATOMIC_NAME(st)(CPUArchState *env, target_ulong addr, ABI_TYPE val,
- TCGMemOpIdx oi, uintptr_t retaddr)
+ MemOpIdx oi, uintptr_t retaddr)
{
DATA_TYPE *haddr = atomic_mmu_lookup(env, addr, oi, DATA_SIZE,
PAGE_WRITE, retaddr);
@@ -260,7 +260,7 @@ void ATOMIC_NAME(st)(CPUArchState *env, target_ulong addr, ABI_TYPE val,
#endif
#else
ABI_TYPE ATOMIC_NAME(xchg)(CPUArchState *env, target_ulong addr, ABI_TYPE val,
- TCGMemOpIdx oi, uintptr_t retaddr)
+ MemOpIdx oi, uintptr_t retaddr)
{
DATA_TYPE *haddr = atomic_mmu_lookup(env, addr, oi, DATA_SIZE,
PAGE_READ | PAGE_WRITE, retaddr);
@@ -275,7 +275,7 @@ ABI_TYPE ATOMIC_NAME(xchg)(CPUArchState *env, target_ulong addr, ABI_TYPE val,
#define GEN_ATOMIC_HELPER(X) \
ABI_TYPE ATOMIC_NAME(X)(CPUArchState *env, target_ulong addr, \
- ABI_TYPE val, TCGMemOpIdx oi, uintptr_t retaddr) \
+ ABI_TYPE val, MemOpIdx oi, uintptr_t retaddr) \
{ \
DATA_TYPE *haddr = atomic_mmu_lookup(env, addr, oi, DATA_SIZE, \
PAGE_READ | PAGE_WRITE, retaddr); \
@@ -305,7 +305,7 @@ GEN_ATOMIC_HELPER(xor_fetch)
*/
#define GEN_ATOMIC_HELPER_FN(X, FN, XDATA_TYPE, RET) \
ABI_TYPE ATOMIC_NAME(X)(CPUArchState *env, target_ulong addr, \
- ABI_TYPE xval, TCGMemOpIdx oi, uintptr_t retaddr) \
+ ABI_TYPE xval, MemOpIdx oi, uintptr_t retaddr) \
{ \
XDATA_TYPE *haddr = atomic_mmu_lookup(env, addr, oi, DATA_SIZE, \
PAGE_READ | PAGE_WRITE, retaddr); \
diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h
index 44ccd86f3e..f91ebd0743 100644
--- a/include/tcg/tcg.h
+++ b/include/tcg/tcg.h
@@ -1148,7 +1148,7 @@ static inline size_t tcg_current_code_size(TCGContext *s)
}
/* Combine the MemOp and mmu_idx parameters into a single value. */
-typedef uint32_t TCGMemOpIdx;
+typedef uint32_t MemOpIdx;
/**
* make_memop_idx
@@ -1157,7 +1157,7 @@ typedef uint32_t TCGMemOpIdx;
*
* Encode these values into a single parameter.
*/
-static inline TCGMemOpIdx make_memop_idx(MemOp op, unsigned idx)
+static inline MemOpIdx make_memop_idx(MemOp op, unsigned idx)
{
tcg_debug_assert(idx <= 15);
return (op << 4) | idx;
@@ -1169,7 +1169,7 @@ static inline TCGMemOpIdx make_memop_idx(MemOp op, unsigned idx)
*
* Extract the memory operation from the combined value.
*/
-static inline MemOp get_memop(TCGMemOpIdx oi)
+static inline MemOp get_memop(MemOpIdx oi)
{
return oi >> 4;
}
@@ -1180,7 +1180,7 @@ static inline MemOp get_memop(TCGMemOpIdx oi)
*
* Extract the mmu index from the combined value.
*/
-static inline unsigned get_mmuidx(TCGMemOpIdx oi)
+static inline unsigned get_mmuidx(MemOpIdx oi)
{
return oi & 15;
}
@@ -1278,46 +1278,46 @@ uint64_t dup_const(unsigned vece, uint64_t c);
#ifdef CONFIG_SOFTMMU
/* Value zero-extended to tcg register size. */
tcg_target_ulong helper_ret_ldub_mmu(CPUArchState *env, target_ulong addr,
- TCGMemOpIdx oi, uintptr_t retaddr);
+ MemOpIdx oi, uintptr_t retaddr);
tcg_target_ulong helper_le_lduw_mmu(CPUArchState *env, target_ulong addr,
- TCGMemOpIdx oi, uintptr_t retaddr);
+ MemOpIdx oi, uintptr_t retaddr);
tcg_target_ulong helper_le_ldul_mmu(CPUArchState *env, target_ulong addr,
- TCGMemOpIdx oi, uintptr_t retaddr);
+ MemOpIdx oi, uintptr_t retaddr);
uint64_t helper_le_ldq_mmu(CPUArchState *env, target_ulong addr,
- TCGMemOpIdx oi, uintptr_t retaddr);
+ MemOpIdx oi, uintptr_t retaddr);
tcg_target_ulong helper_be_lduw_mmu(CPUArchState *env, target_ulong addr,
- TCGMemOpIdx oi, uintptr_t retaddr);
+ MemOpIdx oi, uintptr_t retaddr);
tcg_target_ulong helper_be_ldul_mmu(CPUArchState *env, target_ulong addr,
- TCGMemOpIdx oi, uintptr_t retaddr);
+ MemOpIdx oi, uintptr_t retaddr);
uint64_t helper_be_ldq_mmu(CPUArchState *env, target_ulong addr,
- TCGMemOpIdx oi, uintptr_t retaddr);
+ MemOpIdx oi, uintptr_t retaddr);
/* Value sign-extended to tcg register size. */
tcg_target_ulong helper_ret_ldsb_mmu(CPUArchState *env, target_ulong addr,
- TCGMemOpIdx oi, uintptr_t retaddr);
+ MemOpIdx oi, uintptr_t retaddr);
tcg_target_ulong helper_le_ldsw_mmu(CPUArchState *env, target_ulong addr,
- TCGMemOpIdx oi, uintptr_t retaddr);
+ MemOpIdx oi, uintptr_t retaddr);
tcg_target_ulong helper_le_ldsl_mmu(CPUArchState *env, target_ulong addr,
- TCGMemOpIdx oi, uintptr_t retaddr);
+ MemOpIdx oi, uintptr_t retaddr);
tcg_target_ulong helper_be_ldsw_mmu(CPUArchState *env, target_ulong addr,
- TCGMemOpIdx oi, uintptr_t retaddr);
+ MemOpIdx oi, uintptr_t retaddr);
tcg_target_ulong helper_be_ldsl_mmu(CPUArchState *env, target_ulong addr,
- TCGMemOpIdx oi, uintptr_t retaddr);
+ MemOpIdx oi, uintptr_t retaddr);
void helper_ret_stb_mmu(CPUArchState *env, target_ulong addr, uint8_t val,
- TCGMemOpIdx oi, uintptr_t retaddr);
+ MemOpIdx oi, uintptr_t retaddr);
void helper_le_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val,
- TCGMemOpIdx oi, uintptr_t retaddr);
+ MemOpIdx oi, uintptr_t retaddr);
void helper_le_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val,
- TCGMemOpIdx oi, uintptr_t retaddr);
+ MemOpIdx oi, uintptr_t retaddr);
void helper_le_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val,
- TCGMemOpIdx oi, uintptr_t retaddr);
+ MemOpIdx oi, uintptr_t retaddr);
void helper_be_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val,
- TCGMemOpIdx oi, uintptr_t retaddr);
+ MemOpIdx oi, uintptr_t retaddr);
void helper_be_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val,
- TCGMemOpIdx oi, uintptr_t retaddr);
+ MemOpIdx oi, uintptr_t retaddr);
void helper_be_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val,
- TCGMemOpIdx oi, uintptr_t retaddr);
+ MemOpIdx oi, uintptr_t retaddr);
/* Temporary aliases until backends are converted. */
#ifdef TARGET_WORDS_BIGENDIAN
@@ -1345,30 +1345,30 @@ void helper_be_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val,
uint32_t cpu_atomic_cmpxchgb_mmu(CPUArchState *env, target_ulong addr,
uint32_t cmpv, uint32_t newv,
- TCGMemOpIdx oi, uintptr_t retaddr);
+ MemOpIdx oi, uintptr_t retaddr);
uint32_t cpu_atomic_cmpxchgw_le_mmu(CPUArchState *env, target_ulong addr,
uint32_t cmpv, uint32_t newv,
- TCGMemOpIdx oi, uintptr_t retaddr);
+ MemOpIdx oi, uintptr_t retaddr);
uint32_t cpu_atomic_cmpxchgl_le_mmu(CPUArchState *env, target_ulong addr,
uint32_t cmpv, uint32_t newv,
- TCGMemOpIdx oi, uintptr_t retaddr);
+ MemOpIdx oi, uintptr_t retaddr);
uint64_t cpu_atomic_cmpxchgq_le_mmu(CPUArchState *env, target_ulong addr,
uint64_t cmpv, uint64_t newv,
- TCGMemOpIdx oi, uintptr_t retaddr);
+ MemOpIdx oi, uintptr_t retaddr);
uint32_t cpu_atomic_cmpxchgw_be_mmu(CPUArchState *env, target_ulong addr,
uint32_t cmpv, uint32_t newv,
- TCGMemOpIdx oi, uintptr_t retaddr);
+ MemOpIdx oi, uintptr_t retaddr);
uint32_t cpu_atomic_cmpxchgl_be_mmu(CPUArchState *env, target_ulong addr,
uint32_t cmpv, uint32_t newv,
- TCGMemOpIdx oi, uintptr_t retaddr);
+ MemOpIdx oi, uintptr_t retaddr);
uint64_t cpu_atomic_cmpxchgq_be_mmu(CPUArchState *env, target_ulong addr,
uint64_t cmpv, uint64_t newv,
- TCGMemOpIdx oi, uintptr_t retaddr);
+ MemOpIdx oi, uintptr_t retaddr);
#define GEN_ATOMIC_HELPER(NAME, TYPE, SUFFIX) \
TYPE cpu_atomic_ ## NAME ## SUFFIX ## _mmu \
(CPUArchState *env, target_ulong addr, TYPE val, \
- TCGMemOpIdx oi, uintptr_t retaddr);
+ MemOpIdx oi, uintptr_t retaddr);
#ifdef CONFIG_ATOMIC64
#define GEN_ATOMIC_HELPER_ALL(NAME) \
@@ -1415,19 +1415,19 @@ GEN_ATOMIC_HELPER_ALL(xchg)
Int128 cpu_atomic_cmpxchgo_le_mmu(CPUArchState *env, target_ulong addr,
Int128 cmpv, Int128 newv,
- TCGMemOpIdx oi, uintptr_t retaddr);
+ MemOpIdx oi, uintptr_t retaddr);
Int128 cpu_atomic_cmpxchgo_be_mmu(CPUArchState *env, target_ulong addr,
Int128 cmpv, Int128 newv,
- TCGMemOpIdx oi, uintptr_t retaddr);
+ MemOpIdx oi, uintptr_t retaddr);
Int128 cpu_atomic_ldo_le_mmu(CPUArchState *env, target_ulong addr,
- TCGMemOpIdx oi, uintptr_t retaddr);
+ MemOpIdx oi, uintptr_t retaddr);
Int128 cpu_atomic_ldo_be_mmu(CPUArchState *env, target_ulong addr,
- TCGMemOpIdx oi, uintptr_t retaddr);
+ MemOpIdx oi, uintptr_t retaddr);
void cpu_atomic_sto_le_mmu(CPUArchState *env, target_ulong addr, Int128 val,
- TCGMemOpIdx oi, uintptr_t retaddr);
+ MemOpIdx oi, uintptr_t retaddr);
void cpu_atomic_sto_be_mmu(CPUArchState *env, target_ulong addr, Int128 val,
- TCGMemOpIdx oi, uintptr_t retaddr);
+ MemOpIdx oi, uintptr_t retaddr);
#ifdef CONFIG_DEBUG_TCG
void tcg_assert_listed_vecop(TCGOpcode);
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index 0a1fdbefdd..d72f65f42b 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -1749,7 +1749,7 @@ bool tlb_plugin_lookup(CPUState *cpu, target_ulong addr, int mmu_idx,
* @prot may be PAGE_READ, PAGE_WRITE, or PAGE_READ|PAGE_WRITE.
*/
static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr,
- TCGMemOpIdx oi, int size, int prot,
+ MemOpIdx oi, int size, int prot,
uintptr_t retaddr)
{
size_t mmu_idx = get_mmuidx(oi);
@@ -1850,7 +1850,7 @@ static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr,
*/
typedef uint64_t FullLoadHelper(CPUArchState *env, target_ulong addr,
- TCGMemOpIdx oi, uintptr_t retaddr);
+ MemOpIdx oi, uintptr_t retaddr);
static inline uint64_t QEMU_ALWAYS_INLINE
load_memop(const void *haddr, MemOp op)
@@ -1876,7 +1876,7 @@ load_memop(const void *haddr, MemOp op)
}
static inline uint64_t QEMU_ALWAYS_INLINE
-load_helper(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi,
+load_helper(CPUArchState *env, target_ulong addr, MemOpIdx oi,
uintptr_t retaddr, MemOp op, bool code_read,
FullLoadHelper *full_load)
{
@@ -1991,78 +1991,78 @@ load_helper(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi,
*/
static uint64_t full_ldub_mmu(CPUArchState *env, target_ulong addr,
- TCGMemOpIdx oi, uintptr_t retaddr)
+ MemOpIdx oi, uintptr_t retaddr)
{
return load_helper(env, addr, oi, retaddr, MO_UB, false, full_ldub_mmu);
}
tcg_target_ulong helper_ret_ldub_mmu(CPUArchState *env, target_ulong addr,
- TCGMemOpIdx oi, uintptr_t retaddr)
+ MemOpIdx oi, uintptr_t retaddr)
{
return full_ldub_mmu(env, addr, oi, retaddr);
}
static uint64_t full_le_lduw_mmu(CPUArchState *env, target_ulong addr,
- TCGMemOpIdx oi, uintptr_t retaddr)
+ MemOpIdx oi, uintptr_t retaddr)
{
return load_helper(env, addr, oi, retaddr, MO_LEUW, false,
full_le_lduw_mmu);
}
tcg_target_ulong helper_le_lduw_mmu(CPUArchState *env, target_ulong addr,
- TCGMemOpIdx oi, uintptr_t retaddr)
+ MemOpIdx oi, uintptr_t retaddr)
{
return full_le_lduw_mmu(env, addr, oi, retaddr);
}
static uint64_t full_be_lduw_mmu(CPUArchState *env, target_ulong addr,
- TCGMemOpIdx oi, uintptr_t retaddr)
+ MemOpIdx oi, uintptr_t retaddr)
{
return load_helper(env, addr, oi, retaddr, MO_BEUW, false,
full_be_lduw_mmu);
}
tcg_target_ulong helper_be_lduw_mmu(CPUArchState *env, target_ulong addr,
- TCGMemOpIdx oi, uintptr_t retaddr)
+ MemOpIdx oi, uintptr_t retaddr)
{
return full_be_lduw_mmu(env, addr, oi, retaddr);
}
static uint64_t full_le_ldul_mmu(CPUArchState *env, target_ulong addr,
- TCGMemOpIdx oi, uintptr_t retaddr)
+ MemOpIdx oi, uintptr_t retaddr)
{
return load_helper(env, addr, oi, retaddr, MO_LEUL, false,
full_le_ldul_mmu);
}
tcg_target_ulong helper_le_ldul_mmu(CPUArchState *env, target_ulong addr,
- TCGMemOpIdx oi, uintptr_t retaddr)
+ MemOpIdx oi, uintptr_t retaddr)
{
return full_le_ldul_mmu(env, addr, oi, retaddr);
}
static uint64_t full_be_ldul_mmu(CPUArchState *env, target_ulong addr,
- TCGMemOpIdx oi, uintptr_t retaddr)
+ MemOpIdx oi, uintptr_t retaddr)
{
return load_helper(env, addr, oi, retaddr, MO_BEUL, false,
full_be_ldul_mmu);
}
tcg_target_ulong helper_be_ldul_mmu(CPUArchState *env, target_ulong addr,
- TCGMemOpIdx oi, uintptr_t retaddr)
+ MemOpIdx oi, uintptr_t retaddr)
{
return full_be_ldul_mmu(env, addr, oi, retaddr);
}
uint64_t helper_le_ldq_mmu(CPUArchState *env, target_ulong addr,
- TCGMemOpIdx oi, uintptr_t retaddr)
+ MemOpIdx oi, uintptr_t retaddr)
{
return load_helper(env, addr, oi, retaddr, MO_LEQ, false,
helper_le_ldq_mmu);
}
uint64_t helper_be_ldq_mmu(CPUArchState *env, target_ulong addr,
- TCGMemOpIdx oi, uintptr_t retaddr)
+ MemOpIdx oi, uintptr_t retaddr)
{
return load_helper(env, addr, oi, retaddr, MO_BEQ, false,
helper_be_ldq_mmu);
@@ -2075,31 +2075,31 @@ uint64_t helper_be_ldq_mmu(CPUArchState *env, target_ulong addr,
tcg_target_ulong helper_ret_ldsb_mmu(CPUArchState *env, target_ulong addr,
- TCGMemOpIdx oi, uintptr_t retaddr)
+ MemOpIdx oi, uintptr_t retaddr)
{
return (int8_t)helper_ret_ldub_mmu(env, addr, oi, retaddr);
}
tcg_target_ulong helper_le_ldsw_mmu(CPUArchState *env, target_ulong addr,
- TCGMemOpIdx oi, uintptr_t retaddr)
+ MemOpIdx oi, uintptr_t retaddr)
{
return (int16_t)helper_le_lduw_mmu(env, addr, oi, retaddr);
}
tcg_target_ulong helper_be_ldsw_mmu(CPUArchState *env, target_ulong addr,
- TCGMemOpIdx oi, uintptr_t retaddr)
+ MemOpIdx oi, uintptr_t retaddr)
{
return (int16_t)helper_be_lduw_mmu(env, addr, oi, retaddr);
}
tcg_target_ulong helper_le_ldsl_mmu(CPUArchState *env, target_ulong addr,
- TCGMemOpIdx oi, uintptr_t retaddr)
+ MemOpIdx oi, uintptr_t retaddr)
{
return (int32_t)helper_le_ldul_mmu(env, addr, oi, retaddr);
}
tcg_target_ulong helper_be_ldsl_mmu(CPUArchState *env, target_ulong addr,
- TCGMemOpIdx oi, uintptr_t retaddr)
+ MemOpIdx oi, uintptr_t retaddr)
{
return (int32_t)helper_be_ldul_mmu(env, addr, oi, retaddr);
}
@@ -2113,7 +2113,7 @@ static inline uint64_t cpu_load_helper(CPUArchState *env, abi_ptr addr,
MemOp op, FullLoadHelper *full_load)
{
uint16_t meminfo;
- TCGMemOpIdx oi;
+ MemOpIdx oi;
uint64_t ret;
meminfo = trace_mem_get_info(op, mmu_idx, false);
@@ -2337,7 +2337,7 @@ store_helper_unaligned(CPUArchState *env, target_ulong addr, uint64_t val,
uintptr_t index, index2;
CPUTLBEntry *entry, *entry2;
target_ulong page2, tlb_addr, tlb_addr2;
- TCGMemOpIdx oi;
+ MemOpIdx oi;
size_t size2;
int i;
@@ -2404,7 +2404,7 @@ store_helper_unaligned(CPUArchState *env, target_ulong addr, uint64_t val,
static inline void QEMU_ALWAYS_INLINE
store_helper(CPUArchState *env, target_ulong addr, uint64_t val,
- TCGMemOpIdx oi, uintptr_t retaddr, MemOp op)
+ MemOpIdx oi, uintptr_t retaddr, MemOp op)
{
uintptr_t mmu_idx = get_mmuidx(oi);
uintptr_t index = tlb_index(env, mmu_idx, addr);
@@ -2502,43 +2502,43 @@ store_helper(CPUArchState *env, target_ulong addr, uint64_t val,
void __attribute__((noinline))
helper_ret_stb_mmu(CPUArchState *env, target_ulong addr, uint8_t val,
- TCGMemOpIdx oi, uintptr_t retaddr)
+ MemOpIdx oi, uintptr_t retaddr)
{
store_helper(env, addr, val, oi, retaddr, MO_UB);
}
void helper_le_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val,
- TCGMemOpIdx oi, uintptr_t retaddr)
+ MemOpIdx oi, uintptr_t retaddr)
{
store_helper(env, addr, val, oi, retaddr, MO_LEUW);
}
void helper_be_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val,
- TCGMemOpIdx oi, uintptr_t retaddr)
+ MemOpIdx oi, uintptr_t retaddr)
{
store_helper(env, addr, val, oi, retaddr, MO_BEUW);
}
void helper_le_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val,
- TCGMemOpIdx oi, uintptr_t retaddr)
+ MemOpIdx oi, uintptr_t retaddr)
{
store_helper(env, addr, val, oi, retaddr, MO_LEUL);
}
void helper_be_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val,
- TCGMemOpIdx oi, uintptr_t retaddr)
+ MemOpIdx oi, uintptr_t retaddr)
{
store_helper(env, addr, val, oi, retaddr, MO_BEUL);
}
void helper_le_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val,
- TCGMemOpIdx oi, uintptr_t retaddr)
+ MemOpIdx oi, uintptr_t retaddr)
{
store_helper(env, addr, val, oi, retaddr, MO_LEQ);
}
void helper_be_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val,
- TCGMemOpIdx oi, uintptr_t retaddr)
+ MemOpIdx oi, uintptr_t retaddr)
{
store_helper(env, addr, val, oi, retaddr, MO_BEQ);
}
@@ -2551,7 +2551,7 @@ static inline void QEMU_ALWAYS_INLINE
cpu_store_helper(CPUArchState *env, target_ulong addr, uint64_t val,
int mmu_idx, uintptr_t retaddr, MemOp op)
{
- TCGMemOpIdx oi;
+ MemOpIdx oi;
uint16_t meminfo;
meminfo = trace_mem_get_info(op, mmu_idx, true);
@@ -2717,49 +2717,49 @@ void cpu_stq_le_data(CPUArchState *env, target_ulong ptr, uint64_t val)
/* Code access functions. */
static uint64_t full_ldub_code(CPUArchState *env, target_ulong addr,
- TCGMemOpIdx oi, uintptr_t retaddr)
+ MemOpIdx oi, uintptr_t retaddr)
{
return load_helper(env, addr, oi, retaddr, MO_8, true, full_ldub_code);
}
uint32_t cpu_ldub_code(CPUArchState *env, abi_ptr addr)
{
- TCGMemOpIdx oi = make_memop_idx(MO_UB, cpu_mmu_index(env, true));
+ MemOpIdx oi = make_memop_idx(MO_UB, cpu_mmu_index(env, true));
return full_ldub_code(env, addr, oi, 0);
}
static uint64_t full_lduw_code(CPUArchState *env, target_ulong addr,
- TCGMemOpIdx oi, uintptr_t retaddr)
+ MemOpIdx oi, uintptr_t retaddr)
{
return load_helper(env, addr, oi, retaddr, MO_TEUW, true, full_lduw_code);
}
uint32_t cpu_lduw_code(CPUArchState *env, abi_ptr addr)
{
- TCGMemOpIdx oi = make_memop_idx(MO_TEUW, cpu_mmu_index(env, true));
+ MemOpIdx oi = make_memop_idx(MO_TEUW, cpu_mmu_index(env, true));
return full_lduw_code(env, addr, oi, 0);
}
static uint64_t full_ldl_code(CPUArchState *env, target_ulong addr,
- TCGMemOpIdx oi, uintptr_t retaddr)
+ MemOpIdx oi, uintptr_t retaddr)
{
return load_helper(env, addr, oi, retaddr, MO_TEUL, true, full_ldl_code);
}
uint32_t cpu_ldl_code(CPUArchState *env, abi_ptr addr)
{
- TCGMemOpIdx oi = make_memop_idx(MO_TEUL, cpu_mmu_index(env, true));
+ MemOpIdx oi = make_memop_idx(MO_TEUL, cpu_mmu_index(env, true));
return full_ldl_code(env, addr, oi, 0);
}
static uint64_t full_ldq_code(CPUArchState *env, target_ulong addr,
- TCGMemOpIdx oi, uintptr_t retaddr)
+ MemOpIdx oi, uintptr_t retaddr)
{
return load_helper(env, addr, oi, retaddr, MO_TEQ, true, full_ldq_code);
}
uint64_t cpu_ldq_code(CPUArchState *env, abi_ptr addr)
{
- TCGMemOpIdx oi = make_memop_idx(MO_TEQ, cpu_mmu_index(env, true));
+ MemOpIdx oi = make_memop_idx(MO_TEQ, cpu_mmu_index(env, true));
return full_ldq_code(env, addr, oi, 0);
}
diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
index f17b75e0aa..eb672eae3a 100644
--- a/accel/tcg/user-exec.c
+++ b/accel/tcg/user-exec.c
@@ -1204,7 +1204,7 @@ uint64_t cpu_ldq_code(CPUArchState *env, abi_ptr ptr)
* @prot may be PAGE_READ, PAGE_WRITE, or PAGE_READ|PAGE_WRITE.
*/
static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr,
- TCGMemOpIdx oi, int size, int prot,
+ MemOpIdx oi, int size, int prot,
uintptr_t retaddr)
{
MemOp mop = get_memop(oi);
diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
index 26f79f9141..13d1e3f808 100644
--- a/target/arm/helper-a64.c
+++ b/target/arm/helper-a64.c
@@ -531,8 +531,8 @@ uint64_t HELPER(paired_cmpxchg64_le)(CPUARMState *env, uint64_t addr,
clear_helper_retaddr();
#else
int mem_idx = cpu_mmu_index(env, false);
- TCGMemOpIdx oi0 = make_memop_idx(MO_LEQ | MO_ALIGN_16, mem_idx);
- TCGMemOpIdx oi1 = make_memop_idx(MO_LEQ, mem_idx);
+ MemOpIdx oi0 = make_memop_idx(MO_LEQ | MO_ALIGN_16, mem_idx);
+ MemOpIdx oi1 = make_memop_idx(MO_LEQ, mem_idx);
o0 = helper_le_ldq_mmu(env, addr + 0, oi0, ra);
o1 = helper_le_ldq_mmu(env, addr + 8, oi1, ra);
@@ -555,7 +555,7 @@ uint64_t HELPER(paired_cmpxchg64_le_parallel)(CPUARMState *env, uint64_t addr,
uintptr_t ra = GETPC();
bool success;
int mem_idx;
- TCGMemOpIdx oi;
+ MemOpIdx oi;
assert(HAVE_CMPXCHG128);
@@ -601,8 +601,8 @@ uint64_t HELPER(paired_cmpxchg64_be)(CPUARMState *env, uint64_t addr,
clear_helper_retaddr();
#else
int mem_idx = cpu_mmu_index(env, false);
- TCGMemOpIdx oi0 = make_memop_idx(MO_BEQ | MO_ALIGN_16, mem_idx);
- TCGMemOpIdx oi1 = make_memop_idx(MO_BEQ, mem_idx);
+ MemOpIdx oi0 = make_memop_idx(MO_BEQ | MO_ALIGN_16, mem_idx);
+ MemOpIdx oi1 = make_memop_idx(MO_BEQ, mem_idx);
o1 = helper_be_ldq_mmu(env, addr + 0, oi0, ra);
o0 = helper_be_ldq_mmu(env, addr + 8, oi1, ra);
@@ -625,7 +625,7 @@ uint64_t HELPER(paired_cmpxchg64_be_parallel)(CPUARMState *env, uint64_t addr,
uintptr_t ra = GETPC();
bool success;
int mem_idx;
- TCGMemOpIdx oi;
+ MemOpIdx oi;
assert(HAVE_CMPXCHG128);
@@ -651,7 +651,7 @@ void HELPER(casp_le_parallel)(CPUARMState *env, uint32_t rs, uint64_t addr,
Int128 oldv, cmpv, newv;
uintptr_t ra = GETPC();
int mem_idx;
- TCGMemOpIdx oi;
+ MemOpIdx oi;
assert(HAVE_CMPXCHG128);
@@ -672,7 +672,7 @@ void HELPER(casp_be_parallel)(CPUARMState *env, uint32_t rs, uint64_t addr,
Int128 oldv, cmpv, newv;
uintptr_t ra = GETPC();
int mem_idx;
- TCGMemOpIdx oi;
+ MemOpIdx oi;
assert(HAVE_CMPXCHG128);
diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
index 20761c9487..efb522dc44 100644
--- a/target/arm/m_helper.c
+++ b/target/arm/m_helper.c
@@ -1930,7 +1930,7 @@ static bool do_v7m_function_return(ARMCPU *cpu)
{
bool threadmode, spsel;
- TCGMemOpIdx oi;
+ MemOpIdx oi;
ARMMMUIdx mmu_idx;
uint32_t *frame_sp_p;
uint32_t frameptr;
diff --git a/target/i386/tcg/mem_helper.c b/target/i386/tcg/mem_helper.c
index 2da3cd14b6..0fd696f9c1 100644
--- a/target/i386/tcg/mem_helper.c
+++ b/target/i386/tcg/mem_helper.c
@@ -67,7 +67,7 @@ void helper_cmpxchg8b(CPUX86State *env, target_ulong a0)
{
uintptr_t ra = GETPC();
int mem_idx = cpu_mmu_index(env, false);
- TCGMemOpIdx oi = make_memop_idx(MO_TEQ, mem_idx);
+ MemOpIdx oi = make_memop_idx(MO_TEQ, mem_idx);
oldv = cpu_atomic_cmpxchgq_le_mmu(env, a0, cmpv, newv, oi, ra);
}
@@ -136,7 +136,7 @@ void helper_cmpxchg16b(CPUX86State *env, target_ulong a0)
Int128 newv = int128_make128(env->regs[R_EBX], env->regs[R_ECX]);
int mem_idx = cpu_mmu_index(env, false);
- TCGMemOpIdx oi = make_memop_idx(MO_TEQ | MO_ALIGN_16, mem_idx);
+ MemOpIdx oi = make_memop_idx(MO_TEQ | MO_ALIGN_16, mem_idx);
Int128 oldv = cpu_atomic_cmpxchgo_le_mmu(env, a0, cmpv, newv, oi, ra);
if (int128_eq(oldv, cmpv)) {
diff --git a/target/m68k/op_helper.c b/target/m68k/op_helper.c
index d006d1cb3e..5918a29516 100644
--- a/target/m68k/op_helper.c
+++ b/target/m68k/op_helper.c
@@ -785,7 +785,7 @@ static void do_cas2l(CPUM68KState *env, uint32_t regs, uint32_t a1, uint32_t a2,
uintptr_t ra = GETPC();
#if defined(CONFIG_ATOMIC64)
int mmu_idx = cpu_mmu_index(env, 0);
- TCGMemOpIdx oi = make_memop_idx(MO_BEQ, mmu_idx);
+ MemOpIdx oi = make_memop_idx(MO_BEQ, mmu_idx);
#endif
if (parallel) {
diff --git a/target/mips/tcg/msa_helper.c b/target/mips/tcg/msa_helper.c
index 04af54f66d..167d9a591c 100644
--- a/target/mips/tcg/msa_helper.c
+++ b/target/mips/tcg/msa_helper.c
@@ -8211,9 +8211,9 @@ void helper_msa_ffint_u_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
#define DF_ELEMENTS(df) (MSA_WRLEN / DF_BITS(df))
#if !defined(CONFIG_USER_ONLY)
-#define MEMOP_IDX(DF) \
- TCGMemOpIdx oi = make_memop_idx(MO_TE | DF | MO_UNALN, \
- cpu_mmu_index(env, false));
+#define MEMOP_IDX(DF) \
+ MemOpIdx oi = make_memop_idx(MO_TE | DF | MO_UNALN, \
+ cpu_mmu_index(env, false));
#else
#define MEMOP_IDX(DF)
#endif
diff --git a/target/s390x/tcg/mem_helper.c b/target/s390x/tcg/mem_helper.c
index 21a4de4067..ec88f5dbb0 100644
--- a/target/s390x/tcg/mem_helper.c
+++ b/target/s390x/tcg/mem_helper.c
@@ -238,7 +238,7 @@ static void do_access_memset(CPUS390XState *env, vaddr vaddr, char *haddr,
g_assert(haddr);
memset(haddr, byte, size);
#else
- TCGMemOpIdx oi = make_memop_idx(MO_UB, mmu_idx);
+ MemOpIdx oi = make_memop_idx(MO_UB, mmu_idx);
int i;
if (likely(haddr)) {
@@ -281,7 +281,7 @@ static uint8_t do_access_get_byte(CPUS390XState *env, vaddr vaddr, char **haddr,
#ifdef CONFIG_USER_ONLY
return ldub_p(*haddr + offset);
#else
- TCGMemOpIdx oi = make_memop_idx(MO_UB, mmu_idx);
+ MemOpIdx oi = make_memop_idx(MO_UB, mmu_idx);
uint8_t byte;
if (likely(*haddr)) {
@@ -315,7 +315,7 @@ static void do_access_set_byte(CPUS390XState *env, vaddr vaddr, char **haddr,
#ifdef CONFIG_USER_ONLY
stb_p(*haddr + offset, byte);
#else
- TCGMemOpIdx oi = make_memop_idx(MO_UB, mmu_idx);
+ MemOpIdx oi = make_memop_idx(MO_UB, mmu_idx);
if (likely(*haddr)) {
stb_p(*haddr + offset, byte);
@@ -1803,7 +1803,7 @@ void HELPER(cdsg_parallel)(CPUS390XState *env, uint64_t addr,
Int128 cmpv = int128_make128(env->regs[r1 + 1], env->regs[r1]);
Int128 newv = int128_make128(env->regs[r3 + 1], env->regs[r3]);
int mem_idx;
- TCGMemOpIdx oi;
+ MemOpIdx oi;
Int128 oldv;
bool fail;
@@ -1883,7 +1883,7 @@ static uint32_t do_csst(CPUS390XState *env, uint32_t r3, uint64_t a1,
uint32_t *haddr = g2h(env_cpu(env), a1);
ov = qatomic_cmpxchg__nocheck(haddr, cv, nv);
#else
- TCGMemOpIdx oi = make_memop_idx(MO_TEUL | MO_ALIGN, mem_idx);
+ MemOpIdx oi = make_memop_idx(MO_TEUL | MO_ALIGN, mem_idx);
ov = cpu_atomic_cmpxchgl_be_mmu(env, a1, cv, nv, oi, ra);
#endif
} else {
@@ -1903,7 +1903,7 @@ static uint32_t do_csst(CPUS390XState *env, uint32_t r3, uint64_t a1,
if (parallel) {
#ifdef CONFIG_ATOMIC64
- TCGMemOpIdx oi = make_memop_idx(MO_TEQ | MO_ALIGN, mem_idx);
+ MemOpIdx oi = make_memop_idx(MO_TEQ | MO_ALIGN, mem_idx);
ov = cpu_atomic_cmpxchgq_be_mmu(env, a1, cv, nv, oi, ra);
#else
/* Note that we asserted !parallel above. */
@@ -1939,7 +1939,7 @@ static uint32_t do_csst(CPUS390XState *env, uint32_t r3, uint64_t a1,
cpu_stq_data_ra(env, a1 + 0, int128_gethi(nv), ra);
cpu_stq_data_ra(env, a1 + 8, int128_getlo(nv), ra);
} else if (HAVE_CMPXCHG128) {
- TCGMemOpIdx oi = make_memop_idx(MO_TEQ | MO_ALIGN_16, mem_idx);
+ MemOpIdx oi = make_memop_idx(MO_TEQ | MO_ALIGN_16, mem_idx);
ov = cpu_atomic_cmpxchgo_be_mmu(env, a1, cv, nv, oi, ra);
cc = !int128_eq(ov, cv);
} else {
@@ -1978,7 +1978,7 @@ static uint32_t do_csst(CPUS390XState *env, uint32_t r3, uint64_t a1,
cpu_stq_data_ra(env, a2 + 0, svh, ra);
cpu_stq_data_ra(env, a2 + 8, svl, ra);
} else if (HAVE_ATOMIC128) {
- TCGMemOpIdx oi = make_memop_idx(MO_TEQ | MO_ALIGN_16, mem_idx);
+ MemOpIdx oi = make_memop_idx(MO_TEQ | MO_ALIGN_16, mem_idx);
Int128 sv = int128_make128(svl, svh);
cpu_atomic_sto_be_mmu(env, a2, sv, oi, ra);
} else {
@@ -2474,7 +2474,7 @@ uint64_t HELPER(lpq_parallel)(CPUS390XState *env, uint64_t addr)
uintptr_t ra = GETPC();
uint64_t hi, lo;
int mem_idx;
- TCGMemOpIdx oi;
+ MemOpIdx oi;
Int128 v;
assert(HAVE_ATOMIC128);
@@ -2505,7 +2505,7 @@ void HELPER(stpq_parallel)(CPUS390XState *env, uint64_t addr,
{
uintptr_t ra = GETPC();
int mem_idx;
- TCGMemOpIdx oi;
+ MemOpIdx oi;
Int128 v;
assert(HAVE_ATOMIC128);
diff --git a/target/sparc/ldst_helper.c b/target/sparc/ldst_helper.c
index 69b812e68c..5c558d312a 100644
--- a/target/sparc/ldst_helper.c
+++ b/target/sparc/ldst_helper.c
@@ -1313,7 +1313,7 @@ uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr,
case ASI_SNF:
case ASI_SNFL:
{
- TCGMemOpIdx oi;
+ MemOpIdx oi;
int idx = (env->pstate & PS_PRIV
? (asi & 1 ? MMU_KERNEL_SECONDARY_IDX : MMU_KERNEL_IDX)
: (asi & 1 ? MMU_USER_SECONDARY_IDX : MMU_USER_IDX));
diff --git a/tcg/optimize.c b/tcg/optimize.c
index 9876ac52a8..c239c3bd07 100644
--- a/tcg/optimize.c
+++ b/tcg/optimize.c
@@ -1023,7 +1023,7 @@ void tcg_optimize(TCGContext *s)
CASE_OP_32_64(qemu_ld):
{
- TCGMemOpIdx oi = op->args[nb_oargs + nb_iargs];
+ MemOpIdx oi = op->args[nb_oargs + nb_iargs];
MemOp mop = get_memop(oi);
if (!(mop & MO_SIGN)) {
mask = (2ULL << ((8 << (mop & MO_SIZE)) - 1)) - 1;
diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c
index e01f68f44d..e1490c372e 100644
--- a/tcg/tcg-op.c
+++ b/tcg/tcg-op.c
@@ -2797,7 +2797,7 @@ static inline MemOp tcg_canonicalize_memop(MemOp op, bool is64, bool st)
static void gen_ldst_i32(TCGOpcode opc, TCGv_i32 val, TCGv addr,
MemOp memop, TCGArg idx)
{
- TCGMemOpIdx oi = make_memop_idx(memop, idx);
+ MemOpIdx oi = make_memop_idx(memop, idx);
#if TARGET_LONG_BITS == 32
tcg_gen_op3i_i32(opc, val, addr, oi);
#else
@@ -2812,7 +2812,7 @@ static void gen_ldst_i32(TCGOpcode opc, TCGv_i32 val, TCGv addr,
static void gen_ldst_i64(TCGOpcode opc, TCGv_i64 val, TCGv addr,
MemOp memop, TCGArg idx)
{
- TCGMemOpIdx oi = make_memop_idx(memop, idx);
+ MemOpIdx oi = make_memop_idx(memop, idx);
#if TARGET_LONG_BITS == 32
if (TCG_TARGET_REG_BITS == 32) {
tcg_gen_op4i_i32(opc, TCGV_LOW(val), TCGV_HIGH(val), addr, oi);
@@ -3132,7 +3132,7 @@ void tcg_gen_atomic_cmpxchg_i32(TCGv_i32 retv, TCGv addr, TCGv_i32 cmpv,
tcg_temp_free_i32(t1);
} else {
gen_atomic_cx_i32 gen;
- TCGMemOpIdx oi;
+ MemOpIdx oi;
gen = table_cmpxchg[memop & (MO_SIZE | MO_BSWAP)];
tcg_debug_assert(gen != NULL);
@@ -3171,7 +3171,7 @@ void tcg_gen_atomic_cmpxchg_i64(TCGv_i64 retv, TCGv addr, TCGv_i64 cmpv,
} else if ((memop & MO_SIZE) == MO_64) {
#ifdef CONFIG_ATOMIC64
gen_atomic_cx_i64 gen;
- TCGMemOpIdx oi;
+ MemOpIdx oi;
gen = table_cmpxchg[memop & (MO_SIZE | MO_BSWAP)];
tcg_debug_assert(gen != NULL);
@@ -3227,7 +3227,7 @@ static void do_atomic_op_i32(TCGv_i32 ret, TCGv addr, TCGv_i32 val,
TCGArg idx, MemOp memop, void * const table[])
{
gen_atomic_op_i32 gen;
- TCGMemOpIdx oi;
+ MemOpIdx oi;
memop = tcg_canonicalize_memop(memop, 0, 0);
@@ -3269,7 +3269,7 @@ static void do_atomic_op_i64(TCGv_i64 ret, TCGv addr, TCGv_i64 val,
if ((memop & MO_SIZE) == MO_64) {
#ifdef CONFIG_ATOMIC64
gen_atomic_op_i64 gen;
- TCGMemOpIdx oi;
+ MemOpIdx oi;
gen = table[memop & (MO_SIZE | MO_BSWAP)];
tcg_debug_assert(gen != NULL);
diff --git a/tcg/tcg.c b/tcg/tcg.c
index 4142d42d77..658be0c6b6 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -1910,7 +1910,7 @@ static void tcg_dump_ops(TCGContext *s, bool have_prefs)
case INDEX_op_qemu_ld_i64:
case INDEX_op_qemu_st_i64:
{
- TCGMemOpIdx oi = op->args[k++];
+ MemOpIdx oi = op->args[k++];
MemOp op = get_memop(oi);
unsigned ix = get_mmuidx(oi);
diff --git a/tcg/tci.c b/tcg/tci.c
index b672c7cae5..5c08dc0a9a 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -61,7 +61,7 @@ static uint64_t tci_uint64(uint32_t high, uint32_t low)
* i = immediate (uint32_t)
* I = immediate (tcg_target_ulong)
* l = label or pointer
- * m = immediate (TCGMemOpIdx)
+ * m = immediate (MemOpIdx)
* n = immediate (call return length)
* r = register
* s = signed ldst offset
@@ -105,7 +105,7 @@ static void tci_args_ri(uint32_t insn, TCGReg *r0, tcg_target_ulong *i1)
}
static void tci_args_rrm(uint32_t insn, TCGReg *r0,
- TCGReg *r1, TCGMemOpIdx *m2)
+ TCGReg *r1, MemOpIdx *m2)
{
*r0 = extract32(insn, 8, 4);
*r1 = extract32(insn, 12, 4);
@@ -145,7 +145,7 @@ static void tci_args_rrrc(uint32_t insn,
}
static void tci_args_rrrm(uint32_t insn,
- TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGMemOpIdx *m3)
+ TCGReg *r0, TCGReg *r1, TCGReg *r2, MemOpIdx *m3)
{
*r0 = extract32(insn, 8, 4);
*r1 = extract32(insn, 12, 4);
@@ -289,7 +289,7 @@ static bool tci_compare64(uint64_t u0, uint64_t u1, TCGCond condition)
}
static uint64_t tci_qemu_ld(CPUArchState *env, target_ulong taddr,
- TCGMemOpIdx oi, const void *tb_ptr)
+ MemOpIdx oi, const void *tb_ptr)
{
MemOp mop = get_memop(oi) & (MO_BSWAP | MO_SSIZE);
uintptr_t ra = (uintptr_t)tb_ptr;
@@ -374,7 +374,7 @@ static uint64_t tci_qemu_ld(CPUArchState *env, target_ulong taddr,
}
static void tci_qemu_st(CPUArchState *env, target_ulong taddr, uint64_t val,
- TCGMemOpIdx oi, const void *tb_ptr)
+ MemOpIdx oi, const void *tb_ptr)
{
MemOp mop = get_memop(oi) & (MO_BSWAP | MO_SSIZE);
uintptr_t ra = (uintptr_t)tb_ptr;
@@ -482,7 +482,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
uint32_t tmp32;
uint64_t tmp64;
uint64_t T1, T2;
- TCGMemOpIdx oi;
+ MemOpIdx oi;
int32_t ofs;
void *ptr;
@@ -1148,7 +1148,7 @@ int print_insn_tci(bfd_vma addr, disassemble_info *info)
tcg_target_ulong i1;
int32_t s2;
TCGCond c;
- TCGMemOpIdx oi;
+ MemOpIdx oi;
uint8_t pos, len;
void *ptr;
diff --git a/accel/tcg/atomic_common.c.inc b/accel/tcg/atomic_common.c.inc
index 6c0339f610..ebaa793464 100644
--- a/accel/tcg/atomic_common.c.inc
+++ b/accel/tcg/atomic_common.c.inc
@@ -14,7 +14,7 @@
*/
static uint16_t atomic_trace_rmw_pre(CPUArchState *env, target_ulong addr,
- TCGMemOpIdx oi)
+ MemOpIdx oi)
{
CPUState *cpu = env_cpu(env);
uint16_t info = trace_mem_get_info(get_memop(oi), get_mmuidx(oi), false);
@@ -34,7 +34,7 @@ static void atomic_trace_rmw_post(CPUArchState *env, target_ulong addr,
#if HAVE_ATOMIC128
static uint16_t atomic_trace_ld_pre(CPUArchState *env, target_ulong addr,
- TCGMemOpIdx oi)
+ MemOpIdx oi)
{
uint16_t info = trace_mem_get_info(get_memop(oi), get_mmuidx(oi), false);
@@ -50,7 +50,7 @@ static void atomic_trace_ld_post(CPUArchState *env, target_ulong addr,
}
static uint16_t atomic_trace_st_pre(CPUArchState *env, target_ulong addr,
- TCGMemOpIdx oi)
+ MemOpIdx oi)
{
uint16_t info = trace_mem_get_info(get_memop(oi), get_mmuidx(oi), true);
diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc
index 6f43c048a5..5edca8d44d 100644
--- a/tcg/aarch64/tcg-target.c.inc
+++ b/tcg/aarch64/tcg-target.c.inc
@@ -1545,7 +1545,7 @@ static void tcg_out_cltz(TCGContext *s, TCGType ext, TCGReg d,
#include "../tcg-ldst.c.inc"
/* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr,
- * TCGMemOpIdx oi, uintptr_t ra)
+ * MemOpIdx oi, uintptr_t ra)
*/
static void * const qemu_ld_helpers[MO_SIZE + 1] = {
[MO_8] = helper_ret_ldub_mmu,
@@ -1561,7 +1561,7 @@ static void * const qemu_ld_helpers[MO_SIZE + 1] = {
};
/* helper signature: helper_ret_st_mmu(CPUState *env, target_ulong addr,
- * uintxx_t val, TCGMemOpIdx oi,
+ * uintxx_t val, MemOpIdx oi,
* uintptr_t ra)
*/
static void * const qemu_st_helpers[MO_SIZE + 1] = {
@@ -1586,7 +1586,7 @@ static inline void tcg_out_adr(TCGContext *s, TCGReg rd, const void *target)
static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
{
- TCGMemOpIdx oi = lb->oi;
+ MemOpIdx oi = lb->oi;
MemOp opc = get_memop(oi);
MemOp size = opc & MO_SIZE;
@@ -1611,7 +1611,7 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
{
- TCGMemOpIdx oi = lb->oi;
+ MemOpIdx oi = lb->oi;
MemOp opc = get_memop(oi);
MemOp size = opc & MO_SIZE;
@@ -1629,7 +1629,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
return true;
}
-static void add_qemu_ldst_label(TCGContext *s, bool is_ld, TCGMemOpIdx oi,
+static void add_qemu_ldst_label(TCGContext *s, bool is_ld, MemOpIdx oi,
TCGType ext, TCGReg data_reg, TCGReg addr_reg,
tcg_insn_unit *raddr, tcg_insn_unit *label_ptr)
{
@@ -1778,7 +1778,7 @@ static void tcg_out_qemu_st_direct(TCGContext *s, MemOp memop,
}
static void tcg_out_qemu_ld(TCGContext *s, TCGReg data_reg, TCGReg addr_reg,
- TCGMemOpIdx oi, TCGType ext)
+ MemOpIdx oi, TCGType ext)
{
MemOp memop = get_memop(oi);
const TCGType otype = TARGET_LONG_BITS == 64 ? TCG_TYPE_I64 : TCG_TYPE_I32;
@@ -1803,7 +1803,7 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg data_reg, TCGReg addr_reg,
}
static void tcg_out_qemu_st(TCGContext *s, TCGReg data_reg, TCGReg addr_reg,
- TCGMemOpIdx oi)
+ MemOpIdx oi)
{
MemOp memop = get_memop(oi);
const TCGType otype = TARGET_LONG_BITS == 64 ? TCG_TYPE_I64 : TCG_TYPE_I32;
diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
index 8939b2c2da..cbe3057a9d 100644
--- a/tcg/arm/tcg-target.c.inc
+++ b/tcg/arm/tcg-target.c.inc
@@ -1588,7 +1588,7 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGReg addrlo, TCGReg addrhi,
/* Record the context of a call to the out of line helper code for the slow
path for a load or store, so that we can later generate the correct
helper code. */
-static void add_qemu_ldst_label(TCGContext *s, bool is_ld, TCGMemOpIdx oi,
+static void add_qemu_ldst_label(TCGContext *s, bool is_ld, MemOpIdx oi,
TCGReg datalo, TCGReg datahi, TCGReg addrlo,
TCGReg addrhi, tcg_insn_unit *raddr,
tcg_insn_unit *label_ptr)
@@ -1608,7 +1608,7 @@ static void add_qemu_ldst_label(TCGContext *s, bool is_ld, TCGMemOpIdx oi,
static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
{
TCGReg argreg, datalo, datahi;
- TCGMemOpIdx oi = lb->oi;
+ MemOpIdx oi = lb->oi;
MemOp opc = get_memop(oi);
void *func;
@@ -1672,7 +1672,7 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
{
TCGReg argreg, datalo, datahi;
- TCGMemOpIdx oi = lb->oi;
+ MemOpIdx oi = lb->oi;
MemOp opc = get_memop(oi);
if (!reloc_pc24(lb->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) {
@@ -1801,7 +1801,7 @@ static inline void tcg_out_qemu_ld_direct(TCGContext *s, MemOp opc,
static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is64)
{
TCGReg addrlo, datalo, datahi, addrhi __attribute__((unused));
- TCGMemOpIdx oi;
+ MemOpIdx oi;
MemOp opc;
#ifdef CONFIG_SOFTMMU
int mem_index;
@@ -1906,7 +1906,7 @@ static inline void tcg_out_qemu_st_direct(TCGContext *s, MemOp opc,
static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is64)
{
TCGReg addrlo, datalo, datahi, addrhi __attribute__((unused));
- TCGMemOpIdx oi;
+ MemOpIdx oi;
MemOp opc;
#ifdef CONFIG_SOFTMMU
int mem_index;
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
index 5fd4e4392f..1e42a877fb 100644
--- a/tcg/i386/tcg-target.c.inc
+++ b/tcg/i386/tcg-target.c.inc
@@ -1740,7 +1740,7 @@ static inline void tcg_out_tlb_load(TCGContext *s, TCGReg addrlo, TCGReg addrhi,
* for a load or store, so that we can later generate the correct helper code
*/
static void add_qemu_ldst_label(TCGContext *s, bool is_ld, bool is_64,
- TCGMemOpIdx oi,
+ MemOpIdx oi,
TCGReg datalo, TCGReg datahi,
TCGReg addrlo, TCGReg addrhi,
tcg_insn_unit *raddr,
@@ -1767,7 +1767,7 @@ static void add_qemu_ldst_label(TCGContext *s, bool is_ld, bool is_64,
*/
static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
{
- TCGMemOpIdx oi = l->oi;
+ MemOpIdx oi = l->oi;
MemOp opc = get_memop(oi);
TCGReg data_reg;
tcg_insn_unit **label_ptr = &l->label_ptr[0];
@@ -1852,7 +1852,7 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
*/
static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
{
- TCGMemOpIdx oi = l->oi;
+ MemOpIdx oi = l->oi;
MemOp opc = get_memop(oi);
MemOp s_bits = opc & MO_SIZE;
tcg_insn_unit **label_ptr = &l->label_ptr[0];
@@ -2053,7 +2053,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is64)
{
TCGReg datalo, datahi, addrlo;
TCGReg addrhi __attribute__((unused));
- TCGMemOpIdx oi;
+ MemOpIdx oi;
MemOp opc;
#if defined(CONFIG_SOFTMMU)
int mem_index;
@@ -2142,7 +2142,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is64)
{
TCGReg datalo, datahi, addrlo;
TCGReg addrhi __attribute__((unused));
- TCGMemOpIdx oi;
+ MemOpIdx oi;
MemOp opc;
#if defined(CONFIG_SOFTMMU)
int mem_index;
diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc
index cc279205d6..02dc4b63ae 100644
--- a/tcg/mips/tcg-target.c.inc
+++ b/tcg/mips/tcg-target.c.inc
@@ -1140,7 +1140,7 @@ QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -32768);
* Clobbers TMP0, TMP1, TMP2, TMP3.
*/
static void tcg_out_tlb_load(TCGContext *s, TCGReg base, TCGReg addrl,
- TCGReg addrh, TCGMemOpIdx oi,
+ TCGReg addrh, MemOpIdx oi,
tcg_insn_unit *label_ptr[2], bool is_load)
{
MemOp opc = get_memop(oi);
@@ -1216,7 +1216,7 @@ static void tcg_out_tlb_load(TCGContext *s, TCGReg base, TCGReg addrl,
tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_TMP2, addrl);
}
-static void add_qemu_ldst_label(TCGContext *s, int is_ld, TCGMemOpIdx oi,
+static void add_qemu_ldst_label(TCGContext *s, int is_ld, MemOpIdx oi,
TCGType ext,
TCGReg datalo, TCGReg datahi,
TCGReg addrlo, TCGReg addrhi,
@@ -1241,7 +1241,7 @@ static void add_qemu_ldst_label(TCGContext *s, int is_ld, TCGMemOpIdx oi,
static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
{
const tcg_insn_unit *tgt_rx = tcg_splitwx_to_rx(s->code_ptr);
- TCGMemOpIdx oi = l->oi;
+ MemOpIdx oi = l->oi;
MemOp opc = get_memop(oi);
TCGReg v0;
int i;
@@ -1295,7 +1295,7 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
{
const tcg_insn_unit *tgt_rx = tcg_splitwx_to_rx(s->code_ptr);
- TCGMemOpIdx oi = l->oi;
+ MemOpIdx oi = l->oi;
MemOp opc = get_memop(oi);
MemOp s_bits = opc & MO_SIZE;
int i;
@@ -1454,7 +1454,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64)
{
TCGReg addr_regl, addr_regh __attribute__((unused));
TCGReg data_regl, data_regh;
- TCGMemOpIdx oi;
+ MemOpIdx oi;
MemOp opc;
#if defined(CONFIG_SOFTMMU)
tcg_insn_unit *label_ptr[2];
@@ -1556,7 +1556,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64)
{
TCGReg addr_regl, addr_regh __attribute__((unused));
TCGReg data_regl, data_regh;
- TCGMemOpIdx oi;
+ MemOpIdx oi;
MemOp opc;
#if defined(CONFIG_SOFTMMU)
tcg_insn_unit *label_ptr[2];
diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
index 3fef2aa6b2..2d4ca1f445 100644
--- a/tcg/ppc/tcg-target.c.inc
+++ b/tcg/ppc/tcg-target.c.inc
@@ -2088,7 +2088,7 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, MemOp opc,
/* Record the context of a call to the out of line helper code for the slow
path for a load or store, so that we can later generate the correct
helper code. */
-static void add_qemu_ldst_label(TCGContext *s, bool is_ld, TCGMemOpIdx oi,
+static void add_qemu_ldst_label(TCGContext *s, bool is_ld, MemOpIdx oi,
TCGReg datalo_reg, TCGReg datahi_reg,
TCGReg addrlo_reg, TCGReg addrhi_reg,
tcg_insn_unit *raddr, tcg_insn_unit *lptr)
@@ -2107,7 +2107,7 @@ static void add_qemu_ldst_label(TCGContext *s, bool is_ld, TCGMemOpIdx oi,
static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
{
- TCGMemOpIdx oi = lb->oi;
+ MemOpIdx oi = lb->oi;
MemOp opc = get_memop(oi);
TCGReg hi, lo, arg = TCG_REG_R3;
@@ -2154,7 +2154,7 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
{
- TCGMemOpIdx oi = lb->oi;
+ MemOpIdx oi = lb->oi;
MemOp opc = get_memop(oi);
MemOp s_bits = opc & MO_SIZE;
TCGReg hi, lo, arg = TCG_REG_R3;
@@ -2218,7 +2218,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64)
{
TCGReg datalo, datahi, addrlo, rbase;
TCGReg addrhi __attribute__((unused));
- TCGMemOpIdx oi;
+ MemOpIdx oi;
MemOp opc, s_bits;
#ifdef CONFIG_SOFTMMU
int mem_index;
@@ -2293,7 +2293,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64)
{
TCGReg datalo, datahi, addrlo, rbase;
TCGReg addrhi __attribute__((unused));
- TCGMemOpIdx oi;
+ MemOpIdx oi;
MemOp opc, s_bits;
#ifdef CONFIG_SOFTMMU
int mem_index;
diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
index 6264e58b3a..c1b0c3764d 100644
--- a/tcg/riscv/tcg-target.c.inc
+++ b/tcg/riscv/tcg-target.c.inc
@@ -850,7 +850,7 @@ static void tcg_out_mb(TCGContext *s, TCGArg a0)
#include "../tcg-ldst.c.inc"
/* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr,
- * TCGMemOpIdx oi, uintptr_t ra)
+ * MemOpIdx oi, uintptr_t ra)
*/
static void * const qemu_ld_helpers[MO_SSIZE + 1] = {
[MO_UB] = helper_ret_ldub_mmu,
@@ -875,7 +875,7 @@ static void * const qemu_ld_helpers[MO_SSIZE + 1] = {
};
/* helper signature: helper_ret_st_mmu(CPUState *env, target_ulong addr,
- * uintxx_t val, TCGMemOpIdx oi,
+ * uintxx_t val, MemOpIdx oi,
* uintptr_t ra)
*/
static void * const qemu_st_helpers[MO_SIZE + 1] = {
@@ -906,7 +906,7 @@ static void tcg_out_goto(TCGContext *s, const tcg_insn_unit *target)
}
static void tcg_out_tlb_load(TCGContext *s, TCGReg addrl,
- TCGReg addrh, TCGMemOpIdx oi,
+ TCGReg addrh, MemOpIdx oi,
tcg_insn_unit **label_ptr, bool is_load)
{
MemOp opc = get_memop(oi);
@@ -959,7 +959,7 @@ static void tcg_out_tlb_load(TCGContext *s, TCGReg addrl,
tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, TCG_REG_TMP2, addrl);
}
-static void add_qemu_ldst_label(TCGContext *s, int is_ld, TCGMemOpIdx oi,
+static void add_qemu_ldst_label(TCGContext *s, int is_ld, MemOpIdx oi,
TCGType ext,
TCGReg datalo, TCGReg datahi,
TCGReg addrlo, TCGReg addrhi,
@@ -980,7 +980,7 @@ static void add_qemu_ldst_label(TCGContext *s, int is_ld, TCGMemOpIdx oi,
static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
{
- TCGMemOpIdx oi = l->oi;
+ MemOpIdx oi = l->oi;
MemOp opc = get_memop(oi);
TCGReg a0 = tcg_target_call_iarg_regs[0];
TCGReg a1 = tcg_target_call_iarg_regs[1];
@@ -1012,7 +1012,7 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
{
- TCGMemOpIdx oi = l->oi;
+ MemOpIdx oi = l->oi;
MemOp opc = get_memop(oi);
MemOp s_bits = opc & MO_SIZE;
TCGReg a0 = tcg_target_call_iarg_regs[0];
@@ -1104,7 +1104,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64)
{
TCGReg addr_regl, addr_regh __attribute__((unused));
TCGReg data_regl, data_regh;
- TCGMemOpIdx oi;
+ MemOpIdx oi;
MemOp opc;
#if defined(CONFIG_SOFTMMU)
tcg_insn_unit *label_ptr[1];
@@ -1173,7 +1173,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64)
{
TCGReg addr_regl, addr_regh __attribute__((unused));
TCGReg data_regl, data_regh;
- TCGMemOpIdx oi;
+ MemOpIdx oi;
MemOp opc;
#if defined(CONFIG_SOFTMMU)
tcg_insn_unit *label_ptr[1];
diff --git a/tcg/s390/tcg-target.c.inc b/tcg/s390/tcg-target.c.inc
index 67a2ba5ff3..fd0b3316d2 100644
--- a/tcg/s390/tcg-target.c.inc
+++ b/tcg/s390/tcg-target.c.inc
@@ -1547,7 +1547,7 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGReg addr_reg, MemOp opc,
return addr_reg;
}
-static void add_qemu_ldst_label(TCGContext *s, bool is_ld, TCGMemOpIdx oi,
+static void add_qemu_ldst_label(TCGContext *s, bool is_ld, MemOpIdx oi,
TCGReg data, TCGReg addr,
tcg_insn_unit *raddr, tcg_insn_unit *label_ptr)
{
@@ -1565,7 +1565,7 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
{
TCGReg addr_reg = lb->addrlo_reg;
TCGReg data_reg = lb->datalo_reg;
- TCGMemOpIdx oi = lb->oi;
+ MemOpIdx oi = lb->oi;
MemOp opc = get_memop(oi);
if (!patch_reloc(lb->label_ptr[0], R_390_PC16DBL,
@@ -1590,7 +1590,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
{
TCGReg addr_reg = lb->addrlo_reg;
TCGReg data_reg = lb->datalo_reg;
- TCGMemOpIdx oi = lb->oi;
+ MemOpIdx oi = lb->oi;
MemOp opc = get_memop(oi);
if (!patch_reloc(lb->label_ptr[0], R_390_PC16DBL,
@@ -1644,7 +1644,7 @@ static void tcg_prepare_user_ldst(TCGContext *s, TCGReg *addr_reg,
#endif /* CONFIG_SOFTMMU */
static void tcg_out_qemu_ld(TCGContext* s, TCGReg data_reg, TCGReg addr_reg,
- TCGMemOpIdx oi)
+ MemOpIdx oi)
{
MemOp opc = get_memop(oi);
#ifdef CONFIG_SOFTMMU
@@ -1671,7 +1671,7 @@ static void tcg_out_qemu_ld(TCGContext* s, TCGReg data_reg, TCGReg addr_reg,
}
static void tcg_out_qemu_st(TCGContext* s, TCGReg data_reg, TCGReg addr_reg,
- TCGMemOpIdx oi)
+ MemOpIdx oi)
{
MemOp opc = get_memop(oi);
#ifdef CONFIG_SOFTMMU
diff --git a/tcg/sparc/tcg-target.c.inc b/tcg/sparc/tcg-target.c.inc
index b9bce29282..0e3f460584 100644
--- a/tcg/sparc/tcg-target.c.inc
+++ b/tcg/sparc/tcg-target.c.inc
@@ -1140,7 +1140,7 @@ static const int qemu_st_opc[(MO_SIZE | MO_BSWAP) + 1] = {
};
static void tcg_out_qemu_ld(TCGContext *s, TCGReg data, TCGReg addr,
- TCGMemOpIdx oi, bool is_64)
+ MemOpIdx oi, bool is_64)
{
MemOp memop = get_memop(oi);
#ifdef CONFIG_SOFTMMU
@@ -1222,7 +1222,7 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg data, TCGReg addr,
}
static void tcg_out_qemu_st(TCGContext *s, TCGReg data, TCGReg addr,
- TCGMemOpIdx oi)
+ MemOpIdx oi)
{
MemOp memop = get_memop(oi);
#ifdef CONFIG_SOFTMMU
diff --git a/tcg/tcg-ldst.c.inc b/tcg/tcg-ldst.c.inc
index c3ce88e69d..6c6848d034 100644
--- a/tcg/tcg-ldst.c.inc
+++ b/tcg/tcg-ldst.c.inc
@@ -22,7 +22,7 @@
typedef struct TCGLabelQemuLdst {
bool is_ld; /* qemu_ld: true, qemu_st: false */
- TCGMemOpIdx oi;
+ MemOpIdx oi;
TCGType type; /* result type of a load */
TCGReg addrlo_reg; /* reg index for low word of guest virtual addr */
TCGReg addrhi_reg; /* reg index for high word of guest virtual addr */
--
2.25.1
^ permalink raw reply related [flat|nested] 102+ messages in thread* Re: [PATCH for-6.2 20/43] tcg: Rename TCGMemOpIdx to MemOpIdx
2021-07-29 0:46 ` [PATCH for-6.2 20/43] tcg: Rename TCGMemOpIdx to MemOpIdx Richard Henderson
@ 2021-07-29 6:27 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 102+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-07-29 6:27 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
On 7/29/21 2:46 AM, Richard Henderson wrote:
> We're about to move this out of tcg.h, so rename it
> as we did when moving MemOp.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> accel/tcg/atomic_template.h | 24 +++++------
> include/tcg/tcg.h | 74 ++++++++++++++++-----------------
> accel/tcg/cputlb.c | 78 +++++++++++++++++------------------
> accel/tcg/user-exec.c | 2 +-
> target/arm/helper-a64.c | 16 +++----
> target/arm/m_helper.c | 2 +-
> target/i386/tcg/mem_helper.c | 4 +-
> target/m68k/op_helper.c | 2 +-
> target/mips/tcg/msa_helper.c | 6 +--
> target/s390x/tcg/mem_helper.c | 20 ++++-----
> target/sparc/ldst_helper.c | 2 +-
> tcg/optimize.c | 2 +-
> tcg/tcg-op.c | 12 +++---
> tcg/tcg.c | 2 +-
> tcg/tci.c | 14 +++----
> accel/tcg/atomic_common.c.inc | 6 +--
> tcg/aarch64/tcg-target.c.inc | 14 +++----
> tcg/arm/tcg-target.c.inc | 10 ++---
> tcg/i386/tcg-target.c.inc | 10 ++---
> tcg/mips/tcg-target.c.inc | 12 +++---
> tcg/ppc/tcg-target.c.inc | 10 ++---
> tcg/riscv/tcg-target.c.inc | 16 +++----
> tcg/s390/tcg-target.c.inc | 10 ++---
> tcg/sparc/tcg-target.c.inc | 4 +-
> tcg/tcg-ldst.c.inc | 2 +-
> 25 files changed, 177 insertions(+), 177 deletions(-)
Maybe mention "mechanical change using sed".
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
^ permalink raw reply [flat|nested] 102+ messages in thread
* [PATCH for-6.2 21/43] tcg: Split out MemOpIdx to exec/memopidx.h
2021-07-29 0:46 [PATCH for-6.2 00/43] Unaligned accesses for user-only Richard Henderson
` (19 preceding siblings ...)
2021-07-29 0:46 ` [PATCH for-6.2 20/43] tcg: Rename TCGMemOpIdx to MemOpIdx Richard Henderson
@ 2021-07-29 0:46 ` Richard Henderson
2021-07-29 6:27 ` Philippe Mathieu-Daudé
2021-07-29 0:46 ` [PATCH for-6.2 22/43] trace/mem: Pass MemOpIdx to trace_mem_get_info Richard Henderson
` (23 subsequent siblings)
44 siblings, 1 reply; 102+ messages in thread
From: Richard Henderson @ 2021-07-29 0:46 UTC (permalink / raw)
To: qemu-devel
Move this code from tcg/tcg.h to its own header.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/exec/memopidx.h | 55 +++++++++++++++++++++++++++++++++++++++++
include/tcg/tcg.h | 39 +----------------------------
2 files changed, 56 insertions(+), 38 deletions(-)
create mode 100644 include/exec/memopidx.h
diff --git a/include/exec/memopidx.h b/include/exec/memopidx.h
new file mode 100644
index 0000000000..83bce97874
--- /dev/null
+++ b/include/exec/memopidx.h
@@ -0,0 +1,55 @@
+/*
+ * Combine the MemOp and mmu_idx parameters into a single value.
+ *
+ * Authors:
+ * Richard Henderson <rth@twiddle.net>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#ifndef EXEC_MEMOPIDX_H
+#define EXEC_MEMOPIDX_H 1
+
+#include "exec/memop.h"
+
+typedef uint32_t MemOpIdx;
+
+/**
+ * make_memop_idx
+ * @op: memory operation
+ * @idx: mmu index
+ *
+ * Encode these values into a single parameter.
+ */
+static inline MemOpIdx make_memop_idx(MemOp op, unsigned idx)
+{
+#ifdef CONFIG_DEBUG_TCG
+ assert(idx <= 15);
+#endif
+ return (op << 4) | idx;
+}
+
+/**
+ * get_memop
+ * @oi: combined op/idx parameter
+ *
+ * Extract the memory operation from the combined value.
+ */
+static inline MemOp get_memop(MemOpIdx oi)
+{
+ return oi >> 4;
+}
+
+/**
+ * get_mmuidx
+ * @oi: combined op/idx parameter
+ *
+ * Extract the mmu index from the combined value.
+ */
+static inline unsigned get_mmuidx(MemOpIdx oi)
+{
+ return oi & 15;
+}
+
+#endif
diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h
index f91ebd0743..e67ef34694 100644
--- a/include/tcg/tcg.h
+++ b/include/tcg/tcg.h
@@ -27,6 +27,7 @@
#include "cpu.h"
#include "exec/memop.h"
+#include "exec/memopidx.h"
#include "qemu/bitops.h"
#include "qemu/plugin.h"
#include "qemu/queue.h"
@@ -1147,44 +1148,6 @@ static inline size_t tcg_current_code_size(TCGContext *s)
return tcg_ptr_byte_diff(s->code_ptr, s->code_buf);
}
-/* Combine the MemOp and mmu_idx parameters into a single value. */
-typedef uint32_t MemOpIdx;
-
-/**
- * make_memop_idx
- * @op: memory operation
- * @idx: mmu index
- *
- * Encode these values into a single parameter.
- */
-static inline MemOpIdx make_memop_idx(MemOp op, unsigned idx)
-{
- tcg_debug_assert(idx <= 15);
- return (op << 4) | idx;
-}
-
-/**
- * get_memop
- * @oi: combined op/idx parameter
- *
- * Extract the memory operation from the combined value.
- */
-static inline MemOp get_memop(MemOpIdx oi)
-{
- return oi >> 4;
-}
-
-/**
- * get_mmuidx
- * @oi: combined op/idx parameter
- *
- * Extract the mmu index from the combined value.
- */
-static inline unsigned get_mmuidx(MemOpIdx oi)
-{
- return oi & 15;
-}
-
/**
* tcg_qemu_tb_exec:
* @env: pointer to CPUArchState for the CPU
--
2.25.1
^ permalink raw reply related [flat|nested] 102+ messages in thread* Re: [PATCH for-6.2 21/43] tcg: Split out MemOpIdx to exec/memopidx.h
2021-07-29 0:46 ` [PATCH for-6.2 21/43] tcg: Split out MemOpIdx to exec/memopidx.h Richard Henderson
@ 2021-07-29 6:27 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 102+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-07-29 6:27 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
On 7/29/21 2:46 AM, Richard Henderson wrote:
> Move this code from tcg/tcg.h to its own header.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> include/exec/memopidx.h | 55 +++++++++++++++++++++++++++++++++++++++++
> include/tcg/tcg.h | 39 +----------------------------
> 2 files changed, 56 insertions(+), 38 deletions(-)
> create mode 100644 include/exec/memopidx.h
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
^ permalink raw reply [flat|nested] 102+ messages in thread
* [PATCH for-6.2 22/43] trace/mem: Pass MemOpIdx to trace_mem_get_info
2021-07-29 0:46 [PATCH for-6.2 00/43] Unaligned accesses for user-only Richard Henderson
` (20 preceding siblings ...)
2021-07-29 0:46 ` [PATCH for-6.2 21/43] tcg: Split out MemOpIdx to exec/memopidx.h Richard Henderson
@ 2021-07-29 0:46 ` Richard Henderson
2021-07-29 0:46 ` [PATCH for-6.2 23/43] accel/tcg: Remove double bswap for helper_atomic_sto_*_mmu Richard Henderson
` (22 subsequent siblings)
44 siblings, 0 replies; 102+ messages in thread
From: Richard Henderson @ 2021-07-29 0:46 UTC (permalink / raw)
To: qemu-devel
We (will) often have the complete MemOpIdx handy, so use that.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
trace/mem.h | 32 +++++++++-----------------
accel/tcg/cputlb.c | 12 ++++------
accel/tcg/user-exec.c | 42 +++++++++++++++++++++++------------
tcg/tcg-op.c | 8 +++----
accel/tcg/atomic_common.c.inc | 6 ++---
5 files changed, 49 insertions(+), 51 deletions(-)
diff --git a/trace/mem.h b/trace/mem.h
index 2f27e7bdf0..699566c661 100644
--- a/trace/mem.h
+++ b/trace/mem.h
@@ -10,7 +10,7 @@
#ifndef TRACE__MEM_H
#define TRACE__MEM_H
-#include "tcg/tcg.h"
+#include "exec/memopidx.h"
#define TRACE_MEM_SZ_SHIFT_MASK 0xf /* size shift mask */
#define TRACE_MEM_SE (1ULL << 4) /* sign extended (y/n) */
@@ -19,45 +19,33 @@
#define TRACE_MEM_MMU_SHIFT 8 /* mmu idx */
/**
- * trace_mem_build_info:
+ * trace_mem_get_info:
*
* Return a value for the 'info' argument in guest memory access traces.
*/
-static inline uint16_t trace_mem_build_info(int size_shift, bool sign_extend,
- MemOp endianness, bool store,
- unsigned int mmu_idx)
+static inline uint16_t trace_mem_get_info(MemOpIdx oi, bool store)
{
+ MemOp op = get_memop(oi);
+ uint32_t size_shift = op & MO_SIZE;
+ bool sign_extend = op & MO_SIGN;
+ bool big_endian = (op & MO_BSWAP) == MO_BE;
uint16_t res;
res = size_shift & TRACE_MEM_SZ_SHIFT_MASK;
if (sign_extend) {
res |= TRACE_MEM_SE;
}
- if (endianness == MO_BE) {
+ if (big_endian) {
res |= TRACE_MEM_BE;
}
if (store) {
res |= TRACE_MEM_ST;
}
#ifdef CONFIG_SOFTMMU
- res |= mmu_idx << TRACE_MEM_MMU_SHIFT;
+ res |= get_mmuidx(oi) << TRACE_MEM_MMU_SHIFT;
#endif
+
return res;
}
-
-/**
- * trace_mem_get_info:
- *
- * Return a value for the 'info' argument in guest memory access traces.
- */
-static inline uint16_t trace_mem_get_info(MemOp op,
- unsigned int mmu_idx,
- bool store)
-{
- return trace_mem_build_info(op & MO_SIZE, !!(op & MO_SIGN),
- op & MO_BSWAP, store,
- mmu_idx);
-}
-
#endif /* TRACE__MEM_H */
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index d72f65f42b..0aa6157ec4 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -2112,14 +2112,12 @@ static inline uint64_t cpu_load_helper(CPUArchState *env, abi_ptr addr,
int mmu_idx, uintptr_t retaddr,
MemOp op, FullLoadHelper *full_load)
{
- uint16_t meminfo;
- MemOpIdx oi;
+ MemOpIdx oi = make_memop_idx(op, mmu_idx);
+ uint16_t meminfo = trace_mem_get_info(oi, false);
uint64_t ret;
- meminfo = trace_mem_get_info(op, mmu_idx, false);
trace_guest_mem_before_exec(env_cpu(env), addr, meminfo);
- oi = make_memop_idx(op, mmu_idx);
ret = full_load(env, addr, oi, retaddr);
qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, meminfo);
@@ -2551,13 +2549,11 @@ static inline void QEMU_ALWAYS_INLINE
cpu_store_helper(CPUArchState *env, target_ulong addr, uint64_t val,
int mmu_idx, uintptr_t retaddr, MemOp op)
{
- MemOpIdx oi;
- uint16_t meminfo;
+ MemOpIdx oi = make_memop_idx(op, mmu_idx);
+ uint16_t meminfo = trace_mem_get_info(oi, true);
- meminfo = trace_mem_get_info(op, mmu_idx, true);
trace_guest_mem_before_exec(env_cpu(env), addr, meminfo);
- oi = make_memop_idx(op, mmu_idx);
store_helper(env, addr, val, oi, retaddr, op);
qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, meminfo);
diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
index eb672eae3a..9f6fa729d0 100644
--- a/accel/tcg/user-exec.c
+++ b/accel/tcg/user-exec.c
@@ -864,8 +864,9 @@ static void cpu_unaligned_access(CPUState *cpu, vaddr addr,
uint32_t cpu_ldub_data(CPUArchState *env, abi_ptr ptr)
{
+ MemOpIdx oi = make_memop_idx(MO_UB, MMU_USER_IDX);
+ uint16_t meminfo = trace_mem_get_info(oi, false);
uint32_t ret;
- uint16_t meminfo = trace_mem_get_info(MO_UB, MMU_USER_IDX, false);
trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
ret = ldub_p(g2h(env_cpu(env), ptr));
@@ -880,8 +881,9 @@ int cpu_ldsb_data(CPUArchState *env, abi_ptr ptr)
uint32_t cpu_lduw_be_data(CPUArchState *env, abi_ptr ptr)
{
+ MemOpIdx oi = make_memop_idx(MO_BEUW, MMU_USER_IDX);
+ uint16_t meminfo = trace_mem_get_info(oi, false);
uint32_t ret;
- uint16_t meminfo = trace_mem_get_info(MO_BEUW, MMU_USER_IDX, false);
trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
ret = lduw_be_p(g2h(env_cpu(env), ptr));
@@ -896,8 +898,9 @@ int cpu_ldsw_be_data(CPUArchState *env, abi_ptr ptr)
uint32_t cpu_ldl_be_data(CPUArchState *env, abi_ptr ptr)
{
+ MemOpIdx oi = make_memop_idx(MO_BEUL, MMU_USER_IDX);
+ uint16_t meminfo = trace_mem_get_info(oi, false);
uint32_t ret;
- uint16_t meminfo = trace_mem_get_info(MO_BEUL, MMU_USER_IDX, false);
trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
ret = ldl_be_p(g2h(env_cpu(env), ptr));
@@ -907,8 +910,9 @@ uint32_t cpu_ldl_be_data(CPUArchState *env, abi_ptr ptr)
uint64_t cpu_ldq_be_data(CPUArchState *env, abi_ptr ptr)
{
+ MemOpIdx oi = make_memop_idx(MO_BEQ, MMU_USER_IDX);
+ uint16_t meminfo = trace_mem_get_info(oi, false);
uint64_t ret;
- uint16_t meminfo = trace_mem_get_info(MO_BEQ, MMU_USER_IDX, false);
trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
ret = ldq_be_p(g2h(env_cpu(env), ptr));
@@ -918,8 +922,9 @@ uint64_t cpu_ldq_be_data(CPUArchState *env, abi_ptr ptr)
uint32_t cpu_lduw_le_data(CPUArchState *env, abi_ptr ptr)
{
+ MemOpIdx oi = make_memop_idx(MO_LEUW, MMU_USER_IDX);
+ uint16_t meminfo = trace_mem_get_info(oi, false);
uint32_t ret;
- uint16_t meminfo = trace_mem_get_info(MO_LEUW, MMU_USER_IDX, false);
trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
ret = lduw_le_p(g2h(env_cpu(env), ptr));
@@ -934,8 +939,9 @@ int cpu_ldsw_le_data(CPUArchState *env, abi_ptr ptr)
uint32_t cpu_ldl_le_data(CPUArchState *env, abi_ptr ptr)
{
+ MemOpIdx oi = make_memop_idx(MO_LEUL, MMU_USER_IDX);
+ uint16_t meminfo = trace_mem_get_info(oi, false);
uint32_t ret;
- uint16_t meminfo = trace_mem_get_info(MO_LEUL, MMU_USER_IDX, false);
trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
ret = ldl_le_p(g2h(env_cpu(env), ptr));
@@ -945,8 +951,9 @@ uint32_t cpu_ldl_le_data(CPUArchState *env, abi_ptr ptr)
uint64_t cpu_ldq_le_data(CPUArchState *env, abi_ptr ptr)
{
+ MemOpIdx oi = make_memop_idx(MO_LEQ, MMU_USER_IDX);
+ uint16_t meminfo = trace_mem_get_info(oi, false);
uint64_t ret;
- uint16_t meminfo = trace_mem_get_info(MO_LEQ, MMU_USER_IDX, false);
trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
ret = ldq_le_p(g2h(env_cpu(env), ptr));
@@ -1041,7 +1048,8 @@ uint64_t cpu_ldq_le_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr)
void cpu_stb_data(CPUArchState *env, abi_ptr ptr, uint32_t val)
{
- uint16_t meminfo = trace_mem_get_info(MO_UB, MMU_USER_IDX, true);
+ MemOpIdx oi = make_memop_idx(MO_UB, MMU_USER_IDX);
+ uint16_t meminfo = trace_mem_get_info(oi, true);
trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
stb_p(g2h(env_cpu(env), ptr), val);
@@ -1050,7 +1058,8 @@ void cpu_stb_data(CPUArchState *env, abi_ptr ptr, uint32_t val)
void cpu_stw_be_data(CPUArchState *env, abi_ptr ptr, uint32_t val)
{
- uint16_t meminfo = trace_mem_get_info(MO_BEUW, MMU_USER_IDX, true);
+ MemOpIdx oi = make_memop_idx(MO_BEUW, MMU_USER_IDX);
+ uint16_t meminfo = trace_mem_get_info(oi, true);
trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
stw_be_p(g2h(env_cpu(env), ptr), val);
@@ -1059,7 +1068,8 @@ void cpu_stw_be_data(CPUArchState *env, abi_ptr ptr, uint32_t val)
void cpu_stl_be_data(CPUArchState *env, abi_ptr ptr, uint32_t val)
{
- uint16_t meminfo = trace_mem_get_info(MO_BEUL, MMU_USER_IDX, true);
+ MemOpIdx oi = make_memop_idx(MO_BEUL, MMU_USER_IDX);
+ uint16_t meminfo = trace_mem_get_info(oi, true);
trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
stl_be_p(g2h(env_cpu(env), ptr), val);
@@ -1068,7 +1078,8 @@ void cpu_stl_be_data(CPUArchState *env, abi_ptr ptr, uint32_t val)
void cpu_stq_be_data(CPUArchState *env, abi_ptr ptr, uint64_t val)
{
- uint16_t meminfo = trace_mem_get_info(MO_BEQ, MMU_USER_IDX, true);
+ MemOpIdx oi = make_memop_idx(MO_BEQ, MMU_USER_IDX);
+ uint16_t meminfo = trace_mem_get_info(oi, true);
trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
stq_be_p(g2h(env_cpu(env), ptr), val);
@@ -1077,7 +1088,8 @@ void cpu_stq_be_data(CPUArchState *env, abi_ptr ptr, uint64_t val)
void cpu_stw_le_data(CPUArchState *env, abi_ptr ptr, uint32_t val)
{
- uint16_t meminfo = trace_mem_get_info(MO_LEUW, MMU_USER_IDX, true);
+ MemOpIdx oi = make_memop_idx(MO_LEUW, MMU_USER_IDX);
+ uint16_t meminfo = trace_mem_get_info(oi, true);
trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
stw_le_p(g2h(env_cpu(env), ptr), val);
@@ -1086,7 +1098,8 @@ void cpu_stw_le_data(CPUArchState *env, abi_ptr ptr, uint32_t val)
void cpu_stl_le_data(CPUArchState *env, abi_ptr ptr, uint32_t val)
{
- uint16_t meminfo = trace_mem_get_info(MO_LEUL, MMU_USER_IDX, true);
+ MemOpIdx oi = make_memop_idx(MO_LEUL, MMU_USER_IDX);
+ uint16_t meminfo = trace_mem_get_info(oi, true);
trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
stl_le_p(g2h(env_cpu(env), ptr), val);
@@ -1095,7 +1108,8 @@ void cpu_stl_le_data(CPUArchState *env, abi_ptr ptr, uint32_t val)
void cpu_stq_le_data(CPUArchState *env, abi_ptr ptr, uint64_t val)
{
- uint16_t meminfo = trace_mem_get_info(MO_LEQ, MMU_USER_IDX, true);
+ MemOpIdx oi = make_memop_idx(MO_LEQ, MMU_USER_IDX);
+ uint16_t meminfo = trace_mem_get_info(oi, true);
trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
stq_le_p(g2h(env_cpu(env), ptr), val);
diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c
index e1490c372e..37b440af7f 100644
--- a/tcg/tcg-op.c
+++ b/tcg/tcg-op.c
@@ -2866,7 +2866,7 @@ static inline void plugin_gen_mem_callbacks(TCGv vaddr, uint16_t info)
void tcg_gen_qemu_ld_i32(TCGv_i32 val, TCGv addr, TCGArg idx, MemOp memop)
{
MemOp orig_memop;
- uint16_t info = trace_mem_get_info(memop, idx, 0);
+ uint16_t info = trace_mem_get_info(make_memop_idx(memop, idx), 0);
tcg_gen_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD);
memop = tcg_canonicalize_memop(memop, 0, 0);
@@ -2904,7 +2904,7 @@ void tcg_gen_qemu_ld_i32(TCGv_i32 val, TCGv addr, TCGArg idx, MemOp memop)
void tcg_gen_qemu_st_i32(TCGv_i32 val, TCGv addr, TCGArg idx, MemOp memop)
{
TCGv_i32 swap = NULL;
- uint16_t info = trace_mem_get_info(memop, idx, 1);
+ uint16_t info = trace_mem_get_info(make_memop_idx(memop, idx), 1);
tcg_gen_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST);
memop = tcg_canonicalize_memop(memop, 0, 1);
@@ -2956,7 +2956,7 @@ void tcg_gen_qemu_ld_i64(TCGv_i64 val, TCGv addr, TCGArg idx, MemOp memop)
tcg_gen_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD);
memop = tcg_canonicalize_memop(memop, 1, 0);
- info = trace_mem_get_info(memop, idx, 0);
+ info = trace_mem_get_info(make_memop_idx(memop, idx), 0);
trace_guest_mem_before_tcg(tcg_ctx->cpu, cpu_env, addr, info);
orig_memop = memop;
@@ -3004,7 +3004,7 @@ void tcg_gen_qemu_st_i64(TCGv_i64 val, TCGv addr, TCGArg idx, MemOp memop)
tcg_gen_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST);
memop = tcg_canonicalize_memop(memop, 1, 1);
- info = trace_mem_get_info(memop, idx, 1);
+ info = trace_mem_get_info(make_memop_idx(memop, idx), 1);
trace_guest_mem_before_tcg(tcg_ctx->cpu, cpu_env, addr, info);
if (!TCG_TARGET_HAS_MEMORY_BSWAP && (memop & MO_BSWAP)) {
diff --git a/accel/tcg/atomic_common.c.inc b/accel/tcg/atomic_common.c.inc
index ebaa793464..6019a957b9 100644
--- a/accel/tcg/atomic_common.c.inc
+++ b/accel/tcg/atomic_common.c.inc
@@ -17,7 +17,7 @@ static uint16_t atomic_trace_rmw_pre(CPUArchState *env, target_ulong addr,
MemOpIdx oi)
{
CPUState *cpu = env_cpu(env);
- uint16_t info = trace_mem_get_info(get_memop(oi), get_mmuidx(oi), false);
+ uint16_t info = trace_mem_get_info(oi, false);
trace_guest_mem_before_exec(cpu, addr, info);
trace_guest_mem_before_exec(cpu, addr, info | TRACE_MEM_ST);
@@ -36,7 +36,7 @@ static void atomic_trace_rmw_post(CPUArchState *env, target_ulong addr,
static uint16_t atomic_trace_ld_pre(CPUArchState *env, target_ulong addr,
MemOpIdx oi)
{
- uint16_t info = trace_mem_get_info(get_memop(oi), get_mmuidx(oi), false);
+ uint16_t info = trace_mem_get_info(oi, false);
trace_guest_mem_before_exec(env_cpu(env), addr, info);
@@ -52,7 +52,7 @@ static void atomic_trace_ld_post(CPUArchState *env, target_ulong addr,
static uint16_t atomic_trace_st_pre(CPUArchState *env, target_ulong addr,
MemOpIdx oi)
{
- uint16_t info = trace_mem_get_info(get_memop(oi), get_mmuidx(oi), true);
+ uint16_t info = trace_mem_get_info(oi, true);
trace_guest_mem_before_exec(env_cpu(env), addr, info);
--
2.25.1
^ permalink raw reply related [flat|nested] 102+ messages in thread* [PATCH for-6.2 23/43] accel/tcg: Remove double bswap for helper_atomic_sto_*_mmu
2021-07-29 0:46 [PATCH for-6.2 00/43] Unaligned accesses for user-only Richard Henderson
` (21 preceding siblings ...)
2021-07-29 0:46 ` [PATCH for-6.2 22/43] trace/mem: Pass MemOpIdx to trace_mem_get_info Richard Henderson
@ 2021-07-29 0:46 ` Richard Henderson
2021-07-29 6:29 ` [PATCH for-6.1? " Philippe Mathieu-Daudé
2021-07-29 0:46 ` [PATCH for-6.2 24/43] accel/tcg: Pass MemOpIdx to atomic_trace_*_post Richard Henderson
` (21 subsequent siblings)
44 siblings, 1 reply; 102+ messages in thread
From: Richard Henderson @ 2021-07-29 0:46 UTC (permalink / raw)
To: qemu-devel
This crept in as either a cut-and-paste error, or rebase error.
Fixes: cfec388518d
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
accel/tcg/atomic_template.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/accel/tcg/atomic_template.h b/accel/tcg/atomic_template.h
index 4427fab6df..4230ff2957 100644
--- a/accel/tcg/atomic_template.h
+++ b/accel/tcg/atomic_template.h
@@ -251,7 +251,6 @@ void ATOMIC_NAME(st)(CPUArchState *env, target_ulong addr, ABI_TYPE val,
PAGE_WRITE, retaddr);
uint16_t info = atomic_trace_st_pre(env, addr, oi);
- val = BSWAP(val);
val = BSWAP(val);
atomic16_set(haddr, val);
ATOMIC_MMU_CLEANUP;
--
2.25.1
^ permalink raw reply related [flat|nested] 102+ messages in thread* Re: [PATCH for-6.1? 23/43] accel/tcg: Remove double bswap for helper_atomic_sto_*_mmu
2021-07-29 0:46 ` [PATCH for-6.2 23/43] accel/tcg: Remove double bswap for helper_atomic_sto_*_mmu Richard Henderson
@ 2021-07-29 6:29 ` Philippe Mathieu-Daudé
2021-07-29 18:37 ` Richard Henderson
0 siblings, 1 reply; 102+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-07-29 6:29 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
On 7/29/21 2:46 AM, Richard Henderson wrote:
> This crept in as either a cut-and-paste error, or rebase error.
>
> Fixes: cfec388518d
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> accel/tcg/atomic_template.h | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git a/accel/tcg/atomic_template.h b/accel/tcg/atomic_template.h
> index 4427fab6df..4230ff2957 100644
> --- a/accel/tcg/atomic_template.h
> +++ b/accel/tcg/atomic_template.h
> @@ -251,7 +251,6 @@ void ATOMIC_NAME(st)(CPUArchState *env, target_ulong addr, ABI_TYPE val,
> PAGE_WRITE, retaddr);
> uint16_t info = atomic_trace_st_pre(env, addr, oi);
>
> - val = BSWAP(val);
> val = BSWAP(val);
> atomic16_set(haddr, val);
> ATOMIC_MMU_CLEANUP;
Why not merge this for 6.1? Because old bug, no regression?
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
^ permalink raw reply [flat|nested] 102+ messages in thread
* Re: [PATCH for-6.1? 23/43] accel/tcg: Remove double bswap for helper_atomic_sto_*_mmu
2021-07-29 6:29 ` [PATCH for-6.1? " Philippe Mathieu-Daudé
@ 2021-07-29 18:37 ` Richard Henderson
0 siblings, 0 replies; 102+ messages in thread
From: Richard Henderson @ 2021-07-29 18:37 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
On 7/28/21 8:29 PM, Philippe Mathieu-Daudé wrote:
> On 7/29/21 2:46 AM, Richard Henderson wrote:
>> This crept in as either a cut-and-paste error, or rebase error.
>>
>> Fixes: cfec388518d
>> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
>> ---
>> accel/tcg/atomic_template.h | 1 -
>> 1 file changed, 1 deletion(-)
>>
>> diff --git a/accel/tcg/atomic_template.h b/accel/tcg/atomic_template.h
>> index 4427fab6df..4230ff2957 100644
>> --- a/accel/tcg/atomic_template.h
>> +++ b/accel/tcg/atomic_template.h
>> @@ -251,7 +251,6 @@ void ATOMIC_NAME(st)(CPUArchState *env, target_ulong addr, ABI_TYPE val,
>> PAGE_WRITE, retaddr);
>> uint16_t info = atomic_trace_st_pre(env, addr, oi);
>>
>> - val = BSWAP(val);
>> val = BSWAP(val);
>> atomic16_set(haddr, val);
>> ATOMIC_MMU_CLEANUP;
>
> Why not merge this for 6.1? Because old bug, no regression?
Probably should.
r~
^ permalink raw reply [flat|nested] 102+ messages in thread
* [PATCH for-6.2 24/43] accel/tcg: Pass MemOpIdx to atomic_trace_*_post
2021-07-29 0:46 [PATCH for-6.2 00/43] Unaligned accesses for user-only Richard Henderson
` (22 preceding siblings ...)
2021-07-29 0:46 ` [PATCH for-6.2 23/43] accel/tcg: Remove double bswap for helper_atomic_sto_*_mmu Richard Henderson
@ 2021-07-29 0:46 ` Richard Henderson
2021-07-29 6:31 ` Philippe Mathieu-Daudé
2021-07-29 0:46 ` [PATCH for-6.2 25/43] plugins: Reorg arguments to qemu_plugin_vcpu_mem_cb Richard Henderson
` (20 subsequent siblings)
44 siblings, 1 reply; 102+ messages in thread
From: Richard Henderson @ 2021-07-29 0:46 UTC (permalink / raw)
To: qemu-devel
We will shortly use the MemOpIdx directly, but in the meantime
re-compute the trace meminfo.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
accel/tcg/atomic_template.h | 48 +++++++++++++++++------------------
accel/tcg/atomic_common.c.inc | 30 +++++++++++-----------
2 files changed, 39 insertions(+), 39 deletions(-)
diff --git a/accel/tcg/atomic_template.h b/accel/tcg/atomic_template.h
index 4230ff2957..c08d859a8a 100644
--- a/accel/tcg/atomic_template.h
+++ b/accel/tcg/atomic_template.h
@@ -77,15 +77,15 @@ ABI_TYPE ATOMIC_NAME(cmpxchg)(CPUArchState *env, target_ulong addr,
DATA_TYPE *haddr = atomic_mmu_lookup(env, addr, oi, DATA_SIZE,
PAGE_READ | PAGE_WRITE, retaddr);
DATA_TYPE ret;
- uint16_t info = atomic_trace_rmw_pre(env, addr, oi);
+ atomic_trace_rmw_pre(env, addr, oi);
#if DATA_SIZE == 16
ret = atomic16_cmpxchg(haddr, cmpv, newv);
#else
ret = qatomic_cmpxchg__nocheck(haddr, cmpv, newv);
#endif
ATOMIC_MMU_CLEANUP;
- atomic_trace_rmw_post(env, addr, info);
+ atomic_trace_rmw_post(env, addr, oi);
return ret;
}
@@ -97,11 +97,11 @@ ABI_TYPE ATOMIC_NAME(ld)(CPUArchState *env, target_ulong addr,
DATA_TYPE *haddr = atomic_mmu_lookup(env, addr, oi, DATA_SIZE,
PAGE_READ, retaddr);
DATA_TYPE val;
- uint16_t info = atomic_trace_ld_pre(env, addr, oi);
+ atomic_trace_ld_pre(env, addr, oi);
val = atomic16_read(haddr);
ATOMIC_MMU_CLEANUP;
- atomic_trace_ld_post(env, addr, info);
+ atomic_trace_ld_post(env, addr, oi);
return val;
}
@@ -110,11 +110,11 @@ void ATOMIC_NAME(st)(CPUArchState *env, target_ulong addr, ABI_TYPE val,
{
DATA_TYPE *haddr = atomic_mmu_lookup(env, addr, oi, DATA_SIZE,
PAGE_WRITE, retaddr);
- uint16_t info = atomic_trace_st_pre(env, addr, oi);
+ atomic_trace_st_pre(env, addr, oi);
atomic16_set(haddr, val);
ATOMIC_MMU_CLEANUP;
- atomic_trace_st_post(env, addr, info);
+ atomic_trace_st_post(env, addr, oi);
}
#endif
#else
@@ -124,11 +124,11 @@ ABI_TYPE ATOMIC_NAME(xchg)(CPUArchState *env, target_ulong addr, ABI_TYPE val,
DATA_TYPE *haddr = atomic_mmu_lookup(env, addr, oi, DATA_SIZE,
PAGE_READ | PAGE_WRITE, retaddr);
DATA_TYPE ret;
- uint16_t info = atomic_trace_rmw_pre(env, addr, oi);
+ atomic_trace_rmw_pre(env, addr, oi);
ret = qatomic_xchg__nocheck(haddr, val);
ATOMIC_MMU_CLEANUP;
- atomic_trace_rmw_post(env, addr, info);
+ atomic_trace_rmw_post(env, addr, oi);
return ret;
}
@@ -139,10 +139,10 @@ ABI_TYPE ATOMIC_NAME(X)(CPUArchState *env, target_ulong addr, \
DATA_TYPE *haddr = atomic_mmu_lookup(env, addr, oi, DATA_SIZE, \
PAGE_READ | PAGE_WRITE, retaddr); \
DATA_TYPE ret; \
- uint16_t info = atomic_trace_rmw_pre(env, addr, oi); \
+ atomic_trace_rmw_pre(env, addr, oi); \
ret = qatomic_##X(haddr, val); \
ATOMIC_MMU_CLEANUP; \
- atomic_trace_rmw_post(env, addr, info); \
+ atomic_trace_rmw_post(env, addr, oi); \
return ret; \
}
@@ -172,7 +172,7 @@ ABI_TYPE ATOMIC_NAME(X)(CPUArchState *env, target_ulong addr, \
XDATA_TYPE *haddr = atomic_mmu_lookup(env, addr, oi, DATA_SIZE, \
PAGE_READ | PAGE_WRITE, retaddr); \
XDATA_TYPE cmp, old, new, val = xval; \
- uint16_t info = atomic_trace_rmw_pre(env, addr, oi); \
+ atomic_trace_rmw_pre(env, addr, oi); \
smp_mb(); \
cmp = qatomic_read__nocheck(haddr); \
do { \
@@ -180,7 +180,7 @@ ABI_TYPE ATOMIC_NAME(X)(CPUArchState *env, target_ulong addr, \
cmp = qatomic_cmpxchg__nocheck(haddr, old, new); \
} while (cmp != old); \
ATOMIC_MMU_CLEANUP; \
- atomic_trace_rmw_post(env, addr, info); \
+ atomic_trace_rmw_post(env, addr, oi); \
return RET; \
}
@@ -216,15 +216,15 @@ ABI_TYPE ATOMIC_NAME(cmpxchg)(CPUArchState *env, target_ulong addr,
DATA_TYPE *haddr = atomic_mmu_lookup(env, addr, oi, DATA_SIZE,
PAGE_READ | PAGE_WRITE, retaddr);
DATA_TYPE ret;
- uint16_t info = atomic_trace_rmw_pre(env, addr, oi);
+ atomic_trace_rmw_pre(env, addr, oi);
#if DATA_SIZE == 16
ret = atomic16_cmpxchg(haddr, BSWAP(cmpv), BSWAP(newv));
#else
ret = qatomic_cmpxchg__nocheck(haddr, BSWAP(cmpv), BSWAP(newv));
#endif
ATOMIC_MMU_CLEANUP;
- atomic_trace_rmw_post(env, addr, info);
+ atomic_trace_rmw_post(env, addr, oi);
return BSWAP(ret);
}
@@ -236,11 +236,11 @@ ABI_TYPE ATOMIC_NAME(ld)(CPUArchState *env, target_ulong addr,
DATA_TYPE *haddr = atomic_mmu_lookup(env, addr, oi, DATA_SIZE,
PAGE_READ, retaddr);
DATA_TYPE val;
- uint16_t info = atomic_trace_ld_pre(env, addr, oi);
+ atomic_trace_ld_pre(env, addr, oi);
val = atomic16_read(haddr);
ATOMIC_MMU_CLEANUP;
- atomic_trace_ld_post(env, addr, info);
+ atomic_trace_ld_post(env, addr, oi);
return BSWAP(val);
}
@@ -249,12 +249,12 @@ void ATOMIC_NAME(st)(CPUArchState *env, target_ulong addr, ABI_TYPE val,
{
DATA_TYPE *haddr = atomic_mmu_lookup(env, addr, oi, DATA_SIZE,
PAGE_WRITE, retaddr);
- uint16_t info = atomic_trace_st_pre(env, addr, oi);
+ atomic_trace_st_pre(env, addr, oi);
val = BSWAP(val);
atomic16_set(haddr, val);
ATOMIC_MMU_CLEANUP;
- atomic_trace_st_post(env, addr, info);
+ atomic_trace_st_post(env, addr, oi);
}
#endif
#else
@@ -264,11 +264,11 @@ ABI_TYPE ATOMIC_NAME(xchg)(CPUArchState *env, target_ulong addr, ABI_TYPE val,
DATA_TYPE *haddr = atomic_mmu_lookup(env, addr, oi, DATA_SIZE,
PAGE_READ | PAGE_WRITE, retaddr);
ABI_TYPE ret;
- uint16_t info = atomic_trace_rmw_pre(env, addr, oi);
+ atomic_trace_rmw_pre(env, addr, oi);
ret = qatomic_xchg__nocheck(haddr, BSWAP(val));
ATOMIC_MMU_CLEANUP;
- atomic_trace_rmw_post(env, addr, info);
+ atomic_trace_rmw_post(env, addr, oi);
return BSWAP(ret);
}
@@ -279,10 +279,10 @@ ABI_TYPE ATOMIC_NAME(X)(CPUArchState *env, target_ulong addr, \
DATA_TYPE *haddr = atomic_mmu_lookup(env, addr, oi, DATA_SIZE, \
PAGE_READ | PAGE_WRITE, retaddr); \
DATA_TYPE ret; \
- uint16_t info = atomic_trace_rmw_pre(env, addr, oi); \
+ atomic_trace_rmw_pre(env, addr, oi); \
ret = qatomic_##X(haddr, BSWAP(val)); \
ATOMIC_MMU_CLEANUP; \
- atomic_trace_rmw_post(env, addr, info); \
+ atomic_trace_rmw_post(env, addr, oi); \
return BSWAP(ret); \
}
@@ -309,7 +309,7 @@ ABI_TYPE ATOMIC_NAME(X)(CPUArchState *env, target_ulong addr, \
XDATA_TYPE *haddr = atomic_mmu_lookup(env, addr, oi, DATA_SIZE, \
PAGE_READ | PAGE_WRITE, retaddr); \
XDATA_TYPE ldo, ldn, old, new, val = xval; \
- uint16_t info = atomic_trace_rmw_pre(env, addr, oi); \
+ atomic_trace_rmw_pre(env, addr, oi); \
smp_mb(); \
ldn = qatomic_read__nocheck(haddr); \
do { \
@@ -317,7 +317,7 @@ ABI_TYPE ATOMIC_NAME(X)(CPUArchState *env, target_ulong addr, \
ldn = qatomic_cmpxchg__nocheck(haddr, ldo, BSWAP(new)); \
} while (ldo != ldn); \
ATOMIC_MMU_CLEANUP; \
- atomic_trace_rmw_post(env, addr, info); \
+ atomic_trace_rmw_post(env, addr, oi); \
return RET; \
}
diff --git a/accel/tcg/atomic_common.c.inc b/accel/tcg/atomic_common.c.inc
index 6019a957b9..db81eb5e66 100644
--- a/accel/tcg/atomic_common.c.inc
+++ b/accel/tcg/atomic_common.c.inc
@@ -13,55 +13,55 @@
* See the COPYING file in the top-level directory.
*/
-static uint16_t atomic_trace_rmw_pre(CPUArchState *env, target_ulong addr,
- MemOpIdx oi)
+static void atomic_trace_rmw_pre(CPUArchState *env, target_ulong addr,
+ MemOpIdx oi)
{
CPUState *cpu = env_cpu(env);
uint16_t info = trace_mem_get_info(oi, false);
trace_guest_mem_before_exec(cpu, addr, info);
trace_guest_mem_before_exec(cpu, addr, info | TRACE_MEM_ST);
-
- return info;
}
static void atomic_trace_rmw_post(CPUArchState *env, target_ulong addr,
- uint16_t info)
+ MemOpIdx oi)
{
+ uint16_t info = trace_mem_get_info(oi, false);
+
qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, info);
qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, info | TRACE_MEM_ST);
}
#if HAVE_ATOMIC128
-static uint16_t atomic_trace_ld_pre(CPUArchState *env, target_ulong addr,
- MemOpIdx oi)
+static void atomic_trace_ld_pre(CPUArchState *env, target_ulong addr,
+ MemOpIdx oi)
{
uint16_t info = trace_mem_get_info(oi, false);
trace_guest_mem_before_exec(env_cpu(env), addr, info);
-
- return info;
}
static void atomic_trace_ld_post(CPUArchState *env, target_ulong addr,
- uint16_t info)
+ MemOpIdx oi)
{
+ uint16_t info = trace_mem_get_info(oi, false);
+
qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, info);
}
-static uint16_t atomic_trace_st_pre(CPUArchState *env, target_ulong addr,
- MemOpIdx oi)
+static void atomic_trace_st_pre(CPUArchState *env, target_ulong addr,
+ MemOpIdx oi)
{
uint16_t info = trace_mem_get_info(oi, true);
trace_guest_mem_before_exec(env_cpu(env), addr, info);
-
- return info;
}
static void atomic_trace_st_post(CPUArchState *env, target_ulong addr,
- uint16_t info)
+ MemOpIdx oi)
{
+ uint16_t info = trace_mem_get_info(oi, false);
+
qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, info);
}
#endif
--
2.25.1
^ permalink raw reply related [flat|nested] 102+ messages in thread* [PATCH for-6.2 25/43] plugins: Reorg arguments to qemu_plugin_vcpu_mem_cb
2021-07-29 0:46 [PATCH for-6.2 00/43] Unaligned accesses for user-only Richard Henderson
` (23 preceding siblings ...)
2021-07-29 0:46 ` [PATCH for-6.2 24/43] accel/tcg: Pass MemOpIdx to atomic_trace_*_post Richard Henderson
@ 2021-07-29 0:46 ` Richard Henderson
2021-08-30 21:26 ` Philippe Mathieu-Daudé
2021-07-29 0:46 ` [PATCH for-6.2 26/43] trace: Split guest_mem_before Richard Henderson
` (19 subsequent siblings)
44 siblings, 1 reply; 102+ messages in thread
From: Richard Henderson @ 2021-07-29 0:46 UTC (permalink / raw)
To: qemu-devel
Use the MemOpIdx directly, rather than the rearrangement
of the same bits currently done by the trace infrastructure.
Pass in enum qemu_plugin_mem_rw so that we are able to treat
read-modify-write operations as a single operation.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/qemu/plugin.h | 26 ++++++++++++++++++++++++--
accel/tcg/cputlb.c | 4 ++--
accel/tcg/plugin-gen.c | 5 ++---
accel/tcg/user-exec.c | 28 ++++++++++++++--------------
plugins/api.c | 19 +++++++++++--------
plugins/core.c | 10 +++++-----
tcg/tcg-op.c | 30 +++++++++++++++++++++---------
accel/tcg/atomic_common.c.inc | 13 +++----------
8 files changed, 82 insertions(+), 53 deletions(-)
diff --git a/include/qemu/plugin.h b/include/qemu/plugin.h
index 9a8438f683..b3172b147f 100644
--- a/include/qemu/plugin.h
+++ b/include/qemu/plugin.h
@@ -12,6 +12,7 @@
#include "qemu/error-report.h"
#include "qemu/queue.h"
#include "qemu/option.h"
+#include "exec/memopidx.h"
/*
* Events that plugins can subscribe to.
@@ -36,6 +37,25 @@ enum qemu_plugin_event {
struct qemu_plugin_desc;
typedef QTAILQ_HEAD(, qemu_plugin_desc) QemuPluginList;
+/*
+ * Construct a qemu_plugin_meminfo_t.
+ */
+static inline qemu_plugin_meminfo_t
+make_plugin_meminfo(MemOpIdx oi, enum qemu_plugin_mem_rw rw)
+{
+ return oi | (rw << 16);
+}
+
+/*
+ * Extract the memory operation direction from a qemu_plugin_meminfo_t.
+ * Other portions may be extracted via get_memop and get_mmuidx.
+ */
+static inline enum qemu_plugin_mem_rw
+get_plugin_meminfo_rw(qemu_plugin_meminfo_t i)
+{
+ return i >> 16;
+}
+
#ifdef CONFIG_PLUGIN
extern QemuOptsList qemu_plugin_opts;
@@ -180,7 +200,8 @@ qemu_plugin_vcpu_syscall(CPUState *cpu, int64_t num, uint64_t a1,
uint64_t a6, uint64_t a7, uint64_t a8);
void qemu_plugin_vcpu_syscall_ret(CPUState *cpu, int64_t num, int64_t ret);
-void qemu_plugin_vcpu_mem_cb(CPUState *cpu, uint64_t vaddr, uint32_t meminfo);
+void qemu_plugin_vcpu_mem_cb(CPUState *cpu, uint64_t vaddr,
+ MemOpIdx oi, enum qemu_plugin_mem_rw rw);
void qemu_plugin_flush_cb(void);
@@ -244,7 +265,8 @@ void qemu_plugin_vcpu_syscall_ret(CPUState *cpu, int64_t num, int64_t ret)
{ }
static inline void qemu_plugin_vcpu_mem_cb(CPUState *cpu, uint64_t vaddr,
- uint32_t meminfo)
+ MemOpIdx oi,
+ enum qemu_plugin_mem_rw rw)
{ }
static inline void qemu_plugin_flush_cb(void)
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index 0aa6157ec4..ee07457880 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -2120,7 +2120,7 @@ static inline uint64_t cpu_load_helper(CPUArchState *env, abi_ptr addr,
ret = full_load(env, addr, oi, retaddr);
- qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, meminfo);
+ qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_R);
return ret;
}
@@ -2556,7 +2556,7 @@ cpu_store_helper(CPUArchState *env, target_ulong addr, uint64_t val,
store_helper(env, addr, val, oi, retaddr, op);
- qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, meminfo);
+ qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_W);
}
void cpu_stb_mmuidx_ra(CPUArchState *env, target_ulong addr, uint32_t val,
diff --git a/accel/tcg/plugin-gen.c b/accel/tcg/plugin-gen.c
index 88e25c6df9..f5fd5f279c 100644
--- a/accel/tcg/plugin-gen.c
+++ b/accel/tcg/plugin-gen.c
@@ -45,7 +45,6 @@
#include "qemu/osdep.h"
#include "tcg/tcg.h"
#include "tcg/tcg-op.h"
-#include "trace/mem.h"
#include "exec/exec-all.h"
#include "exec/plugin-gen.h"
#include "exec/translator.h"
@@ -211,9 +210,9 @@ static void gen_mem_wrapped(enum plugin_gen_cb type,
const union mem_gen_fn *f, TCGv addr,
uint32_t info, bool is_mem)
{
- int wr = !!(info & TRACE_MEM_ST);
+ enum qemu_plugin_mem_rw rw = get_plugin_meminfo_rw(info);
- gen_plugin_cb_start(PLUGIN_GEN_FROM_MEM, type, wr);
+ gen_plugin_cb_start(PLUGIN_GEN_FROM_MEM, type, rw);
if (is_mem) {
f->mem_fn(addr, info);
} else {
diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
index 9f6fa729d0..9f8f3a8031 100644
--- a/accel/tcg/user-exec.c
+++ b/accel/tcg/user-exec.c
@@ -870,7 +870,7 @@ uint32_t cpu_ldub_data(CPUArchState *env, abi_ptr ptr)
trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
ret = ldub_p(g2h(env_cpu(env), ptr));
- qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
+ qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_R);
return ret;
}
@@ -887,7 +887,7 @@ uint32_t cpu_lduw_be_data(CPUArchState *env, abi_ptr ptr)
trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
ret = lduw_be_p(g2h(env_cpu(env), ptr));
- qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
+ qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_R);
return ret;
}
@@ -904,7 +904,7 @@ uint32_t cpu_ldl_be_data(CPUArchState *env, abi_ptr ptr)
trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
ret = ldl_be_p(g2h(env_cpu(env), ptr));
- qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
+ qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_R);
return ret;
}
@@ -916,7 +916,7 @@ uint64_t cpu_ldq_be_data(CPUArchState *env, abi_ptr ptr)
trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
ret = ldq_be_p(g2h(env_cpu(env), ptr));
- qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
+ qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_R);
return ret;
}
@@ -928,7 +928,7 @@ uint32_t cpu_lduw_le_data(CPUArchState *env, abi_ptr ptr)
trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
ret = lduw_le_p(g2h(env_cpu(env), ptr));
- qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
+ qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_R);
return ret;
}
@@ -945,7 +945,7 @@ uint32_t cpu_ldl_le_data(CPUArchState *env, abi_ptr ptr)
trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
ret = ldl_le_p(g2h(env_cpu(env), ptr));
- qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
+ qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_R);
return ret;
}
@@ -957,7 +957,7 @@ uint64_t cpu_ldq_le_data(CPUArchState *env, abi_ptr ptr)
trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
ret = ldq_le_p(g2h(env_cpu(env), ptr));
- qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
+ qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_R);
return ret;
}
@@ -1053,7 +1053,7 @@ void cpu_stb_data(CPUArchState *env, abi_ptr ptr, uint32_t val)
trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
stb_p(g2h(env_cpu(env), ptr), val);
- qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
+ qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_W);
}
void cpu_stw_be_data(CPUArchState *env, abi_ptr ptr, uint32_t val)
@@ -1063,7 +1063,7 @@ void cpu_stw_be_data(CPUArchState *env, abi_ptr ptr, uint32_t val)
trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
stw_be_p(g2h(env_cpu(env), ptr), val);
- qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
+ qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_W);
}
void cpu_stl_be_data(CPUArchState *env, abi_ptr ptr, uint32_t val)
@@ -1073,7 +1073,7 @@ void cpu_stl_be_data(CPUArchState *env, abi_ptr ptr, uint32_t val)
trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
stl_be_p(g2h(env_cpu(env), ptr), val);
- qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
+ qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_W);
}
void cpu_stq_be_data(CPUArchState *env, abi_ptr ptr, uint64_t val)
@@ -1083,7 +1083,7 @@ void cpu_stq_be_data(CPUArchState *env, abi_ptr ptr, uint64_t val)
trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
stq_be_p(g2h(env_cpu(env), ptr), val);
- qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
+ qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_W);
}
void cpu_stw_le_data(CPUArchState *env, abi_ptr ptr, uint32_t val)
@@ -1093,7 +1093,7 @@ void cpu_stw_le_data(CPUArchState *env, abi_ptr ptr, uint32_t val)
trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
stw_le_p(g2h(env_cpu(env), ptr), val);
- qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
+ qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_W);
}
void cpu_stl_le_data(CPUArchState *env, abi_ptr ptr, uint32_t val)
@@ -1103,7 +1103,7 @@ void cpu_stl_le_data(CPUArchState *env, abi_ptr ptr, uint32_t val)
trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
stl_le_p(g2h(env_cpu(env), ptr), val);
- qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
+ qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_W);
}
void cpu_stq_le_data(CPUArchState *env, abi_ptr ptr, uint64_t val)
@@ -1113,7 +1113,7 @@ void cpu_stq_le_data(CPUArchState *env, abi_ptr ptr, uint64_t val)
trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
stq_le_p(g2h(env_cpu(env), ptr), val);
- qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
+ qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_W);
}
void cpu_stb_data_ra(CPUArchState *env, abi_ptr ptr,
diff --git a/plugins/api.c b/plugins/api.c
index 2d521e6ba8..bf4b9b9548 100644
--- a/plugins/api.c
+++ b/plugins/api.c
@@ -45,7 +45,6 @@
#include "qemu/plugin-memory.h"
#include "hw/boards.h"
#endif
-#include "trace/mem.h"
/* Uninstall and Reset handlers */
@@ -246,22 +245,25 @@ const char *qemu_plugin_insn_symbol(const struct qemu_plugin_insn *insn)
unsigned qemu_plugin_mem_size_shift(qemu_plugin_meminfo_t info)
{
- return info & TRACE_MEM_SZ_SHIFT_MASK;
+ MemOp op = get_memop(info);
+ return op & MO_SIZE;
}
bool qemu_plugin_mem_is_sign_extended(qemu_plugin_meminfo_t info)
{
- return !!(info & TRACE_MEM_SE);
+ MemOp op = get_memop(info);
+ return op & MO_SIGN;
}
bool qemu_plugin_mem_is_big_endian(qemu_plugin_meminfo_t info)
{
- return !!(info & TRACE_MEM_BE);
+ MemOp op = get_memop(info);
+ return (op & MO_BSWAP) == MO_BE;
}
bool qemu_plugin_mem_is_store(qemu_plugin_meminfo_t info)
{
- return !!(info & TRACE_MEM_ST);
+ return get_plugin_meminfo_rw(info) & QEMU_PLUGIN_MEM_W;
}
/*
@@ -277,11 +279,12 @@ struct qemu_plugin_hwaddr *qemu_plugin_get_hwaddr(qemu_plugin_meminfo_t info,
{
#ifdef CONFIG_SOFTMMU
CPUState *cpu = current_cpu;
- unsigned int mmu_idx = info >> TRACE_MEM_MMU_SHIFT;
- hwaddr_info.is_store = info & TRACE_MEM_ST;
+ unsigned int mmu_idx = get_mmuidx(info);
+ enum qemu_plugin_mem_rw rw = get_plugin_meminfo_rw(info);
+ hwaddr_info.is_store = (rw & QEMU_PLUGIN_MEM_W) != 0;
if (!tlb_plugin_lookup(cpu, vaddr, mmu_idx,
- info & TRACE_MEM_ST, &hwaddr_info)) {
+ hwaddr_info.is_store, &hwaddr_info)) {
error_report("invalid use of qemu_plugin_get_hwaddr");
return NULL;
}
diff --git a/plugins/core.c b/plugins/core.c
index 6b2490f973..792262da08 100644
--- a/plugins/core.c
+++ b/plugins/core.c
@@ -27,7 +27,6 @@
#include "exec/helper-proto.h"
#include "tcg/tcg.h"
#include "tcg/tcg-op.h"
-#include "trace/mem.h" /* mem_info macros */
#include "plugin.h"
#include "qemu/compiler.h"
@@ -446,7 +445,8 @@ void exec_inline_op(struct qemu_plugin_dyn_cb *cb)
}
}
-void qemu_plugin_vcpu_mem_cb(CPUState *cpu, uint64_t vaddr, uint32_t info)
+void qemu_plugin_vcpu_mem_cb(CPUState *cpu, uint64_t vaddr,
+ MemOpIdx oi, enum qemu_plugin_mem_rw rw)
{
GArray *arr = cpu->plugin_mem_cbs;
size_t i;
@@ -457,14 +457,14 @@ void qemu_plugin_vcpu_mem_cb(CPUState *cpu, uint64_t vaddr, uint32_t info)
for (i = 0; i < arr->len; i++) {
struct qemu_plugin_dyn_cb *cb =
&g_array_index(arr, struct qemu_plugin_dyn_cb, i);
- int w = !!(info & TRACE_MEM_ST) + 1;
- if (!(w & cb->rw)) {
+ if (!(rw & cb->rw)) {
break;
}
switch (cb->type) {
case PLUGIN_CB_REGULAR:
- cb->f.vcpu_mem(cpu->cpu_index, info, vaddr, cb->userp);
+ cb->f.vcpu_mem(cpu->cpu_index, make_plugin_meminfo(oi, rw),
+ vaddr, cb->userp);
break;
case PLUGIN_CB_INLINE:
exec_inline_op(cb);
diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c
index 37b440af7f..af7bb851b5 100644
--- a/tcg/tcg-op.c
+++ b/tcg/tcg-op.c
@@ -2853,10 +2853,12 @@ static inline TCGv plugin_prep_mem_callbacks(TCGv vaddr)
return vaddr;
}
-static inline void plugin_gen_mem_callbacks(TCGv vaddr, uint16_t info)
+static void plugin_gen_mem_callbacks(TCGv vaddr, MemOpIdx oi,
+ enum qemu_plugin_mem_rw rw)
{
#ifdef CONFIG_PLUGIN
if (tcg_ctx->plugin_insn != NULL) {
+ qemu_plugin_meminfo_t info = make_plugin_meminfo(oi, rw);
plugin_gen_empty_mem_callback(vaddr, info);
tcg_temp_free(vaddr);
}
@@ -2866,10 +2868,13 @@ static inline void plugin_gen_mem_callbacks(TCGv vaddr, uint16_t info)
void tcg_gen_qemu_ld_i32(TCGv_i32 val, TCGv addr, TCGArg idx, MemOp memop)
{
MemOp orig_memop;
- uint16_t info = trace_mem_get_info(make_memop_idx(memop, idx), 0);
+ MemOpIdx oi;
+ uint16_t info;
tcg_gen_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD);
memop = tcg_canonicalize_memop(memop, 0, 0);
+ oi = make_memop_idx(memop, idx);
+ info = trace_mem_get_info(oi, 0);
trace_guest_mem_before_tcg(tcg_ctx->cpu, cpu_env, addr, info);
orig_memop = memop;
@@ -2883,7 +2888,7 @@ void tcg_gen_qemu_ld_i32(TCGv_i32 val, TCGv addr, TCGArg idx, MemOp memop)
addr = plugin_prep_mem_callbacks(addr);
gen_ldst_i32(INDEX_op_qemu_ld_i32, val, addr, memop, idx);
- plugin_gen_mem_callbacks(addr, info);
+ plugin_gen_mem_callbacks(addr, oi, QEMU_PLUGIN_MEM_R);
if ((orig_memop ^ memop) & MO_BSWAP) {
switch (orig_memop & MO_SIZE) {
@@ -2904,10 +2909,13 @@ void tcg_gen_qemu_ld_i32(TCGv_i32 val, TCGv addr, TCGArg idx, MemOp memop)
void tcg_gen_qemu_st_i32(TCGv_i32 val, TCGv addr, TCGArg idx, MemOp memop)
{
TCGv_i32 swap = NULL;
- uint16_t info = trace_mem_get_info(make_memop_idx(memop, idx), 1);
+ MemOpIdx oi;
+ uint16_t info;
tcg_gen_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST);
memop = tcg_canonicalize_memop(memop, 0, 1);
+ oi = make_memop_idx(memop, idx);
+ info = trace_mem_get_info(oi, 1);
trace_guest_mem_before_tcg(tcg_ctx->cpu, cpu_env, addr, info);
if (!TCG_TARGET_HAS_MEMORY_BSWAP && (memop & MO_BSWAP)) {
@@ -2932,7 +2940,7 @@ void tcg_gen_qemu_st_i32(TCGv_i32 val, TCGv addr, TCGArg idx, MemOp memop)
} else {
gen_ldst_i32(INDEX_op_qemu_st_i32, val, addr, memop, idx);
}
- plugin_gen_mem_callbacks(addr, info);
+ plugin_gen_mem_callbacks(addr, oi, QEMU_PLUGIN_MEM_W);
if (swap) {
tcg_temp_free_i32(swap);
@@ -2942,6 +2950,7 @@ void tcg_gen_qemu_st_i32(TCGv_i32 val, TCGv addr, TCGArg idx, MemOp memop)
void tcg_gen_qemu_ld_i64(TCGv_i64 val, TCGv addr, TCGArg idx, MemOp memop)
{
MemOp orig_memop;
+ MemOpIdx oi;
uint16_t info;
if (TCG_TARGET_REG_BITS == 32 && (memop & MO_SIZE) < MO_64) {
@@ -2956,7 +2965,8 @@ void tcg_gen_qemu_ld_i64(TCGv_i64 val, TCGv addr, TCGArg idx, MemOp memop)
tcg_gen_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD);
memop = tcg_canonicalize_memop(memop, 1, 0);
- info = trace_mem_get_info(make_memop_idx(memop, idx), 0);
+ oi = make_memop_idx(memop, idx);
+ info = trace_mem_get_info(oi, 0);
trace_guest_mem_before_tcg(tcg_ctx->cpu, cpu_env, addr, info);
orig_memop = memop;
@@ -2970,7 +2980,7 @@ void tcg_gen_qemu_ld_i64(TCGv_i64 val, TCGv addr, TCGArg idx, MemOp memop)
addr = plugin_prep_mem_callbacks(addr);
gen_ldst_i64(INDEX_op_qemu_ld_i64, val, addr, memop, idx);
- plugin_gen_mem_callbacks(addr, info);
+ plugin_gen_mem_callbacks(addr, oi, QEMU_PLUGIN_MEM_R);
if ((orig_memop ^ memop) & MO_BSWAP) {
int flags = (orig_memop & MO_SIGN
@@ -2995,6 +3005,7 @@ void tcg_gen_qemu_ld_i64(TCGv_i64 val, TCGv addr, TCGArg idx, MemOp memop)
void tcg_gen_qemu_st_i64(TCGv_i64 val, TCGv addr, TCGArg idx, MemOp memop)
{
TCGv_i64 swap = NULL;
+ MemOpIdx oi;
uint16_t info;
if (TCG_TARGET_REG_BITS == 32 && (memop & MO_SIZE) < MO_64) {
@@ -3004,7 +3015,8 @@ void tcg_gen_qemu_st_i64(TCGv_i64 val, TCGv addr, TCGArg idx, MemOp memop)
tcg_gen_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST);
memop = tcg_canonicalize_memop(memop, 1, 1);
- info = trace_mem_get_info(make_memop_idx(memop, idx), 1);
+ oi = make_memop_idx(memop, idx);
+ info = trace_mem_get_info(oi, 1);
trace_guest_mem_before_tcg(tcg_ctx->cpu, cpu_env, addr, info);
if (!TCG_TARGET_HAS_MEMORY_BSWAP && (memop & MO_BSWAP)) {
@@ -3028,7 +3040,7 @@ void tcg_gen_qemu_st_i64(TCGv_i64 val, TCGv addr, TCGArg idx, MemOp memop)
addr = plugin_prep_mem_callbacks(addr);
gen_ldst_i64(INDEX_op_qemu_st_i64, val, addr, memop, idx);
- plugin_gen_mem_callbacks(addr, info);
+ plugin_gen_mem_callbacks(addr, oi, QEMU_PLUGIN_MEM_W);
if (swap) {
tcg_temp_free_i64(swap);
diff --git a/accel/tcg/atomic_common.c.inc b/accel/tcg/atomic_common.c.inc
index db81eb5e66..f3ab96e888 100644
--- a/accel/tcg/atomic_common.c.inc
+++ b/accel/tcg/atomic_common.c.inc
@@ -26,10 +26,7 @@ static void atomic_trace_rmw_pre(CPUArchState *env, target_ulong addr,
static void atomic_trace_rmw_post(CPUArchState *env, target_ulong addr,
MemOpIdx oi)
{
- uint16_t info = trace_mem_get_info(oi, false);
-
- qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, info);
- qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, info | TRACE_MEM_ST);
+ qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_RW);
}
#if HAVE_ATOMIC128
@@ -44,9 +41,7 @@ static void atomic_trace_ld_pre(CPUArchState *env, target_ulong addr,
static void atomic_trace_ld_post(CPUArchState *env, target_ulong addr,
MemOpIdx oi)
{
- uint16_t info = trace_mem_get_info(oi, false);
-
- qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, info);
+ qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_R);
}
static void atomic_trace_st_pre(CPUArchState *env, target_ulong addr,
@@ -60,9 +55,7 @@ static void atomic_trace_st_pre(CPUArchState *env, target_ulong addr,
static void atomic_trace_st_post(CPUArchState *env, target_ulong addr,
MemOpIdx oi)
{
- uint16_t info = trace_mem_get_info(oi, false);
-
- qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, info);
+ qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_W);
}
#endif
--
2.25.1
^ permalink raw reply related [flat|nested] 102+ messages in thread* Re: [PATCH for-6.2 25/43] plugins: Reorg arguments to qemu_plugin_vcpu_mem_cb
2021-07-29 0:46 ` [PATCH for-6.2 25/43] plugins: Reorg arguments to qemu_plugin_vcpu_mem_cb Richard Henderson
@ 2021-08-30 21:26 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 102+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-08-30 21:26 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
On 7/29/21 2:46 AM, Richard Henderson wrote:
> Use the MemOpIdx directly, rather than the rearrangement
> of the same bits currently done by the trace infrastructure.
> Pass in enum qemu_plugin_mem_rw so that we are able to treat
> read-modify-write operations as a single operation.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> include/qemu/plugin.h | 26 ++++++++++++++++++++++++--
> accel/tcg/cputlb.c | 4 ++--
> accel/tcg/plugin-gen.c | 5 ++---
> accel/tcg/user-exec.c | 28 ++++++++++++++--------------
> plugins/api.c | 19 +++++++++++--------
> plugins/core.c | 10 +++++-----
> tcg/tcg-op.c | 30 +++++++++++++++++++++---------
> accel/tcg/atomic_common.c.inc | 13 +++----------
> 8 files changed, 82 insertions(+), 53 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
^ permalink raw reply [flat|nested] 102+ messages in thread
* [PATCH for-6.2 26/43] trace: Split guest_mem_before
2021-07-29 0:46 [PATCH for-6.2 00/43] Unaligned accesses for user-only Richard Henderson
` (24 preceding siblings ...)
2021-07-29 0:46 ` [PATCH for-6.2 25/43] plugins: Reorg arguments to qemu_plugin_vcpu_mem_cb Richard Henderson
@ 2021-07-29 0:46 ` Richard Henderson
2021-07-29 0:46 ` [PATCH for-6.2 27/43] target/arm: Use MO_128 for 16 byte atomics Richard Henderson
` (18 subsequent siblings)
44 siblings, 0 replies; 102+ messages in thread
From: Richard Henderson @ 2021-07-29 0:46 UTC (permalink / raw)
To: qemu-devel
There is no point in encoding load/store within a bit of
the memory trace info operand. Represent atomic operations
as a single read-modify-write tracepoint. Use MemOpIdx
instead of inventing a form specifically for traces.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
accel/tcg/atomic_template.h | 1 -
trace/mem.h | 51 -----------------------------------
accel/tcg/cputlb.c | 7 ++---
accel/tcg/user-exec.c | 43 ++++++++++-------------------
tcg/tcg-op.c | 17 +++---------
accel/tcg/atomic_common.c.inc | 12 +++------
trace-events | 18 +++----------
7 files changed, 27 insertions(+), 122 deletions(-)
delete mode 100644 trace/mem.h
diff --git a/accel/tcg/atomic_template.h b/accel/tcg/atomic_template.h
index c08d859a8a..2d917b6b1f 100644
--- a/accel/tcg/atomic_template.h
+++ b/accel/tcg/atomic_template.h
@@ -19,7 +19,6 @@
*/
#include "qemu/plugin.h"
-#include "trace/mem.h"
#if DATA_SIZE == 16
# define SUFFIX o
diff --git a/trace/mem.h b/trace/mem.h
deleted file mode 100644
index 699566c661..0000000000
--- a/trace/mem.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * Helper functions for guest memory tracing
- *
- * Copyright (C) 2016 Lluís Vilanova <vilanova@ac.upc.edu>
- *
- * This work is licensed under the terms of the GNU GPL, version 2 or later.
- * See the COPYING file in the top-level directory.
- */
-
-#ifndef TRACE__MEM_H
-#define TRACE__MEM_H
-
-#include "exec/memopidx.h"
-
-#define TRACE_MEM_SZ_SHIFT_MASK 0xf /* size shift mask */
-#define TRACE_MEM_SE (1ULL << 4) /* sign extended (y/n) */
-#define TRACE_MEM_BE (1ULL << 5) /* big endian (y/n) */
-#define TRACE_MEM_ST (1ULL << 6) /* store (y/n) */
-#define TRACE_MEM_MMU_SHIFT 8 /* mmu idx */
-
-/**
- * trace_mem_get_info:
- *
- * Return a value for the 'info' argument in guest memory access traces.
- */
-static inline uint16_t trace_mem_get_info(MemOpIdx oi, bool store)
-{
- MemOp op = get_memop(oi);
- uint32_t size_shift = op & MO_SIZE;
- bool sign_extend = op & MO_SIGN;
- bool big_endian = (op & MO_BSWAP) == MO_BE;
- uint16_t res;
-
- res = size_shift & TRACE_MEM_SZ_SHIFT_MASK;
- if (sign_extend) {
- res |= TRACE_MEM_SE;
- }
- if (big_endian) {
- res |= TRACE_MEM_BE;
- }
- if (store) {
- res |= TRACE_MEM_ST;
- }
-#ifdef CONFIG_SOFTMMU
- res |= get_mmuidx(oi) << TRACE_MEM_MMU_SHIFT;
-#endif
-
- return res;
-}
-
-#endif /* TRACE__MEM_H */
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index ee07457880..46140ccff3 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -34,7 +34,6 @@
#include "qemu/atomic128.h"
#include "exec/translate-all.h"
#include "trace/trace-root.h"
-#include "trace/mem.h"
#include "tb-hash.h"
#include "internal.h"
#ifdef CONFIG_PLUGIN
@@ -2113,10 +2112,9 @@ static inline uint64_t cpu_load_helper(CPUArchState *env, abi_ptr addr,
MemOp op, FullLoadHelper *full_load)
{
MemOpIdx oi = make_memop_idx(op, mmu_idx);
- uint16_t meminfo = trace_mem_get_info(oi, false);
uint64_t ret;
- trace_guest_mem_before_exec(env_cpu(env), addr, meminfo);
+ trace_guest_ld_before_exec(env_cpu(env), addr, oi);
ret = full_load(env, addr, oi, retaddr);
@@ -2550,9 +2548,8 @@ cpu_store_helper(CPUArchState *env, target_ulong addr, uint64_t val,
int mmu_idx, uintptr_t retaddr, MemOp op)
{
MemOpIdx oi = make_memop_idx(op, mmu_idx);
- uint16_t meminfo = trace_mem_get_info(oi, true);
- trace_guest_mem_before_exec(env_cpu(env), addr, meminfo);
+ trace_guest_st_before_exec(env_cpu(env), addr, oi);
store_helper(env, addr, val, oi, retaddr, op);
diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
index 9f8f3a8031..eda577013f 100644
--- a/accel/tcg/user-exec.c
+++ b/accel/tcg/user-exec.c
@@ -27,7 +27,6 @@
#include "exec/helper-proto.h"
#include "qemu/atomic128.h"
#include "trace/trace-root.h"
-#include "trace/mem.h"
#undef EAX
#undef ECX
@@ -865,10 +864,9 @@ static void cpu_unaligned_access(CPUState *cpu, vaddr addr,
uint32_t cpu_ldub_data(CPUArchState *env, abi_ptr ptr)
{
MemOpIdx oi = make_memop_idx(MO_UB, MMU_USER_IDX);
- uint16_t meminfo = trace_mem_get_info(oi, false);
uint32_t ret;
- trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
+ trace_guest_ld_before_exec(env_cpu(env), ptr, oi);
ret = ldub_p(g2h(env_cpu(env), ptr));
qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_R);
return ret;
@@ -882,10 +880,9 @@ int cpu_ldsb_data(CPUArchState *env, abi_ptr ptr)
uint32_t cpu_lduw_be_data(CPUArchState *env, abi_ptr ptr)
{
MemOpIdx oi = make_memop_idx(MO_BEUW, MMU_USER_IDX);
- uint16_t meminfo = trace_mem_get_info(oi, false);
uint32_t ret;
- trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
+ trace_guest_ld_before_exec(env_cpu(env), ptr, oi);
ret = lduw_be_p(g2h(env_cpu(env), ptr));
qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_R);
return ret;
@@ -899,10 +896,9 @@ int cpu_ldsw_be_data(CPUArchState *env, abi_ptr ptr)
uint32_t cpu_ldl_be_data(CPUArchState *env, abi_ptr ptr)
{
MemOpIdx oi = make_memop_idx(MO_BEUL, MMU_USER_IDX);
- uint16_t meminfo = trace_mem_get_info(oi, false);
uint32_t ret;
- trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
+ trace_guest_ld_before_exec(env_cpu(env), ptr, oi);
ret = ldl_be_p(g2h(env_cpu(env), ptr));
qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_R);
return ret;
@@ -911,10 +907,9 @@ uint32_t cpu_ldl_be_data(CPUArchState *env, abi_ptr ptr)
uint64_t cpu_ldq_be_data(CPUArchState *env, abi_ptr ptr)
{
MemOpIdx oi = make_memop_idx(MO_BEQ, MMU_USER_IDX);
- uint16_t meminfo = trace_mem_get_info(oi, false);
uint64_t ret;
- trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
+ trace_guest_ld_before_exec(env_cpu(env), ptr, oi);
ret = ldq_be_p(g2h(env_cpu(env), ptr));
qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_R);
return ret;
@@ -923,10 +918,9 @@ uint64_t cpu_ldq_be_data(CPUArchState *env, abi_ptr ptr)
uint32_t cpu_lduw_le_data(CPUArchState *env, abi_ptr ptr)
{
MemOpIdx oi = make_memop_idx(MO_LEUW, MMU_USER_IDX);
- uint16_t meminfo = trace_mem_get_info(oi, false);
uint32_t ret;
- trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
+ trace_guest_ld_before_exec(env_cpu(env), ptr, oi);
ret = lduw_le_p(g2h(env_cpu(env), ptr));
qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_R);
return ret;
@@ -940,10 +934,9 @@ int cpu_ldsw_le_data(CPUArchState *env, abi_ptr ptr)
uint32_t cpu_ldl_le_data(CPUArchState *env, abi_ptr ptr)
{
MemOpIdx oi = make_memop_idx(MO_LEUL, MMU_USER_IDX);
- uint16_t meminfo = trace_mem_get_info(oi, false);
uint32_t ret;
- trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
+ trace_guest_ld_before_exec(env_cpu(env), ptr, oi);
ret = ldl_le_p(g2h(env_cpu(env), ptr));
qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_R);
return ret;
@@ -952,10 +945,9 @@ uint32_t cpu_ldl_le_data(CPUArchState *env, abi_ptr ptr)
uint64_t cpu_ldq_le_data(CPUArchState *env, abi_ptr ptr)
{
MemOpIdx oi = make_memop_idx(MO_LEQ, MMU_USER_IDX);
- uint16_t meminfo = trace_mem_get_info(oi, false);
uint64_t ret;
- trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
+ trace_guest_ld_before_exec(env_cpu(env), ptr, oi);
ret = ldq_le_p(g2h(env_cpu(env), ptr));
qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_R);
return ret;
@@ -1049,9 +1041,8 @@ uint64_t cpu_ldq_le_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr)
void cpu_stb_data(CPUArchState *env, abi_ptr ptr, uint32_t val)
{
MemOpIdx oi = make_memop_idx(MO_UB, MMU_USER_IDX);
- uint16_t meminfo = trace_mem_get_info(oi, true);
- trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
+ trace_guest_st_before_exec(env_cpu(env), ptr, oi);
stb_p(g2h(env_cpu(env), ptr), val);
qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_W);
}
@@ -1059,9 +1050,8 @@ void cpu_stb_data(CPUArchState *env, abi_ptr ptr, uint32_t val)
void cpu_stw_be_data(CPUArchState *env, abi_ptr ptr, uint32_t val)
{
MemOpIdx oi = make_memop_idx(MO_BEUW, MMU_USER_IDX);
- uint16_t meminfo = trace_mem_get_info(oi, true);
- trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
+ trace_guest_st_before_exec(env_cpu(env), ptr, oi);
stw_be_p(g2h(env_cpu(env), ptr), val);
qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_W);
}
@@ -1069,9 +1059,8 @@ void cpu_stw_be_data(CPUArchState *env, abi_ptr ptr, uint32_t val)
void cpu_stl_be_data(CPUArchState *env, abi_ptr ptr, uint32_t val)
{
MemOpIdx oi = make_memop_idx(MO_BEUL, MMU_USER_IDX);
- uint16_t meminfo = trace_mem_get_info(oi, true);
- trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
+ trace_guest_st_before_exec(env_cpu(env), ptr, oi);
stl_be_p(g2h(env_cpu(env), ptr), val);
qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_W);
}
@@ -1079,9 +1068,8 @@ void cpu_stl_be_data(CPUArchState *env, abi_ptr ptr, uint32_t val)
void cpu_stq_be_data(CPUArchState *env, abi_ptr ptr, uint64_t val)
{
MemOpIdx oi = make_memop_idx(MO_BEQ, MMU_USER_IDX);
- uint16_t meminfo = trace_mem_get_info(oi, true);
- trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
+ trace_guest_st_before_exec(env_cpu(env), ptr, oi);
stq_be_p(g2h(env_cpu(env), ptr), val);
qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_W);
}
@@ -1089,9 +1077,8 @@ void cpu_stq_be_data(CPUArchState *env, abi_ptr ptr, uint64_t val)
void cpu_stw_le_data(CPUArchState *env, abi_ptr ptr, uint32_t val)
{
MemOpIdx oi = make_memop_idx(MO_LEUW, MMU_USER_IDX);
- uint16_t meminfo = trace_mem_get_info(oi, true);
- trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
+ trace_guest_st_before_exec(env_cpu(env), ptr, oi);
stw_le_p(g2h(env_cpu(env), ptr), val);
qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_W);
}
@@ -1099,9 +1086,8 @@ void cpu_stw_le_data(CPUArchState *env, abi_ptr ptr, uint32_t val)
void cpu_stl_le_data(CPUArchState *env, abi_ptr ptr, uint32_t val)
{
MemOpIdx oi = make_memop_idx(MO_LEUL, MMU_USER_IDX);
- uint16_t meminfo = trace_mem_get_info(oi, true);
- trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
+ trace_guest_st_before_exec(env_cpu(env), ptr, oi);
stl_le_p(g2h(env_cpu(env), ptr), val);
qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_W);
}
@@ -1109,9 +1095,8 @@ void cpu_stl_le_data(CPUArchState *env, abi_ptr ptr, uint32_t val)
void cpu_stq_le_data(CPUArchState *env, abi_ptr ptr, uint64_t val)
{
MemOpIdx oi = make_memop_idx(MO_LEQ, MMU_USER_IDX);
- uint16_t meminfo = trace_mem_get_info(oi, true);
- trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
+ trace_guest_st_before_exec(env_cpu(env), ptr, oi);
stq_le_p(g2h(env_cpu(env), ptr), val);
qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_W);
}
diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c
index af7bb851b5..b1cfd36f29 100644
--- a/tcg/tcg-op.c
+++ b/tcg/tcg-op.c
@@ -28,7 +28,6 @@
#include "tcg/tcg-op.h"
#include "tcg/tcg-mo.h"
#include "trace-tcg.h"
-#include "trace/mem.h"
#include "exec/plugin-gen.h"
/* Reduce the number of ifdefs below. This assumes that all uses of
@@ -2869,13 +2868,11 @@ void tcg_gen_qemu_ld_i32(TCGv_i32 val, TCGv addr, TCGArg idx, MemOp memop)
{
MemOp orig_memop;
MemOpIdx oi;
- uint16_t info;
tcg_gen_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD);
memop = tcg_canonicalize_memop(memop, 0, 0);
oi = make_memop_idx(memop, idx);
- info = trace_mem_get_info(oi, 0);
- trace_guest_mem_before_tcg(tcg_ctx->cpu, cpu_env, addr, info);
+ trace_guest_ld_before_tcg(tcg_ctx->cpu, cpu_env, addr, oi);
orig_memop = memop;
if (!TCG_TARGET_HAS_MEMORY_BSWAP && (memop & MO_BSWAP)) {
@@ -2910,13 +2907,11 @@ void tcg_gen_qemu_st_i32(TCGv_i32 val, TCGv addr, TCGArg idx, MemOp memop)
{
TCGv_i32 swap = NULL;
MemOpIdx oi;
- uint16_t info;
tcg_gen_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST);
memop = tcg_canonicalize_memop(memop, 0, 1);
oi = make_memop_idx(memop, idx);
- info = trace_mem_get_info(oi, 1);
- trace_guest_mem_before_tcg(tcg_ctx->cpu, cpu_env, addr, info);
+ trace_guest_st_before_tcg(tcg_ctx->cpu, cpu_env, addr, oi);
if (!TCG_TARGET_HAS_MEMORY_BSWAP && (memop & MO_BSWAP)) {
swap = tcg_temp_new_i32();
@@ -2951,7 +2946,6 @@ void tcg_gen_qemu_ld_i64(TCGv_i64 val, TCGv addr, TCGArg idx, MemOp memop)
{
MemOp orig_memop;
MemOpIdx oi;
- uint16_t info;
if (TCG_TARGET_REG_BITS == 32 && (memop & MO_SIZE) < MO_64) {
tcg_gen_qemu_ld_i32(TCGV_LOW(val), addr, idx, memop);
@@ -2966,8 +2960,7 @@ void tcg_gen_qemu_ld_i64(TCGv_i64 val, TCGv addr, TCGArg idx, MemOp memop)
tcg_gen_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD);
memop = tcg_canonicalize_memop(memop, 1, 0);
oi = make_memop_idx(memop, idx);
- info = trace_mem_get_info(oi, 0);
- trace_guest_mem_before_tcg(tcg_ctx->cpu, cpu_env, addr, info);
+ trace_guest_ld_before_tcg(tcg_ctx->cpu, cpu_env, addr, oi);
orig_memop = memop;
if (!TCG_TARGET_HAS_MEMORY_BSWAP && (memop & MO_BSWAP)) {
@@ -3006,7 +2999,6 @@ void tcg_gen_qemu_st_i64(TCGv_i64 val, TCGv addr, TCGArg idx, MemOp memop)
{
TCGv_i64 swap = NULL;
MemOpIdx oi;
- uint16_t info;
if (TCG_TARGET_REG_BITS == 32 && (memop & MO_SIZE) < MO_64) {
tcg_gen_qemu_st_i32(TCGV_LOW(val), addr, idx, memop);
@@ -3016,8 +3008,7 @@ void tcg_gen_qemu_st_i64(TCGv_i64 val, TCGv addr, TCGArg idx, MemOp memop)
tcg_gen_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST);
memop = tcg_canonicalize_memop(memop, 1, 1);
oi = make_memop_idx(memop, idx);
- info = trace_mem_get_info(oi, 1);
- trace_guest_mem_before_tcg(tcg_ctx->cpu, cpu_env, addr, info);
+ trace_guest_st_before_tcg(tcg_ctx->cpu, cpu_env, addr, oi);
if (!TCG_TARGET_HAS_MEMORY_BSWAP && (memop & MO_BSWAP)) {
swap = tcg_temp_new_i64();
diff --git a/accel/tcg/atomic_common.c.inc b/accel/tcg/atomic_common.c.inc
index f3ab96e888..1df1f243e9 100644
--- a/accel/tcg/atomic_common.c.inc
+++ b/accel/tcg/atomic_common.c.inc
@@ -17,10 +17,8 @@ static void atomic_trace_rmw_pre(CPUArchState *env, target_ulong addr,
MemOpIdx oi)
{
CPUState *cpu = env_cpu(env);
- uint16_t info = trace_mem_get_info(oi, false);
- trace_guest_mem_before_exec(cpu, addr, info);
- trace_guest_mem_before_exec(cpu, addr, info | TRACE_MEM_ST);
+ trace_guest_rmw_before_exec(cpu, addr, oi);
}
static void atomic_trace_rmw_post(CPUArchState *env, target_ulong addr,
@@ -33,9 +31,7 @@ static void atomic_trace_rmw_post(CPUArchState *env, target_ulong addr,
static void atomic_trace_ld_pre(CPUArchState *env, target_ulong addr,
MemOpIdx oi)
{
- uint16_t info = trace_mem_get_info(oi, false);
-
- trace_guest_mem_before_exec(env_cpu(env), addr, info);
+ trace_guest_ld_before_exec(env_cpu(env), addr, oi);
}
static void atomic_trace_ld_post(CPUArchState *env, target_ulong addr,
@@ -47,9 +43,7 @@ static void atomic_trace_ld_post(CPUArchState *env, target_ulong addr,
static void atomic_trace_st_pre(CPUArchState *env, target_ulong addr,
MemOpIdx oi)
{
- uint16_t info = trace_mem_get_info(oi, true);
-
- trace_guest_mem_before_exec(env_cpu(env), addr, info);
+ trace_guest_st_before_exec(env_cpu(env), addr, oi);
}
static void atomic_trace_st_post(CPUArchState *env, target_ulong addr,
diff --git a/trace-events b/trace-events
index c4cca29939..a637a61eba 100644
--- a/trace-events
+++ b/trace-events
@@ -120,26 +120,16 @@ vcpu guest_cpu_reset(void)
# tcg/tcg-op.c
# @vaddr: Access' virtual address.
-# @info : Access' information (see below).
+# @memopidx: Access' information (see below).
#
# Start virtual memory access (before any potential access violation).
-#
# Does not include memory accesses performed by devices.
#
-# Access information can be parsed as:
-#
-# struct mem_info {
-# uint8_t size_shift : 4; /* interpreted as "1 << size_shift" bytes */
-# bool sign_extend: 1; /* sign-extended */
-# uint8_t endianness : 1; /* 0: little, 1: big */
-# bool store : 1; /* whether it is a store operation */
-# pad : 1;
-# uint8_t mmuidx : 4; /* mmuidx (softmmu only) */
-# };
-#
# Mode: user, softmmu
# Targets: TCG(all)
-vcpu tcg guest_mem_before(TCGv vaddr, uint16_t info) "info=%d", "vaddr=0x%016"PRIx64" info=%d"
+vcpu tcg guest_ld_before(TCGv vaddr, uint32_t memopidx) "info=%d", "vaddr=0x%016"PRIx64" memopidx=0x%x"
+vcpu tcg guest_st_before(TCGv vaddr, uint32_t memopidx) "info=%d", "vaddr=0x%016"PRIx64" memopidx=0x%x"
+vcpu tcg guest_rmw_before(TCGv vaddr, uint32_t memopidx) "info=%d", "vaddr=0x%016"PRIx64" memopidx=0x%x"
# include/user/syscall-trace.h
--
2.25.1
^ permalink raw reply related [flat|nested] 102+ messages in thread* [PATCH for-6.2 27/43] target/arm: Use MO_128 for 16 byte atomics
2021-07-29 0:46 [PATCH for-6.2 00/43] Unaligned accesses for user-only Richard Henderson
` (25 preceding siblings ...)
2021-07-29 0:46 ` [PATCH for-6.2 26/43] trace: Split guest_mem_before Richard Henderson
@ 2021-07-29 0:46 ` Richard Henderson
2021-07-29 6:32 ` Philippe Mathieu-Daudé
2021-07-29 0:46 ` [PATCH for-6.2 28/43] target/i386: " Richard Henderson
` (17 subsequent siblings)
44 siblings, 1 reply; 102+ messages in thread
From: Richard Henderson @ 2021-07-29 0:46 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm
Cc: qemu-arm@nongnu.org
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/helper-a64.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
index 13d1e3f808..f06399f351 100644
--- a/target/arm/helper-a64.c
+++ b/target/arm/helper-a64.c
@@ -560,7 +560,7 @@ uint64_t HELPER(paired_cmpxchg64_le_parallel)(CPUARMState *env, uint64_t addr,
assert(HAVE_CMPXCHG128);
mem_idx = cpu_mmu_index(env, false);
- oi = make_memop_idx(MO_LEQ | MO_ALIGN_16, mem_idx);
+ oi = make_memop_idx(MO_LE | MO_128 | MO_ALIGN, mem_idx);
cmpv = int128_make128(env->exclusive_val, env->exclusive_high);
newv = int128_make128(new_lo, new_hi);
@@ -630,7 +630,7 @@ uint64_t HELPER(paired_cmpxchg64_be_parallel)(CPUARMState *env, uint64_t addr,
assert(HAVE_CMPXCHG128);
mem_idx = cpu_mmu_index(env, false);
- oi = make_memop_idx(MO_BEQ | MO_ALIGN_16, mem_idx);
+ oi = make_memop_idx(MO_BE | MO_128 | MO_ALIGN, mem_idx);
/*
* High and low need to be switched here because this is not actually a
@@ -656,7 +656,7 @@ void HELPER(casp_le_parallel)(CPUARMState *env, uint32_t rs, uint64_t addr,
assert(HAVE_CMPXCHG128);
mem_idx = cpu_mmu_index(env, false);
- oi = make_memop_idx(MO_LEQ | MO_ALIGN_16, mem_idx);
+ oi = make_memop_idx(MO_LE | MO_128 | MO_ALIGN, mem_idx);
cmpv = int128_make128(env->xregs[rs], env->xregs[rs + 1]);
newv = int128_make128(new_lo, new_hi);
@@ -677,7 +677,7 @@ void HELPER(casp_be_parallel)(CPUARMState *env, uint32_t rs, uint64_t addr,
assert(HAVE_CMPXCHG128);
mem_idx = cpu_mmu_index(env, false);
- oi = make_memop_idx(MO_LEQ | MO_ALIGN_16, mem_idx);
+ oi = make_memop_idx(MO_LE | MO_128 | MO_ALIGN, mem_idx);
cmpv = int128_make128(env->xregs[rs + 1], env->xregs[rs]);
newv = int128_make128(new_lo, new_hi);
--
2.25.1
^ permalink raw reply related [flat|nested] 102+ messages in thread* [PATCH for-6.2 28/43] target/i386: Use MO_128 for 16 byte atomics
2021-07-29 0:46 [PATCH for-6.2 00/43] Unaligned accesses for user-only Richard Henderson
` (26 preceding siblings ...)
2021-07-29 0:46 ` [PATCH for-6.2 27/43] target/arm: Use MO_128 for 16 byte atomics Richard Henderson
@ 2021-07-29 0:46 ` Richard Henderson
2021-07-29 0:46 ` [PATCH for-6.2 29/43] target/ppc: " Richard Henderson
` (16 subsequent siblings)
44 siblings, 0 replies; 102+ messages in thread
From: Richard Henderson @ 2021-07-29 0:46 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/i386/tcg/mem_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/i386/tcg/mem_helper.c b/target/i386/tcg/mem_helper.c
index 0fd696f9c1..a207e624cb 100644
--- a/target/i386/tcg/mem_helper.c
+++ b/target/i386/tcg/mem_helper.c
@@ -136,7 +136,7 @@ void helper_cmpxchg16b(CPUX86State *env, target_ulong a0)
Int128 newv = int128_make128(env->regs[R_EBX], env->regs[R_ECX]);
int mem_idx = cpu_mmu_index(env, false);
- MemOpIdx oi = make_memop_idx(MO_TEQ | MO_ALIGN_16, mem_idx);
+ MemOpIdx oi = make_memop_idx(MO_TE | MO_128 | MO_ALIGN, mem_idx);
Int128 oldv = cpu_atomic_cmpxchgo_le_mmu(env, a0, cmpv, newv, oi, ra);
if (int128_eq(oldv, cmpv)) {
--
2.25.1
^ permalink raw reply related [flat|nested] 102+ messages in thread* [PATCH for-6.2 29/43] target/ppc: Use MO_128 for 16 byte atomics
2021-07-29 0:46 [PATCH for-6.2 00/43] Unaligned accesses for user-only Richard Henderson
` (27 preceding siblings ...)
2021-07-29 0:46 ` [PATCH for-6.2 28/43] target/i386: " Richard Henderson
@ 2021-07-29 0:46 ` Richard Henderson
2021-07-29 6:34 ` Philippe Mathieu-Daudé
2021-07-29 0:46 ` [PATCH for-6.2 30/43] target/s390x: " Richard Henderson
` (15 subsequent siblings)
44 siblings, 1 reply; 102+ messages in thread
From: Richard Henderson @ 2021-07-29 0:46 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-ppc
Cc: qemu-ppc@nongnu.org
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/ppc/translate.c | 12 +++++++-----
1 file changed, 7 insertions(+), 5 deletions(-)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 171b216e17..540efa858f 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -3461,10 +3461,12 @@ static void gen_std(DisasContext *ctx)
if (HAVE_ATOMIC128) {
TCGv_i32 oi = tcg_temp_new_i32();
if (ctx->le_mode) {
- tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ, ctx->mem_idx));
+ tcg_gen_movi_i32(oi, make_memop_idx(MO_LE | MO_128,
+ ctx->mem_idx));
gen_helper_stq_le_parallel(cpu_env, EA, lo, hi, oi);
} else {
- tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ, ctx->mem_idx));
+ tcg_gen_movi_i32(oi, make_memop_idx(MO_BE | MO_128,
+ ctx->mem_idx));
gen_helper_stq_be_parallel(cpu_env, EA, lo, hi, oi);
}
tcg_temp_free_i32(oi);
@@ -4066,11 +4068,11 @@ static void gen_lqarx(DisasContext *ctx)
if (HAVE_ATOMIC128) {
TCGv_i32 oi = tcg_temp_new_i32();
if (ctx->le_mode) {
- tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ | MO_ALIGN_16,
+ tcg_gen_movi_i32(oi, make_memop_idx(MO_LE | MO_128 | MO_ALIGN,
ctx->mem_idx));
gen_helper_lq_le_parallel(lo, cpu_env, EA, oi);
} else {
- tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ | MO_ALIGN_16,
+ tcg_gen_movi_i32(oi, make_memop_idx(MO_BE | MO_128 | MO_ALIGN,
ctx->mem_idx));
gen_helper_lq_be_parallel(lo, cpu_env, EA, oi);
}
@@ -4121,7 +4123,7 @@ static void gen_stqcx_(DisasContext *ctx)
if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
if (HAVE_CMPXCHG128) {
- TCGv_i32 oi = tcg_const_i32(DEF_MEMOP(MO_Q) | MO_ALIGN_16);
+ TCGv_i32 oi = tcg_const_i32(DEF_MEMOP(MO_128) | MO_ALIGN);
if (ctx->le_mode) {
gen_helper_stqcx_le_parallel(cpu_crf[0], cpu_env,
EA, lo, hi, oi);
--
2.25.1
^ permalink raw reply related [flat|nested] 102+ messages in thread* [PATCH for-6.2 30/43] target/s390x: Use MO_128 for 16 byte atomics
2021-07-29 0:46 [PATCH for-6.2 00/43] Unaligned accesses for user-only Richard Henderson
` (28 preceding siblings ...)
2021-07-29 0:46 ` [PATCH for-6.2 29/43] target/ppc: " Richard Henderson
@ 2021-07-29 0:46 ` Richard Henderson
2021-07-29 6:33 ` Philippe Mathieu-Daudé
2021-07-29 8:04 ` David Hildenbrand
2021-07-29 0:46 ` [PATCH for-6.2 31/43] target/hexagon: Implement cpu_mmu_index Richard Henderson
` (14 subsequent siblings)
44 siblings, 2 replies; 102+ messages in thread
From: Richard Henderson @ 2021-07-29 0:46 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-s390x
Cc: qemu-s390x@nongnu.org
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/s390x/tcg/mem_helper.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/s390x/tcg/mem_helper.c b/target/s390x/tcg/mem_helper.c
index ec88f5dbb0..3782c1c098 100644
--- a/target/s390x/tcg/mem_helper.c
+++ b/target/s390x/tcg/mem_helper.c
@@ -1810,7 +1810,7 @@ void HELPER(cdsg_parallel)(CPUS390XState *env, uint64_t addr,
assert(HAVE_CMPXCHG128);
mem_idx = cpu_mmu_index(env, false);
- oi = make_memop_idx(MO_TEQ | MO_ALIGN_16, mem_idx);
+ oi = make_memop_idx(MO_TE | MO_128 | MO_ALIGN, mem_idx);
oldv = cpu_atomic_cmpxchgo_be_mmu(env, addr, cmpv, newv, oi, ra);
fail = !int128_eq(oldv, cmpv);
@@ -1939,7 +1939,7 @@ static uint32_t do_csst(CPUS390XState *env, uint32_t r3, uint64_t a1,
cpu_stq_data_ra(env, a1 + 0, int128_gethi(nv), ra);
cpu_stq_data_ra(env, a1 + 8, int128_getlo(nv), ra);
} else if (HAVE_CMPXCHG128) {
- MemOpIdx oi = make_memop_idx(MO_TEQ | MO_ALIGN_16, mem_idx);
+ MemOpIdx oi = make_memop_idx(MO_TE | MO_128 | MO_ALIGN, mem_idx);
ov = cpu_atomic_cmpxchgo_be_mmu(env, a1, cv, nv, oi, ra);
cc = !int128_eq(ov, cv);
} else {
--
2.25.1
^ permalink raw reply related [flat|nested] 102+ messages in thread* Re: [PATCH for-6.2 30/43] target/s390x: Use MO_128 for 16 byte atomics
2021-07-29 0:46 ` [PATCH for-6.2 30/43] target/s390x: " Richard Henderson
@ 2021-07-29 6:33 ` Philippe Mathieu-Daudé
2021-07-29 8:04 ` David Hildenbrand
1 sibling, 0 replies; 102+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-07-29 6:33 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: qemu-s390x
On 7/29/21 2:46 AM, Richard Henderson wrote:
> Cc: qemu-s390x@nongnu.org
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/s390x/tcg/mem_helper.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
^ permalink raw reply [flat|nested] 102+ messages in thread
* Re: [PATCH for-6.2 30/43] target/s390x: Use MO_128 for 16 byte atomics
2021-07-29 0:46 ` [PATCH for-6.2 30/43] target/s390x: " Richard Henderson
2021-07-29 6:33 ` Philippe Mathieu-Daudé
@ 2021-07-29 8:04 ` David Hildenbrand
1 sibling, 0 replies; 102+ messages in thread
From: David Hildenbrand @ 2021-07-29 8:04 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: qemu-s390x
On 29.07.21 02:46, Richard Henderson wrote:
> Cc: qemu-s390x@nongnu.org
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/s390x/tcg/mem_helper.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/target/s390x/tcg/mem_helper.c b/target/s390x/tcg/mem_helper.c
> index ec88f5dbb0..3782c1c098 100644
> --- a/target/s390x/tcg/mem_helper.c
> +++ b/target/s390x/tcg/mem_helper.c
> @@ -1810,7 +1810,7 @@ void HELPER(cdsg_parallel)(CPUS390XState *env, uint64_t addr,
> assert(HAVE_CMPXCHG128);
>
> mem_idx = cpu_mmu_index(env, false);
> - oi = make_memop_idx(MO_TEQ | MO_ALIGN_16, mem_idx);
> + oi = make_memop_idx(MO_TE | MO_128 | MO_ALIGN, mem_idx);
> oldv = cpu_atomic_cmpxchgo_be_mmu(env, addr, cmpv, newv, oi, ra);
> fail = !int128_eq(oldv, cmpv);
>
> @@ -1939,7 +1939,7 @@ static uint32_t do_csst(CPUS390XState *env, uint32_t r3, uint64_t a1,
> cpu_stq_data_ra(env, a1 + 0, int128_gethi(nv), ra);
> cpu_stq_data_ra(env, a1 + 8, int128_getlo(nv), ra);
> } else if (HAVE_CMPXCHG128) {
> - MemOpIdx oi = make_memop_idx(MO_TEQ | MO_ALIGN_16, mem_idx);
> + MemOpIdx oi = make_memop_idx(MO_TE | MO_128 | MO_ALIGN, mem_idx);
> ov = cpu_atomic_cmpxchgo_be_mmu(env, a1, cv, nv, oi, ra);
> cc = !int128_eq(ov, cv);
> } else {
>
Reviewed-by: David Hildenbrand <david@redhat.com>
--
Thanks,
David / dhildenb
^ permalink raw reply [flat|nested] 102+ messages in thread
* [PATCH for-6.2 31/43] target/hexagon: Implement cpu_mmu_index
2021-07-29 0:46 [PATCH for-6.2 00/43] Unaligned accesses for user-only Richard Henderson
` (29 preceding siblings ...)
2021-07-29 0:46 ` [PATCH for-6.2 30/43] target/s390x: " Richard Henderson
@ 2021-07-29 0:46 ` Richard Henderson
2021-07-29 2:37 ` Taylor Simpson
2021-07-29 6:35 ` Philippe Mathieu-Daudé
2021-07-29 0:46 ` [PATCH for-6.2 32/43] accel/tcg: Add cpu_{ld,st}*_mmu interfaces Richard Henderson
` (13 subsequent siblings)
44 siblings, 2 replies; 102+ messages in thread
From: Richard Henderson @ 2021-07-29 0:46 UTC (permalink / raw)
To: qemu-devel; +Cc: Taylor Simpson
The function is trivial for user-only, but still must be present.
Cc: Taylor Simpson <tsimpson@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/hexagon/cpu.h | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h
index 2855dd3881..bde538fd5c 100644
--- a/target/hexagon/cpu.h
+++ b/target/hexagon/cpu.h
@@ -144,6 +144,15 @@ static inline void cpu_get_tb_cpu_state(CPUHexagonState *env, target_ulong *pc,
#endif
}
+static inline int cpu_mmu_index(CPUHexagonState *env, bool ifetch)
+{
+#ifdef CONFIG_USER_ONLY
+ return MMU_USER_IDX;
+#else
+#error System mode not supported on Hexagon yet
+#endif
+}
+
typedef struct CPUHexagonState CPUArchState;
typedef HexagonCPU ArchCPU;
--
2.25.1
^ permalink raw reply related [flat|nested] 102+ messages in thread* RE: [PATCH for-6.2 31/43] target/hexagon: Implement cpu_mmu_index
2021-07-29 0:46 ` [PATCH for-6.2 31/43] target/hexagon: Implement cpu_mmu_index Richard Henderson
@ 2021-07-29 2:37 ` Taylor Simpson
2021-07-29 6:35 ` Philippe Mathieu-Daudé
1 sibling, 0 replies; 102+ messages in thread
From: Taylor Simpson @ 2021-07-29 2:37 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
> -----Original Message-----
> From: Richard Henderson <richard.henderson@linaro.org>
> Sent: Wednesday, July 28, 2021 6:47 PM
> To: qemu-devel@nongnu.org
> Cc: Taylor Simpson <tsimpson@quicinc.com>
> Subject: [PATCH for-6.2 31/43] target/hexagon: Implement cpu_mmu_index
>
> The function is trivial for user-only, but still must be present.
>
> Cc: Taylor Simpson <tsimpson@quicinc.com>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/hexagon/cpu.h | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h index
> 2855dd3881..bde538fd5c 100644
> --- a/target/hexagon/cpu.h
> +++ b/target/hexagon/cpu.h
> @@ -144,6 +144,15 @@ static inline void
> cpu_get_tb_cpu_state(CPUHexagonState *env, target_ulong *pc, #endif }
>
> +static inline int cpu_mmu_index(CPUHexagonState *env, bool ifetch) {
> +#ifdef CONFIG_USER_ONLY
> + return MMU_USER_IDX;
> +#else
> +#error System mode not supported on Hexagon yet #endif }
> +
Reviewed-by: Taylor Simpson <tsimpson@quicinc.com>
^ permalink raw reply [flat|nested] 102+ messages in thread* Re: [PATCH for-6.2 31/43] target/hexagon: Implement cpu_mmu_index
2021-07-29 0:46 ` [PATCH for-6.2 31/43] target/hexagon: Implement cpu_mmu_index Richard Henderson
2021-07-29 2:37 ` Taylor Simpson
@ 2021-07-29 6:35 ` Philippe Mathieu-Daudé
1 sibling, 0 replies; 102+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-07-29 6:35 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: Taylor Simpson
On 7/29/21 2:46 AM, Richard Henderson wrote:
> The function is trivial for user-only, but still must be present.
>
> Cc: Taylor Simpson <tsimpson@quicinc.com>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/hexagon/cpu.h | 9 +++++++++
> 1 file changed, 9 insertions(+)
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
^ permalink raw reply [flat|nested] 102+ messages in thread
* [PATCH for-6.2 32/43] accel/tcg: Add cpu_{ld,st}*_mmu interfaces
2021-07-29 0:46 [PATCH for-6.2 00/43] Unaligned accesses for user-only Richard Henderson
` (30 preceding siblings ...)
2021-07-29 0:46 ` [PATCH for-6.2 31/43] target/hexagon: Implement cpu_mmu_index Richard Henderson
@ 2021-07-29 0:46 ` Richard Henderson
2021-07-29 0:46 ` [PATCH for-6.2 33/43] accel/tcg: Move cpu_atomic decls to exec/cpu_ldst.h Richard Henderson
` (12 subsequent siblings)
44 siblings, 0 replies; 102+ messages in thread
From: Richard Henderson @ 2021-07-29 0:46 UTC (permalink / raw)
To: qemu-devel
These functions are much closer to the softmmu helper
functions, in that they take the complete MemOpIdx,
and from that they may enforce required alignment.
The previous cpu_ldst.h functions did not have alignment info,
and so did not enforce it. Retain this by adding MO_UNALN to
the MemOp that we create in calling the new functions.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/exec/cpu_ldst.h | 245 ++++++++--------------
accel/tcg/cputlb.c | 392 ++++++++++++------------------------
accel/tcg/user-exec.c | 390 +++++++++++++++--------------------
accel/tcg/ldst_common.c.inc | 307 ++++++++++++++++++++++++++++
4 files changed, 679 insertions(+), 655 deletions(-)
create mode 100644 accel/tcg/ldst_common.c.inc
diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h
index ce6ce82618..a4dad0772f 100644
--- a/include/exec/cpu_ldst.h
+++ b/include/exec/cpu_ldst.h
@@ -28,10 +28,12 @@
* load: cpu_ld{sign}{size}{end}_{mmusuffix}(env, ptr)
* cpu_ld{sign}{size}{end}_{mmusuffix}_ra(env, ptr, retaddr)
* cpu_ld{sign}{size}{end}_mmuidx_ra(env, ptr, mmu_idx, retaddr)
+ * cpu_ld{sign}{size}{end}_mmu(env, ptr, oi, retaddr)
*
* store: cpu_st{size}{end}_{mmusuffix}(env, ptr, val)
* cpu_st{size}{end}_{mmusuffix}_ra(env, ptr, val, retaddr)
* cpu_st{size}{end}_mmuidx_ra(env, ptr, val, mmu_idx, retaddr)
+ * cpu_st{size}{end}_mmu(env, ptr, val, oi, retaddr)
*
* sign is:
* (empty): for 32 and 64 bit sizes
@@ -53,10 +55,15 @@
* The "mmuidx" suffix carries an extra mmu_idx argument that specifies
* the index to use; the "data" and "code" suffixes take the index from
* cpu_mmu_index().
+ *
+ * The "mmu" suffix carries the full MemOpIdx, with both mmu_idx and the
+ * MemOp including alignment requirements. The alignment will be enforced.
*/
#ifndef CPU_LDST_H
#define CPU_LDST_H
+#include "exec/memopidx.h"
+
#if defined(CONFIG_USER_ONLY)
/* sparc32plus has 64bit long but 32bit space address
* this can make bad result with g2h() and h2g()
@@ -118,12 +125,10 @@ typedef target_ulong abi_ptr;
uint32_t cpu_ldub_data(CPUArchState *env, abi_ptr ptr);
int cpu_ldsb_data(CPUArchState *env, abi_ptr ptr);
-
uint32_t cpu_lduw_be_data(CPUArchState *env, abi_ptr ptr);
int cpu_ldsw_be_data(CPUArchState *env, abi_ptr ptr);
uint32_t cpu_ldl_be_data(CPUArchState *env, abi_ptr ptr);
uint64_t cpu_ldq_be_data(CPUArchState *env, abi_ptr ptr);
-
uint32_t cpu_lduw_le_data(CPUArchState *env, abi_ptr ptr);
int cpu_ldsw_le_data(CPUArchState *env, abi_ptr ptr);
uint32_t cpu_ldl_le_data(CPUArchState *env, abi_ptr ptr);
@@ -131,37 +136,31 @@ uint64_t cpu_ldq_le_data(CPUArchState *env, abi_ptr ptr);
uint32_t cpu_ldub_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra);
int cpu_ldsb_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra);
-
uint32_t cpu_lduw_be_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra);
int cpu_ldsw_be_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra);
uint32_t cpu_ldl_be_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra);
uint64_t cpu_ldq_be_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra);
-
uint32_t cpu_lduw_le_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra);
int cpu_ldsw_le_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra);
uint32_t cpu_ldl_le_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra);
uint64_t cpu_ldq_le_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra);
void cpu_stb_data(CPUArchState *env, abi_ptr ptr, uint32_t val);
-
void cpu_stw_be_data(CPUArchState *env, abi_ptr ptr, uint32_t val);
void cpu_stl_be_data(CPUArchState *env, abi_ptr ptr, uint32_t val);
void cpu_stq_be_data(CPUArchState *env, abi_ptr ptr, uint64_t val);
-
void cpu_stw_le_data(CPUArchState *env, abi_ptr ptr, uint32_t val);
void cpu_stl_le_data(CPUArchState *env, abi_ptr ptr, uint32_t val);
void cpu_stq_le_data(CPUArchState *env, abi_ptr ptr, uint64_t val);
void cpu_stb_data_ra(CPUArchState *env, abi_ptr ptr,
uint32_t val, uintptr_t ra);
-
void cpu_stw_be_data_ra(CPUArchState *env, abi_ptr ptr,
uint32_t val, uintptr_t ra);
void cpu_stl_be_data_ra(CPUArchState *env, abi_ptr ptr,
uint32_t val, uintptr_t ra);
void cpu_stq_be_data_ra(CPUArchState *env, abi_ptr ptr,
uint64_t val, uintptr_t ra);
-
void cpu_stw_le_data_ra(CPUArchState *env, abi_ptr ptr,
uint32_t val, uintptr_t ra);
void cpu_stl_le_data_ra(CPUArchState *env, abi_ptr ptr,
@@ -169,6 +168,71 @@ void cpu_stl_le_data_ra(CPUArchState *env, abi_ptr ptr,
void cpu_stq_le_data_ra(CPUArchState *env, abi_ptr ptr,
uint64_t val, uintptr_t ra);
+uint32_t cpu_ldub_mmuidx_ra(CPUArchState *env, abi_ptr ptr,
+ int mmu_idx, uintptr_t ra);
+int cpu_ldsb_mmuidx_ra(CPUArchState *env, abi_ptr ptr,
+ int mmu_idx, uintptr_t ra);
+uint32_t cpu_lduw_be_mmuidx_ra(CPUArchState *env, abi_ptr ptr,
+ int mmu_idx, uintptr_t ra);
+int cpu_ldsw_be_mmuidx_ra(CPUArchState *env, abi_ptr ptr,
+ int mmu_idx, uintptr_t ra);
+uint32_t cpu_ldl_be_mmuidx_ra(CPUArchState *env, abi_ptr ptr,
+ int mmu_idx, uintptr_t ra);
+uint64_t cpu_ldq_be_mmuidx_ra(CPUArchState *env, abi_ptr ptr,
+ int mmu_idx, uintptr_t ra);
+uint32_t cpu_lduw_le_mmuidx_ra(CPUArchState *env, abi_ptr ptr,
+ int mmu_idx, uintptr_t ra);
+int cpu_ldsw_le_mmuidx_ra(CPUArchState *env, abi_ptr ptr,
+ int mmu_idx, uintptr_t ra);
+uint32_t cpu_ldl_le_mmuidx_ra(CPUArchState *env, abi_ptr ptr,
+ int mmu_idx, uintptr_t ra);
+uint64_t cpu_ldq_le_mmuidx_ra(CPUArchState *env, abi_ptr ptr,
+ int mmu_idx, uintptr_t ra);
+
+void cpu_stb_mmuidx_ra(CPUArchState *env, abi_ptr ptr, uint32_t val,
+ int mmu_idx, uintptr_t ra);
+void cpu_stw_be_mmuidx_ra(CPUArchState *env, abi_ptr ptr, uint32_t val,
+ int mmu_idx, uintptr_t ra);
+void cpu_stl_be_mmuidx_ra(CPUArchState *env, abi_ptr ptr, uint32_t val,
+ int mmu_idx, uintptr_t ra);
+void cpu_stq_be_mmuidx_ra(CPUArchState *env, abi_ptr ptr, uint64_t val,
+ int mmu_idx, uintptr_t ra);
+void cpu_stw_le_mmuidx_ra(CPUArchState *env, abi_ptr ptr, uint32_t val,
+ int mmu_idx, uintptr_t ra);
+void cpu_stl_le_mmuidx_ra(CPUArchState *env, abi_ptr ptr, uint32_t val,
+ int mmu_idx, uintptr_t ra);
+void cpu_stq_le_mmuidx_ra(CPUArchState *env, abi_ptr ptr, uint64_t val,
+ int mmu_idx, uintptr_t ra);
+
+uint8_t cpu_ldb_mmu(CPUArchState *env, abi_ptr ptr, MemOpIdx oi, uintptr_t ra);
+uint16_t cpu_ldw_be_mmu(CPUArchState *env, abi_ptr ptr,
+ MemOpIdx oi, uintptr_t ra);
+uint32_t cpu_ldl_be_mmu(CPUArchState *env, abi_ptr ptr,
+ MemOpIdx oi, uintptr_t ra);
+uint64_t cpu_ldq_be_mmu(CPUArchState *env, abi_ptr ptr,
+ MemOpIdx oi, uintptr_t ra);
+uint16_t cpu_ldw_le_mmu(CPUArchState *env, abi_ptr ptr,
+ MemOpIdx oi, uintptr_t ra);
+uint32_t cpu_ldl_le_mmu(CPUArchState *env, abi_ptr ptr,
+ MemOpIdx oi, uintptr_t ra);
+uint64_t cpu_ldq_le_mmu(CPUArchState *env, abi_ptr ptr,
+ MemOpIdx oi, uintptr_t ra);
+
+void cpu_stb_mmu(CPUArchState *env, abi_ptr ptr, uint8_t val,
+ MemOpIdx oi, uintptr_t ra);
+void cpu_stw_be_mmu(CPUArchState *env, abi_ptr ptr, uint16_t val,
+ MemOpIdx oi, uintptr_t ra);
+void cpu_stl_be_mmu(CPUArchState *env, abi_ptr ptr, uint32_t val,
+ MemOpIdx oi, uintptr_t ra);
+void cpu_stq_be_mmu(CPUArchState *env, abi_ptr ptr, uint64_t val,
+ MemOpIdx oi, uintptr_t ra);
+void cpu_stw_le_mmu(CPUArchState *env, abi_ptr ptr, uint16_t val,
+ MemOpIdx oi, uintptr_t ra);
+void cpu_stl_le_mmu(CPUArchState *env, abi_ptr ptr, uint32_t val,
+ MemOpIdx oi, uintptr_t ra);
+void cpu_stq_le_mmu(CPUArchState *env, abi_ptr ptr, uint64_t val,
+ MemOpIdx oi, uintptr_t ra);
+
#if defined(CONFIG_USER_ONLY)
extern __thread uintptr_t helper_retaddr;
@@ -193,119 +257,6 @@ static inline void clear_helper_retaddr(void)
helper_retaddr = 0;
}
-/*
- * Provide the same *_mmuidx_ra interface as for softmmu.
- * The mmu_idx argument is ignored.
- */
-
-static inline uint32_t cpu_ldub_mmuidx_ra(CPUArchState *env, abi_ptr addr,
- int mmu_idx, uintptr_t ra)
-{
- return cpu_ldub_data_ra(env, addr, ra);
-}
-
-static inline int cpu_ldsb_mmuidx_ra(CPUArchState *env, abi_ptr addr,
- int mmu_idx, uintptr_t ra)
-{
- return cpu_ldsb_data_ra(env, addr, ra);
-}
-
-static inline uint32_t cpu_lduw_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
- int mmu_idx, uintptr_t ra)
-{
- return cpu_lduw_be_data_ra(env, addr, ra);
-}
-
-static inline int cpu_ldsw_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
- int mmu_idx, uintptr_t ra)
-{
- return cpu_ldsw_be_data_ra(env, addr, ra);
-}
-
-static inline uint32_t cpu_ldl_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
- int mmu_idx, uintptr_t ra)
-{
- return cpu_ldl_be_data_ra(env, addr, ra);
-}
-
-static inline uint64_t cpu_ldq_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
- int mmu_idx, uintptr_t ra)
-{
- return cpu_ldq_be_data_ra(env, addr, ra);
-}
-
-static inline uint32_t cpu_lduw_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
- int mmu_idx, uintptr_t ra)
-{
- return cpu_lduw_le_data_ra(env, addr, ra);
-}
-
-static inline int cpu_ldsw_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
- int mmu_idx, uintptr_t ra)
-{
- return cpu_ldsw_le_data_ra(env, addr, ra);
-}
-
-static inline uint32_t cpu_ldl_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
- int mmu_idx, uintptr_t ra)
-{
- return cpu_ldl_le_data_ra(env, addr, ra);
-}
-
-static inline uint64_t cpu_ldq_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
- int mmu_idx, uintptr_t ra)
-{
- return cpu_ldq_le_data_ra(env, addr, ra);
-}
-
-static inline void cpu_stb_mmuidx_ra(CPUArchState *env, abi_ptr addr,
- uint32_t val, int mmu_idx, uintptr_t ra)
-{
- cpu_stb_data_ra(env, addr, val, ra);
-}
-
-static inline void cpu_stw_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
- uint32_t val, int mmu_idx,
- uintptr_t ra)
-{
- cpu_stw_be_data_ra(env, addr, val, ra);
-}
-
-static inline void cpu_stl_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
- uint32_t val, int mmu_idx,
- uintptr_t ra)
-{
- cpu_stl_be_data_ra(env, addr, val, ra);
-}
-
-static inline void cpu_stq_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
- uint64_t val, int mmu_idx,
- uintptr_t ra)
-{
- cpu_stq_be_data_ra(env, addr, val, ra);
-}
-
-static inline void cpu_stw_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
- uint32_t val, int mmu_idx,
- uintptr_t ra)
-{
- cpu_stw_le_data_ra(env, addr, val, ra);
-}
-
-static inline void cpu_stl_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
- uint32_t val, int mmu_idx,
- uintptr_t ra)
-{
- cpu_stl_le_data_ra(env, addr, val, ra);
-}
-
-static inline void cpu_stq_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
- uint64_t val, int mmu_idx,
- uintptr_t ra)
-{
- cpu_stq_le_data_ra(env, addr, val, ra);
-}
-
#else
/* Needed for TCG_OVERSIZED_GUEST */
@@ -336,46 +287,6 @@ static inline CPUTLBEntry *tlb_entry(CPUArchState *env, uintptr_t mmu_idx,
return &env_tlb(env)->f[mmu_idx].table[tlb_index(env, mmu_idx, addr)];
}
-uint32_t cpu_ldub_mmuidx_ra(CPUArchState *env, abi_ptr addr,
- int mmu_idx, uintptr_t ra);
-int cpu_ldsb_mmuidx_ra(CPUArchState *env, abi_ptr addr,
- int mmu_idx, uintptr_t ra);
-
-uint32_t cpu_lduw_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
- int mmu_idx, uintptr_t ra);
-int cpu_ldsw_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
- int mmu_idx, uintptr_t ra);
-uint32_t cpu_ldl_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
- int mmu_idx, uintptr_t ra);
-uint64_t cpu_ldq_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
- int mmu_idx, uintptr_t ra);
-
-uint32_t cpu_lduw_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
- int mmu_idx, uintptr_t ra);
-int cpu_ldsw_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
- int mmu_idx, uintptr_t ra);
-uint32_t cpu_ldl_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
- int mmu_idx, uintptr_t ra);
-uint64_t cpu_ldq_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
- int mmu_idx, uintptr_t ra);
-
-void cpu_stb_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint32_t val,
- int mmu_idx, uintptr_t retaddr);
-
-void cpu_stw_be_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint32_t val,
- int mmu_idx, uintptr_t retaddr);
-void cpu_stl_be_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint32_t val,
- int mmu_idx, uintptr_t retaddr);
-void cpu_stq_be_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint64_t val,
- int mmu_idx, uintptr_t retaddr);
-
-void cpu_stw_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint32_t val,
- int mmu_idx, uintptr_t retaddr);
-void cpu_stl_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint32_t val,
- int mmu_idx, uintptr_t retaddr);
-void cpu_stq_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint64_t val,
- int mmu_idx, uintptr_t retaddr);
-
#endif /* defined(CONFIG_USER_ONLY) */
#ifdef TARGET_WORDS_BIGENDIAN
@@ -391,6 +302,9 @@ void cpu_stq_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint64_t val,
# define cpu_ldsw_mmuidx_ra cpu_ldsw_be_mmuidx_ra
# define cpu_ldl_mmuidx_ra cpu_ldl_be_mmuidx_ra
# define cpu_ldq_mmuidx_ra cpu_ldq_be_mmuidx_ra
+# define cpu_ldw_mmu cpu_ldw_be_mmu
+# define cpu_ldl_mmu cpu_ldl_be_mmu
+# define cpu_ldq_mmu cpu_ldq_be_mmu
# define cpu_stw_data cpu_stw_be_data
# define cpu_stl_data cpu_stl_be_data
# define cpu_stq_data cpu_stq_be_data
@@ -400,6 +314,9 @@ void cpu_stq_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint64_t val,
# define cpu_stw_mmuidx_ra cpu_stw_be_mmuidx_ra
# define cpu_stl_mmuidx_ra cpu_stl_be_mmuidx_ra
# define cpu_stq_mmuidx_ra cpu_stq_be_mmuidx_ra
+# define cpu_stw_mmu cpu_stw_be_mmu
+# define cpu_stl_mmu cpu_stl_be_mmu
+# define cpu_stq_mmu cpu_stq_be_mmu
#else
# define cpu_lduw_data cpu_lduw_le_data
# define cpu_ldsw_data cpu_ldsw_le_data
@@ -413,6 +330,9 @@ void cpu_stq_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint64_t val,
# define cpu_ldsw_mmuidx_ra cpu_ldsw_le_mmuidx_ra
# define cpu_ldl_mmuidx_ra cpu_ldl_le_mmuidx_ra
# define cpu_ldq_mmuidx_ra cpu_ldq_le_mmuidx_ra
+# define cpu_ldw_mmu cpu_ldw_le_mmu
+# define cpu_ldl_mmu cpu_ldl_le_mmu
+# define cpu_ldq_mmu cpu_ldq_le_mmu
# define cpu_stw_data cpu_stw_le_data
# define cpu_stl_data cpu_stl_le_data
# define cpu_stq_data cpu_stq_le_data
@@ -422,6 +342,9 @@ void cpu_stq_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint64_t val,
# define cpu_stw_mmuidx_ra cpu_stw_le_mmuidx_ra
# define cpu_stl_mmuidx_ra cpu_stl_le_mmuidx_ra
# define cpu_stq_mmuidx_ra cpu_stq_le_mmuidx_ra
+# define cpu_stw_mmu cpu_stw_le_mmu
+# define cpu_stl_mmu cpu_stl_le_mmu
+# define cpu_stq_mmu cpu_stq_le_mmu
#endif
uint32_t cpu_ldub_code(CPUArchState *env, abi_ptr addr);
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index 46140ccff3..b350cafa3d 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -1839,6 +1839,25 @@ static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr,
cpu_loop_exit_atomic(env_cpu(env), retaddr);
}
+/*
+ * Verify that we have passed the correct MemOp to the correct function.
+ *
+ * In the case of the helper_*_mmu functions, we will have done this by
+ * using the MemOp to look up the helper during code generation.
+ *
+ * In the case of the cpu_*_mmu functions, this is up to the caller.
+ * We could present one function to target code, and dispatch based on
+ * the MemOp, but so far we have worked hard to avoid an indirect function
+ * call along the memory path.
+ */
+static void validate_memop(MemOpIdx oi, MemOp expected)
+{
+#ifdef CONFIG_DEBUG_TCG
+ MemOp have = get_memop(oi) & (MO_SIZE | MO_BSWAP);
+ assert(have == expected);
+#endif
+}
+
/*
* Load Helpers
*
@@ -1992,6 +2011,7 @@ load_helper(CPUArchState *env, target_ulong addr, MemOpIdx oi,
static uint64_t full_ldub_mmu(CPUArchState *env, target_ulong addr,
MemOpIdx oi, uintptr_t retaddr)
{
+ validate_memop(oi, MO_UB);
return load_helper(env, addr, oi, retaddr, MO_UB, false, full_ldub_mmu);
}
@@ -2004,6 +2024,7 @@ tcg_target_ulong helper_ret_ldub_mmu(CPUArchState *env, target_ulong addr,
static uint64_t full_le_lduw_mmu(CPUArchState *env, target_ulong addr,
MemOpIdx oi, uintptr_t retaddr)
{
+ validate_memop(oi, MO_LEUW);
return load_helper(env, addr, oi, retaddr, MO_LEUW, false,
full_le_lduw_mmu);
}
@@ -2017,6 +2038,7 @@ tcg_target_ulong helper_le_lduw_mmu(CPUArchState *env, target_ulong addr,
static uint64_t full_be_lduw_mmu(CPUArchState *env, target_ulong addr,
MemOpIdx oi, uintptr_t retaddr)
{
+ validate_memop(oi, MO_BEUW);
return load_helper(env, addr, oi, retaddr, MO_BEUW, false,
full_be_lduw_mmu);
}
@@ -2030,6 +2052,7 @@ tcg_target_ulong helper_be_lduw_mmu(CPUArchState *env, target_ulong addr,
static uint64_t full_le_ldul_mmu(CPUArchState *env, target_ulong addr,
MemOpIdx oi, uintptr_t retaddr)
{
+ validate_memop(oi, MO_LEUL);
return load_helper(env, addr, oi, retaddr, MO_LEUL, false,
full_le_ldul_mmu);
}
@@ -2043,6 +2066,7 @@ tcg_target_ulong helper_le_ldul_mmu(CPUArchState *env, target_ulong addr,
static uint64_t full_be_ldul_mmu(CPUArchState *env, target_ulong addr,
MemOpIdx oi, uintptr_t retaddr)
{
+ validate_memop(oi, MO_BEUL);
return load_helper(env, addr, oi, retaddr, MO_BEUL, false,
full_be_ldul_mmu);
}
@@ -2056,6 +2080,7 @@ tcg_target_ulong helper_be_ldul_mmu(CPUArchState *env, target_ulong addr,
uint64_t helper_le_ldq_mmu(CPUArchState *env, target_ulong addr,
MemOpIdx oi, uintptr_t retaddr)
{
+ validate_memop(oi, MO_LEQ);
return load_helper(env, addr, oi, retaddr, MO_LEQ, false,
helper_le_ldq_mmu);
}
@@ -2063,6 +2088,7 @@ uint64_t helper_le_ldq_mmu(CPUArchState *env, target_ulong addr,
uint64_t helper_be_ldq_mmu(CPUArchState *env, target_ulong addr,
MemOpIdx oi, uintptr_t retaddr)
{
+ validate_memop(oi, MO_BEQ);
return load_helper(env, addr, oi, retaddr, MO_BEQ, false,
helper_be_ldq_mmu);
}
@@ -2108,186 +2134,56 @@ tcg_target_ulong helper_be_ldsl_mmu(CPUArchState *env, target_ulong addr,
*/
static inline uint64_t cpu_load_helper(CPUArchState *env, abi_ptr addr,
- int mmu_idx, uintptr_t retaddr,
- MemOp op, FullLoadHelper *full_load)
+ MemOpIdx oi, uintptr_t retaddr,
+ FullLoadHelper *full_load)
{
- MemOpIdx oi = make_memop_idx(op, mmu_idx);
uint64_t ret;
trace_guest_ld_before_exec(env_cpu(env), addr, oi);
-
ret = full_load(env, addr, oi, retaddr);
-
qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_R);
-
return ret;
}
-uint32_t cpu_ldub_mmuidx_ra(CPUArchState *env, abi_ptr addr,
- int mmu_idx, uintptr_t ra)
+uint8_t cpu_ldb_mmu(CPUArchState *env, abi_ptr addr, MemOpIdx oi, uintptr_t ra)
{
- return cpu_load_helper(env, addr, mmu_idx, ra, MO_UB, full_ldub_mmu);
+ return cpu_load_helper(env, addr, oi, ra, full_ldub_mmu);
}
-int cpu_ldsb_mmuidx_ra(CPUArchState *env, abi_ptr addr,
- int mmu_idx, uintptr_t ra)
+uint16_t cpu_ldw_be_mmu(CPUArchState *env, abi_ptr addr,
+ MemOpIdx oi, uintptr_t ra)
{
- return (int8_t)cpu_ldub_mmuidx_ra(env, addr, mmu_idx, ra);
+ return cpu_load_helper(env, addr, oi, ra, full_be_lduw_mmu);
}
-uint32_t cpu_lduw_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
- int mmu_idx, uintptr_t ra)
+uint32_t cpu_ldl_be_mmu(CPUArchState *env, abi_ptr addr,
+ MemOpIdx oi, uintptr_t ra)
{
- return cpu_load_helper(env, addr, mmu_idx, ra, MO_BEUW, full_be_lduw_mmu);
+ return cpu_load_helper(env, addr, oi, ra, full_be_ldul_mmu);
}
-int cpu_ldsw_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
- int mmu_idx, uintptr_t ra)
+uint64_t cpu_ldq_be_mmu(CPUArchState *env, abi_ptr addr,
+ MemOpIdx oi, uintptr_t ra)
{
- return (int16_t)cpu_lduw_be_mmuidx_ra(env, addr, mmu_idx, ra);
+ return cpu_load_helper(env, addr, oi, MO_BEQ, helper_be_ldq_mmu);
}
-uint32_t cpu_ldl_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
- int mmu_idx, uintptr_t ra)
+uint16_t cpu_ldw_le_mmu(CPUArchState *env, abi_ptr addr,
+ MemOpIdx oi, uintptr_t ra)
{
- return cpu_load_helper(env, addr, mmu_idx, ra, MO_BEUL, full_be_ldul_mmu);
+ return cpu_load_helper(env, addr, oi, ra, full_le_lduw_mmu);
}
-uint64_t cpu_ldq_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
- int mmu_idx, uintptr_t ra)
+uint32_t cpu_ldl_le_mmu(CPUArchState *env, abi_ptr addr,
+ MemOpIdx oi, uintptr_t ra)
{
- return cpu_load_helper(env, addr, mmu_idx, ra, MO_BEQ, helper_be_ldq_mmu);
+ return cpu_load_helper(env, addr, oi, ra, full_le_ldul_mmu);
}
-uint32_t cpu_lduw_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
- int mmu_idx, uintptr_t ra)
+uint64_t cpu_ldq_le_mmu(CPUArchState *env, abi_ptr addr,
+ MemOpIdx oi, uintptr_t ra)
{
- return cpu_load_helper(env, addr, mmu_idx, ra, MO_LEUW, full_le_lduw_mmu);
-}
-
-int cpu_ldsw_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
- int mmu_idx, uintptr_t ra)
-{
- return (int16_t)cpu_lduw_le_mmuidx_ra(env, addr, mmu_idx, ra);
-}
-
-uint32_t cpu_ldl_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
- int mmu_idx, uintptr_t ra)
-{
- return cpu_load_helper(env, addr, mmu_idx, ra, MO_LEUL, full_le_ldul_mmu);
-}
-
-uint64_t cpu_ldq_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
- int mmu_idx, uintptr_t ra)
-{
- return cpu_load_helper(env, addr, mmu_idx, ra, MO_LEQ, helper_le_ldq_mmu);
-}
-
-uint32_t cpu_ldub_data_ra(CPUArchState *env, target_ulong ptr,
- uintptr_t retaddr)
-{
- return cpu_ldub_mmuidx_ra(env, ptr, cpu_mmu_index(env, false), retaddr);
-}
-
-int cpu_ldsb_data_ra(CPUArchState *env, target_ulong ptr, uintptr_t retaddr)
-{
- return cpu_ldsb_mmuidx_ra(env, ptr, cpu_mmu_index(env, false), retaddr);
-}
-
-uint32_t cpu_lduw_be_data_ra(CPUArchState *env, target_ulong ptr,
- uintptr_t retaddr)
-{
- return cpu_lduw_be_mmuidx_ra(env, ptr, cpu_mmu_index(env, false), retaddr);
-}
-
-int cpu_ldsw_be_data_ra(CPUArchState *env, target_ulong ptr, uintptr_t retaddr)
-{
- return cpu_ldsw_be_mmuidx_ra(env, ptr, cpu_mmu_index(env, false), retaddr);
-}
-
-uint32_t cpu_ldl_be_data_ra(CPUArchState *env, target_ulong ptr,
- uintptr_t retaddr)
-{
- return cpu_ldl_be_mmuidx_ra(env, ptr, cpu_mmu_index(env, false), retaddr);
-}
-
-uint64_t cpu_ldq_be_data_ra(CPUArchState *env, target_ulong ptr,
- uintptr_t retaddr)
-{
- return cpu_ldq_be_mmuidx_ra(env, ptr, cpu_mmu_index(env, false), retaddr);
-}
-
-uint32_t cpu_lduw_le_data_ra(CPUArchState *env, target_ulong ptr,
- uintptr_t retaddr)
-{
- return cpu_lduw_le_mmuidx_ra(env, ptr, cpu_mmu_index(env, false), retaddr);
-}
-
-int cpu_ldsw_le_data_ra(CPUArchState *env, target_ulong ptr, uintptr_t retaddr)
-{
- return cpu_ldsw_le_mmuidx_ra(env, ptr, cpu_mmu_index(env, false), retaddr);
-}
-
-uint32_t cpu_ldl_le_data_ra(CPUArchState *env, target_ulong ptr,
- uintptr_t retaddr)
-{
- return cpu_ldl_le_mmuidx_ra(env, ptr, cpu_mmu_index(env, false), retaddr);
-}
-
-uint64_t cpu_ldq_le_data_ra(CPUArchState *env, target_ulong ptr,
- uintptr_t retaddr)
-{
- return cpu_ldq_le_mmuidx_ra(env, ptr, cpu_mmu_index(env, false), retaddr);
-}
-
-uint32_t cpu_ldub_data(CPUArchState *env, target_ulong ptr)
-{
- return cpu_ldub_data_ra(env, ptr, 0);
-}
-
-int cpu_ldsb_data(CPUArchState *env, target_ulong ptr)
-{
- return cpu_ldsb_data_ra(env, ptr, 0);
-}
-
-uint32_t cpu_lduw_be_data(CPUArchState *env, target_ulong ptr)
-{
- return cpu_lduw_be_data_ra(env, ptr, 0);
-}
-
-int cpu_ldsw_be_data(CPUArchState *env, target_ulong ptr)
-{
- return cpu_ldsw_be_data_ra(env, ptr, 0);
-}
-
-uint32_t cpu_ldl_be_data(CPUArchState *env, target_ulong ptr)
-{
- return cpu_ldl_be_data_ra(env, ptr, 0);
-}
-
-uint64_t cpu_ldq_be_data(CPUArchState *env, target_ulong ptr)
-{
- return cpu_ldq_be_data_ra(env, ptr, 0);
-}
-
-uint32_t cpu_lduw_le_data(CPUArchState *env, target_ulong ptr)
-{
- return cpu_lduw_le_data_ra(env, ptr, 0);
-}
-
-int cpu_ldsw_le_data(CPUArchState *env, target_ulong ptr)
-{
- return cpu_ldsw_le_data_ra(env, ptr, 0);
-}
-
-uint32_t cpu_ldl_le_data(CPUArchState *env, target_ulong ptr)
-{
- return cpu_ldl_le_data_ra(env, ptr, 0);
-}
-
-uint64_t cpu_ldq_le_data(CPUArchState *env, target_ulong ptr)
-{
- return cpu_ldq_le_data_ra(env, ptr, 0);
+ return cpu_load_helper(env, addr, oi, ra, helper_le_ldq_mmu);
}
/*
@@ -2324,6 +2220,9 @@ store_memop(void *haddr, uint64_t val, MemOp op)
}
}
+static void full_stb_mmu(CPUArchState *env, target_ulong addr, uint64_t val,
+ MemOpIdx oi, uintptr_t retaddr);
+
static void __attribute__((noinline))
store_helper_unaligned(CPUArchState *env, target_ulong addr, uint64_t val,
uintptr_t retaddr, size_t size, uintptr_t mmu_idx,
@@ -2387,13 +2286,13 @@ store_helper_unaligned(CPUArchState *env, target_ulong addr, uint64_t val,
for (i = 0; i < size; ++i) {
/* Big-endian extract. */
uint8_t val8 = val >> (((size - 1) * 8) - (i * 8));
- helper_ret_stb_mmu(env, addr + i, val8, oi, retaddr);
+ full_stb_mmu(env, addr + i, val8, oi, retaddr);
}
} else {
for (i = 0; i < size; ++i) {
/* Little-endian extract. */
uint8_t val8 = val >> (i * 8);
- helper_ret_stb_mmu(env, addr + i, val8, oi, retaddr);
+ full_stb_mmu(env, addr + i, val8, oi, retaddr);
}
}
}
@@ -2496,46 +2395,83 @@ store_helper(CPUArchState *env, target_ulong addr, uint64_t val,
store_memop(haddr, val, op);
}
-void __attribute__((noinline))
-helper_ret_stb_mmu(CPUArchState *env, target_ulong addr, uint8_t val,
- MemOpIdx oi, uintptr_t retaddr)
+static void __attribute__((noinline))
+full_stb_mmu(CPUArchState *env, target_ulong addr, uint64_t val,
+ MemOpIdx oi, uintptr_t retaddr)
{
+ validate_memop(oi, MO_UB);
store_helper(env, addr, val, oi, retaddr, MO_UB);
}
+void helper_ret_stb_mmu(CPUArchState *env, target_ulong addr, uint8_t val,
+ MemOpIdx oi, uintptr_t retaddr)
+{
+ full_stb_mmu(env, addr, val, oi, retaddr);
+}
+
+static void full_le_stw_mmu(CPUArchState *env, target_ulong addr, uint64_t val,
+ MemOpIdx oi, uintptr_t retaddr)
+{
+ validate_memop(oi, MO_LEUW);
+ store_helper(env, addr, val, oi, retaddr, MO_LEUW);
+}
+
void helper_le_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val,
MemOpIdx oi, uintptr_t retaddr)
{
- store_helper(env, addr, val, oi, retaddr, MO_LEUW);
+ full_le_stw_mmu(env, addr, val, oi, retaddr);
+}
+
+static void full_be_stw_mmu(CPUArchState *env, target_ulong addr, uint64_t val,
+ MemOpIdx oi, uintptr_t retaddr)
+{
+ validate_memop(oi, MO_BEUW);
+ store_helper(env, addr, val, oi, retaddr, MO_BEUW);
}
void helper_be_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val,
MemOpIdx oi, uintptr_t retaddr)
{
- store_helper(env, addr, val, oi, retaddr, MO_BEUW);
+ full_be_stw_mmu(env, addr, val, oi, retaddr);
+}
+
+static void full_le_stl_mmu(CPUArchState *env, target_ulong addr, uint64_t val,
+ MemOpIdx oi, uintptr_t retaddr)
+{
+ validate_memop(oi, MO_LEUL);
+ store_helper(env, addr, val, oi, retaddr, MO_LEUL);
}
void helper_le_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val,
MemOpIdx oi, uintptr_t retaddr)
{
- store_helper(env, addr, val, oi, retaddr, MO_LEUL);
+ full_le_stl_mmu(env, addr, val, oi, retaddr);
+}
+
+static void full_be_stl_mmu(CPUArchState *env, target_ulong addr, uint64_t val,
+ MemOpIdx oi, uintptr_t retaddr)
+{
+ validate_memop(oi, MO_BEUL);
+ store_helper(env, addr, val, oi, retaddr, MO_BEUL);
}
void helper_be_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val,
MemOpIdx oi, uintptr_t retaddr)
{
- store_helper(env, addr, val, oi, retaddr, MO_BEUL);
+ full_be_stl_mmu(env, addr, val, oi, retaddr);
}
void helper_le_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val,
MemOpIdx oi, uintptr_t retaddr)
{
+ validate_memop(oi, MO_LEQ);
store_helper(env, addr, val, oi, retaddr, MO_LEQ);
}
void helper_be_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val,
MemOpIdx oi, uintptr_t retaddr)
{
+ validate_memop(oi, MO_BEQ);
store_helper(env, addr, val, oi, retaddr, MO_BEQ);
}
@@ -2543,137 +2479,61 @@ void helper_be_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val,
* Store Helpers for cpu_ldst.h
*/
-static inline void QEMU_ALWAYS_INLINE
-cpu_store_helper(CPUArchState *env, target_ulong addr, uint64_t val,
- int mmu_idx, uintptr_t retaddr, MemOp op)
+typedef void FullStoreHelper(CPUArchState *env, target_ulong addr,
+ uint64_t val, MemOpIdx oi, uintptr_t retaddr);
+
+static inline void cpu_store_helper(CPUArchState *env, target_ulong addr,
+ uint64_t val, MemOpIdx oi, uintptr_t ra,
+ FullStoreHelper *full_store)
{
- MemOpIdx oi = make_memop_idx(op, mmu_idx);
-
trace_guest_st_before_exec(env_cpu(env), addr, oi);
-
- store_helper(env, addr, val, oi, retaddr, op);
-
+ full_store(env, addr, val, oi, ra);
qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_W);
}
-void cpu_stb_mmuidx_ra(CPUArchState *env, target_ulong addr, uint32_t val,
- int mmu_idx, uintptr_t retaddr)
+void cpu_stb_mmu(CPUArchState *env, target_ulong addr, uint8_t val,
+ MemOpIdx oi, uintptr_t retaddr)
{
- cpu_store_helper(env, addr, val, mmu_idx, retaddr, MO_UB);
+ cpu_store_helper(env, addr, val, oi, retaddr, full_stb_mmu);
}
-void cpu_stw_be_mmuidx_ra(CPUArchState *env, target_ulong addr, uint32_t val,
- int mmu_idx, uintptr_t retaddr)
+void cpu_stw_be_mmu(CPUArchState *env, target_ulong addr, uint16_t val,
+ MemOpIdx oi, uintptr_t retaddr)
{
- cpu_store_helper(env, addr, val, mmu_idx, retaddr, MO_BEUW);
+ cpu_store_helper(env, addr, val, oi, retaddr, full_be_stw_mmu);
}
-void cpu_stl_be_mmuidx_ra(CPUArchState *env, target_ulong addr, uint32_t val,
- int mmu_idx, uintptr_t retaddr)
+void cpu_stl_be_mmu(CPUArchState *env, target_ulong addr, uint32_t val,
+ MemOpIdx oi, uintptr_t retaddr)
{
- cpu_store_helper(env, addr, val, mmu_idx, retaddr, MO_BEUL);
+ cpu_store_helper(env, addr, val, oi, retaddr, full_be_stl_mmu);
}
-void cpu_stq_be_mmuidx_ra(CPUArchState *env, target_ulong addr, uint64_t val,
- int mmu_idx, uintptr_t retaddr)
+void cpu_stq_be_mmu(CPUArchState *env, target_ulong addr, uint64_t val,
+ MemOpIdx oi, uintptr_t retaddr)
{
- cpu_store_helper(env, addr, val, mmu_idx, retaddr, MO_BEQ);
+ cpu_store_helper(env, addr, val, oi, retaddr, helper_be_stq_mmu);
}
-void cpu_stw_le_mmuidx_ra(CPUArchState *env, target_ulong addr, uint32_t val,
- int mmu_idx, uintptr_t retaddr)
+void cpu_stw_le_mmu(CPUArchState *env, target_ulong addr, uint16_t val,
+ MemOpIdx oi, uintptr_t retaddr)
{
- cpu_store_helper(env, addr, val, mmu_idx, retaddr, MO_LEUW);
+ cpu_store_helper(env, addr, val, oi, retaddr, full_le_stw_mmu);
}
-void cpu_stl_le_mmuidx_ra(CPUArchState *env, target_ulong addr, uint32_t val,
- int mmu_idx, uintptr_t retaddr)
+void cpu_stl_le_mmu(CPUArchState *env, target_ulong addr, uint32_t val,
+ MemOpIdx oi, uintptr_t retaddr)
{
- cpu_store_helper(env, addr, val, mmu_idx, retaddr, MO_LEUL);
+ cpu_store_helper(env, addr, val, oi, retaddr, full_le_stl_mmu);
}
-void cpu_stq_le_mmuidx_ra(CPUArchState *env, target_ulong addr, uint64_t val,
- int mmu_idx, uintptr_t retaddr)
+void cpu_stq_le_mmu(CPUArchState *env, target_ulong addr, uint64_t val,
+ MemOpIdx oi, uintptr_t retaddr)
{
- cpu_store_helper(env, addr, val, mmu_idx, retaddr, MO_LEQ);
+ cpu_store_helper(env, addr, val, oi, retaddr, helper_le_stq_mmu);
}
-void cpu_stb_data_ra(CPUArchState *env, target_ulong ptr,
- uint32_t val, uintptr_t retaddr)
-{
- cpu_stb_mmuidx_ra(env, ptr, val, cpu_mmu_index(env, false), retaddr);
-}
-
-void cpu_stw_be_data_ra(CPUArchState *env, target_ulong ptr,
- uint32_t val, uintptr_t retaddr)
-{
- cpu_stw_be_mmuidx_ra(env, ptr, val, cpu_mmu_index(env, false), retaddr);
-}
-
-void cpu_stl_be_data_ra(CPUArchState *env, target_ulong ptr,
- uint32_t val, uintptr_t retaddr)
-{
- cpu_stl_be_mmuidx_ra(env, ptr, val, cpu_mmu_index(env, false), retaddr);
-}
-
-void cpu_stq_be_data_ra(CPUArchState *env, target_ulong ptr,
- uint64_t val, uintptr_t retaddr)
-{
- cpu_stq_be_mmuidx_ra(env, ptr, val, cpu_mmu_index(env, false), retaddr);
-}
-
-void cpu_stw_le_data_ra(CPUArchState *env, target_ulong ptr,
- uint32_t val, uintptr_t retaddr)
-{
- cpu_stw_le_mmuidx_ra(env, ptr, val, cpu_mmu_index(env, false), retaddr);
-}
-
-void cpu_stl_le_data_ra(CPUArchState *env, target_ulong ptr,
- uint32_t val, uintptr_t retaddr)
-{
- cpu_stl_le_mmuidx_ra(env, ptr, val, cpu_mmu_index(env, false), retaddr);
-}
-
-void cpu_stq_le_data_ra(CPUArchState *env, target_ulong ptr,
- uint64_t val, uintptr_t retaddr)
-{
- cpu_stq_le_mmuidx_ra(env, ptr, val, cpu_mmu_index(env, false), retaddr);
-}
-
-void cpu_stb_data(CPUArchState *env, target_ulong ptr, uint32_t val)
-{
- cpu_stb_data_ra(env, ptr, val, 0);
-}
-
-void cpu_stw_be_data(CPUArchState *env, target_ulong ptr, uint32_t val)
-{
- cpu_stw_be_data_ra(env, ptr, val, 0);
-}
-
-void cpu_stl_be_data(CPUArchState *env, target_ulong ptr, uint32_t val)
-{
- cpu_stl_be_data_ra(env, ptr, val, 0);
-}
-
-void cpu_stq_be_data(CPUArchState *env, target_ulong ptr, uint64_t val)
-{
- cpu_stq_be_data_ra(env, ptr, val, 0);
-}
-
-void cpu_stw_le_data(CPUArchState *env, target_ulong ptr, uint32_t val)
-{
- cpu_stw_le_data_ra(env, ptr, val, 0);
-}
-
-void cpu_stl_le_data(CPUArchState *env, target_ulong ptr, uint32_t val)
-{
- cpu_stl_le_data_ra(env, ptr, val, 0);
-}
-
-void cpu_stq_le_data(CPUArchState *env, target_ulong ptr, uint64_t val)
-{
- cpu_stq_le_data_ra(env, ptr, val, 0);
-}
+#include "ldst_common.c.inc"
/*
* First set of functions passes in OI and RETADDR.
diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
index eda577013f..e8a82dd43f 100644
--- a/accel/tcg/user-exec.c
+++ b/accel/tcg/user-exec.c
@@ -851,6 +851,21 @@ int cpu_signal_handler(int host_signum, void *pinfo,
/* The softmmu versions of these helpers are in cputlb.c. */
+/*
+ * Verify that we have passed the correct MemOp to the correct function.
+ *
+ * We could present one function to target code, and dispatch based on
+ * the MemOp, but so far we have worked hard to avoid an indirect function
+ * call along the memory path.
+ */
+static void validate_memop(MemOpIdx oi, MemOp expected)
+{
+#ifdef CONFIG_DEBUG_TCG
+ MemOp have = get_memop(oi) & (MO_SIZE | MO_BSWAP);
+ assert(have == expected);
+#endif
+}
+
static void cpu_unaligned_access(CPUState *cpu, vaddr addr,
MMUAccessType access_type,
int mmu_idx, uintptr_t ra)
@@ -861,300 +876,217 @@ static void cpu_unaligned_access(CPUState *cpu, vaddr addr,
g_assert_not_reached();
}
-uint32_t cpu_ldub_data(CPUArchState *env, abi_ptr ptr)
+static void *cpu_mmu_lookup(CPUArchState *env, target_ulong addr,
+ MemOpIdx oi, uintptr_t ra, MMUAccessType type)
{
- MemOpIdx oi = make_memop_idx(MO_UB, MMU_USER_IDX);
- uint32_t ret;
+ MemOp mop = get_memop(oi);
+ int a_bits = get_alignment_bits(mop);
+ void *ret;
- trace_guest_ld_before_exec(env_cpu(env), ptr, oi);
- ret = ldub_p(g2h(env_cpu(env), ptr));
- qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_R);
+ /* Enforce guest required alignment. */
+ if (unlikely(addr & ((1 << a_bits) - 1))) {
+ cpu_unaligned_access(env_cpu(env), addr, type, get_mmuidx(oi), ra);
+ }
+
+ ret = g2h(env_cpu(env), addr);
+ set_helper_retaddr(ra);
return ret;
}
-int cpu_ldsb_data(CPUArchState *env, abi_ptr ptr)
+uint8_t cpu_ldb_mmu(CPUArchState *env, abi_ptr addr,
+ MemOpIdx oi, uintptr_t ra)
{
- return (int8_t)cpu_ldub_data(env, ptr);
-}
+ void *haddr;
+ uint8_t ret;
-uint32_t cpu_lduw_be_data(CPUArchState *env, abi_ptr ptr)
-{
- MemOpIdx oi = make_memop_idx(MO_BEUW, MMU_USER_IDX);
- uint32_t ret;
-
- trace_guest_ld_before_exec(env_cpu(env), ptr, oi);
- ret = lduw_be_p(g2h(env_cpu(env), ptr));
- qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_R);
+ validate_memop(oi, MO_UB);
+ trace_guest_ld_before_exec(env_cpu(env), addr, oi);
+ haddr = cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_LOAD);
+ ret = ldub_p(haddr);
+ clear_helper_retaddr();
+ qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_R);
return ret;
}
-int cpu_ldsw_be_data(CPUArchState *env, abi_ptr ptr)
+uint16_t cpu_ldw_be_mmu(CPUArchState *env, abi_ptr addr,
+ MemOpIdx oi, uintptr_t ra)
{
- return (int16_t)cpu_lduw_be_data(env, ptr);
-}
+ void *haddr;
+ uint16_t ret;
-uint32_t cpu_ldl_be_data(CPUArchState *env, abi_ptr ptr)
-{
- MemOpIdx oi = make_memop_idx(MO_BEUL, MMU_USER_IDX);
- uint32_t ret;
-
- trace_guest_ld_before_exec(env_cpu(env), ptr, oi);
- ret = ldl_be_p(g2h(env_cpu(env), ptr));
- qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_R);
+ validate_memop(oi, MO_BEUW);
+ trace_guest_ld_before_exec(env_cpu(env), addr, oi);
+ haddr = cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_LOAD);
+ ret = lduw_be_p(haddr);
+ clear_helper_retaddr();
+ qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_R);
return ret;
}
-uint64_t cpu_ldq_be_data(CPUArchState *env, abi_ptr ptr)
+uint32_t cpu_ldl_be_mmu(CPUArchState *env, abi_ptr addr,
+ MemOpIdx oi, uintptr_t ra)
{
- MemOpIdx oi = make_memop_idx(MO_BEQ, MMU_USER_IDX);
+ void *haddr;
+ uint32_t ret;
+
+ validate_memop(oi, MO_BEUL);
+ trace_guest_ld_before_exec(env_cpu(env), addr, oi);
+ haddr = cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_LOAD);
+ ret = ldl_be_p(haddr);
+ clear_helper_retaddr();
+ qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_R);
+ return ret;
+}
+
+uint64_t cpu_ldq_be_mmu(CPUArchState *env, abi_ptr addr,
+ MemOpIdx oi, uintptr_t ra)
+{
+ void *haddr;
uint64_t ret;
- trace_guest_ld_before_exec(env_cpu(env), ptr, oi);
- ret = ldq_be_p(g2h(env_cpu(env), ptr));
- qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_R);
+ validate_memop(oi, MO_BEQ);
+ trace_guest_ld_before_exec(env_cpu(env), addr, oi);
+ haddr = cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_LOAD);
+ ret = ldq_be_p(haddr);
+ clear_helper_retaddr();
+ qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_R);
return ret;
}
-uint32_t cpu_lduw_le_data(CPUArchState *env, abi_ptr ptr)
+uint16_t cpu_ldw_le_mmu(CPUArchState *env, abi_ptr addr,
+ MemOpIdx oi, uintptr_t ra)
{
- MemOpIdx oi = make_memop_idx(MO_LEUW, MMU_USER_IDX);
+ void *haddr;
+ uint16_t ret;
+
+ validate_memop(oi, MO_LEUW);
+ trace_guest_ld_before_exec(env_cpu(env), addr, oi);
+ haddr = cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_LOAD);
+ ret = lduw_le_p(haddr);
+ clear_helper_retaddr();
+ qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_R);
+ return ret;
+}
+
+uint32_t cpu_ldl_le_mmu(CPUArchState *env, abi_ptr addr,
+ MemOpIdx oi, uintptr_t ra)
+{
+ void *haddr;
uint32_t ret;
- trace_guest_ld_before_exec(env_cpu(env), ptr, oi);
- ret = lduw_le_p(g2h(env_cpu(env), ptr));
- qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_R);
+ validate_memop(oi, MO_LEUL);
+ trace_guest_ld_before_exec(env_cpu(env), addr, oi);
+ haddr = cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_LOAD);
+ ret = ldl_le_p(haddr);
+ clear_helper_retaddr();
+ qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_R);
return ret;
}
-int cpu_ldsw_le_data(CPUArchState *env, abi_ptr ptr)
+uint64_t cpu_ldq_le_mmu(CPUArchState *env, abi_ptr addr,
+ MemOpIdx oi, uintptr_t ra)
{
- return (int16_t)cpu_lduw_le_data(env, ptr);
-}
-
-uint32_t cpu_ldl_le_data(CPUArchState *env, abi_ptr ptr)
-{
- MemOpIdx oi = make_memop_idx(MO_LEUL, MMU_USER_IDX);
- uint32_t ret;
-
- trace_guest_ld_before_exec(env_cpu(env), ptr, oi);
- ret = ldl_le_p(g2h(env_cpu(env), ptr));
- qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_R);
- return ret;
-}
-
-uint64_t cpu_ldq_le_data(CPUArchState *env, abi_ptr ptr)
-{
- MemOpIdx oi = make_memop_idx(MO_LEQ, MMU_USER_IDX);
+ void *haddr;
uint64_t ret;
- trace_guest_ld_before_exec(env_cpu(env), ptr, oi);
- ret = ldq_le_p(g2h(env_cpu(env), ptr));
- qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_R);
+ validate_memop(oi, MO_LEQ);
+ trace_guest_ld_before_exec(env_cpu(env), addr, oi);
+ haddr = cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_LOAD);
+ ret = ldq_le_p(haddr);
+ clear_helper_retaddr();
+ qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_R);
return ret;
}
-uint32_t cpu_ldub_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr)
+void cpu_stb_mmu(CPUArchState *env, abi_ptr addr, uint8_t val,
+ MemOpIdx oi, uintptr_t ra)
{
- uint32_t ret;
+ void *haddr;
- set_helper_retaddr(retaddr);
- ret = cpu_ldub_data(env, ptr);
+ validate_memop(oi, MO_UB);
+ trace_guest_st_before_exec(env_cpu(env), addr, oi);
+ haddr = cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_STORE);
+ stb_p(haddr, val);
clear_helper_retaddr();
- return ret;
+ qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_W);
}
-int cpu_ldsb_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr)
+void cpu_stw_be_mmu(CPUArchState *env, abi_ptr addr, uint16_t val,
+ MemOpIdx oi, uintptr_t ra)
{
- return (int8_t)cpu_ldub_data_ra(env, ptr, retaddr);
-}
+ void *haddr;
-uint32_t cpu_lduw_be_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr)
-{
- uint32_t ret;
-
- set_helper_retaddr(retaddr);
- ret = cpu_lduw_be_data(env, ptr);
+ validate_memop(oi, MO_BEUW);
+ trace_guest_st_before_exec(env_cpu(env), addr, oi);
+ haddr = cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_STORE);
+ stw_be_p(haddr, val);
clear_helper_retaddr();
- return ret;
+ qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_W);
}
-int cpu_ldsw_be_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr)
+void cpu_stl_be_mmu(CPUArchState *env, abi_ptr addr, uint32_t val,
+ MemOpIdx oi, uintptr_t ra)
{
- return (int16_t)cpu_lduw_be_data_ra(env, ptr, retaddr);
-}
+ void *haddr;
-uint32_t cpu_ldl_be_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr)
-{
- uint32_t ret;
-
- set_helper_retaddr(retaddr);
- ret = cpu_ldl_be_data(env, ptr);
+ validate_memop(oi, MO_BEUL);
+ trace_guest_st_before_exec(env_cpu(env), addr, oi);
+ haddr = cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_STORE);
+ stl_be_p(haddr, val);
clear_helper_retaddr();
- return ret;
+ qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_W);
}
-uint64_t cpu_ldq_be_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr)
+void cpu_stq_be_mmu(CPUArchState *env, abi_ptr addr, uint64_t val,
+ MemOpIdx oi, uintptr_t ra)
{
- uint64_t ret;
+ void *haddr;
- set_helper_retaddr(retaddr);
- ret = cpu_ldq_be_data(env, ptr);
+ validate_memop(oi, MO_BEQ);
+ trace_guest_st_before_exec(env_cpu(env), addr, oi);
+ haddr = cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_STORE);
+ stq_be_p(haddr, val);
clear_helper_retaddr();
- return ret;
+ qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_W);
}
-uint32_t cpu_lduw_le_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr)
+void cpu_stw_le_mmu(CPUArchState *env, abi_ptr addr, uint16_t val,
+ MemOpIdx oi, uintptr_t ra)
{
- uint32_t ret;
+ void *haddr;
- set_helper_retaddr(retaddr);
- ret = cpu_lduw_le_data(env, ptr);
+ validate_memop(oi, MO_LEUW);
+ trace_guest_st_before_exec(env_cpu(env), addr, oi);
+ haddr = cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_STORE);
+ stw_le_p(haddr, val);
clear_helper_retaddr();
- return ret;
+ qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_W);
}
-int cpu_ldsw_le_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr)
+void cpu_stl_le_mmu(CPUArchState *env, abi_ptr addr, uint32_t val,
+ MemOpIdx oi, uintptr_t ra)
{
- return (int16_t)cpu_lduw_le_data_ra(env, ptr, retaddr);
-}
+ void *haddr;
-uint32_t cpu_ldl_le_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr)
-{
- uint32_t ret;
-
- set_helper_retaddr(retaddr);
- ret = cpu_ldl_le_data(env, ptr);
+ validate_memop(oi, MO_LEUL);
+ trace_guest_st_before_exec(env_cpu(env), addr, oi);
+ haddr = cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_STORE);
+ stl_le_p(haddr, val);
clear_helper_retaddr();
- return ret;
+ qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_W);
}
-uint64_t cpu_ldq_le_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr)
+void cpu_stq_le_mmu(CPUArchState *env, abi_ptr addr, uint64_t val,
+ MemOpIdx oi, uintptr_t ra)
{
- uint64_t ret;
+ void *haddr;
- set_helper_retaddr(retaddr);
- ret = cpu_ldq_le_data(env, ptr);
- clear_helper_retaddr();
- return ret;
-}
-
-void cpu_stb_data(CPUArchState *env, abi_ptr ptr, uint32_t val)
-{
- MemOpIdx oi = make_memop_idx(MO_UB, MMU_USER_IDX);
-
- trace_guest_st_before_exec(env_cpu(env), ptr, oi);
- stb_p(g2h(env_cpu(env), ptr), val);
- qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_W);
-}
-
-void cpu_stw_be_data(CPUArchState *env, abi_ptr ptr, uint32_t val)
-{
- MemOpIdx oi = make_memop_idx(MO_BEUW, MMU_USER_IDX);
-
- trace_guest_st_before_exec(env_cpu(env), ptr, oi);
- stw_be_p(g2h(env_cpu(env), ptr), val);
- qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_W);
-}
-
-void cpu_stl_be_data(CPUArchState *env, abi_ptr ptr, uint32_t val)
-{
- MemOpIdx oi = make_memop_idx(MO_BEUL, MMU_USER_IDX);
-
- trace_guest_st_before_exec(env_cpu(env), ptr, oi);
- stl_be_p(g2h(env_cpu(env), ptr), val);
- qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_W);
-}
-
-void cpu_stq_be_data(CPUArchState *env, abi_ptr ptr, uint64_t val)
-{
- MemOpIdx oi = make_memop_idx(MO_BEQ, MMU_USER_IDX);
-
- trace_guest_st_before_exec(env_cpu(env), ptr, oi);
- stq_be_p(g2h(env_cpu(env), ptr), val);
- qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_W);
-}
-
-void cpu_stw_le_data(CPUArchState *env, abi_ptr ptr, uint32_t val)
-{
- MemOpIdx oi = make_memop_idx(MO_LEUW, MMU_USER_IDX);
-
- trace_guest_st_before_exec(env_cpu(env), ptr, oi);
- stw_le_p(g2h(env_cpu(env), ptr), val);
- qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_W);
-}
-
-void cpu_stl_le_data(CPUArchState *env, abi_ptr ptr, uint32_t val)
-{
- MemOpIdx oi = make_memop_idx(MO_LEUL, MMU_USER_IDX);
-
- trace_guest_st_before_exec(env_cpu(env), ptr, oi);
- stl_le_p(g2h(env_cpu(env), ptr), val);
- qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_W);
-}
-
-void cpu_stq_le_data(CPUArchState *env, abi_ptr ptr, uint64_t val)
-{
- MemOpIdx oi = make_memop_idx(MO_LEQ, MMU_USER_IDX);
-
- trace_guest_st_before_exec(env_cpu(env), ptr, oi);
- stq_le_p(g2h(env_cpu(env), ptr), val);
- qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_W);
-}
-
-void cpu_stb_data_ra(CPUArchState *env, abi_ptr ptr,
- uint32_t val, uintptr_t retaddr)
-{
- set_helper_retaddr(retaddr);
- cpu_stb_data(env, ptr, val);
- clear_helper_retaddr();
-}
-
-void cpu_stw_be_data_ra(CPUArchState *env, abi_ptr ptr,
- uint32_t val, uintptr_t retaddr)
-{
- set_helper_retaddr(retaddr);
- cpu_stw_be_data(env, ptr, val);
- clear_helper_retaddr();
-}
-
-void cpu_stl_be_data_ra(CPUArchState *env, abi_ptr ptr,
- uint32_t val, uintptr_t retaddr)
-{
- set_helper_retaddr(retaddr);
- cpu_stl_be_data(env, ptr, val);
- clear_helper_retaddr();
-}
-
-void cpu_stq_be_data_ra(CPUArchState *env, abi_ptr ptr,
- uint64_t val, uintptr_t retaddr)
-{
- set_helper_retaddr(retaddr);
- cpu_stq_be_data(env, ptr, val);
- clear_helper_retaddr();
-}
-
-void cpu_stw_le_data_ra(CPUArchState *env, abi_ptr ptr,
- uint32_t val, uintptr_t retaddr)
-{
- set_helper_retaddr(retaddr);
- cpu_stw_le_data(env, ptr, val);
- clear_helper_retaddr();
-}
-
-void cpu_stl_le_data_ra(CPUArchState *env, abi_ptr ptr,
- uint32_t val, uintptr_t retaddr)
-{
- set_helper_retaddr(retaddr);
- cpu_stl_le_data(env, ptr, val);
- clear_helper_retaddr();
-}
-
-void cpu_stq_le_data_ra(CPUArchState *env, abi_ptr ptr,
- uint64_t val, uintptr_t retaddr)
-{
- set_helper_retaddr(retaddr);
- cpu_stq_le_data(env, ptr, val);
+ validate_memop(oi, MO_LEQ);
+ trace_guest_st_before_exec(env_cpu(env), addr, oi);
+ haddr = cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_STORE);
+ stq_le_p(haddr, val);
clear_helper_retaddr();
+ qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_W);
}
uint32_t cpu_ldub_code(CPUArchState *env, abi_ptr ptr)
@@ -1197,6 +1129,8 @@ uint64_t cpu_ldq_code(CPUArchState *env, abi_ptr ptr)
return ret;
}
+#include "ldst_common.c.inc"
+
/*
* Do not allow unaligned operations to proceed. Return the host address.
*
diff --git a/accel/tcg/ldst_common.c.inc b/accel/tcg/ldst_common.c.inc
new file mode 100644
index 0000000000..bfefb275e7
--- /dev/null
+++ b/accel/tcg/ldst_common.c.inc
@@ -0,0 +1,307 @@
+/*
+ * Routines common to user and system emulation of load/store.
+ *
+ * Copyright (c) 2003 Fabrice Bellard
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+uint32_t cpu_ldub_mmuidx_ra(CPUArchState *env, abi_ptr addr,
+ int mmu_idx, uintptr_t ra)
+{
+ MemOpIdx oi = make_memop_idx(MO_UB, mmu_idx);
+ return cpu_ldb_mmu(env, addr, oi, ra);
+}
+
+int cpu_ldsb_mmuidx_ra(CPUArchState *env, abi_ptr addr,
+ int mmu_idx, uintptr_t ra)
+{
+ return (int8_t)cpu_ldub_mmuidx_ra(env, addr, mmu_idx, ra);
+}
+
+uint32_t cpu_lduw_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
+ int mmu_idx, uintptr_t ra)
+{
+ MemOpIdx oi = make_memop_idx(MO_BEUW | MO_UNALN, mmu_idx);
+ return cpu_ldw_be_mmu(env, addr, oi, ra);
+}
+
+int cpu_ldsw_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
+ int mmu_idx, uintptr_t ra)
+{
+ return (int16_t)cpu_lduw_be_mmuidx_ra(env, addr, mmu_idx, ra);
+}
+
+uint32_t cpu_ldl_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
+ int mmu_idx, uintptr_t ra)
+{
+ MemOpIdx oi = make_memop_idx(MO_BEUL | MO_UNALN, mmu_idx);
+ return cpu_ldl_be_mmu(env, addr, oi, ra);
+}
+
+uint64_t cpu_ldq_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
+ int mmu_idx, uintptr_t ra)
+{
+ MemOpIdx oi = make_memop_idx(MO_BEQ | MO_UNALN, mmu_idx);
+ return cpu_ldq_be_mmu(env, addr, oi, ra);
+}
+
+uint32_t cpu_lduw_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
+ int mmu_idx, uintptr_t ra)
+{
+ MemOpIdx oi = make_memop_idx(MO_LEUW | MO_UNALN, mmu_idx);
+ return cpu_ldw_le_mmu(env, addr, oi, ra);
+}
+
+int cpu_ldsw_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
+ int mmu_idx, uintptr_t ra)
+{
+ return (int16_t)cpu_lduw_le_mmuidx_ra(env, addr, mmu_idx, ra);
+}
+
+uint32_t cpu_ldl_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
+ int mmu_idx, uintptr_t ra)
+{
+ MemOpIdx oi = make_memop_idx(MO_LEUL | MO_UNALN, mmu_idx);
+ return cpu_ldl_le_mmu(env, addr, oi, ra);
+}
+
+uint64_t cpu_ldq_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
+ int mmu_idx, uintptr_t ra)
+{
+ MemOpIdx oi = make_memop_idx(MO_LEQ | MO_UNALN, mmu_idx);
+ return cpu_ldq_le_mmu(env, addr, oi, ra);
+}
+
+void cpu_stb_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint32_t val,
+ int mmu_idx, uintptr_t ra)
+{
+ MemOpIdx oi = make_memop_idx(MO_UB, mmu_idx);
+ cpu_stb_mmu(env, addr, val, oi, ra);
+}
+
+void cpu_stw_be_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint32_t val,
+ int mmu_idx, uintptr_t ra)
+{
+ MemOpIdx oi = make_memop_idx(MO_BEUW | MO_UNALN, mmu_idx);
+ cpu_stw_be_mmu(env, addr, val, oi, ra);
+}
+
+void cpu_stl_be_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint32_t val,
+ int mmu_idx, uintptr_t ra)
+{
+ MemOpIdx oi = make_memop_idx(MO_BEUL | MO_UNALN, mmu_idx);
+ cpu_stl_be_mmu(env, addr, val, oi, ra);
+}
+
+void cpu_stq_be_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint64_t val,
+ int mmu_idx, uintptr_t ra)
+{
+ MemOpIdx oi = make_memop_idx(MO_BEQ | MO_UNALN, mmu_idx);
+ cpu_stq_be_mmu(env, addr, val, oi, ra);
+}
+
+void cpu_stw_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint32_t val,
+ int mmu_idx, uintptr_t ra)
+{
+ MemOpIdx oi = make_memop_idx(MO_LEUW | MO_UNALN, mmu_idx);
+ cpu_stw_le_mmu(env, addr, val, oi, ra);
+}
+
+void cpu_stl_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint32_t val,
+ int mmu_idx, uintptr_t ra)
+{
+ MemOpIdx oi = make_memop_idx(MO_LEUL | MO_UNALN, mmu_idx);
+ cpu_stl_le_mmu(env, addr, val, oi, ra);
+}
+
+void cpu_stq_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint64_t val,
+ int mmu_idx, uintptr_t ra)
+{
+ MemOpIdx oi = make_memop_idx(MO_LEQ | MO_UNALN, mmu_idx);
+ cpu_stq_le_mmu(env, addr, val, oi, ra);
+}
+
+/*--------------------------*/
+
+uint32_t cpu_ldub_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra)
+{
+ return cpu_ldub_mmuidx_ra(env, addr, cpu_mmu_index(env, false), ra);
+}
+
+int cpu_ldsb_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra)
+{
+ return (int8_t)cpu_ldub_data_ra(env, addr, ra);
+}
+
+uint32_t cpu_lduw_be_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra)
+{
+ return cpu_lduw_be_mmuidx_ra(env, addr, cpu_mmu_index(env, false), ra);
+}
+
+int cpu_ldsw_be_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra)
+{
+ return (int16_t)cpu_lduw_be_data_ra(env, addr, ra);
+}
+
+uint32_t cpu_ldl_be_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra)
+{
+ return cpu_ldl_be_mmuidx_ra(env, addr, cpu_mmu_index(env, false), ra);
+}
+
+uint64_t cpu_ldq_be_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra)
+{
+ return cpu_ldq_be_mmuidx_ra(env, addr, cpu_mmu_index(env, false), ra);
+}
+
+uint32_t cpu_lduw_le_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra)
+{
+ return cpu_lduw_le_mmuidx_ra(env, addr, cpu_mmu_index(env, false), ra);
+}
+
+int cpu_ldsw_le_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra)
+{
+ return (int16_t)cpu_lduw_le_data_ra(env, addr, ra);
+}
+
+uint32_t cpu_ldl_le_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra)
+{
+ return cpu_ldl_le_mmuidx_ra(env, addr, cpu_mmu_index(env, false), ra);
+}
+
+uint64_t cpu_ldq_le_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra)
+{
+ return cpu_ldq_le_mmuidx_ra(env, addr, cpu_mmu_index(env, false), ra);
+}
+
+void cpu_stb_data_ra(CPUArchState *env, abi_ptr addr,
+ uint32_t val, uintptr_t ra)
+{
+ cpu_stb_mmuidx_ra(env, addr, val, cpu_mmu_index(env, false), ra);
+}
+
+void cpu_stw_be_data_ra(CPUArchState *env, abi_ptr addr,
+ uint32_t val, uintptr_t ra)
+{
+ cpu_stw_be_mmuidx_ra(env, addr, val, cpu_mmu_index(env, false), ra);
+}
+
+void cpu_stl_be_data_ra(CPUArchState *env, abi_ptr addr,
+ uint32_t val, uintptr_t ra)
+{
+ cpu_stl_be_mmuidx_ra(env, addr, val, cpu_mmu_index(env, false), ra);
+}
+
+void cpu_stq_be_data_ra(CPUArchState *env, abi_ptr addr,
+ uint64_t val, uintptr_t ra)
+{
+ cpu_stq_be_mmuidx_ra(env, addr, val, cpu_mmu_index(env, false), ra);
+}
+
+void cpu_stw_le_data_ra(CPUArchState *env, abi_ptr addr,
+ uint32_t val, uintptr_t ra)
+{
+ cpu_stw_le_mmuidx_ra(env, addr, val, cpu_mmu_index(env, false), ra);
+}
+
+void cpu_stl_le_data_ra(CPUArchState *env, abi_ptr addr,
+ uint32_t val, uintptr_t ra)
+{
+ cpu_stl_le_mmuidx_ra(env, addr, val, cpu_mmu_index(env, false), ra);
+}
+
+void cpu_stq_le_data_ra(CPUArchState *env, abi_ptr addr,
+ uint64_t val, uintptr_t ra)
+{
+ cpu_stq_le_mmuidx_ra(env, addr, val, cpu_mmu_index(env, false), ra);
+}
+
+/*--------------------------*/
+
+uint32_t cpu_ldub_data(CPUArchState *env, abi_ptr addr)
+{
+ return cpu_ldub_data_ra(env, addr, 0);
+}
+
+int cpu_ldsb_data(CPUArchState *env, abi_ptr addr)
+{
+ return (int8_t)cpu_ldub_data(env, addr);
+}
+
+uint32_t cpu_lduw_be_data(CPUArchState *env, abi_ptr addr)
+{
+ return cpu_lduw_be_data_ra(env, addr, 0);
+}
+
+int cpu_ldsw_be_data(CPUArchState *env, abi_ptr addr)
+{
+ return (int16_t)cpu_lduw_be_data(env, addr);
+}
+
+uint32_t cpu_ldl_be_data(CPUArchState *env, abi_ptr addr)
+{
+ return cpu_ldl_be_data_ra(env, addr, 0);
+}
+
+uint64_t cpu_ldq_be_data(CPUArchState *env, abi_ptr addr)
+{
+ return cpu_ldq_be_data_ra(env, addr, 0);
+}
+
+uint32_t cpu_lduw_le_data(CPUArchState *env, abi_ptr addr)
+{
+ return cpu_lduw_le_data_ra(env, addr, 0);
+}
+
+int cpu_ldsw_le_data(CPUArchState *env, abi_ptr addr)
+{
+ return (int16_t)cpu_lduw_le_data(env, addr);
+}
+
+uint32_t cpu_ldl_le_data(CPUArchState *env, abi_ptr addr)
+{
+ return cpu_ldl_le_data_ra(env, addr, 0);
+}
+
+uint64_t cpu_ldq_le_data(CPUArchState *env, abi_ptr addr)
+{
+ return cpu_ldq_le_data_ra(env, addr, 0);
+}
+
+void cpu_stb_data(CPUArchState *env, abi_ptr addr, uint32_t val)
+{
+ cpu_stb_data_ra(env, addr, val, 0);
+}
+
+void cpu_stw_be_data(CPUArchState *env, abi_ptr addr, uint32_t val)
+{
+ cpu_stw_be_data_ra(env, addr, val, 0);
+}
+
+void cpu_stl_be_data(CPUArchState *env, abi_ptr addr, uint32_t val)
+{
+ cpu_stl_be_data_ra(env, addr, val, 0);
+}
+
+void cpu_stq_be_data(CPUArchState *env, abi_ptr addr, uint64_t val)
+{
+ cpu_stq_be_data_ra(env, addr, val, 0);
+}
+
+void cpu_stw_le_data(CPUArchState *env, abi_ptr addr, uint32_t val)
+{
+ cpu_stw_le_data_ra(env, addr, val, 0);
+}
+
+void cpu_stl_le_data(CPUArchState *env, abi_ptr addr, uint32_t val)
+{
+ cpu_stl_le_data_ra(env, addr, val, 0);
+}
+
+void cpu_stq_le_data(CPUArchState *env, abi_ptr addr, uint64_t val)
+{
+ cpu_stq_le_data_ra(env, addr, val, 0);
+}
--
2.25.1
^ permalink raw reply related [flat|nested] 102+ messages in thread* [PATCH for-6.2 33/43] accel/tcg: Move cpu_atomic decls to exec/cpu_ldst.h
2021-07-29 0:46 [PATCH for-6.2 00/43] Unaligned accesses for user-only Richard Henderson
` (31 preceding siblings ...)
2021-07-29 0:46 ` [PATCH for-6.2 32/43] accel/tcg: Add cpu_{ld,st}*_mmu interfaces Richard Henderson
@ 2021-07-29 0:46 ` Richard Henderson
2021-07-29 7:36 ` Philippe Mathieu-Daudé
2021-07-29 0:46 ` [PATCH for-6.2 34/43] target/mips: Use cpu_*_data_ra for msa load/store Richard Henderson
` (11 subsequent siblings)
44 siblings, 1 reply; 102+ messages in thread
From: Richard Henderson @ 2021-07-29 0:46 UTC (permalink / raw)
To: qemu-devel
The previous placement in tcg/tcg.h was not logical.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/exec/cpu_ldst.h | 87 +++++++++++++++++++++++++++++++++++
include/tcg/tcg.h | 87 -----------------------------------
target/arm/helper-a64.c | 1 -
target/m68k/op_helper.c | 1 -
target/ppc/mem_helper.c | 1 -
target/s390x/tcg/mem_helper.c | 1 -
6 files changed, 87 insertions(+), 91 deletions(-)
diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h
index a4dad0772f..a878fd0105 100644
--- a/include/exec/cpu_ldst.h
+++ b/include/exec/cpu_ldst.h
@@ -63,6 +63,7 @@
#define CPU_LDST_H
#include "exec/memopidx.h"
+#include "qemu/int128.h"
#if defined(CONFIG_USER_ONLY)
/* sparc32plus has 64bit long but 32bit space address
@@ -233,6 +234,92 @@ void cpu_stl_le_mmu(CPUArchState *env, abi_ptr ptr, uint32_t val,
void cpu_stq_le_mmu(CPUArchState *env, abi_ptr ptr, uint64_t val,
MemOpIdx oi, uintptr_t ra);
+uint32_t cpu_atomic_cmpxchgb_mmu(CPUArchState *env, target_ulong addr,
+ uint32_t cmpv, uint32_t newv,
+ MemOpIdx oi, uintptr_t retaddr);
+uint32_t cpu_atomic_cmpxchgw_le_mmu(CPUArchState *env, target_ulong addr,
+ uint32_t cmpv, uint32_t newv,
+ MemOpIdx oi, uintptr_t retaddr);
+uint32_t cpu_atomic_cmpxchgl_le_mmu(CPUArchState *env, target_ulong addr,
+ uint32_t cmpv, uint32_t newv,
+ MemOpIdx oi, uintptr_t retaddr);
+uint64_t cpu_atomic_cmpxchgq_le_mmu(CPUArchState *env, target_ulong addr,
+ uint64_t cmpv, uint64_t newv,
+ MemOpIdx oi, uintptr_t retaddr);
+uint32_t cpu_atomic_cmpxchgw_be_mmu(CPUArchState *env, target_ulong addr,
+ uint32_t cmpv, uint32_t newv,
+ MemOpIdx oi, uintptr_t retaddr);
+uint32_t cpu_atomic_cmpxchgl_be_mmu(CPUArchState *env, target_ulong addr,
+ uint32_t cmpv, uint32_t newv,
+ MemOpIdx oi, uintptr_t retaddr);
+uint64_t cpu_atomic_cmpxchgq_be_mmu(CPUArchState *env, target_ulong addr,
+ uint64_t cmpv, uint64_t newv,
+ MemOpIdx oi, uintptr_t retaddr);
+
+#define GEN_ATOMIC_HELPER(NAME, TYPE, SUFFIX) \
+TYPE cpu_atomic_ ## NAME ## SUFFIX ## _mmu \
+ (CPUArchState *env, target_ulong addr, TYPE val, \
+ MemOpIdx oi, uintptr_t retaddr);
+
+#ifdef CONFIG_ATOMIC64
+#define GEN_ATOMIC_HELPER_ALL(NAME) \
+ GEN_ATOMIC_HELPER(NAME, uint32_t, b) \
+ GEN_ATOMIC_HELPER(NAME, uint32_t, w_le) \
+ GEN_ATOMIC_HELPER(NAME, uint32_t, w_be) \
+ GEN_ATOMIC_HELPER(NAME, uint32_t, l_le) \
+ GEN_ATOMIC_HELPER(NAME, uint32_t, l_be) \
+ GEN_ATOMIC_HELPER(NAME, uint64_t, q_le) \
+ GEN_ATOMIC_HELPER(NAME, uint64_t, q_be)
+#else
+#define GEN_ATOMIC_HELPER_ALL(NAME) \
+ GEN_ATOMIC_HELPER(NAME, uint32_t, b) \
+ GEN_ATOMIC_HELPER(NAME, uint32_t, w_le) \
+ GEN_ATOMIC_HELPER(NAME, uint32_t, w_be) \
+ GEN_ATOMIC_HELPER(NAME, uint32_t, l_le) \
+ GEN_ATOMIC_HELPER(NAME, uint32_t, l_be)
+#endif
+
+GEN_ATOMIC_HELPER_ALL(fetch_add)
+GEN_ATOMIC_HELPER_ALL(fetch_sub)
+GEN_ATOMIC_HELPER_ALL(fetch_and)
+GEN_ATOMIC_HELPER_ALL(fetch_or)
+GEN_ATOMIC_HELPER_ALL(fetch_xor)
+GEN_ATOMIC_HELPER_ALL(fetch_smin)
+GEN_ATOMIC_HELPER_ALL(fetch_umin)
+GEN_ATOMIC_HELPER_ALL(fetch_smax)
+GEN_ATOMIC_HELPER_ALL(fetch_umax)
+
+GEN_ATOMIC_HELPER_ALL(add_fetch)
+GEN_ATOMIC_HELPER_ALL(sub_fetch)
+GEN_ATOMIC_HELPER_ALL(and_fetch)
+GEN_ATOMIC_HELPER_ALL(or_fetch)
+GEN_ATOMIC_HELPER_ALL(xor_fetch)
+GEN_ATOMIC_HELPER_ALL(smin_fetch)
+GEN_ATOMIC_HELPER_ALL(umin_fetch)
+GEN_ATOMIC_HELPER_ALL(smax_fetch)
+GEN_ATOMIC_HELPER_ALL(umax_fetch)
+
+GEN_ATOMIC_HELPER_ALL(xchg)
+
+#undef GEN_ATOMIC_HELPER_ALL
+#undef GEN_ATOMIC_HELPER
+
+Int128 cpu_atomic_cmpxchgo_le_mmu(CPUArchState *env, target_ulong addr,
+ Int128 cmpv, Int128 newv,
+ MemOpIdx oi, uintptr_t retaddr);
+Int128 cpu_atomic_cmpxchgo_be_mmu(CPUArchState *env, target_ulong addr,
+ Int128 cmpv, Int128 newv,
+ MemOpIdx oi, uintptr_t retaddr);
+
+Int128 cpu_atomic_ldo_le_mmu(CPUArchState *env, target_ulong addr,
+ MemOpIdx oi, uintptr_t retaddr);
+Int128 cpu_atomic_ldo_be_mmu(CPUArchState *env, target_ulong addr,
+ MemOpIdx oi, uintptr_t retaddr);
+void cpu_atomic_sto_le_mmu(CPUArchState *env, target_ulong addr, Int128 val,
+ MemOpIdx oi, uintptr_t retaddr);
+void cpu_atomic_sto_be_mmu(CPUArchState *env, target_ulong addr, Int128 val,
+ MemOpIdx oi, uintptr_t retaddr);
+
#if defined(CONFIG_USER_ONLY)
extern __thread uintptr_t helper_retaddr;
diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h
index e67ef34694..114ad66b25 100644
--- a/include/tcg/tcg.h
+++ b/include/tcg/tcg.h
@@ -33,7 +33,6 @@
#include "qemu/queue.h"
#include "tcg/tcg-mo.h"
#include "tcg-target.h"
-#include "qemu/int128.h"
#include "tcg/tcg-cond.h"
/* XXX: make safe guess about sizes */
@@ -1306,92 +1305,6 @@ void helper_be_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val,
#endif
#endif /* CONFIG_SOFTMMU */
-uint32_t cpu_atomic_cmpxchgb_mmu(CPUArchState *env, target_ulong addr,
- uint32_t cmpv, uint32_t newv,
- MemOpIdx oi, uintptr_t retaddr);
-uint32_t cpu_atomic_cmpxchgw_le_mmu(CPUArchState *env, target_ulong addr,
- uint32_t cmpv, uint32_t newv,
- MemOpIdx oi, uintptr_t retaddr);
-uint32_t cpu_atomic_cmpxchgl_le_mmu(CPUArchState *env, target_ulong addr,
- uint32_t cmpv, uint32_t newv,
- MemOpIdx oi, uintptr_t retaddr);
-uint64_t cpu_atomic_cmpxchgq_le_mmu(CPUArchState *env, target_ulong addr,
- uint64_t cmpv, uint64_t newv,
- MemOpIdx oi, uintptr_t retaddr);
-uint32_t cpu_atomic_cmpxchgw_be_mmu(CPUArchState *env, target_ulong addr,
- uint32_t cmpv, uint32_t newv,
- MemOpIdx oi, uintptr_t retaddr);
-uint32_t cpu_atomic_cmpxchgl_be_mmu(CPUArchState *env, target_ulong addr,
- uint32_t cmpv, uint32_t newv,
- MemOpIdx oi, uintptr_t retaddr);
-uint64_t cpu_atomic_cmpxchgq_be_mmu(CPUArchState *env, target_ulong addr,
- uint64_t cmpv, uint64_t newv,
- MemOpIdx oi, uintptr_t retaddr);
-
-#define GEN_ATOMIC_HELPER(NAME, TYPE, SUFFIX) \
-TYPE cpu_atomic_ ## NAME ## SUFFIX ## _mmu \
- (CPUArchState *env, target_ulong addr, TYPE val, \
- MemOpIdx oi, uintptr_t retaddr);
-
-#ifdef CONFIG_ATOMIC64
-#define GEN_ATOMIC_HELPER_ALL(NAME) \
- GEN_ATOMIC_HELPER(NAME, uint32_t, b) \
- GEN_ATOMIC_HELPER(NAME, uint32_t, w_le) \
- GEN_ATOMIC_HELPER(NAME, uint32_t, w_be) \
- GEN_ATOMIC_HELPER(NAME, uint32_t, l_le) \
- GEN_ATOMIC_HELPER(NAME, uint32_t, l_be) \
- GEN_ATOMIC_HELPER(NAME, uint64_t, q_le) \
- GEN_ATOMIC_HELPER(NAME, uint64_t, q_be)
-#else
-#define GEN_ATOMIC_HELPER_ALL(NAME) \
- GEN_ATOMIC_HELPER(NAME, uint32_t, b) \
- GEN_ATOMIC_HELPER(NAME, uint32_t, w_le) \
- GEN_ATOMIC_HELPER(NAME, uint32_t, w_be) \
- GEN_ATOMIC_HELPER(NAME, uint32_t, l_le) \
- GEN_ATOMIC_HELPER(NAME, uint32_t, l_be)
-#endif
-
-GEN_ATOMIC_HELPER_ALL(fetch_add)
-GEN_ATOMIC_HELPER_ALL(fetch_sub)
-GEN_ATOMIC_HELPER_ALL(fetch_and)
-GEN_ATOMIC_HELPER_ALL(fetch_or)
-GEN_ATOMIC_HELPER_ALL(fetch_xor)
-GEN_ATOMIC_HELPER_ALL(fetch_smin)
-GEN_ATOMIC_HELPER_ALL(fetch_umin)
-GEN_ATOMIC_HELPER_ALL(fetch_smax)
-GEN_ATOMIC_HELPER_ALL(fetch_umax)
-
-GEN_ATOMIC_HELPER_ALL(add_fetch)
-GEN_ATOMIC_HELPER_ALL(sub_fetch)
-GEN_ATOMIC_HELPER_ALL(and_fetch)
-GEN_ATOMIC_HELPER_ALL(or_fetch)
-GEN_ATOMIC_HELPER_ALL(xor_fetch)
-GEN_ATOMIC_HELPER_ALL(smin_fetch)
-GEN_ATOMIC_HELPER_ALL(umin_fetch)
-GEN_ATOMIC_HELPER_ALL(smax_fetch)
-GEN_ATOMIC_HELPER_ALL(umax_fetch)
-
-GEN_ATOMIC_HELPER_ALL(xchg)
-
-#undef GEN_ATOMIC_HELPER_ALL
-#undef GEN_ATOMIC_HELPER
-
-Int128 cpu_atomic_cmpxchgo_le_mmu(CPUArchState *env, target_ulong addr,
- Int128 cmpv, Int128 newv,
- MemOpIdx oi, uintptr_t retaddr);
-Int128 cpu_atomic_cmpxchgo_be_mmu(CPUArchState *env, target_ulong addr,
- Int128 cmpv, Int128 newv,
- MemOpIdx oi, uintptr_t retaddr);
-
-Int128 cpu_atomic_ldo_le_mmu(CPUArchState *env, target_ulong addr,
- MemOpIdx oi, uintptr_t retaddr);
-Int128 cpu_atomic_ldo_be_mmu(CPUArchState *env, target_ulong addr,
- MemOpIdx oi, uintptr_t retaddr);
-void cpu_atomic_sto_le_mmu(CPUArchState *env, target_ulong addr, Int128 val,
- MemOpIdx oi, uintptr_t retaddr);
-void cpu_atomic_sto_be_mmu(CPUArchState *env, target_ulong addr, Int128 val,
- MemOpIdx oi, uintptr_t retaddr);
-
#ifdef CONFIG_DEBUG_TCG
void tcg_assert_listed_vecop(TCGOpcode);
#else
diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
index f06399f351..f1a4089a4f 100644
--- a/target/arm/helper-a64.c
+++ b/target/arm/helper-a64.c
@@ -32,7 +32,6 @@
#include "exec/cpu_ldst.h"
#include "qemu/int128.h"
#include "qemu/atomic128.h"
-#include "tcg/tcg.h"
#include "fpu/softfloat.h"
#include <zlib.h> /* For crc32 */
diff --git a/target/m68k/op_helper.c b/target/m68k/op_helper.c
index 5918a29516..d2065fa992 100644
--- a/target/m68k/op_helper.c
+++ b/target/m68k/op_helper.c
@@ -22,7 +22,6 @@
#include "exec/exec-all.h"
#include "exec/cpu_ldst.h"
#include "semihosting/semihost.h"
-#include "tcg/tcg.h"
#if defined(CONFIG_USER_ONLY)
diff --git a/target/ppc/mem_helper.c b/target/ppc/mem_helper.c
index e2282baa8d..39945d9ea5 100644
--- a/target/ppc/mem_helper.c
+++ b/target/ppc/mem_helper.c
@@ -25,7 +25,6 @@
#include "exec/helper-proto.h"
#include "helper_regs.h"
#include "exec/cpu_ldst.h"
-#include "tcg/tcg.h"
#include "internal.h"
#include "qemu/atomic128.h"
diff --git a/target/s390x/tcg/mem_helper.c b/target/s390x/tcg/mem_helper.c
index 3782c1c098..b20a82a914 100644
--- a/target/s390x/tcg/mem_helper.c
+++ b/target/s390x/tcg/mem_helper.c
@@ -27,7 +27,6 @@
#include "exec/cpu_ldst.h"
#include "qemu/int128.h"
#include "qemu/atomic128.h"
-#include "tcg/tcg.h"
#if !defined(CONFIG_USER_ONLY)
#include "hw/s390x/storage-keys.h"
--
2.25.1
^ permalink raw reply related [flat|nested] 102+ messages in thread* Re: [PATCH for-6.2 33/43] accel/tcg: Move cpu_atomic decls to exec/cpu_ldst.h
2021-07-29 0:46 ` [PATCH for-6.2 33/43] accel/tcg: Move cpu_atomic decls to exec/cpu_ldst.h Richard Henderson
@ 2021-07-29 7:36 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 102+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-07-29 7:36 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
On 7/29/21 2:46 AM, Richard Henderson wrote:
> The previous placement in tcg/tcg.h was not logical.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> include/exec/cpu_ldst.h | 87 +++++++++++++++++++++++++++++++++++
> include/tcg/tcg.h | 87 -----------------------------------
> target/arm/helper-a64.c | 1 -
> target/m68k/op_helper.c | 1 -
> target/ppc/mem_helper.c | 1 -
> target/s390x/tcg/mem_helper.c | 1 -
> 6 files changed, 87 insertions(+), 91 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
^ permalink raw reply [flat|nested] 102+ messages in thread
* [PATCH for-6.2 34/43] target/mips: Use cpu_*_data_ra for msa load/store
2021-07-29 0:46 [PATCH for-6.2 00/43] Unaligned accesses for user-only Richard Henderson
` (32 preceding siblings ...)
2021-07-29 0:46 ` [PATCH for-6.2 33/43] accel/tcg: Move cpu_atomic decls to exec/cpu_ldst.h Richard Henderson
@ 2021-07-29 0:46 ` Richard Henderson
2021-07-29 7:38 ` Philippe Mathieu-Daudé
2021-07-29 0:46 ` [PATCH for-6.2 35/43] target/mips: Use 8-byte memory ops " Richard Henderson
` (10 subsequent siblings)
44 siblings, 1 reply; 102+ messages in thread
From: Richard Henderson @ 2021-07-29 0:46 UTC (permalink / raw)
To: qemu-devel; +Cc: Philippe Mathieu-Daudé
We should not have been using the helper_ret_* set of
functions, as they are supposed to be private to tcg.
Nor should we have been using the plain cpu_*_data set
of functions, as they do not handle unwinding properly.
Cc: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/mips/tcg/msa_helper.c | 420 +++++++++++------------------------
1 file changed, 135 insertions(+), 285 deletions(-)
diff --git a/target/mips/tcg/msa_helper.c b/target/mips/tcg/msa_helper.c
index 167d9a591c..a8880ce81c 100644
--- a/target/mips/tcg/msa_helper.c
+++ b/target/mips/tcg/msa_helper.c
@@ -8222,79 +8222,42 @@ void helper_msa_ld_b(CPUMIPSState *env, uint32_t wd,
target_ulong addr)
{
wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
- MEMOP_IDX(DF_BYTE)
-#if !defined(CONFIG_USER_ONLY)
+ uintptr_t ra = GETPC();
+
#if !defined(HOST_WORDS_BIGENDIAN)
- pwd->b[0] = helper_ret_ldub_mmu(env, addr + (0 << DF_BYTE), oi, GETPC());
- pwd->b[1] = helper_ret_ldub_mmu(env, addr + (1 << DF_BYTE), oi, GETPC());
- pwd->b[2] = helper_ret_ldub_mmu(env, addr + (2 << DF_BYTE), oi, GETPC());
- pwd->b[3] = helper_ret_ldub_mmu(env, addr + (3 << DF_BYTE), oi, GETPC());
- pwd->b[4] = helper_ret_ldub_mmu(env, addr + (4 << DF_BYTE), oi, GETPC());
- pwd->b[5] = helper_ret_ldub_mmu(env, addr + (5 << DF_BYTE), oi, GETPC());
- pwd->b[6] = helper_ret_ldub_mmu(env, addr + (6 << DF_BYTE), oi, GETPC());
- pwd->b[7] = helper_ret_ldub_mmu(env, addr + (7 << DF_BYTE), oi, GETPC());
- pwd->b[8] = helper_ret_ldub_mmu(env, addr + (8 << DF_BYTE), oi, GETPC());
- pwd->b[9] = helper_ret_ldub_mmu(env, addr + (9 << DF_BYTE), oi, GETPC());
- pwd->b[10] = helper_ret_ldub_mmu(env, addr + (10 << DF_BYTE), oi, GETPC());
- pwd->b[11] = helper_ret_ldub_mmu(env, addr + (11 << DF_BYTE), oi, GETPC());
- pwd->b[12] = helper_ret_ldub_mmu(env, addr + (12 << DF_BYTE), oi, GETPC());
- pwd->b[13] = helper_ret_ldub_mmu(env, addr + (13 << DF_BYTE), oi, GETPC());
- pwd->b[14] = helper_ret_ldub_mmu(env, addr + (14 << DF_BYTE), oi, GETPC());
- pwd->b[15] = helper_ret_ldub_mmu(env, addr + (15 << DF_BYTE), oi, GETPC());
+ pwd->b[0] = cpu_ldub_data_ra(env, addr + (0 << DF_BYTE), ra);
+ pwd->b[1] = cpu_ldub_data_ra(env, addr + (1 << DF_BYTE), ra);
+ pwd->b[2] = cpu_ldub_data_ra(env, addr + (2 << DF_BYTE), ra);
+ pwd->b[3] = cpu_ldub_data_ra(env, addr + (3 << DF_BYTE), ra);
+ pwd->b[4] = cpu_ldub_data_ra(env, addr + (4 << DF_BYTE), ra);
+ pwd->b[5] = cpu_ldub_data_ra(env, addr + (5 << DF_BYTE), ra);
+ pwd->b[6] = cpu_ldub_data_ra(env, addr + (6 << DF_BYTE), ra);
+ pwd->b[7] = cpu_ldub_data_ra(env, addr + (7 << DF_BYTE), ra);
+ pwd->b[8] = cpu_ldub_data_ra(env, addr + (8 << DF_BYTE), ra);
+ pwd->b[9] = cpu_ldub_data_ra(env, addr + (9 << DF_BYTE), ra);
+ pwd->b[10] = cpu_ldub_data_ra(env, addr + (10 << DF_BYTE), ra);
+ pwd->b[11] = cpu_ldub_data_ra(env, addr + (11 << DF_BYTE), ra);
+ pwd->b[12] = cpu_ldub_data_ra(env, addr + (12 << DF_BYTE), ra);
+ pwd->b[13] = cpu_ldub_data_ra(env, addr + (13 << DF_BYTE), ra);
+ pwd->b[14] = cpu_ldub_data_ra(env, addr + (14 << DF_BYTE), ra);
+ pwd->b[15] = cpu_ldub_data_ra(env, addr + (15 << DF_BYTE), ra);
#else
- pwd->b[0] = helper_ret_ldub_mmu(env, addr + (7 << DF_BYTE), oi, GETPC());
- pwd->b[1] = helper_ret_ldub_mmu(env, addr + (6 << DF_BYTE), oi, GETPC());
- pwd->b[2] = helper_ret_ldub_mmu(env, addr + (5 << DF_BYTE), oi, GETPC());
- pwd->b[3] = helper_ret_ldub_mmu(env, addr + (4 << DF_BYTE), oi, GETPC());
- pwd->b[4] = helper_ret_ldub_mmu(env, addr + (3 << DF_BYTE), oi, GETPC());
- pwd->b[5] = helper_ret_ldub_mmu(env, addr + (2 << DF_BYTE), oi, GETPC());
- pwd->b[6] = helper_ret_ldub_mmu(env, addr + (1 << DF_BYTE), oi, GETPC());
- pwd->b[7] = helper_ret_ldub_mmu(env, addr + (0 << DF_BYTE), oi, GETPC());
- pwd->b[8] = helper_ret_ldub_mmu(env, addr + (15 << DF_BYTE), oi, GETPC());
- pwd->b[9] = helper_ret_ldub_mmu(env, addr + (14 << DF_BYTE), oi, GETPC());
- pwd->b[10] = helper_ret_ldub_mmu(env, addr + (13 << DF_BYTE), oi, GETPC());
- pwd->b[11] = helper_ret_ldub_mmu(env, addr + (12 << DF_BYTE), oi, GETPC());
- pwd->b[12] = helper_ret_ldub_mmu(env, addr + (11 << DF_BYTE), oi, GETPC());
- pwd->b[13] = helper_ret_ldub_mmu(env, addr + (10 << DF_BYTE), oi, GETPC());
- pwd->b[14] = helper_ret_ldub_mmu(env, addr + (9 << DF_BYTE), oi, GETPC());
- pwd->b[15] = helper_ret_ldub_mmu(env, addr + (8 << DF_BYTE), oi, GETPC());
-#endif
-#else
-#if !defined(HOST_WORDS_BIGENDIAN)
- pwd->b[0] = cpu_ldub_data(env, addr + (0 << DF_BYTE));
- pwd->b[1] = cpu_ldub_data(env, addr + (1 << DF_BYTE));
- pwd->b[2] = cpu_ldub_data(env, addr + (2 << DF_BYTE));
- pwd->b[3] = cpu_ldub_data(env, addr + (3 << DF_BYTE));
- pwd->b[4] = cpu_ldub_data(env, addr + (4 << DF_BYTE));
- pwd->b[5] = cpu_ldub_data(env, addr + (5 << DF_BYTE));
- pwd->b[6] = cpu_ldub_data(env, addr + (6 << DF_BYTE));
- pwd->b[7] = cpu_ldub_data(env, addr + (7 << DF_BYTE));
- pwd->b[8] = cpu_ldub_data(env, addr + (8 << DF_BYTE));
- pwd->b[9] = cpu_ldub_data(env, addr + (9 << DF_BYTE));
- pwd->b[10] = cpu_ldub_data(env, addr + (10 << DF_BYTE));
- pwd->b[11] = cpu_ldub_data(env, addr + (11 << DF_BYTE));
- pwd->b[12] = cpu_ldub_data(env, addr + (12 << DF_BYTE));
- pwd->b[13] = cpu_ldub_data(env, addr + (13 << DF_BYTE));
- pwd->b[14] = cpu_ldub_data(env, addr + (14 << DF_BYTE));
- pwd->b[15] = cpu_ldub_data(env, addr + (15 << DF_BYTE));
-#else
- pwd->b[0] = cpu_ldub_data(env, addr + (7 << DF_BYTE));
- pwd->b[1] = cpu_ldub_data(env, addr + (6 << DF_BYTE));
- pwd->b[2] = cpu_ldub_data(env, addr + (5 << DF_BYTE));
- pwd->b[3] = cpu_ldub_data(env, addr + (4 << DF_BYTE));
- pwd->b[4] = cpu_ldub_data(env, addr + (3 << DF_BYTE));
- pwd->b[5] = cpu_ldub_data(env, addr + (2 << DF_BYTE));
- pwd->b[6] = cpu_ldub_data(env, addr + (1 << DF_BYTE));
- pwd->b[7] = cpu_ldub_data(env, addr + (0 << DF_BYTE));
- pwd->b[8] = cpu_ldub_data(env, addr + (15 << DF_BYTE));
- pwd->b[9] = cpu_ldub_data(env, addr + (14 << DF_BYTE));
- pwd->b[10] = cpu_ldub_data(env, addr + (13 << DF_BYTE));
- pwd->b[11] = cpu_ldub_data(env, addr + (12 << DF_BYTE));
- pwd->b[12] = cpu_ldub_data(env, addr + (11 << DF_BYTE));
- pwd->b[13] = cpu_ldub_data(env, addr + (10 << DF_BYTE));
- pwd->b[14] = cpu_ldub_data(env, addr + (9 << DF_BYTE));
- pwd->b[15] = cpu_ldub_data(env, addr + (8 << DF_BYTE));
-#endif
+ pwd->b[0] = cpu_ldub_data_ra(env, addr + (7 << DF_BYTE), ra);
+ pwd->b[1] = cpu_ldub_data_ra(env, addr + (6 << DF_BYTE), ra);
+ pwd->b[2] = cpu_ldub_data_ra(env, addr + (5 << DF_BYTE), ra);
+ pwd->b[3] = cpu_ldub_data_ra(env, addr + (4 << DF_BYTE), ra);
+ pwd->b[4] = cpu_ldub_data_ra(env, addr + (3 << DF_BYTE), ra);
+ pwd->b[5] = cpu_ldub_data_ra(env, addr + (2 << DF_BYTE), ra);
+ pwd->b[6] = cpu_ldub_data_ra(env, addr + (1 << DF_BYTE), ra);
+ pwd->b[7] = cpu_ldub_data_ra(env, addr + (0 << DF_BYTE), ra);
+ pwd->b[8] = cpu_ldub_data_ra(env, addr + (15 << DF_BYTE), ra);
+ pwd->b[9] = cpu_ldub_data_ra(env, addr + (14 << DF_BYTE), ra);
+ pwd->b[10] = cpu_ldub_data_ra(env, addr + (13 << DF_BYTE), ra);
+ pwd->b[11] = cpu_ldub_data_ra(env, addr + (12 << DF_BYTE), ra);
+ pwd->b[12] = cpu_ldub_data_ra(env, addr + (11 << DF_BYTE), ra);
+ pwd->b[13] = cpu_ldub_data_ra(env, addr + (10 << DF_BYTE), ra);
+ pwd->b[14] = cpu_ldub_data_ra(env, addr + (9 << DF_BYTE), ra);
+ pwd->b[15] = cpu_ldub_data_ra(env, addr + (8 << DF_BYTE), ra);
#endif
}
@@ -8302,47 +8265,26 @@ void helper_msa_ld_h(CPUMIPSState *env, uint32_t wd,
target_ulong addr)
{
wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
- MEMOP_IDX(DF_HALF)
-#if !defined(CONFIG_USER_ONLY)
+ uintptr_t ra = GETPC();
+
#if !defined(HOST_WORDS_BIGENDIAN)
- pwd->h[0] = helper_ret_lduw_mmu(env, addr + (0 << DF_HALF), oi, GETPC());
- pwd->h[1] = helper_ret_lduw_mmu(env, addr + (1 << DF_HALF), oi, GETPC());
- pwd->h[2] = helper_ret_lduw_mmu(env, addr + (2 << DF_HALF), oi, GETPC());
- pwd->h[3] = helper_ret_lduw_mmu(env, addr + (3 << DF_HALF), oi, GETPC());
- pwd->h[4] = helper_ret_lduw_mmu(env, addr + (4 << DF_HALF), oi, GETPC());
- pwd->h[5] = helper_ret_lduw_mmu(env, addr + (5 << DF_HALF), oi, GETPC());
- pwd->h[6] = helper_ret_lduw_mmu(env, addr + (6 << DF_HALF), oi, GETPC());
- pwd->h[7] = helper_ret_lduw_mmu(env, addr + (7 << DF_HALF), oi, GETPC());
+ pwd->h[0] = cpu_lduw_data_ra(env, addr + (0 << DF_HALF), ra);
+ pwd->h[1] = cpu_lduw_data_ra(env, addr + (1 << DF_HALF), ra);
+ pwd->h[2] = cpu_lduw_data_ra(env, addr + (2 << DF_HALF), ra);
+ pwd->h[3] = cpu_lduw_data_ra(env, addr + (3 << DF_HALF), ra);
+ pwd->h[4] = cpu_lduw_data_ra(env, addr + (4 << DF_HALF), ra);
+ pwd->h[5] = cpu_lduw_data_ra(env, addr + (5 << DF_HALF), ra);
+ pwd->h[6] = cpu_lduw_data_ra(env, addr + (6 << DF_HALF), ra);
+ pwd->h[7] = cpu_lduw_data_ra(env, addr + (7 << DF_HALF), ra);
#else
- pwd->h[0] = helper_ret_lduw_mmu(env, addr + (3 << DF_HALF), oi, GETPC());
- pwd->h[1] = helper_ret_lduw_mmu(env, addr + (2 << DF_HALF), oi, GETPC());
- pwd->h[2] = helper_ret_lduw_mmu(env, addr + (1 << DF_HALF), oi, GETPC());
- pwd->h[3] = helper_ret_lduw_mmu(env, addr + (0 << DF_HALF), oi, GETPC());
- pwd->h[4] = helper_ret_lduw_mmu(env, addr + (7 << DF_HALF), oi, GETPC());
- pwd->h[5] = helper_ret_lduw_mmu(env, addr + (6 << DF_HALF), oi, GETPC());
- pwd->h[6] = helper_ret_lduw_mmu(env, addr + (5 << DF_HALF), oi, GETPC());
- pwd->h[7] = helper_ret_lduw_mmu(env, addr + (4 << DF_HALF), oi, GETPC());
-#endif
-#else
-#if !defined(HOST_WORDS_BIGENDIAN)
- pwd->h[0] = cpu_lduw_data(env, addr + (0 << DF_HALF));
- pwd->h[1] = cpu_lduw_data(env, addr + (1 << DF_HALF));
- pwd->h[2] = cpu_lduw_data(env, addr + (2 << DF_HALF));
- pwd->h[3] = cpu_lduw_data(env, addr + (3 << DF_HALF));
- pwd->h[4] = cpu_lduw_data(env, addr + (4 << DF_HALF));
- pwd->h[5] = cpu_lduw_data(env, addr + (5 << DF_HALF));
- pwd->h[6] = cpu_lduw_data(env, addr + (6 << DF_HALF));
- pwd->h[7] = cpu_lduw_data(env, addr + (7 << DF_HALF));
-#else
- pwd->h[0] = cpu_lduw_data(env, addr + (3 << DF_HALF));
- pwd->h[1] = cpu_lduw_data(env, addr + (2 << DF_HALF));
- pwd->h[2] = cpu_lduw_data(env, addr + (1 << DF_HALF));
- pwd->h[3] = cpu_lduw_data(env, addr + (0 << DF_HALF));
- pwd->h[4] = cpu_lduw_data(env, addr + (7 << DF_HALF));
- pwd->h[5] = cpu_lduw_data(env, addr + (6 << DF_HALF));
- pwd->h[6] = cpu_lduw_data(env, addr + (5 << DF_HALF));
- pwd->h[7] = cpu_lduw_data(env, addr + (4 << DF_HALF));
-#endif
+ pwd->h[0] = cpu_lduw_data_ra(env, addr + (3 << DF_HALF), ra);
+ pwd->h[1] = cpu_lduw_data_ra(env, addr + (2 << DF_HALF), ra);
+ pwd->h[2] = cpu_lduw_data_ra(env, addr + (1 << DF_HALF), ra);
+ pwd->h[3] = cpu_lduw_data_ra(env, addr + (0 << DF_HALF), ra);
+ pwd->h[4] = cpu_lduw_data_ra(env, addr + (7 << DF_HALF), ra);
+ pwd->h[5] = cpu_lduw_data_ra(env, addr + (6 << DF_HALF), ra);
+ pwd->h[6] = cpu_lduw_data_ra(env, addr + (5 << DF_HALF), ra);
+ pwd->h[7] = cpu_lduw_data_ra(env, addr + (4 << DF_HALF), ra);
#endif
}
@@ -8350,31 +8292,18 @@ void helper_msa_ld_w(CPUMIPSState *env, uint32_t wd,
target_ulong addr)
{
wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
- MEMOP_IDX(DF_WORD)
-#if !defined(CONFIG_USER_ONLY)
+ uintptr_t ra = GETPC();
+
#if !defined(HOST_WORDS_BIGENDIAN)
- pwd->w[0] = helper_ret_ldul_mmu(env, addr + (0 << DF_WORD), oi, GETPC());
- pwd->w[1] = helper_ret_ldul_mmu(env, addr + (1 << DF_WORD), oi, GETPC());
- pwd->w[2] = helper_ret_ldul_mmu(env, addr + (2 << DF_WORD), oi, GETPC());
- pwd->w[3] = helper_ret_ldul_mmu(env, addr + (3 << DF_WORD), oi, GETPC());
+ pwd->w[0] = cpu_ldl_data_ra(env, addr + (0 << DF_WORD), ra);
+ pwd->w[1] = cpu_ldl_data_ra(env, addr + (1 << DF_WORD), ra);
+ pwd->w[2] = cpu_ldl_data_ra(env, addr + (2 << DF_WORD), ra);
+ pwd->w[3] = cpu_ldl_data_ra(env, addr + (3 << DF_WORD), ra);
#else
- pwd->w[0] = helper_ret_ldul_mmu(env, addr + (1 << DF_WORD), oi, GETPC());
- pwd->w[1] = helper_ret_ldul_mmu(env, addr + (0 << DF_WORD), oi, GETPC());
- pwd->w[2] = helper_ret_ldul_mmu(env, addr + (3 << DF_WORD), oi, GETPC());
- pwd->w[3] = helper_ret_ldul_mmu(env, addr + (2 << DF_WORD), oi, GETPC());
-#endif
-#else
-#if !defined(HOST_WORDS_BIGENDIAN)
- pwd->w[0] = cpu_ldl_data(env, addr + (0 << DF_WORD));
- pwd->w[1] = cpu_ldl_data(env, addr + (1 << DF_WORD));
- pwd->w[2] = cpu_ldl_data(env, addr + (2 << DF_WORD));
- pwd->w[3] = cpu_ldl_data(env, addr + (3 << DF_WORD));
-#else
- pwd->w[0] = cpu_ldl_data(env, addr + (1 << DF_WORD));
- pwd->w[1] = cpu_ldl_data(env, addr + (0 << DF_WORD));
- pwd->w[2] = cpu_ldl_data(env, addr + (3 << DF_WORD));
- pwd->w[3] = cpu_ldl_data(env, addr + (2 << DF_WORD));
-#endif
+ pwd->w[0] = cpu_ldl_data_ra(env, addr + (1 << DF_WORD), ra);
+ pwd->w[1] = cpu_ldl_data_ra(env, addr + (0 << DF_WORD), ra);
+ pwd->w[2] = cpu_ldl_data_ra(env, addr + (3 << DF_WORD), ra);
+ pwd->w[3] = cpu_ldl_data_ra(env, addr + (2 << DF_WORD), ra);
#endif
}
@@ -8382,14 +8311,10 @@ void helper_msa_ld_d(CPUMIPSState *env, uint32_t wd,
target_ulong addr)
{
wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
- MEMOP_IDX(DF_DOUBLE)
-#if !defined(CONFIG_USER_ONLY)
- pwd->d[0] = helper_ret_ldq_mmu(env, addr + (0 << DF_DOUBLE), oi, GETPC());
- pwd->d[1] = helper_ret_ldq_mmu(env, addr + (1 << DF_DOUBLE), oi, GETPC());
-#else
- pwd->d[0] = cpu_ldq_data(env, addr + (0 << DF_DOUBLE));
- pwd->d[1] = cpu_ldq_data(env, addr + (1 << DF_DOUBLE));
-#endif
+ uintptr_t ra = GETPC();
+
+ pwd->d[0] = cpu_ldq_data_ra(env, addr + (0 << DF_DOUBLE), ra);
+ pwd->d[1] = cpu_ldq_data_ra(env, addr + (1 << DF_DOUBLE), ra);
}
#define MSA_PAGESPAN(x) \
@@ -8415,81 +8340,44 @@ void helper_msa_st_b(CPUMIPSState *env, uint32_t wd,
{
wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
int mmu_idx = cpu_mmu_index(env, false);
+ uintptr_t ra = GETPC();
+
+ ensure_writable_pages(env, addr, mmu_idx, ra);
- MEMOP_IDX(DF_BYTE)
- ensure_writable_pages(env, addr, mmu_idx, GETPC());
-#if !defined(CONFIG_USER_ONLY)
#if !defined(HOST_WORDS_BIGENDIAN)
- helper_ret_stb_mmu(env, addr + (0 << DF_BYTE), pwd->b[0], oi, GETPC());
- helper_ret_stb_mmu(env, addr + (1 << DF_BYTE), pwd->b[1], oi, GETPC());
- helper_ret_stb_mmu(env, addr + (2 << DF_BYTE), pwd->b[2], oi, GETPC());
- helper_ret_stb_mmu(env, addr + (3 << DF_BYTE), pwd->b[3], oi, GETPC());
- helper_ret_stb_mmu(env, addr + (4 << DF_BYTE), pwd->b[4], oi, GETPC());
- helper_ret_stb_mmu(env, addr + (5 << DF_BYTE), pwd->b[5], oi, GETPC());
- helper_ret_stb_mmu(env, addr + (6 << DF_BYTE), pwd->b[6], oi, GETPC());
- helper_ret_stb_mmu(env, addr + (7 << DF_BYTE), pwd->b[7], oi, GETPC());
- helper_ret_stb_mmu(env, addr + (8 << DF_BYTE), pwd->b[8], oi, GETPC());
- helper_ret_stb_mmu(env, addr + (9 << DF_BYTE), pwd->b[9], oi, GETPC());
- helper_ret_stb_mmu(env, addr + (10 << DF_BYTE), pwd->b[10], oi, GETPC());
- helper_ret_stb_mmu(env, addr + (11 << DF_BYTE), pwd->b[11], oi, GETPC());
- helper_ret_stb_mmu(env, addr + (12 << DF_BYTE), pwd->b[12], oi, GETPC());
- helper_ret_stb_mmu(env, addr + (13 << DF_BYTE), pwd->b[13], oi, GETPC());
- helper_ret_stb_mmu(env, addr + (14 << DF_BYTE), pwd->b[14], oi, GETPC());
- helper_ret_stb_mmu(env, addr + (15 << DF_BYTE), pwd->b[15], oi, GETPC());
+ cpu_stb_data_ra(env, addr + (0 << DF_BYTE), pwd->b[0], ra);
+ cpu_stb_data_ra(env, addr + (1 << DF_BYTE), pwd->b[1], ra);
+ cpu_stb_data_ra(env, addr + (2 << DF_BYTE), pwd->b[2], ra);
+ cpu_stb_data_ra(env, addr + (3 << DF_BYTE), pwd->b[3], ra);
+ cpu_stb_data_ra(env, addr + (4 << DF_BYTE), pwd->b[4], ra);
+ cpu_stb_data_ra(env, addr + (5 << DF_BYTE), pwd->b[5], ra);
+ cpu_stb_data_ra(env, addr + (6 << DF_BYTE), pwd->b[6], ra);
+ cpu_stb_data_ra(env, addr + (7 << DF_BYTE), pwd->b[7], ra);
+ cpu_stb_data_ra(env, addr + (8 << DF_BYTE), pwd->b[8], ra);
+ cpu_stb_data_ra(env, addr + (9 << DF_BYTE), pwd->b[9], ra);
+ cpu_stb_data_ra(env, addr + (10 << DF_BYTE), pwd->b[10], ra);
+ cpu_stb_data_ra(env, addr + (11 << DF_BYTE), pwd->b[11], ra);
+ cpu_stb_data_ra(env, addr + (12 << DF_BYTE), pwd->b[12], ra);
+ cpu_stb_data_ra(env, addr + (13 << DF_BYTE), pwd->b[13], ra);
+ cpu_stb_data_ra(env, addr + (14 << DF_BYTE), pwd->b[14], ra);
+ cpu_stb_data_ra(env, addr + (15 << DF_BYTE), pwd->b[15], ra);
#else
- helper_ret_stb_mmu(env, addr + (7 << DF_BYTE), pwd->b[0], oi, GETPC());
- helper_ret_stb_mmu(env, addr + (6 << DF_BYTE), pwd->b[1], oi, GETPC());
- helper_ret_stb_mmu(env, addr + (5 << DF_BYTE), pwd->b[2], oi, GETPC());
- helper_ret_stb_mmu(env, addr + (4 << DF_BYTE), pwd->b[3], oi, GETPC());
- helper_ret_stb_mmu(env, addr + (3 << DF_BYTE), pwd->b[4], oi, GETPC());
- helper_ret_stb_mmu(env, addr + (2 << DF_BYTE), pwd->b[5], oi, GETPC());
- helper_ret_stb_mmu(env, addr + (1 << DF_BYTE), pwd->b[6], oi, GETPC());
- helper_ret_stb_mmu(env, addr + (0 << DF_BYTE), pwd->b[7], oi, GETPC());
- helper_ret_stb_mmu(env, addr + (15 << DF_BYTE), pwd->b[8], oi, GETPC());
- helper_ret_stb_mmu(env, addr + (14 << DF_BYTE), pwd->b[9], oi, GETPC());
- helper_ret_stb_mmu(env, addr + (13 << DF_BYTE), pwd->b[10], oi, GETPC());
- helper_ret_stb_mmu(env, addr + (12 << DF_BYTE), pwd->b[11], oi, GETPC());
- helper_ret_stb_mmu(env, addr + (11 << DF_BYTE), pwd->b[12], oi, GETPC());
- helper_ret_stb_mmu(env, addr + (10 << DF_BYTE), pwd->b[13], oi, GETPC());
- helper_ret_stb_mmu(env, addr + (9 << DF_BYTE), pwd->b[14], oi, GETPC());
- helper_ret_stb_mmu(env, addr + (8 << DF_BYTE), pwd->b[15], oi, GETPC());
-#endif
-#else
-#if !defined(HOST_WORDS_BIGENDIAN)
- cpu_stb_data(env, addr + (0 << DF_BYTE), pwd->b[0]);
- cpu_stb_data(env, addr + (1 << DF_BYTE), pwd->b[1]);
- cpu_stb_data(env, addr + (2 << DF_BYTE), pwd->b[2]);
- cpu_stb_data(env, addr + (3 << DF_BYTE), pwd->b[3]);
- cpu_stb_data(env, addr + (4 << DF_BYTE), pwd->b[4]);
- cpu_stb_data(env, addr + (5 << DF_BYTE), pwd->b[5]);
- cpu_stb_data(env, addr + (6 << DF_BYTE), pwd->b[6]);
- cpu_stb_data(env, addr + (7 << DF_BYTE), pwd->b[7]);
- cpu_stb_data(env, addr + (8 << DF_BYTE), pwd->b[8]);
- cpu_stb_data(env, addr + (9 << DF_BYTE), pwd->b[9]);
- cpu_stb_data(env, addr + (10 << DF_BYTE), pwd->b[10]);
- cpu_stb_data(env, addr + (11 << DF_BYTE), pwd->b[11]);
- cpu_stb_data(env, addr + (12 << DF_BYTE), pwd->b[12]);
- cpu_stb_data(env, addr + (13 << DF_BYTE), pwd->b[13]);
- cpu_stb_data(env, addr + (14 << DF_BYTE), pwd->b[14]);
- cpu_stb_data(env, addr + (15 << DF_BYTE), pwd->b[15]);
-#else
- cpu_stb_data(env, addr + (7 << DF_BYTE), pwd->b[0]);
- cpu_stb_data(env, addr + (6 << DF_BYTE), pwd->b[1]);
- cpu_stb_data(env, addr + (5 << DF_BYTE), pwd->b[2]);
- cpu_stb_data(env, addr + (4 << DF_BYTE), pwd->b[3]);
- cpu_stb_data(env, addr + (3 << DF_BYTE), pwd->b[4]);
- cpu_stb_data(env, addr + (2 << DF_BYTE), pwd->b[5]);
- cpu_stb_data(env, addr + (1 << DF_BYTE), pwd->b[6]);
- cpu_stb_data(env, addr + (0 << DF_BYTE), pwd->b[7]);
- cpu_stb_data(env, addr + (15 << DF_BYTE), pwd->b[8]);
- cpu_stb_data(env, addr + (14 << DF_BYTE), pwd->b[9]);
- cpu_stb_data(env, addr + (13 << DF_BYTE), pwd->b[10]);
- cpu_stb_data(env, addr + (12 << DF_BYTE), pwd->b[11]);
- cpu_stb_data(env, addr + (11 << DF_BYTE), pwd->b[12]);
- cpu_stb_data(env, addr + (10 << DF_BYTE), pwd->b[13]);
- cpu_stb_data(env, addr + (9 << DF_BYTE), pwd->b[14]);
- cpu_stb_data(env, addr + (8 << DF_BYTE), pwd->b[15]);
-#endif
+ cpu_stb_data_ra(env, addr + (7 << DF_BYTE), pwd->b[0], ra);
+ cpu_stb_data_ra(env, addr + (6 << DF_BYTE), pwd->b[1], ra);
+ cpu_stb_data_ra(env, addr + (5 << DF_BYTE), pwd->b[2], ra);
+ cpu_stb_data_ra(env, addr + (4 << DF_BYTE), pwd->b[3], ra);
+ cpu_stb_data_ra(env, addr + (3 << DF_BYTE), pwd->b[4], ra);
+ cpu_stb_data_ra(env, addr + (2 << DF_BYTE), pwd->b[5], ra);
+ cpu_stb_data_ra(env, addr + (1 << DF_BYTE), pwd->b[6], ra);
+ cpu_stb_data_ra(env, addr + (0 << DF_BYTE), pwd->b[7], ra);
+ cpu_stb_data_ra(env, addr + (15 << DF_BYTE), pwd->b[8], ra);
+ cpu_stb_data_ra(env, addr + (14 << DF_BYTE), pwd->b[9], ra);
+ cpu_stb_data_ra(env, addr + (13 << DF_BYTE), pwd->b[10], ra);
+ cpu_stb_data_ra(env, addr + (12 << DF_BYTE), pwd->b[11], ra);
+ cpu_stb_data_ra(env, addr + (11 << DF_BYTE), pwd->b[12], ra);
+ cpu_stb_data_ra(env, addr + (10 << DF_BYTE), pwd->b[13], ra);
+ cpu_stb_data_ra(env, addr + (9 << DF_BYTE), pwd->b[14], ra);
+ cpu_stb_data_ra(env, addr + (8 << DF_BYTE), pwd->b[15], ra);
#endif
}
@@ -8498,49 +8386,28 @@ void helper_msa_st_h(CPUMIPSState *env, uint32_t wd,
{
wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
int mmu_idx = cpu_mmu_index(env, false);
+ uintptr_t ra = GETPC();
+
+ ensure_writable_pages(env, addr, mmu_idx, ra);
- MEMOP_IDX(DF_HALF)
- ensure_writable_pages(env, addr, mmu_idx, GETPC());
-#if !defined(CONFIG_USER_ONLY)
#if !defined(HOST_WORDS_BIGENDIAN)
- helper_ret_stw_mmu(env, addr + (0 << DF_HALF), pwd->h[0], oi, GETPC());
- helper_ret_stw_mmu(env, addr + (1 << DF_HALF), pwd->h[1], oi, GETPC());
- helper_ret_stw_mmu(env, addr + (2 << DF_HALF), pwd->h[2], oi, GETPC());
- helper_ret_stw_mmu(env, addr + (3 << DF_HALF), pwd->h[3], oi, GETPC());
- helper_ret_stw_mmu(env, addr + (4 << DF_HALF), pwd->h[4], oi, GETPC());
- helper_ret_stw_mmu(env, addr + (5 << DF_HALF), pwd->h[5], oi, GETPC());
- helper_ret_stw_mmu(env, addr + (6 << DF_HALF), pwd->h[6], oi, GETPC());
- helper_ret_stw_mmu(env, addr + (7 << DF_HALF), pwd->h[7], oi, GETPC());
+ cpu_stw_data_ra(env, addr + (0 << DF_HALF), pwd->h[0], ra);
+ cpu_stw_data_ra(env, addr + (1 << DF_HALF), pwd->h[1], ra);
+ cpu_stw_data_ra(env, addr + (2 << DF_HALF), pwd->h[2], ra);
+ cpu_stw_data_ra(env, addr + (3 << DF_HALF), pwd->h[3], ra);
+ cpu_stw_data_ra(env, addr + (4 << DF_HALF), pwd->h[4], ra);
+ cpu_stw_data_ra(env, addr + (5 << DF_HALF), pwd->h[5], ra);
+ cpu_stw_data_ra(env, addr + (6 << DF_HALF), pwd->h[6], ra);
+ cpu_stw_data_ra(env, addr + (7 << DF_HALF), pwd->h[7], ra);
#else
- helper_ret_stw_mmu(env, addr + (3 << DF_HALF), pwd->h[0], oi, GETPC());
- helper_ret_stw_mmu(env, addr + (2 << DF_HALF), pwd->h[1], oi, GETPC());
- helper_ret_stw_mmu(env, addr + (1 << DF_HALF), pwd->h[2], oi, GETPC());
- helper_ret_stw_mmu(env, addr + (0 << DF_HALF), pwd->h[3], oi, GETPC());
- helper_ret_stw_mmu(env, addr + (7 << DF_HALF), pwd->h[4], oi, GETPC());
- helper_ret_stw_mmu(env, addr + (6 << DF_HALF), pwd->h[5], oi, GETPC());
- helper_ret_stw_mmu(env, addr + (5 << DF_HALF), pwd->h[6], oi, GETPC());
- helper_ret_stw_mmu(env, addr + (4 << DF_HALF), pwd->h[7], oi, GETPC());
-#endif
-#else
-#if !defined(HOST_WORDS_BIGENDIAN)
- cpu_stw_data(env, addr + (0 << DF_HALF), pwd->h[0]);
- cpu_stw_data(env, addr + (1 << DF_HALF), pwd->h[1]);
- cpu_stw_data(env, addr + (2 << DF_HALF), pwd->h[2]);
- cpu_stw_data(env, addr + (3 << DF_HALF), pwd->h[3]);
- cpu_stw_data(env, addr + (4 << DF_HALF), pwd->h[4]);
- cpu_stw_data(env, addr + (5 << DF_HALF), pwd->h[5]);
- cpu_stw_data(env, addr + (6 << DF_HALF), pwd->h[6]);
- cpu_stw_data(env, addr + (7 << DF_HALF), pwd->h[7]);
-#else
- cpu_stw_data(env, addr + (3 << DF_HALF), pwd->h[0]);
- cpu_stw_data(env, addr + (2 << DF_HALF), pwd->h[1]);
- cpu_stw_data(env, addr + (1 << DF_HALF), pwd->h[2]);
- cpu_stw_data(env, addr + (0 << DF_HALF), pwd->h[3]);
- cpu_stw_data(env, addr + (7 << DF_HALF), pwd->h[4]);
- cpu_stw_data(env, addr + (6 << DF_HALF), pwd->h[5]);
- cpu_stw_data(env, addr + (5 << DF_HALF), pwd->h[6]);
- cpu_stw_data(env, addr + (4 << DF_HALF), pwd->h[7]);
-#endif
+ cpu_stw_data_ra(env, addr + (3 << DF_HALF), pwd->h[0], ra);
+ cpu_stw_data_ra(env, addr + (2 << DF_HALF), pwd->h[1], ra);
+ cpu_stw_data_ra(env, addr + (1 << DF_HALF), pwd->h[2], ra);
+ cpu_stw_data_ra(env, addr + (0 << DF_HALF), pwd->h[3], ra);
+ cpu_stw_data_ra(env, addr + (7 << DF_HALF), pwd->h[4], ra);
+ cpu_stw_data_ra(env, addr + (6 << DF_HALF), pwd->h[5], ra);
+ cpu_stw_data_ra(env, addr + (5 << DF_HALF), pwd->h[6], ra);
+ cpu_stw_data_ra(env, addr + (4 << DF_HALF), pwd->h[7], ra);
#endif
}
@@ -8549,33 +8416,20 @@ void helper_msa_st_w(CPUMIPSState *env, uint32_t wd,
{
wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
int mmu_idx = cpu_mmu_index(env, false);
+ uintptr_t ra = GETPC();
+
+ ensure_writable_pages(env, addr, mmu_idx, ra);
- MEMOP_IDX(DF_WORD)
- ensure_writable_pages(env, addr, mmu_idx, GETPC());
-#if !defined(CONFIG_USER_ONLY)
#if !defined(HOST_WORDS_BIGENDIAN)
- helper_ret_stl_mmu(env, addr + (0 << DF_WORD), pwd->w[0], oi, GETPC());
- helper_ret_stl_mmu(env, addr + (1 << DF_WORD), pwd->w[1], oi, GETPC());
- helper_ret_stl_mmu(env, addr + (2 << DF_WORD), pwd->w[2], oi, GETPC());
- helper_ret_stl_mmu(env, addr + (3 << DF_WORD), pwd->w[3], oi, GETPC());
+ cpu_stl_data_ra(env, addr + (0 << DF_WORD), pwd->w[0], ra);
+ cpu_stl_data_ra(env, addr + (1 << DF_WORD), pwd->w[1], ra);
+ cpu_stl_data_ra(env, addr + (2 << DF_WORD), pwd->w[2], ra);
+ cpu_stl_data_ra(env, addr + (3 << DF_WORD), pwd->w[3], ra);
#else
- helper_ret_stl_mmu(env, addr + (1 << DF_WORD), pwd->w[0], oi, GETPC());
- helper_ret_stl_mmu(env, addr + (0 << DF_WORD), pwd->w[1], oi, GETPC());
- helper_ret_stl_mmu(env, addr + (3 << DF_WORD), pwd->w[2], oi, GETPC());
- helper_ret_stl_mmu(env, addr + (2 << DF_WORD), pwd->w[3], oi, GETPC());
-#endif
-#else
-#if !defined(HOST_WORDS_BIGENDIAN)
- cpu_stl_data(env, addr + (0 << DF_WORD), pwd->w[0]);
- cpu_stl_data(env, addr + (1 << DF_WORD), pwd->w[1]);
- cpu_stl_data(env, addr + (2 << DF_WORD), pwd->w[2]);
- cpu_stl_data(env, addr + (3 << DF_WORD), pwd->w[3]);
-#else
- cpu_stl_data(env, addr + (1 << DF_WORD), pwd->w[0]);
- cpu_stl_data(env, addr + (0 << DF_WORD), pwd->w[1]);
- cpu_stl_data(env, addr + (3 << DF_WORD), pwd->w[2]);
- cpu_stl_data(env, addr + (2 << DF_WORD), pwd->w[3]);
-#endif
+ cpu_stl_data_ra(env, addr + (1 << DF_WORD), pwd->w[0], ra);
+ cpu_stl_data_ra(env, addr + (0 << DF_WORD), pwd->w[1], ra);
+ cpu_stl_data_ra(env, addr + (3 << DF_WORD), pwd->w[2], ra);
+ cpu_stl_data_ra(env, addr + (2 << DF_WORD), pwd->w[3], ra);
#endif
}
@@ -8584,14 +8438,10 @@ void helper_msa_st_d(CPUMIPSState *env, uint32_t wd,
{
wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
int mmu_idx = cpu_mmu_index(env, false);
+ uintptr_t ra = GETPC();
- MEMOP_IDX(DF_DOUBLE)
ensure_writable_pages(env, addr, mmu_idx, GETPC());
-#if !defined(CONFIG_USER_ONLY)
- helper_ret_stq_mmu(env, addr + (0 << DF_DOUBLE), pwd->d[0], oi, GETPC());
- helper_ret_stq_mmu(env, addr + (1 << DF_DOUBLE), pwd->d[1], oi, GETPC());
-#else
- cpu_stq_data(env, addr + (0 << DF_DOUBLE), pwd->d[0]);
- cpu_stq_data(env, addr + (1 << DF_DOUBLE), pwd->d[1]);
-#endif
+
+ cpu_stq_data_ra(env, addr + (0 << DF_DOUBLE), pwd->d[0], ra);
+ cpu_stq_data_ra(env, addr + (1 << DF_DOUBLE), pwd->d[1], ra);
}
--
2.25.1
^ permalink raw reply related [flat|nested] 102+ messages in thread* Re: [PATCH for-6.2 34/43] target/mips: Use cpu_*_data_ra for msa load/store
2021-07-29 0:46 ` [PATCH for-6.2 34/43] target/mips: Use cpu_*_data_ra for msa load/store Richard Henderson
@ 2021-07-29 7:38 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 102+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-07-29 7:38 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
On 7/29/21 2:46 AM, Richard Henderson wrote:
> We should not have been using the helper_ret_* set of
> functions, as they are supposed to be private to tcg.
> Nor should we have been using the plain cpu_*_data set
> of functions, as they do not handle unwinding properly.
>
> Cc: Philippe Mathieu-Daudé <f4bug@amsat.org>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/mips/tcg/msa_helper.c | 420 +++++++++++------------------------
> 1 file changed, 135 insertions(+), 285 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
^ permalink raw reply [flat|nested] 102+ messages in thread
* [PATCH for-6.2 35/43] target/mips: Use 8-byte memory ops for msa load/store
2021-07-29 0:46 [PATCH for-6.2 00/43] Unaligned accesses for user-only Richard Henderson
` (33 preceding siblings ...)
2021-07-29 0:46 ` [PATCH for-6.2 34/43] target/mips: Use cpu_*_data_ra for msa load/store Richard Henderson
@ 2021-07-29 0:46 ` Richard Henderson
2021-07-29 0:46 ` [PATCH for-6.2 36/43] target/s390x: Use cpu_*_mmu instead of helper_*_mmu Richard Henderson
` (9 subsequent siblings)
44 siblings, 0 replies; 102+ messages in thread
From: Richard Henderson @ 2021-07-29 0:46 UTC (permalink / raw)
To: qemu-devel; +Cc: Philippe Mathieu-Daudé
Rather than use 4-16 separate operations, use 2 operations
plus some byte reordering as necessary.
Cc: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/mips/tcg/msa_helper.c | 201 +++++++++++++----------------------
1 file changed, 71 insertions(+), 130 deletions(-)
diff --git a/target/mips/tcg/msa_helper.c b/target/mips/tcg/msa_helper.c
index a8880ce81c..e40c1b7057 100644
--- a/target/mips/tcg/msa_helper.c
+++ b/target/mips/tcg/msa_helper.c
@@ -8218,47 +8218,31 @@ void helper_msa_ffint_u_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
#define MEMOP_IDX(DF)
#endif
+#ifdef TARGET_WORDS_BIGENDIAN
+static inline uint64_t bswap16x4(uint64_t x)
+{
+ uint64_t m = 0x00ff00ff00ff00ffull;
+ return ((x & m) << 8) | ((x >> 8) & m);
+}
+
+static inline uint64_t bswap32x2(uint64_t x)
+{
+ return ror64(bswap64(x), 32);
+}
+#endif
+
void helper_msa_ld_b(CPUMIPSState *env, uint32_t wd,
target_ulong addr)
{
wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
uintptr_t ra = GETPC();
+ uint64_t d0, d1;
-#if !defined(HOST_WORDS_BIGENDIAN)
- pwd->b[0] = cpu_ldub_data_ra(env, addr + (0 << DF_BYTE), ra);
- pwd->b[1] = cpu_ldub_data_ra(env, addr + (1 << DF_BYTE), ra);
- pwd->b[2] = cpu_ldub_data_ra(env, addr + (2 << DF_BYTE), ra);
- pwd->b[3] = cpu_ldub_data_ra(env, addr + (3 << DF_BYTE), ra);
- pwd->b[4] = cpu_ldub_data_ra(env, addr + (4 << DF_BYTE), ra);
- pwd->b[5] = cpu_ldub_data_ra(env, addr + (5 << DF_BYTE), ra);
- pwd->b[6] = cpu_ldub_data_ra(env, addr + (6 << DF_BYTE), ra);
- pwd->b[7] = cpu_ldub_data_ra(env, addr + (7 << DF_BYTE), ra);
- pwd->b[8] = cpu_ldub_data_ra(env, addr + (8 << DF_BYTE), ra);
- pwd->b[9] = cpu_ldub_data_ra(env, addr + (9 << DF_BYTE), ra);
- pwd->b[10] = cpu_ldub_data_ra(env, addr + (10 << DF_BYTE), ra);
- pwd->b[11] = cpu_ldub_data_ra(env, addr + (11 << DF_BYTE), ra);
- pwd->b[12] = cpu_ldub_data_ra(env, addr + (12 << DF_BYTE), ra);
- pwd->b[13] = cpu_ldub_data_ra(env, addr + (13 << DF_BYTE), ra);
- pwd->b[14] = cpu_ldub_data_ra(env, addr + (14 << DF_BYTE), ra);
- pwd->b[15] = cpu_ldub_data_ra(env, addr + (15 << DF_BYTE), ra);
-#else
- pwd->b[0] = cpu_ldub_data_ra(env, addr + (7 << DF_BYTE), ra);
- pwd->b[1] = cpu_ldub_data_ra(env, addr + (6 << DF_BYTE), ra);
- pwd->b[2] = cpu_ldub_data_ra(env, addr + (5 << DF_BYTE), ra);
- pwd->b[3] = cpu_ldub_data_ra(env, addr + (4 << DF_BYTE), ra);
- pwd->b[4] = cpu_ldub_data_ra(env, addr + (3 << DF_BYTE), ra);
- pwd->b[5] = cpu_ldub_data_ra(env, addr + (2 << DF_BYTE), ra);
- pwd->b[6] = cpu_ldub_data_ra(env, addr + (1 << DF_BYTE), ra);
- pwd->b[7] = cpu_ldub_data_ra(env, addr + (0 << DF_BYTE), ra);
- pwd->b[8] = cpu_ldub_data_ra(env, addr + (15 << DF_BYTE), ra);
- pwd->b[9] = cpu_ldub_data_ra(env, addr + (14 << DF_BYTE), ra);
- pwd->b[10] = cpu_ldub_data_ra(env, addr + (13 << DF_BYTE), ra);
- pwd->b[11] = cpu_ldub_data_ra(env, addr + (12 << DF_BYTE), ra);
- pwd->b[12] = cpu_ldub_data_ra(env, addr + (11 << DF_BYTE), ra);
- pwd->b[13] = cpu_ldub_data_ra(env, addr + (10 << DF_BYTE), ra);
- pwd->b[14] = cpu_ldub_data_ra(env, addr + (9 << DF_BYTE), ra);
- pwd->b[15] = cpu_ldub_data_ra(env, addr + (8 << DF_BYTE), ra);
-#endif
+ /* Load 8 bytes at a time. Vector element ordering makes this LE. */
+ d0 = cpu_ldq_le_data_ra(env, addr + 0, ra);
+ d1 = cpu_ldq_le_data_ra(env, addr + 8, ra);
+ pwd->d[0] = d0;
+ pwd->d[1] = d1;
}
void helper_msa_ld_h(CPUMIPSState *env, uint32_t wd,
@@ -8266,26 +8250,20 @@ void helper_msa_ld_h(CPUMIPSState *env, uint32_t wd,
{
wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
uintptr_t ra = GETPC();
+ uint64_t d0, d1;
-#if !defined(HOST_WORDS_BIGENDIAN)
- pwd->h[0] = cpu_lduw_data_ra(env, addr + (0 << DF_HALF), ra);
- pwd->h[1] = cpu_lduw_data_ra(env, addr + (1 << DF_HALF), ra);
- pwd->h[2] = cpu_lduw_data_ra(env, addr + (2 << DF_HALF), ra);
- pwd->h[3] = cpu_lduw_data_ra(env, addr + (3 << DF_HALF), ra);
- pwd->h[4] = cpu_lduw_data_ra(env, addr + (4 << DF_HALF), ra);
- pwd->h[5] = cpu_lduw_data_ra(env, addr + (5 << DF_HALF), ra);
- pwd->h[6] = cpu_lduw_data_ra(env, addr + (6 << DF_HALF), ra);
- pwd->h[7] = cpu_lduw_data_ra(env, addr + (7 << DF_HALF), ra);
-#else
- pwd->h[0] = cpu_lduw_data_ra(env, addr + (3 << DF_HALF), ra);
- pwd->h[1] = cpu_lduw_data_ra(env, addr + (2 << DF_HALF), ra);
- pwd->h[2] = cpu_lduw_data_ra(env, addr + (1 << DF_HALF), ra);
- pwd->h[3] = cpu_lduw_data_ra(env, addr + (0 << DF_HALF), ra);
- pwd->h[4] = cpu_lduw_data_ra(env, addr + (7 << DF_HALF), ra);
- pwd->h[5] = cpu_lduw_data_ra(env, addr + (6 << DF_HALF), ra);
- pwd->h[6] = cpu_lduw_data_ra(env, addr + (5 << DF_HALF), ra);
- pwd->h[7] = cpu_lduw_data_ra(env, addr + (4 << DF_HALF), ra);
+ /*
+ * Load 8 bytes at a time. Use little-endian load, then for
+ * big-endian target, we must then swap the four halfwords.
+ */
+ d0 = cpu_ldq_le_data_ra(env, addr + 0, ra);
+ d1 = cpu_ldq_le_data_ra(env, addr + 8, ra);
+#ifdef TARGET_WORDS_BIGENDIAN
+ d0 = bswap16x4(d0);
+ d1 = bswap16x4(d1);
#endif
+ pwd->d[0] = d0;
+ pwd->d[1] = d1;
}
void helper_msa_ld_w(CPUMIPSState *env, uint32_t wd,
@@ -8293,18 +8271,20 @@ void helper_msa_ld_w(CPUMIPSState *env, uint32_t wd,
{
wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
uintptr_t ra = GETPC();
+ uint64_t d0, d1;
-#if !defined(HOST_WORDS_BIGENDIAN)
- pwd->w[0] = cpu_ldl_data_ra(env, addr + (0 << DF_WORD), ra);
- pwd->w[1] = cpu_ldl_data_ra(env, addr + (1 << DF_WORD), ra);
- pwd->w[2] = cpu_ldl_data_ra(env, addr + (2 << DF_WORD), ra);
- pwd->w[3] = cpu_ldl_data_ra(env, addr + (3 << DF_WORD), ra);
-#else
- pwd->w[0] = cpu_ldl_data_ra(env, addr + (1 << DF_WORD), ra);
- pwd->w[1] = cpu_ldl_data_ra(env, addr + (0 << DF_WORD), ra);
- pwd->w[2] = cpu_ldl_data_ra(env, addr + (3 << DF_WORD), ra);
- pwd->w[3] = cpu_ldl_data_ra(env, addr + (2 << DF_WORD), ra);
+ /*
+ * Load 8 bytes at a time. Use little-endian load, then for
+ * big-endian target, we must then bswap the two words.
+ */
+ d0 = cpu_ldq_le_data_ra(env, addr + 0, ra);
+ d1 = cpu_ldq_le_data_ra(env, addr + 8, ra);
+#ifdef TARGET_WORDS_BIGENDIAN
+ d0 = bswap32x2(d0);
+ d1 = bswap32x2(d1);
#endif
+ pwd->d[0] = d0;
+ pwd->d[1] = d1;
}
void helper_msa_ld_d(CPUMIPSState *env, uint32_t wd,
@@ -8312,9 +8292,12 @@ void helper_msa_ld_d(CPUMIPSState *env, uint32_t wd,
{
wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
uintptr_t ra = GETPC();
+ uint64_t d0, d1;
- pwd->d[0] = cpu_ldq_data_ra(env, addr + (0 << DF_DOUBLE), ra);
- pwd->d[1] = cpu_ldq_data_ra(env, addr + (1 << DF_DOUBLE), ra);
+ d0 = cpu_ldq_data_ra(env, addr + 0, ra);
+ d1 = cpu_ldq_data_ra(env, addr + 8, ra);
+ pwd->d[0] = d0;
+ pwd->d[1] = d1;
}
#define MSA_PAGESPAN(x) \
@@ -8344,41 +8327,9 @@ void helper_msa_st_b(CPUMIPSState *env, uint32_t wd,
ensure_writable_pages(env, addr, mmu_idx, ra);
-#if !defined(HOST_WORDS_BIGENDIAN)
- cpu_stb_data_ra(env, addr + (0 << DF_BYTE), pwd->b[0], ra);
- cpu_stb_data_ra(env, addr + (1 << DF_BYTE), pwd->b[1], ra);
- cpu_stb_data_ra(env, addr + (2 << DF_BYTE), pwd->b[2], ra);
- cpu_stb_data_ra(env, addr + (3 << DF_BYTE), pwd->b[3], ra);
- cpu_stb_data_ra(env, addr + (4 << DF_BYTE), pwd->b[4], ra);
- cpu_stb_data_ra(env, addr + (5 << DF_BYTE), pwd->b[5], ra);
- cpu_stb_data_ra(env, addr + (6 << DF_BYTE), pwd->b[6], ra);
- cpu_stb_data_ra(env, addr + (7 << DF_BYTE), pwd->b[7], ra);
- cpu_stb_data_ra(env, addr + (8 << DF_BYTE), pwd->b[8], ra);
- cpu_stb_data_ra(env, addr + (9 << DF_BYTE), pwd->b[9], ra);
- cpu_stb_data_ra(env, addr + (10 << DF_BYTE), pwd->b[10], ra);
- cpu_stb_data_ra(env, addr + (11 << DF_BYTE), pwd->b[11], ra);
- cpu_stb_data_ra(env, addr + (12 << DF_BYTE), pwd->b[12], ra);
- cpu_stb_data_ra(env, addr + (13 << DF_BYTE), pwd->b[13], ra);
- cpu_stb_data_ra(env, addr + (14 << DF_BYTE), pwd->b[14], ra);
- cpu_stb_data_ra(env, addr + (15 << DF_BYTE), pwd->b[15], ra);
-#else
- cpu_stb_data_ra(env, addr + (7 << DF_BYTE), pwd->b[0], ra);
- cpu_stb_data_ra(env, addr + (6 << DF_BYTE), pwd->b[1], ra);
- cpu_stb_data_ra(env, addr + (5 << DF_BYTE), pwd->b[2], ra);
- cpu_stb_data_ra(env, addr + (4 << DF_BYTE), pwd->b[3], ra);
- cpu_stb_data_ra(env, addr + (3 << DF_BYTE), pwd->b[4], ra);
- cpu_stb_data_ra(env, addr + (2 << DF_BYTE), pwd->b[5], ra);
- cpu_stb_data_ra(env, addr + (1 << DF_BYTE), pwd->b[6], ra);
- cpu_stb_data_ra(env, addr + (0 << DF_BYTE), pwd->b[7], ra);
- cpu_stb_data_ra(env, addr + (15 << DF_BYTE), pwd->b[8], ra);
- cpu_stb_data_ra(env, addr + (14 << DF_BYTE), pwd->b[9], ra);
- cpu_stb_data_ra(env, addr + (13 << DF_BYTE), pwd->b[10], ra);
- cpu_stb_data_ra(env, addr + (12 << DF_BYTE), pwd->b[11], ra);
- cpu_stb_data_ra(env, addr + (11 << DF_BYTE), pwd->b[12], ra);
- cpu_stb_data_ra(env, addr + (10 << DF_BYTE), pwd->b[13], ra);
- cpu_stb_data_ra(env, addr + (9 << DF_BYTE), pwd->b[14], ra);
- cpu_stb_data_ra(env, addr + (8 << DF_BYTE), pwd->b[15], ra);
-#endif
+ /* Store 8 bytes at a time. Vector element ordering makes this LE. */
+ cpu_stq_le_data_ra(env, addr + 0, pwd->d[0], ra);
+ cpu_stq_le_data_ra(env, addr + 0, pwd->d[1], ra);
}
void helper_msa_st_h(CPUMIPSState *env, uint32_t wd,
@@ -8387,28 +8338,19 @@ void helper_msa_st_h(CPUMIPSState *env, uint32_t wd,
wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
int mmu_idx = cpu_mmu_index(env, false);
uintptr_t ra = GETPC();
+ uint64_t d0, d1;
ensure_writable_pages(env, addr, mmu_idx, ra);
-#if !defined(HOST_WORDS_BIGENDIAN)
- cpu_stw_data_ra(env, addr + (0 << DF_HALF), pwd->h[0], ra);
- cpu_stw_data_ra(env, addr + (1 << DF_HALF), pwd->h[1], ra);
- cpu_stw_data_ra(env, addr + (2 << DF_HALF), pwd->h[2], ra);
- cpu_stw_data_ra(env, addr + (3 << DF_HALF), pwd->h[3], ra);
- cpu_stw_data_ra(env, addr + (4 << DF_HALF), pwd->h[4], ra);
- cpu_stw_data_ra(env, addr + (5 << DF_HALF), pwd->h[5], ra);
- cpu_stw_data_ra(env, addr + (6 << DF_HALF), pwd->h[6], ra);
- cpu_stw_data_ra(env, addr + (7 << DF_HALF), pwd->h[7], ra);
-#else
- cpu_stw_data_ra(env, addr + (3 << DF_HALF), pwd->h[0], ra);
- cpu_stw_data_ra(env, addr + (2 << DF_HALF), pwd->h[1], ra);
- cpu_stw_data_ra(env, addr + (1 << DF_HALF), pwd->h[2], ra);
- cpu_stw_data_ra(env, addr + (0 << DF_HALF), pwd->h[3], ra);
- cpu_stw_data_ra(env, addr + (7 << DF_HALF), pwd->h[4], ra);
- cpu_stw_data_ra(env, addr + (6 << DF_HALF), pwd->h[5], ra);
- cpu_stw_data_ra(env, addr + (5 << DF_HALF), pwd->h[6], ra);
- cpu_stw_data_ra(env, addr + (4 << DF_HALF), pwd->h[7], ra);
+ /* Store 8 bytes at a time. See helper_msa_ld_h. */
+ d0 = pwd->d[0];
+ d1 = pwd->d[1];
+#ifdef TARGET_WORDS_BIGENDIAN
+ d0 = bswap16x4(d0);
+ d1 = bswap16x4(d1);
#endif
+ cpu_stq_le_data_ra(env, addr + 0, d0, ra);
+ cpu_stq_le_data_ra(env, addr + 8, d1, ra);
}
void helper_msa_st_w(CPUMIPSState *env, uint32_t wd,
@@ -8417,20 +8359,19 @@ void helper_msa_st_w(CPUMIPSState *env, uint32_t wd,
wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
int mmu_idx = cpu_mmu_index(env, false);
uintptr_t ra = GETPC();
+ uint64_t d0, d1;
ensure_writable_pages(env, addr, mmu_idx, ra);
-#if !defined(HOST_WORDS_BIGENDIAN)
- cpu_stl_data_ra(env, addr + (0 << DF_WORD), pwd->w[0], ra);
- cpu_stl_data_ra(env, addr + (1 << DF_WORD), pwd->w[1], ra);
- cpu_stl_data_ra(env, addr + (2 << DF_WORD), pwd->w[2], ra);
- cpu_stl_data_ra(env, addr + (3 << DF_WORD), pwd->w[3], ra);
-#else
- cpu_stl_data_ra(env, addr + (1 << DF_WORD), pwd->w[0], ra);
- cpu_stl_data_ra(env, addr + (0 << DF_WORD), pwd->w[1], ra);
- cpu_stl_data_ra(env, addr + (3 << DF_WORD), pwd->w[2], ra);
- cpu_stl_data_ra(env, addr + (2 << DF_WORD), pwd->w[3], ra);
+ /* Store 8 bytes at a time. See helper_msa_ld_w. */
+ d0 = pwd->d[0];
+ d1 = pwd->d[1];
+#ifdef TARGET_WORDS_BIGENDIAN
+ d0 = bswap32x2(d0);
+ d1 = bswap32x2(d1);
#endif
+ cpu_stq_le_data_ra(env, addr + 0, d0, ra);
+ cpu_stq_le_data_ra(env, addr + 8, d1, ra);
}
void helper_msa_st_d(CPUMIPSState *env, uint32_t wd,
@@ -8442,6 +8383,6 @@ void helper_msa_st_d(CPUMIPSState *env, uint32_t wd,
ensure_writable_pages(env, addr, mmu_idx, GETPC());
- cpu_stq_data_ra(env, addr + (0 << DF_DOUBLE), pwd->d[0], ra);
- cpu_stq_data_ra(env, addr + (1 << DF_DOUBLE), pwd->d[1], ra);
+ cpu_stq_data_ra(env, addr + 0, pwd->d[0], ra);
+ cpu_stq_data_ra(env, addr + 8, pwd->d[1], ra);
}
--
2.25.1
^ permalink raw reply related [flat|nested] 102+ messages in thread* [PATCH for-6.2 36/43] target/s390x: Use cpu_*_mmu instead of helper_*_mmu
2021-07-29 0:46 [PATCH for-6.2 00/43] Unaligned accesses for user-only Richard Henderson
` (34 preceding siblings ...)
2021-07-29 0:46 ` [PATCH for-6.2 35/43] target/mips: Use 8-byte memory ops " Richard Henderson
@ 2021-07-29 0:46 ` Richard Henderson
2021-07-29 7:39 ` Philippe Mathieu-Daudé
2021-07-29 0:46 ` [PATCH for-6.2 37/43] target/sparc: " Richard Henderson
` (8 subsequent siblings)
44 siblings, 1 reply; 102+ messages in thread
From: Richard Henderson @ 2021-07-29 0:46 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-s390x
The helper_*_mmu functions were the only thing available
when this code was written. This could have been adjusted
when we added cpu_*_mmuidx_ra, but now we can most easily
use the newest set of interfaces.
Cc: qemu-s390x@nongnu.org
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/s390x/tcg/mem_helper.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/s390x/tcg/mem_helper.c b/target/s390x/tcg/mem_helper.c
index b20a82a914..4115cadbd7 100644
--- a/target/s390x/tcg/mem_helper.c
+++ b/target/s390x/tcg/mem_helper.c
@@ -248,13 +248,13 @@ static void do_access_memset(CPUS390XState *env, vaddr vaddr, char *haddr,
* page. This is especially relevant to speed up TLB_NOTDIRTY.
*/
g_assert(size > 0);
- helper_ret_stb_mmu(env, vaddr, byte, oi, ra);
+ cpu_stb_mmu(env, vaddr, byte, oi, ra);
haddr = tlb_vaddr_to_host(env, vaddr, MMU_DATA_STORE, mmu_idx);
if (likely(haddr)) {
memset(haddr + 1, byte, size - 1);
} else {
for (i = 1; i < size; i++) {
- helper_ret_stb_mmu(env, vaddr + i, byte, oi, ra);
+ cpu_stb_mmu(env, vaddr + i, byte, oi, ra);
}
}
}
@@ -290,7 +290,7 @@ static uint8_t do_access_get_byte(CPUS390XState *env, vaddr vaddr, char **haddr,
* Do a single access and test if we can then get access to the
* page. This is especially relevant to speed up TLB_NOTDIRTY.
*/
- byte = helper_ret_ldub_mmu(env, vaddr + offset, oi, ra);
+ byte = cpu_ldb_mmu(env, vaddr + offset, oi, ra);
*haddr = tlb_vaddr_to_host(env, vaddr, MMU_DATA_LOAD, mmu_idx);
return byte;
#endif
@@ -324,7 +324,7 @@ static void do_access_set_byte(CPUS390XState *env, vaddr vaddr, char **haddr,
* Do a single access and test if we can then get access to the
* page. This is especially relevant to speed up TLB_NOTDIRTY.
*/
- helper_ret_stb_mmu(env, vaddr + offset, byte, oi, ra);
+ cpu_stb_mmu(env, vaddr + offset, byte, oi, ra);
*haddr = tlb_vaddr_to_host(env, vaddr, MMU_DATA_STORE, mmu_idx);
#endif
}
--
2.25.1
^ permalink raw reply related [flat|nested] 102+ messages in thread* Re: [PATCH for-6.2 36/43] target/s390x: Use cpu_*_mmu instead of helper_*_mmu
2021-07-29 0:46 ` [PATCH for-6.2 36/43] target/s390x: Use cpu_*_mmu instead of helper_*_mmu Richard Henderson
@ 2021-07-29 7:39 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 102+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-07-29 7:39 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: qemu-s390x
On 7/29/21 2:46 AM, Richard Henderson wrote:
> The helper_*_mmu functions were the only thing available
> when this code was written. This could have been adjusted
> when we added cpu_*_mmuidx_ra, but now we can most easily
> use the newest set of interfaces.
>
> Cc: qemu-s390x@nongnu.org
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/s390x/tcg/mem_helper.c | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
^ permalink raw reply [flat|nested] 102+ messages in thread
* [PATCH for-6.2 37/43] target/sparc: Use cpu_*_mmu instead of helper_*_mmu
2021-07-29 0:46 [PATCH for-6.2 00/43] Unaligned accesses for user-only Richard Henderson
` (35 preceding siblings ...)
2021-07-29 0:46 ` [PATCH for-6.2 36/43] target/s390x: Use cpu_*_mmu instead of helper_*_mmu Richard Henderson
@ 2021-07-29 0:46 ` Richard Henderson
2021-07-29 0:46 ` [PATCH for-6.2 38/43] target/arm: " Richard Henderson
` (7 subsequent siblings)
44 siblings, 0 replies; 102+ messages in thread
From: Richard Henderson @ 2021-07-29 0:46 UTC (permalink / raw)
To: qemu-devel; +Cc: Mark Cave-Ayland
The helper_*_mmu functions were the only thing available
when this code was written. This could have been adjusted
when we added cpu_*_mmuidx_ra, but now we can most easily
use the newest set of interfaces.
Cc: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/sparc/ldst_helper.c | 14 +++++++-------
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/target/sparc/ldst_helper.c b/target/sparc/ldst_helper.c
index 5c558d312a..10979404ad 100644
--- a/target/sparc/ldst_helper.c
+++ b/target/sparc/ldst_helper.c
@@ -1328,27 +1328,27 @@ uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr,
oi = make_memop_idx(memop, idx);
switch (size) {
case 1:
- ret = helper_ret_ldub_mmu(env, addr, oi, GETPC());
+ ret = cpu_ldb_mmu(env, addr, oi, GETPC());
break;
case 2:
if (asi & 8) {
- ret = helper_le_lduw_mmu(env, addr, oi, GETPC());
+ ret = cpu_ldw_le_mmu(env, addr, oi, GETPC());
} else {
- ret = helper_be_lduw_mmu(env, addr, oi, GETPC());
+ ret = cpu_ldw_be_mmu(env, addr, oi, GETPC());
}
break;
case 4:
if (asi & 8) {
- ret = helper_le_ldul_mmu(env, addr, oi, GETPC());
+ ret = cpu_ldl_le_mmu(env, addr, oi, GETPC());
} else {
- ret = helper_be_ldul_mmu(env, addr, oi, GETPC());
+ ret = cpu_ldl_be_mmu(env, addr, oi, GETPC());
}
break;
case 8:
if (asi & 8) {
- ret = helper_le_ldq_mmu(env, addr, oi, GETPC());
+ ret = cpu_ldq_le_mmu(env, addr, oi, GETPC());
} else {
- ret = helper_be_ldq_mmu(env, addr, oi, GETPC());
+ ret = cpu_ldq_be_mmu(env, addr, oi, GETPC());
}
break;
default:
--
2.25.1
^ permalink raw reply related [flat|nested] 102+ messages in thread* [PATCH for-6.2 38/43] target/arm: Use cpu_*_mmu instead of helper_*_mmu
2021-07-29 0:46 [PATCH for-6.2 00/43] Unaligned accesses for user-only Richard Henderson
` (36 preceding siblings ...)
2021-07-29 0:46 ` [PATCH for-6.2 37/43] target/sparc: " Richard Henderson
@ 2021-07-29 0:46 ` Richard Henderson
2021-07-29 7:41 ` Philippe Mathieu-Daudé
2021-07-29 0:46 ` [PATCH for-6.2 39/43] tcg: Move helper_*_mmu decls to tcg/tcg-ldst.h Richard Henderson
` (6 subsequent siblings)
44 siblings, 1 reply; 102+ messages in thread
From: Richard Henderson @ 2021-07-29 0:46 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm
The helper_*_mmu functions were the only thing available
when this code was written. This could have been adjusted
when we added cpu_*_mmuidx_ra, but now we can most easily
use the newest set of interfaces.
Cc: qemu-arm@nongnu.org
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/helper-a64.c | 52 +++++++----------------------------------
target/arm/m_helper.c | 6 ++---
2 files changed, 11 insertions(+), 47 deletions(-)
diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
index f1a4089a4f..17c0ebebb2 100644
--- a/target/arm/helper-a64.c
+++ b/target/arm/helper-a64.c
@@ -512,37 +512,19 @@ uint64_t HELPER(paired_cmpxchg64_le)(CPUARMState *env, uint64_t addr,
uintptr_t ra = GETPC();
uint64_t o0, o1;
bool success;
-
-#ifdef CONFIG_USER_ONLY
- /* ??? Enforce alignment. */
- uint64_t *haddr = g2h(env_cpu(env), addr);
-
- set_helper_retaddr(ra);
- o0 = ldq_le_p(haddr + 0);
- o1 = ldq_le_p(haddr + 1);
- oldv = int128_make128(o0, o1);
-
- success = int128_eq(oldv, cmpv);
- if (success) {
- stq_le_p(haddr + 0, int128_getlo(newv));
- stq_le_p(haddr + 1, int128_gethi(newv));
- }
- clear_helper_retaddr();
-#else
int mem_idx = cpu_mmu_index(env, false);
MemOpIdx oi0 = make_memop_idx(MO_LEQ | MO_ALIGN_16, mem_idx);
MemOpIdx oi1 = make_memop_idx(MO_LEQ, mem_idx);
- o0 = helper_le_ldq_mmu(env, addr + 0, oi0, ra);
- o1 = helper_le_ldq_mmu(env, addr + 8, oi1, ra);
+ o0 = cpu_ldq_le_mmu(env, addr + 0, oi0, ra);
+ o1 = cpu_ldq_le_mmu(env, addr + 8, oi1, ra);
oldv = int128_make128(o0, o1);
success = int128_eq(oldv, cmpv);
if (success) {
- helper_le_stq_mmu(env, addr + 0, int128_getlo(newv), oi1, ra);
- helper_le_stq_mmu(env, addr + 8, int128_gethi(newv), oi1, ra);
+ cpu_stq_le_mmu(env, addr + 0, int128_getlo(newv), oi1, ra);
+ cpu_stq_le_mmu(env, addr + 8, int128_gethi(newv), oi1, ra);
}
-#endif
return !success;
}
@@ -582,37 +564,19 @@ uint64_t HELPER(paired_cmpxchg64_be)(CPUARMState *env, uint64_t addr,
uintptr_t ra = GETPC();
uint64_t o0, o1;
bool success;
-
-#ifdef CONFIG_USER_ONLY
- /* ??? Enforce alignment. */
- uint64_t *haddr = g2h(env_cpu(env), addr);
-
- set_helper_retaddr(ra);
- o1 = ldq_be_p(haddr + 0);
- o0 = ldq_be_p(haddr + 1);
- oldv = int128_make128(o0, o1);
-
- success = int128_eq(oldv, cmpv);
- if (success) {
- stq_be_p(haddr + 0, int128_gethi(newv));
- stq_be_p(haddr + 1, int128_getlo(newv));
- }
- clear_helper_retaddr();
-#else
int mem_idx = cpu_mmu_index(env, false);
MemOpIdx oi0 = make_memop_idx(MO_BEQ | MO_ALIGN_16, mem_idx);
MemOpIdx oi1 = make_memop_idx(MO_BEQ, mem_idx);
- o1 = helper_be_ldq_mmu(env, addr + 0, oi0, ra);
- o0 = helper_be_ldq_mmu(env, addr + 8, oi1, ra);
+ o1 = cpu_ldq_be_mmu(env, addr + 0, oi0, ra);
+ o0 = cpu_ldq_be_mmu(env, addr + 8, oi1, ra);
oldv = int128_make128(o0, o1);
success = int128_eq(oldv, cmpv);
if (success) {
- helper_be_stq_mmu(env, addr + 0, int128_gethi(newv), oi1, ra);
- helper_be_stq_mmu(env, addr + 8, int128_getlo(newv), oi1, ra);
+ cpu_stq_be_mmu(env, addr + 0, int128_gethi(newv), oi1, ra);
+ cpu_stq_be_mmu(env, addr + 8, int128_getlo(newv), oi1, ra);
}
-#endif
return !success;
}
diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
index efb522dc44..b6019595f5 100644
--- a/target/arm/m_helper.c
+++ b/target/arm/m_helper.c
@@ -1947,9 +1947,9 @@ static bool do_v7m_function_return(ARMCPU *cpu)
* do them as secure, so work out what MMU index that is.
*/
mmu_idx = arm_v7m_mmu_idx_for_secstate(env, true);
- oi = make_memop_idx(MO_LE, arm_to_core_mmu_idx(mmu_idx));
- newpc = helper_le_ldul_mmu(env, frameptr, oi, 0);
- newpsr = helper_le_ldul_mmu(env, frameptr + 4, oi, 0);
+ oi = make_memop_idx(MO_LEUL, arm_to_core_mmu_idx(mmu_idx));
+ newpc = cpu_ldl_le_mmu(env, frameptr, oi, 0);
+ newpsr = cpu_ldl_le_mmu(env, frameptr + 4, oi, 0);
/* Consistency checks on new IPSR */
newpsr_exc = newpsr & XPSR_EXCP;
--
2.25.1
^ permalink raw reply related [flat|nested] 102+ messages in thread* Re: [PATCH for-6.2 38/43] target/arm: Use cpu_*_mmu instead of helper_*_mmu
2021-07-29 0:46 ` [PATCH for-6.2 38/43] target/arm: " Richard Henderson
@ 2021-07-29 7:41 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 102+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-07-29 7:41 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: qemu-arm
On 7/29/21 2:46 AM, Richard Henderson wrote:
> The helper_*_mmu functions were the only thing available
> when this code was written. This could have been adjusted
> when we added cpu_*_mmuidx_ra, but now we can most easily
> use the newest set of interfaces.
>
> Cc: qemu-arm@nongnu.org
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/arm/helper-a64.c | 52 +++++++----------------------------------
> target/arm/m_helper.c | 6 ++---
> 2 files changed, 11 insertions(+), 47 deletions(-)
Nice.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
^ permalink raw reply [flat|nested] 102+ messages in thread
* [PATCH for-6.2 39/43] tcg: Move helper_*_mmu decls to tcg/tcg-ldst.h
2021-07-29 0:46 [PATCH for-6.2 00/43] Unaligned accesses for user-only Richard Henderson
` (37 preceding siblings ...)
2021-07-29 0:46 ` [PATCH for-6.2 38/43] target/arm: " Richard Henderson
@ 2021-07-29 0:46 ` Richard Henderson
2021-07-29 7:42 ` Philippe Mathieu-Daudé
2021-07-29 0:46 ` [PATCH for-6.2 40/43] linux-user/alpha: Remove TARGET_ALIGNED_ONLY Richard Henderson
` (5 subsequent siblings)
44 siblings, 1 reply; 102+ messages in thread
From: Richard Henderson @ 2021-07-29 0:46 UTC (permalink / raw)
To: qemu-devel
These functions have been replaced by cpu_*_mmu as the
most proper interface to use from target code.
Hide these declarations from code that should not use them.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/tcg/tcg-ldst.h | 74 ++++++++++++++++++++++++++++++++++++++++++
include/tcg/tcg.h | 71 ----------------------------------------
accel/tcg/cputlb.c | 1 +
tcg/tcg.c | 1 +
tcg/tci.c | 1 +
5 files changed, 77 insertions(+), 71 deletions(-)
create mode 100644 include/tcg/tcg-ldst.h
diff --git a/include/tcg/tcg-ldst.h b/include/tcg/tcg-ldst.h
new file mode 100644
index 0000000000..8c86365611
--- /dev/null
+++ b/include/tcg/tcg-ldst.h
@@ -0,0 +1,74 @@
+/*
+ * Memory helpers that will be used by TCG generated code.
+ *
+ * Copyright (c) 2008 Fabrice Bellard
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef TCG_LDST_H
+#define TCG_LDST_H 1
+
+#ifdef CONFIG_SOFTMMU
+
+/* Value zero-extended to tcg register size. */
+tcg_target_ulong helper_ret_ldub_mmu(CPUArchState *env, target_ulong addr,
+ MemOpIdx oi, uintptr_t retaddr);
+tcg_target_ulong helper_le_lduw_mmu(CPUArchState *env, target_ulong addr,
+ MemOpIdx oi, uintptr_t retaddr);
+tcg_target_ulong helper_le_ldul_mmu(CPUArchState *env, target_ulong addr,
+ MemOpIdx oi, uintptr_t retaddr);
+uint64_t helper_le_ldq_mmu(CPUArchState *env, target_ulong addr,
+ MemOpIdx oi, uintptr_t retaddr);
+tcg_target_ulong helper_be_lduw_mmu(CPUArchState *env, target_ulong addr,
+ MemOpIdx oi, uintptr_t retaddr);
+tcg_target_ulong helper_be_ldul_mmu(CPUArchState *env, target_ulong addr,
+ MemOpIdx oi, uintptr_t retaddr);
+uint64_t helper_be_ldq_mmu(CPUArchState *env, target_ulong addr,
+ MemOpIdx oi, uintptr_t retaddr);
+
+/* Value sign-extended to tcg register size. */
+tcg_target_ulong helper_ret_ldsb_mmu(CPUArchState *env, target_ulong addr,
+ MemOpIdx oi, uintptr_t retaddr);
+tcg_target_ulong helper_le_ldsw_mmu(CPUArchState *env, target_ulong addr,
+ MemOpIdx oi, uintptr_t retaddr);
+tcg_target_ulong helper_le_ldsl_mmu(CPUArchState *env, target_ulong addr,
+ MemOpIdx oi, uintptr_t retaddr);
+tcg_target_ulong helper_be_ldsw_mmu(CPUArchState *env, target_ulong addr,
+ MemOpIdx oi, uintptr_t retaddr);
+tcg_target_ulong helper_be_ldsl_mmu(CPUArchState *env, target_ulong addr,
+ MemOpIdx oi, uintptr_t retaddr);
+
+void helper_ret_stb_mmu(CPUArchState *env, target_ulong addr, uint8_t val,
+ MemOpIdx oi, uintptr_t retaddr);
+void helper_le_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val,
+ MemOpIdx oi, uintptr_t retaddr);
+void helper_le_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val,
+ MemOpIdx oi, uintptr_t retaddr);
+void helper_le_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val,
+ MemOpIdx oi, uintptr_t retaddr);
+void helper_be_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val,
+ MemOpIdx oi, uintptr_t retaddr);
+void helper_be_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val,
+ MemOpIdx oi, uintptr_t retaddr);
+void helper_be_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val,
+ MemOpIdx oi, uintptr_t retaddr);
+
+#endif /* CONFIG_SOFTMMU */
+#endif /* TCG_LDST_H */
diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h
index 114ad66b25..82b4abfa31 100644
--- a/include/tcg/tcg.h
+++ b/include/tcg/tcg.h
@@ -1234,77 +1234,6 @@ uint64_t dup_const(unsigned vece, uint64_t c);
: (qemu_build_not_reached_always(), 0)) \
: dup_const(VECE, C))
-/*
- * Memory helpers that will be used by TCG generated code.
- */
-#ifdef CONFIG_SOFTMMU
-/* Value zero-extended to tcg register size. */
-tcg_target_ulong helper_ret_ldub_mmu(CPUArchState *env, target_ulong addr,
- MemOpIdx oi, uintptr_t retaddr);
-tcg_target_ulong helper_le_lduw_mmu(CPUArchState *env, target_ulong addr,
- MemOpIdx oi, uintptr_t retaddr);
-tcg_target_ulong helper_le_ldul_mmu(CPUArchState *env, target_ulong addr,
- MemOpIdx oi, uintptr_t retaddr);
-uint64_t helper_le_ldq_mmu(CPUArchState *env, target_ulong addr,
- MemOpIdx oi, uintptr_t retaddr);
-tcg_target_ulong helper_be_lduw_mmu(CPUArchState *env, target_ulong addr,
- MemOpIdx oi, uintptr_t retaddr);
-tcg_target_ulong helper_be_ldul_mmu(CPUArchState *env, target_ulong addr,
- MemOpIdx oi, uintptr_t retaddr);
-uint64_t helper_be_ldq_mmu(CPUArchState *env, target_ulong addr,
- MemOpIdx oi, uintptr_t retaddr);
-
-/* Value sign-extended to tcg register size. */
-tcg_target_ulong helper_ret_ldsb_mmu(CPUArchState *env, target_ulong addr,
- MemOpIdx oi, uintptr_t retaddr);
-tcg_target_ulong helper_le_ldsw_mmu(CPUArchState *env, target_ulong addr,
- MemOpIdx oi, uintptr_t retaddr);
-tcg_target_ulong helper_le_ldsl_mmu(CPUArchState *env, target_ulong addr,
- MemOpIdx oi, uintptr_t retaddr);
-tcg_target_ulong helper_be_ldsw_mmu(CPUArchState *env, target_ulong addr,
- MemOpIdx oi, uintptr_t retaddr);
-tcg_target_ulong helper_be_ldsl_mmu(CPUArchState *env, target_ulong addr,
- MemOpIdx oi, uintptr_t retaddr);
-
-void helper_ret_stb_mmu(CPUArchState *env, target_ulong addr, uint8_t val,
- MemOpIdx oi, uintptr_t retaddr);
-void helper_le_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val,
- MemOpIdx oi, uintptr_t retaddr);
-void helper_le_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val,
- MemOpIdx oi, uintptr_t retaddr);
-void helper_le_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val,
- MemOpIdx oi, uintptr_t retaddr);
-void helper_be_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val,
- MemOpIdx oi, uintptr_t retaddr);
-void helper_be_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val,
- MemOpIdx oi, uintptr_t retaddr);
-void helper_be_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val,
- MemOpIdx oi, uintptr_t retaddr);
-
-/* Temporary aliases until backends are converted. */
-#ifdef TARGET_WORDS_BIGENDIAN
-# define helper_ret_ldsw_mmu helper_be_ldsw_mmu
-# define helper_ret_lduw_mmu helper_be_lduw_mmu
-# define helper_ret_ldsl_mmu helper_be_ldsl_mmu
-# define helper_ret_ldul_mmu helper_be_ldul_mmu
-# define helper_ret_ldl_mmu helper_be_ldul_mmu
-# define helper_ret_ldq_mmu helper_be_ldq_mmu
-# define helper_ret_stw_mmu helper_be_stw_mmu
-# define helper_ret_stl_mmu helper_be_stl_mmu
-# define helper_ret_stq_mmu helper_be_stq_mmu
-#else
-# define helper_ret_ldsw_mmu helper_le_ldsw_mmu
-# define helper_ret_lduw_mmu helper_le_lduw_mmu
-# define helper_ret_ldsl_mmu helper_le_ldsl_mmu
-# define helper_ret_ldul_mmu helper_le_ldul_mmu
-# define helper_ret_ldl_mmu helper_le_ldul_mmu
-# define helper_ret_ldq_mmu helper_le_ldq_mmu
-# define helper_ret_stw_mmu helper_le_stw_mmu
-# define helper_ret_stl_mmu helper_le_stl_mmu
-# define helper_ret_stq_mmu helper_le_stq_mmu
-#endif
-#endif /* CONFIG_SOFTMMU */
-
#ifdef CONFIG_DEBUG_TCG
void tcg_assert_listed_vecop(TCGOpcode);
#else
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index b350cafa3d..b69a953447 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -39,6 +39,7 @@
#ifdef CONFIG_PLUGIN
#include "qemu/plugin-memory.h"
#endif
+#include "tcg/tcg-ldst.h"
/* DEBUG defines, enable DEBUG_TLB_LOG to log to the CPU_LOG_MMU target */
/* #define DEBUG_TLB */
diff --git a/tcg/tcg.c b/tcg/tcg.c
index 658be0c6b6..024a22cf39 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -58,6 +58,7 @@
#include "elf.h"
#include "exec/log.h"
+#include "tcg/tcg-ldst.h"
#include "tcg-internal.h"
#ifdef CONFIG_TCG_INTERPRETER
diff --git a/tcg/tci.c b/tcg/tci.c
index 5c08dc0a9a..e76087ccac 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -22,6 +22,7 @@
#include "tcg/tcg.h" /* MAX_OPC_PARAM_IARGS */
#include "exec/cpu_ldst.h"
#include "tcg/tcg-op.h"
+#include "tcg/tcg-ldst.h"
#include "qemu/compiler.h"
#include <ffi.h>
--
2.25.1
^ permalink raw reply related [flat|nested] 102+ messages in thread* Re: [PATCH for-6.2 39/43] tcg: Move helper_*_mmu decls to tcg/tcg-ldst.h
2021-07-29 0:46 ` [PATCH for-6.2 39/43] tcg: Move helper_*_mmu decls to tcg/tcg-ldst.h Richard Henderson
@ 2021-07-29 7:42 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 102+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-07-29 7:42 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
On 7/29/21 2:46 AM, Richard Henderson wrote:
> These functions have been replaced by cpu_*_mmu as the
> most proper interface to use from target code.
>
> Hide these declarations from code that should not use them.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> include/tcg/tcg-ldst.h | 74 ++++++++++++++++++++++++++++++++++++++++++
> include/tcg/tcg.h | 71 ----------------------------------------
> accel/tcg/cputlb.c | 1 +
> tcg/tcg.c | 1 +
> tcg/tci.c | 1 +
> 5 files changed, 77 insertions(+), 71 deletions(-)
> create mode 100644 include/tcg/tcg-ldst.h
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
^ permalink raw reply [flat|nested] 102+ messages in thread
* [PATCH for-6.2 40/43] linux-user/alpha: Remove TARGET_ALIGNED_ONLY
2021-07-29 0:46 [PATCH for-6.2 00/43] Unaligned accesses for user-only Richard Henderson
` (38 preceding siblings ...)
2021-07-29 0:46 ` [PATCH for-6.2 39/43] tcg: Move helper_*_mmu decls to tcg/tcg-ldst.h Richard Henderson
@ 2021-07-29 0:46 ` Richard Henderson
2021-07-29 0:46 ` [PATCH for-6.2 41/43] tcg: Add helper_unaligned_mmu for user-only sigbus Richard Henderson
` (4 subsequent siblings)
44 siblings, 0 replies; 102+ messages in thread
From: Richard Henderson @ 2021-07-29 0:46 UTC (permalink / raw)
To: qemu-devel
By default, the Linux kernel fixes up unaligned accesses.
Therefore, as the kernel surrogate, qemu should as well.
No fixups are done for load-locked/store-conditional, so
mark those as MO_ALIGN.
There is a syscall to disable this, and (among other things)
deliver SIGBUS, but it is essentially unused. A survey of
open source code shows no uses of SSI_NVPAIRS except trivial
examples that show how to disable unaligned fixups.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
configs/targets/alpha-linux-user.mak | 1 -
target/alpha/translate.c | 8 ++++----
2 files changed, 4 insertions(+), 5 deletions(-)
diff --git a/configs/targets/alpha-linux-user.mak b/configs/targets/alpha-linux-user.mak
index 7e62fd796a..f7d3fb4afa 100644
--- a/configs/targets/alpha-linux-user.mak
+++ b/configs/targets/alpha-linux-user.mak
@@ -1,4 +1,3 @@
TARGET_ARCH=alpha
TARGET_SYSTBL_ABI=common
TARGET_SYSTBL=syscall.tbl
-TARGET_ALIGNED_ONLY=y
diff --git a/target/alpha/translate.c b/target/alpha/translate.c
index de6c0a8439..8c60e90114 100644
--- a/target/alpha/translate.c
+++ b/target/alpha/translate.c
@@ -293,14 +293,14 @@ static inline void gen_qemu_lds(TCGv t0, TCGv t1, int flags)
static inline void gen_qemu_ldl_l(TCGv t0, TCGv t1, int flags)
{
- tcg_gen_qemu_ld_i64(t0, t1, flags, MO_LESL);
+ tcg_gen_qemu_ld_i64(t0, t1, flags, MO_LESL | MO_ALIGN);
tcg_gen_mov_i64(cpu_lock_addr, t1);
tcg_gen_mov_i64(cpu_lock_value, t0);
}
static inline void gen_qemu_ldq_l(TCGv t0, TCGv t1, int flags)
{
- tcg_gen_qemu_ld_i64(t0, t1, flags, MO_LEQ);
+ tcg_gen_qemu_ld_i64(t0, t1, flags, MO_LEQ | MO_ALIGN);
tcg_gen_mov_i64(cpu_lock_addr, t1);
tcg_gen_mov_i64(cpu_lock_value, t0);
}
@@ -2840,12 +2840,12 @@ static DisasJumpType translate_one(DisasContext *ctx, uint32_t insn)
case 0x2E:
/* STL_C */
ret = gen_store_conditional(ctx, ra, rb, disp16,
- ctx->mem_idx, MO_LESL);
+ ctx->mem_idx, MO_LESL | MO_ALIGN);
break;
case 0x2F:
/* STQ_C */
ret = gen_store_conditional(ctx, ra, rb, disp16,
- ctx->mem_idx, MO_LEQ);
+ ctx->mem_idx, MO_LEQ | MO_ALIGN);
break;
case 0x30:
/* BR */
--
2.25.1
^ permalink raw reply related [flat|nested] 102+ messages in thread* [PATCH for-6.2 41/43] tcg: Add helper_unaligned_mmu for user-only sigbus
2021-07-29 0:46 [PATCH for-6.2 00/43] Unaligned accesses for user-only Richard Henderson
` (39 preceding siblings ...)
2021-07-29 0:46 ` [PATCH for-6.2 40/43] linux-user/alpha: Remove TARGET_ALIGNED_ONLY Richard Henderson
@ 2021-07-29 0:46 ` Richard Henderson
2021-07-29 0:46 ` [PATCH for-6.2 42/43] tcg/i386: Support raising sigbus for user-only Richard Henderson
` (3 subsequent siblings)
44 siblings, 0 replies; 102+ messages in thread
From: Richard Henderson @ 2021-07-29 0:46 UTC (permalink / raw)
To: qemu-devel
To be called from tcg generated code on hosts that support
unaligned accesses natively, in response to an access that
is supposed to be aligned.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/tcg/tcg-ldst.h | 5 +++++
accel/tcg/user-exec.c | 13 ++++++++++---
2 files changed, 15 insertions(+), 3 deletions(-)
diff --git a/include/tcg/tcg-ldst.h b/include/tcg/tcg-ldst.h
index 8c86365611..a934bed042 100644
--- a/include/tcg/tcg-ldst.h
+++ b/include/tcg/tcg-ldst.h
@@ -70,5 +70,10 @@ void helper_be_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val,
void helper_be_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val,
MemOpIdx oi, uintptr_t retaddr);
+#else
+
+void QEMU_NORETURN helper_unaligned_mmu(CPUArchState *env, target_ulong addr,
+ uint32_t type, uintptr_t ra);
+
#endif /* CONFIG_SOFTMMU */
#endif /* TCG_LDST_H */
diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
index e8a82dd43f..5cbae7a7cc 100644
--- a/accel/tcg/user-exec.c
+++ b/accel/tcg/user-exec.c
@@ -27,6 +27,7 @@
#include "exec/helper-proto.h"
#include "qemu/atomic128.h"
#include "trace/trace-root.h"
+#include "tcg/tcg-ldst.h"
#undef EAX
#undef ECX
@@ -866,9 +867,9 @@ static void validate_memop(MemOpIdx oi, MemOp expected)
#endif
}
-static void cpu_unaligned_access(CPUState *cpu, vaddr addr,
- MMUAccessType access_type,
- int mmu_idx, uintptr_t ra)
+static void QEMU_NORETURN
+cpu_unaligned_access(CPUState *cpu, vaddr addr, MMUAccessType access_type,
+ int mmu_idx, uintptr_t ra)
{
CPUClass *cc = CPU_GET_CLASS(cpu);
@@ -876,6 +877,12 @@ static void cpu_unaligned_access(CPUState *cpu, vaddr addr,
g_assert_not_reached();
}
+void helper_unaligned_mmu(CPUArchState *env, target_ulong addr,
+ uint32_t access_type, uintptr_t ra)
+{
+ cpu_unaligned_access(env_cpu(env), addr, access_type, MMU_USER_IDX, ra);
+}
+
static void *cpu_mmu_lookup(CPUArchState *env, target_ulong addr,
MemOpIdx oi, uintptr_t ra, MMUAccessType type)
{
--
2.25.1
^ permalink raw reply related [flat|nested] 102+ messages in thread* [PATCH for-6.2 42/43] tcg/i386: Support raising sigbus for user-only
2021-07-29 0:46 [PATCH for-6.2 00/43] Unaligned accesses for user-only Richard Henderson
` (40 preceding siblings ...)
2021-07-29 0:46 ` [PATCH for-6.2 41/43] tcg: Add helper_unaligned_mmu for user-only sigbus Richard Henderson
@ 2021-07-29 0:46 ` Richard Henderson
2021-07-29 0:46 ` [PATCH for-6.2 43/43] tests/tcg/multiarch: Add sigbus.c Richard Henderson
` (2 subsequent siblings)
44 siblings, 0 replies; 102+ messages in thread
From: Richard Henderson @ 2021-07-29 0:46 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/i386/tcg-target.h | 2 -
tcg/i386/tcg-target.c.inc | 114 ++++++++++++++++++++++++++++++++++++--
2 files changed, 110 insertions(+), 6 deletions(-)
diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h
index b00a6da293..3b2c9437a0 100644
--- a/tcg/i386/tcg-target.h
+++ b/tcg/i386/tcg-target.h
@@ -232,9 +232,7 @@ static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx,
#define TCG_TARGET_HAS_MEMORY_BSWAP have_movbe
-#ifdef CONFIG_SOFTMMU
#define TCG_TARGET_NEED_LDST_LABELS
-#endif
#define TCG_TARGET_NEED_POOL_LABELS
#endif
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
index 1e42a877fb..4abf612891 100644
--- a/tcg/i386/tcg-target.c.inc
+++ b/tcg/i386/tcg-target.c.inc
@@ -420,8 +420,9 @@ static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
#define OPC_VZEROUPPER (0x77 | P_EXT)
#define OPC_XCHG_ax_r32 (0x90)
-#define OPC_GRP3_Ev (0xf7)
-#define OPC_GRP5 (0xff)
+#define OPC_GRP3_Eb (0xf6)
+#define OPC_GRP3_Ev (0xf7)
+#define OPC_GRP5 (0xff)
#define OPC_GRP14 (0x73 | P_EXT | P_DATA16)
/* Group 1 opcode extensions for 0x80-0x83.
@@ -443,6 +444,7 @@ static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
#define SHIFT_SAR 7
/* Group 3 opcode extensions for 0xf6, 0xf7. To be used with OPC_GRP3. */
+#define EXT3_TESTi 0
#define EXT3_NOT 2
#define EXT3_NEG 3
#define EXT3_MUL 4
@@ -1604,9 +1606,9 @@ static void tcg_out_nopn(TCGContext *s, int n)
tcg_out8(s, 0x90);
}
-#if defined(CONFIG_SOFTMMU)
#include "../tcg-ldst.c.inc"
+#if defined(CONFIG_SOFTMMU)
/* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr,
* int mmu_idx, uintptr_t ra)
*/
@@ -1915,7 +1917,96 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
tcg_out_jmp(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)]);
return true;
}
-#elif TCG_TARGET_REG_BITS == 32
+#else
+
+static void tcg_out_test_alignment(TCGContext *s, bool is_ld, TCGReg addrlo,
+ TCGReg addrhi, unsigned a_bits)
+{
+ unsigned a_mask = (1 << a_bits) - 1;
+ TCGLabelQemuLdst *label;
+
+ /*
+ * We are expecting a_bits to max out at 7, so we can usually use testb.
+ * For i686, we have to use testl for %esi/%edi.
+ */
+ if (a_mask <= 0xff && (TCG_TARGET_REG_BITS == 64 || addrlo < 4)) {
+ tcg_out_modrm(s, OPC_GRP3_Eb, EXT3_TESTi, addrlo);
+ tcg_out8(s, a_mask);
+ } else {
+ tcg_out_modrm(s, OPC_GRP3_Ev, EXT3_TESTi, addrlo);
+ tcg_out32(s, a_mask);
+ }
+
+ /* jne slow_path */
+ tcg_out_opc(s, OPC_JCC_long + JCC_JNE, 0, 0, 0);
+
+ label = new_ldst_label(s);
+ label->is_ld = is_ld;
+ label->addrlo_reg = addrlo;
+ label->addrhi_reg = addrhi;
+ label->raddr = tcg_splitwx_to_rx(s->code_ptr + 4);
+ label->label_ptr[0] = s->code_ptr;
+
+ s->code_ptr += 4;
+}
+
+static bool tcg_out_fail_alignment(TCGContext *s, TCGLabelQemuLdst *l)
+{
+ MMUAccessType type = l->is_ld ? MMU_DATA_LOAD : MMU_DATA_STORE;
+ TCGReg retaddr;
+
+ /* resolve label address */
+ tcg_patch32(l->label_ptr[0], s->code_ptr - l->label_ptr[0] - 4);
+
+ if (TCG_TARGET_REG_BITS == 32) {
+ int ofs = 0;
+
+ tcg_out_st(s, TCG_TYPE_PTR, TCG_AREG0, TCG_REG_ESP, ofs);
+ ofs += 4;
+
+ tcg_out_st(s, TCG_TYPE_I32, l->addrlo_reg, TCG_REG_ESP, ofs);
+ ofs += 4;
+ if (TARGET_LONG_BITS == 64) {
+ tcg_out_st(s, TCG_TYPE_I32, l->addrhi_reg, TCG_REG_ESP, ofs);
+ ofs += 4;
+ }
+
+ tcg_out_sti(s, TCG_TYPE_I32, type, TCG_REG_ESP, ofs);
+
+ retaddr = TCG_REG_EAX;
+ tcg_out_movi(s, TCG_TYPE_PTR, retaddr, (uintptr_t)l->raddr);
+ tcg_out_st(s, TCG_TYPE_PTR, retaddr, TCG_REG_ESP, ofs);
+ } else {
+ tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0], TCG_AREG0);
+ tcg_out_mov(s, TCG_TYPE_TL, tcg_target_call_iarg_regs[1],
+ l->addrlo_reg);
+ tcg_out_movi(s, TCG_TYPE_I32, tcg_target_call_iarg_regs[2], type);
+
+ retaddr = tcg_target_call_iarg_regs[3];
+ tcg_out_movi(s, TCG_TYPE_PTR, retaddr, (uintptr_t)l->raddr);
+ }
+
+ /*
+ * "Tail call" to the helper, with the return address back inline,
+ * just for the clarity of the debugging traceback -- the helper
+ * cannot return.
+ */
+ tcg_out_push(s, retaddr);
+ tcg_out_jmp(s, (const void *)helper_unaligned_mmu);
+ return true;
+}
+
+static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
+{
+ return tcg_out_fail_alignment(s, l);
+}
+
+static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
+{
+ return tcg_out_fail_alignment(s, l);
+}
+
+#if TCG_TARGET_REG_BITS == 32
# define x86_guest_base_seg 0
# define x86_guest_base_index -1
# define x86_guest_base_offset guest_base
@@ -1949,6 +2040,7 @@ static inline int setup_guest_base_seg(void)
return 0;
}
# endif
+#endif
#endif /* SOFTMMU */
static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg datalo, TCGReg datahi,
@@ -2058,6 +2150,8 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is64)
#if defined(CONFIG_SOFTMMU)
int mem_index;
tcg_insn_unit *label_ptr[2];
+#else
+ unsigned a_bits;
#endif
datalo = *args++;
@@ -2080,6 +2174,11 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is64)
add_qemu_ldst_label(s, true, is64, oi, datalo, datahi, addrlo, addrhi,
s->code_ptr, label_ptr);
#else
+ a_bits = get_alignment_bits(opc);
+ if (a_bits) {
+ tcg_out_test_alignment(s, true, addrlo, addrhi, a_bits);
+ }
+
tcg_out_qemu_ld_direct(s, datalo, datahi, addrlo, x86_guest_base_index,
x86_guest_base_offset, x86_guest_base_seg,
is64, opc);
@@ -2147,6 +2246,8 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is64)
#if defined(CONFIG_SOFTMMU)
int mem_index;
tcg_insn_unit *label_ptr[2];
+#else
+ unsigned a_bits;
#endif
datalo = *args++;
@@ -2169,6 +2270,11 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is64)
add_qemu_ldst_label(s, false, is64, oi, datalo, datahi, addrlo, addrhi,
s->code_ptr, label_ptr);
#else
+ a_bits = get_alignment_bits(opc);
+ if (a_bits) {
+ tcg_out_test_alignment(s, false, addrlo, addrhi, a_bits);
+ }
+
tcg_out_qemu_st_direct(s, datalo, datahi, addrlo, x86_guest_base_index,
x86_guest_base_offset, x86_guest_base_seg, opc);
#endif
--
2.25.1
^ permalink raw reply related [flat|nested] 102+ messages in thread* [PATCH for-6.2 43/43] tests/tcg/multiarch: Add sigbus.c
2021-07-29 0:46 [PATCH for-6.2 00/43] Unaligned accesses for user-only Richard Henderson
` (41 preceding siblings ...)
2021-07-29 0:46 ` [PATCH for-6.2 42/43] tcg/i386: Support raising sigbus for user-only Richard Henderson
@ 2021-07-29 0:46 ` Richard Henderson
2021-07-29 6:14 ` [PATCH for-6.2 00/43] Unaligned accesses for user-only Philippe Mathieu-Daudé
2021-08-02 13:14 ` Peter Maydell
44 siblings, 0 replies; 102+ messages in thread
From: Richard Henderson @ 2021-07-29 0:46 UTC (permalink / raw)
To: qemu-devel
A mostly generic test for unaligned access raising SIGBUS.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tests/tcg/multiarch/sigbus.c | 68 ++++++++++++++++++++++++++++++++++++
1 file changed, 68 insertions(+)
create mode 100644 tests/tcg/multiarch/sigbus.c
diff --git a/tests/tcg/multiarch/sigbus.c b/tests/tcg/multiarch/sigbus.c
new file mode 100644
index 0000000000..8134c5fd56
--- /dev/null
+++ b/tests/tcg/multiarch/sigbus.c
@@ -0,0 +1,68 @@
+#define _GNU_SOURCE 1
+
+#include <assert.h>
+#include <stdlib.h>
+#include <signal.h>
+#include <endian.h>
+
+
+unsigned long long x = 0x8877665544332211ull;
+void * volatile p = (void *)&x + 1;
+
+void sigbus(int sig, siginfo_t *info, void *uc)
+{
+ assert(sig == SIGBUS);
+ assert(info->si_signo == SIGBUS);
+#ifdef BUS_ADRALN
+ assert(info->si_code == BUS_ADRALN);
+#endif
+ assert(info->si_addr == p);
+ exit(EXIT_SUCCESS);
+}
+
+int main()
+{
+ struct sigaction sa = {
+ .sa_sigaction = sigbus,
+ .sa_flags = SA_SIGINFO
+ };
+ int allow_fail = 0;
+ int tmp;
+
+ tmp = sigaction(SIGBUS, &sa, NULL);
+ assert(tmp == 0);
+
+ /*
+ * Select an operation that's likely to enforce alignment.
+ * On many guests that support unaligned accesses by default,
+ * this is often an atomic operation.
+ */
+#if defined(__aarch64__)
+ asm volatile("ldxr %w0,[%1]" : "=r"(tmp) : "r"(p) : "memory");
+#elif defined(__alpha__)
+ asm volatile("ldl_l %0,0(%1)" : "=r"(tmp) : "r"(p) : "memory");
+#elif defined(__arm__)
+ asm volatile("ldrex %0,[%1]" : "=r"(tmp) : "r"(p) : "memory");
+#elif defined(__powerpc__)
+ asm volatile("lwarx %0,0,%1" : "=r"(tmp) : "r"(p) : "memory");
+#elif defined(__riscv_atomic)
+ asm volatile("lr.w %0,(%1)" : "=r"(tmp) : "r"(p) : "memory");
+#else
+ /* No insn known to fault unaligned -- try for a straight load. */
+ allow_fail = 1;
+ tmp = *(volatile int *)p;
+#endif
+
+ assert(allow_fail);
+
+ /*
+ * We didn't see a signal.
+ * We might as well validate the unaligned load worked.
+ */
+ if (BYTE_ORDER == LITTLE_ENDIAN) {
+ assert(tmp == 0x55443322);
+ } else {
+ assert(tmp == 0x77665544);
+ }
+ return EXIT_SUCCESS;
+}
--
2.25.1
^ permalink raw reply related [flat|nested] 102+ messages in thread* Re: [PATCH for-6.2 00/43] Unaligned accesses for user-only
2021-07-29 0:46 [PATCH for-6.2 00/43] Unaligned accesses for user-only Richard Henderson
` (42 preceding siblings ...)
2021-07-29 0:46 ` [PATCH for-6.2 43/43] tests/tcg/multiarch: Add sigbus.c Richard Henderson
@ 2021-07-29 6:14 ` Philippe Mathieu-Daudé
2021-07-29 14:01 ` Claudio Fontana
2021-08-02 13:14 ` Peter Maydell
44 siblings, 1 reply; 102+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-07-29 6:14 UTC (permalink / raw)
To: Richard Henderson, qemu-devel, Claudio Fontana
On 7/29/21 2:46 AM, Richard Henderson wrote:
> This began with Peter wanting a cpu_ldst.h interface that can handle
> alignment info for Arm M-profile system mode, which will also compile
> for user-only without ifdefs. This is patch 32.
>
> Once I had that interface, I thought I might as well enforce the
> requested alignment in user-only. There are plenty of cases where
> we ought to have been doing that for quite a while. This took rather
> more work than I imagined to start.
>
> So far only x86 host has been fully converted to handle unaligned
> operations in user-only mode. I'll get to the others later. But
> the added testcase is fairly broad, and caught lots of bugs and/or
> missing code between target/ and linux-user/.
>
> Notes:
> * For target/i386 we have no way to signal SIGBUS from user-only.
> In theory we could go through do_unaligned_access in system mode,
> via #AC. But we don't even implement that control in tcg, probably
> because no one ever sets it. The cmpxchg16b insn requires alignment,
> but raises #GP, which maps to SIGSEGV.
>
> * For target/s390x we have no way to signal SIGBUS from user-only.
> The atomic operations raise PGM_SPECIFICATION, which the linux
> kernel maps to SIGILL.
>
> * I think target/hexagon should be setting TARGET_ALIGNED_ONLY=y.
> In the meantime, all memory accesses are allowed to be unaligned.
Now I better understand what you tried to explain me last with
TCGCPUOps. Since Claudio was also involved, Cc'ing him (not asking
for a review, just in case he wants to follow up).
^ permalink raw reply [flat|nested] 102+ messages in thread* Re: [PATCH for-6.2 00/43] Unaligned accesses for user-only
2021-07-29 6:14 ` [PATCH for-6.2 00/43] Unaligned accesses for user-only Philippe Mathieu-Daudé
@ 2021-07-29 14:01 ` Claudio Fontana
0 siblings, 0 replies; 102+ messages in thread
From: Claudio Fontana @ 2021-07-29 14:01 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, Richard Henderson, qemu-devel
On 7/29/21 8:14 AM, Philippe Mathieu-Daudé wrote:
> On 7/29/21 2:46 AM, Richard Henderson wrote:
>> This began with Peter wanting a cpu_ldst.h interface that can handle
>> alignment info for Arm M-profile system mode, which will also compile
>> for user-only without ifdefs. This is patch 32.
>>
>> Once I had that interface, I thought I might as well enforce the
>> requested alignment in user-only. There are plenty of cases where
>> we ought to have been doing that for quite a while. This took rather
>> more work than I imagined to start.
>>
>> So far only x86 host has been fully converted to handle unaligned
>> operations in user-only mode. I'll get to the others later. But
>> the added testcase is fairly broad, and caught lots of bugs and/or
>> missing code between target/ and linux-user/.
>>
>> Notes:
>> * For target/i386 we have no way to signal SIGBUS from user-only.
>> In theory we could go through do_unaligned_access in system mode,
>> via #AC. But we don't even implement that control in tcg, probably
>> because no one ever sets it. The cmpxchg16b insn requires alignment,
>> but raises #GP, which maps to SIGSEGV.
>>
>> * For target/s390x we have no way to signal SIGBUS from user-only.
>> The atomic operations raise PGM_SPECIFICATION, which the linux
>> kernel maps to SIGILL.
>>
>> * I think target/hexagon should be setting TARGET_ALIGNED_ONLY=y.
>> In the meantime, all memory accesses are allowed to be unaligned.
>
> Now I better understand what you tried to explain me last with
> TCGCPUOps. Since Claudio was also involved, Cc'ing him (not asking
> for a review, just in case he wants to follow up).
>
Thanks, what I understand from glancing through the thread is that
at the time we made handling of unaligned access a sysmmu-only TCGCPUOps,
while this series corrects that and implements unaligned accesses for user-only,
so seems good to me.
Ciao,
Claudio
^ permalink raw reply [flat|nested] 102+ messages in thread
* Re: [PATCH for-6.2 00/43] Unaligned accesses for user-only
2021-07-29 0:46 [PATCH for-6.2 00/43] Unaligned accesses for user-only Richard Henderson
` (43 preceding siblings ...)
2021-07-29 6:14 ` [PATCH for-6.2 00/43] Unaligned accesses for user-only Philippe Mathieu-Daudé
@ 2021-08-02 13:14 ` Peter Maydell
44 siblings, 0 replies; 102+ messages in thread
From: Peter Maydell @ 2021-08-02 13:14 UTC (permalink / raw)
To: Richard Henderson; +Cc: QEMU Developers
On Thu, 29 Jul 2021 at 01:50, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> This began with Peter wanting a cpu_ldst.h interface that can handle
> alignment info for Arm M-profile system mode, which will also compile
> for user-only without ifdefs. This is patch 32.
>
> Once I had that interface, I thought I might as well enforce the
> requested alignment in user-only. There are plenty of cases where
> we ought to have been doing that for quite a while. This took rather
> more work than I imagined to start.
>
> So far only x86 host has been fully converted to handle unaligned
> operations in user-only mode. I'll get to the others later. But
> the added testcase is fairly broad, and caught lots of bugs and/or
> missing code between target/ and linux-user/.
>
> Notes:
> * For target/i386 we have no way to signal SIGBUS from user-only.
> In theory we could go through do_unaligned_access in system mode,
> via #AC. But we don't even implement that control in tcg, probably
> because no one ever sets it. The cmpxchg16b insn requires alignment,
> but raises #GP, which maps to SIGSEGV.
>
> * For target/s390x we have no way to signal SIGBUS from user-only.
> The atomic operations raise PGM_SPECIFICATION, which the linux
> kernel maps to SIGILL.
>
> * I think target/hexagon should be setting TARGET_ALIGNED_ONLY=y.
> In the meantime, all memory accesses are allowed to be unaligned.
Could you include suitable updates to docs/devel/loads-stores.rst
as well, please?
thanks
-- PMM
^ permalink raw reply [flat|nested] 102+ messages in thread