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Tue, 13 Dec 2022 07:07:08 GMT Received: from [10.216.17.160] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Mon, 12 Dec 2022 23:07:03 -0800 Message-ID: <3c017429-15c6-11d0-9aef-c718a39d87aa@quicinc.com> Date: Tue, 13 Dec 2022 12:36:59 +0530 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.3.2 Subject: Re: [PATCH 3/7] drm/msm/a6xx: Add support for A640 speed binning Content-Language: en-US To: Konrad Dybcio , , , , CC: , Rob Clark , "Abhinav Kumar" , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Chia-I Wu , Douglas Anderson , , , References: <20221213002423.259039-1-konrad.dybcio@linaro.org> <20221213002423.259039-4-konrad.dybcio@linaro.org> From: Akhil P Oommen In-Reply-To: <20221213002423.259039-4-konrad.dybcio@linaro.org> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: MrJ4nlK9qg5HEWa8kw7rAuhUmlOxUr6O X-Proofpoint-ORIG-GUID: MrJ4nlK9qg5HEWa8kw7rAuhUmlOxUr6O X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.923,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-12-13_03,2022-12-12_02,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 mlxscore=0 mlxlogscore=999 bulkscore=0 suspectscore=0 clxscore=1011 spamscore=0 lowpriorityscore=0 malwarescore=0 adultscore=0 phishscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2210170000 definitions=main-2212130064 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On 12/13/2022 5:54 AM, Konrad Dybcio wrote: > Add support for matching QFPROM fuse values to get the correct speed bin > on A640 (SM8150) GPUs. > > Signed-off-by: Konrad Dybcio > --- > drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 13 +++++++++++++ > 1 file changed, 13 insertions(+) > > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > index 36c8fb699b56..2c1630f0c04c 100644 > --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > @@ -1877,6 +1877,16 @@ static u32 a619_get_speed_bin(u32 fuse) > return UINT_MAX; > } > > +static u32 a640_get_speed_bin(u32 fuse) > +{ > + if (fuse == 0) > + return 0; > + else if (fuse == 1) > + return 1; > + > + return UINT_MAX; > +} > + > static u32 adreno_7c3_get_speed_bin(u32 fuse) > { > if (fuse == 0) > @@ -1902,6 +1912,9 @@ static u32 fuse_to_supp_hw(struct device *dev, struct adreno_rev rev, u32 fuse) > if (adreno_cmp_rev(ADRENO_REV(6, 3, 5, ANY_ID), rev)) > val = adreno_7c3_get_speed_bin(fuse); > > + if (adreno_cmp_rev(ADRENO_REV(6, 4, 0, ANY_ID), rev)) > + val = a640_get_speed_bin(fuse); > + > if (val == UINT_MAX) { > DRM_DEV_ERROR(dev, > "missing support for speed-bin: %u. Some OPPs may not be supported by hardware\n", Reviewed-by: Akhil P Oommen -Akhil. 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Tue, 13 Dec 2022 07:07:08 GMT Received: from [10.216.17.160] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Mon, 12 Dec 2022 23:07:03 -0800 Message-ID: <3c017429-15c6-11d0-9aef-c718a39d87aa@quicinc.com> Date: Tue, 13 Dec 2022 12:36:59 +0530 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.3.2 Subject: Re: [PATCH 3/7] drm/msm/a6xx: Add support for A640 speed binning Content-Language: en-US To: Konrad Dybcio , , , , References: <20221213002423.259039-1-konrad.dybcio@linaro.org> <20221213002423.259039-4-konrad.dybcio@linaro.org> From: Akhil P Oommen In-Reply-To: <20221213002423.259039-4-konrad.dybcio@linaro.org> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: MrJ4nlK9qg5HEWa8kw7rAuhUmlOxUr6O X-Proofpoint-ORIG-GUID: MrJ4nlK9qg5HEWa8kw7rAuhUmlOxUr6O X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.923,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-12-13_03,2022-12-12_02,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 mlxscore=0 mlxlogscore=999 bulkscore=0 suspectscore=0 clxscore=1011 spamscore=0 lowpriorityscore=0 malwarescore=0 adultscore=0 phishscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2210170000 definitions=main-2212130064 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: freedreno@lists.freedesktop.org, Abhinav Kumar , dri-devel@lists.freedesktop.org, Douglas Anderson , Dmitry Baryshkov , marijn.suijten@somainline.org, Sean Paul , linux-kernel@vger.kernel.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On 12/13/2022 5:54 AM, Konrad Dybcio wrote: > Add support for matching QFPROM fuse values to get the correct speed bin > on A640 (SM8150) GPUs. > > Signed-off-by: Konrad Dybcio > --- > drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 13 +++++++++++++ > 1 file changed, 13 insertions(+) > > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > index 36c8fb699b56..2c1630f0c04c 100644 > --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > @@ -1877,6 +1877,16 @@ static u32 a619_get_speed_bin(u32 fuse) > return UINT_MAX; > } > > +static u32 a640_get_speed_bin(u32 fuse) > +{ > + if (fuse == 0) > + return 0; > + else if (fuse == 1) > + return 1; > + > + return UINT_MAX; > +} > + > static u32 adreno_7c3_get_speed_bin(u32 fuse) > { > if (fuse == 0) > @@ -1902,6 +1912,9 @@ static u32 fuse_to_supp_hw(struct device *dev, struct adreno_rev rev, u32 fuse) > if (adreno_cmp_rev(ADRENO_REV(6, 3, 5, ANY_ID), rev)) > val = adreno_7c3_get_speed_bin(fuse); > > + if (adreno_cmp_rev(ADRENO_REV(6, 4, 0, ANY_ID), rev)) > + val = a640_get_speed_bin(fuse); > + > if (val == UINT_MAX) { > DRM_DEV_ERROR(dev, > "missing support for speed-bin: %u. Some OPPs may not be supported by hardware\n", Reviewed-by: Akhil P Oommen -Akhil.