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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id cv1sm1940511pjb.48.2021.11.09.01.48.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Nov 2021 01:48:55 -0800 (PST) From: Greentime Hu To: palmer@dabbelt.com, paul.walmsley@sifive.com, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, aou@eecs.berkeley.edu Subject: [PATCH v9 16/17] riscv: Fix an illegal instruction exception when accessing vlenb without enable vector first Date: Tue, 9 Nov 2021 17:48:28 +0800 Message-Id: <3c0297d8335e4cac54a4397c880092c1c983e04e.1636362169.git.greentime.hu@sifive.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org It triggered an illegal instruction exception when accessing vlenb CSR without enable vector first. To fix this issue, we should enable vector before using it and disable vector after using it. Co-developed-by: Vincent Chen Signed-off-by: Vincent Chen Signed-off-by: Greentime Hu --- arch/riscv/include/asm/vector.h | 2 ++ arch/riscv/kernel/cpufeature.c | 2 ++ arch/riscv/kernel/kernel_mode_vector.c | 6 ++++-- 3 files changed, 8 insertions(+), 2 deletions(-) diff --git a/arch/riscv/include/asm/vector.h b/arch/riscv/include/asm/vector.h index 5d7f14453f68..ca063c8f47f2 100644 --- a/arch/riscv/include/asm/vector.h +++ b/arch/riscv/include/asm/vector.h @@ -8,6 +8,8 @@ #include +void rvv_enable(void); +void rvv_disable(void); void kernel_rvv_begin(void); void kernel_rvv_end(void); diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 8e7557980faf..0139ec20adce 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -159,7 +159,9 @@ void __init riscv_fill_hwcap(void) if (elf_hwcap & COMPAT_HWCAP_ISA_V) { static_branch_enable(&cpu_hwcap_vector); /* There are 32 vector registers with vlenb length. */ + rvv_enable(); riscv_vsize = csr_read(CSR_VLENB) * 32; + rvv_disable(); } #endif } diff --git a/arch/riscv/kernel/kernel_mode_vector.c b/arch/riscv/kernel/kernel_mode_vector.c index 8d2e53ea25c1..1ecb6ec5c56d 100644 --- a/arch/riscv/kernel/kernel_mode_vector.c +++ b/arch/riscv/kernel/kernel_mode_vector.c @@ -71,15 +71,17 @@ static void put_cpu_vector_context(void) preempt_enable(); } -static void rvv_enable(void) +void rvv_enable(void) { csr_set(CSR_STATUS, SR_VS); } +EXPORT_SYMBOL(rvv_enable); -static void rvv_disable(void) +void rvv_disable(void) { csr_clear(CSR_STATUS, SR_VS); } +EXPORT_SYMBOL(rvv_disable); /* * kernel_rvv_begin(): obtain the CPU vector registers for use by the calling -- 2.31.1 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 00583C433F5 for ; Tue, 9 Nov 2021 09:58:55 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id BAAA8610A3 for ; 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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id cv1sm1940511pjb.48.2021.11.09.01.48.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Nov 2021 01:48:55 -0800 (PST) From: Greentime Hu To: palmer@dabbelt.com, paul.walmsley@sifive.com, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, aou@eecs.berkeley.edu Subject: [PATCH v9 16/17] riscv: Fix an illegal instruction exception when accessing vlenb without enable vector first Date: Tue, 9 Nov 2021 17:48:28 +0800 Message-Id: <3c0297d8335e4cac54a4397c880092c1c983e04e.1636362169.git.greentime.hu@sifive.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211109_014857_132836_52275299 X-CRM114-Status: GOOD ( 10.13 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org It triggered an illegal instruction exception when accessing vlenb CSR without enable vector first. To fix this issue, we should enable vector before using it and disable vector after using it. Co-developed-by: Vincent Chen Signed-off-by: Vincent Chen Signed-off-by: Greentime Hu --- arch/riscv/include/asm/vector.h | 2 ++ arch/riscv/kernel/cpufeature.c | 2 ++ arch/riscv/kernel/kernel_mode_vector.c | 6 ++++-- 3 files changed, 8 insertions(+), 2 deletions(-) diff --git a/arch/riscv/include/asm/vector.h b/arch/riscv/include/asm/vector.h index 5d7f14453f68..ca063c8f47f2 100644 --- a/arch/riscv/include/asm/vector.h +++ b/arch/riscv/include/asm/vector.h @@ -8,6 +8,8 @@ #include +void rvv_enable(void); +void rvv_disable(void); void kernel_rvv_begin(void); void kernel_rvv_end(void); diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 8e7557980faf..0139ec20adce 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -159,7 +159,9 @@ void __init riscv_fill_hwcap(void) if (elf_hwcap & COMPAT_HWCAP_ISA_V) { static_branch_enable(&cpu_hwcap_vector); /* There are 32 vector registers with vlenb length. */ + rvv_enable(); riscv_vsize = csr_read(CSR_VLENB) * 32; + rvv_disable(); } #endif } diff --git a/arch/riscv/kernel/kernel_mode_vector.c b/arch/riscv/kernel/kernel_mode_vector.c index 8d2e53ea25c1..1ecb6ec5c56d 100644 --- a/arch/riscv/kernel/kernel_mode_vector.c +++ b/arch/riscv/kernel/kernel_mode_vector.c @@ -71,15 +71,17 @@ static void put_cpu_vector_context(void) preempt_enable(); } -static void rvv_enable(void) +void rvv_enable(void) { csr_set(CSR_STATUS, SR_VS); } +EXPORT_SYMBOL(rvv_enable); -static void rvv_disable(void) +void rvv_disable(void) { csr_clear(CSR_STATUS, SR_VS); } +EXPORT_SYMBOL(rvv_disable); /* * kernel_rvv_begin(): obtain the CPU vector registers for use by the calling -- 2.31.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv