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From: Qi Hu <huqi@loongson.cn>
To: gaosong <gaosong@loongson.cn>,
	Richard Henderson <richard.henderson@linaro.org>,
	qemu-devel@nongnu.org, maobibo <maobibo@loongson.cn>,
	Peter Maydell <peter.maydell@linaro.org>,
	alex.bennee@linaro.org
Subject: Re: [PATCH 5/5] target/loongarch: div if x/0 set dividend to 0
Date: Tue, 20 Sep 2022 10:18:05 +0800	[thread overview]
Message-ID: <3c401d0f-a34f-bd29-03a3-dddfae94ce0a@loongson.cn> (raw)
In-Reply-To: <e8a24cfc-005c-1196-35dd-05efdef6858b@loongson.cn>


On 2022/9/19 19:45, gaosong wrote:
>
> 在 2022/9/17 下午6:12, Richard Henderson 写道:
>> On 9/17/22 11:12, gaosong wrote:
>>>
>>> 在 2022/9/17 下午4:59, Qi Hu 写道:
>>>>
>>>> On 2022/9/17 15:59, Song Gao wrote:
>>>>> div.d, div.du, div,w, div.wu, the LoongArch host if x/0  the 
>>>>> result is 0.
>>>>
>>>> The message has a typo: "div,w" => "div.w"
>>>>
>>>> Also I don't know why we need to do this, since the manual say: 
>>>> "When the divisor is 0, the result can be any value".
>>>>
>>> I tested on LoongArch host,   the result is always 0.
>>
>> But it is legal for a different loongarch host implementation to 
>> return some other value.  Therefore the test itself is not correct.
>>
> I think the manual maybe not correct,  the hardware engineer said that 
> they need to comfirm  whether the result is always 0.
>
> Thanks.
> Song Gao

Hi,

The hardware designers suggested that 0 should not be used as the 
default value when "div 0" occurs. The behavior is not guaranteed in 
future processors.

So I think there are some ways to solve this:

- Remove this case("div 0") from risu test.

- Keep this patch by yourself. If you want to do risu test, patch it. :-)


regards,

Qi

>> r~
>



      reply	other threads:[~2022-09-20  2:19 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-09-17  7:59 [PATCH 0/5] Fix some bugs Song Gao
2022-09-17  7:59 ` [PATCH 1/5] target/loongarch: ftint_xxx insns set the result high 32bit 0xffffffff Song Gao
2022-09-17  7:59 ` [PATCH 2/5] target/loongarch: bstrins.w need set dest register EXT_SIGN Song Gao
2022-09-17  8:41   ` Qi Hu
2022-09-17  9:16     ` gaosong
2022-09-17 10:56       ` Qi Hu
2022-09-17  7:59 ` [PATCH 3/5] target/loongarch: Fix fnm{sub/add}_{s/d} set wrong flags Song Gao
2022-09-17  7:59 ` [PATCH 4/5] target/loongarch: flogb_{s/d} add set float_flag_divbyzero Song Gao
2022-09-17  7:59 ` [PATCH 5/5] target/loongarch: div if x/0 set dividend to 0 Song Gao
2022-09-17  8:59   ` Qi Hu
2022-09-17  9:12     ` gaosong
2022-09-17 10:12       ` Richard Henderson
2022-09-19 11:45         ` gaosong
2022-09-20  2:18           ` Qi Hu [this message]

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