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Wed, 12 Jan 2022 23:27:53 -0800 Message-ID: <3caae1db-b577-1e1f-3377-11272945054c@xilinx.com> Date: Thu, 13 Jan 2022 08:27:50 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.5.0 Subject: Re: [PATCH net-next 2/3] net: macb: Added ZynqMP-specific initialization Content-Language: en-US To: Robert Hancock , , Harini Katakam , Piyush Mehta CC: , , , , , , References: <20220112181113.875567-1-robert.hancock@calian.com> <20220112181113.875567-3-robert.hancock@calian.com> From: Michal Simek In-Reply-To: <20220112181113.875567-3-robert.hancock@calian.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 27d6ed80-f3e3-4c9f-b96a-08d9d66636a9 X-MS-TrafficTypeDiagnostic: SN6PR02MB5549:EE_ X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:8882; 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X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Jan 2022 07:27:54.0955 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 27d6ed80-f3e3-4c9f-b96a-08d9d66636a9 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.62.198];Helo=[xsj-pvapexch02.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: SN1NAM02FT0036.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN6PR02MB5549 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org On 1/12/22 19:11, Robert Hancock wrote: > The GEM controllers on ZynqMP were missing some initialization steps which > are required in some cases when using SGMII mode, which uses the PS-GTR > transceivers managed by the phy-zynqmp driver. > > The GEM core appears to need a hardware-level reset in order to work > properly in SGMII mode in cases where the GT reference clock was not > present at initial power-on. This can be done using a reset mapped to > the zynqmp-reset driver in the device tree. > > Also, when in SGMII mode, the GEM driver needs to ensure the PHY is > initialized and powered on when it is initializing. > > Signed-off-by: Robert Hancock > --- > drivers/net/ethernet/cadence/macb_main.c | 47 +++++++++++++++++++++++- > 1 file changed, 46 insertions(+), 1 deletion(-) > > diff --git a/drivers/net/ethernet/cadence/macb_main.c b/drivers/net/ethernet/cadence/macb_main.c > index a363da928e8b..65b0360c487a 100644 > --- a/drivers/net/ethernet/cadence/macb_main.c > +++ b/drivers/net/ethernet/cadence/macb_main.c > @@ -34,7 +34,9 @@ > #include > #include > #include > +#include > #include > +#include > #include "macb.h" > > /* This structure is only used for MACB on SiFive FU540 devices */ > @@ -4455,6 +4457,49 @@ static int fu540_c000_init(struct platform_device *pdev) > return macb_init(pdev); > } > > +static int zynqmp_init(struct platform_device *pdev) > +{ > + struct net_device *dev = platform_get_drvdata(pdev); > + struct macb *bp = netdev_priv(dev); > + int ret; > + > + /* Fully reset GEM controller at hardware level using zynqmp-reset driver, > + * if mapped in device tree. > + */ > + ret = device_reset(&pdev->dev); > + if (ret) { > + dev_err_probe(&pdev->dev, ret, "failed to reset controller"); > + return ret; > + } > + > + if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII) { > + /* Ensure PS-GTR PHY device used in SGMII mode is ready */ > + struct phy *sgmii_phy = devm_phy_get(&pdev->dev, "sgmii-phy"); > + > + if (IS_ERR(sgmii_phy)) { > + ret = PTR_ERR(sgmii_phy); > + dev_err_probe(&pdev->dev, ret, > + "failed to get PS-GTR PHY\n"); > + return ret; > + } > + > + ret = phy_init(sgmii_phy); > + if (ret) { > + dev_err(&pdev->dev, "failed to init PS-GTR PHY: %d\n", > + ret); > + return ret; > + } I was playing with it recently on u-boot side and device reset should happen between phy init and phy power on to finish calibration. At least that's I was told and that's I use in u-boot driver. Harini/Piyush: Please correct me if I am wrong. Thanks, Michal