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Tue, 21 Sep 2021 00:24:52 +0800 (CST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=xen0n.name; s=mail; t=1632155092; bh=m4csL0K+f7GiCIcZ3k62XxL9BstD//udgSIwJm83txE=; h=Date:Subject:To:References:From:In-Reply-To:From; b=Ftfs7AefPxN3089tg6zqK2PAv/LVUUHhRxhPUx8mKZJd+/vNk1YT78wZxaHdaV6Yg XxQag4v+NJlGDQpbJDcxIPvO6ZQkU/qQTqJ9Pkis1xwmltnsd0aRmiu/3+gJ23GAdB i8V5TIQT65fQx2dBA9pS6Enqi7uBbN4H7DNsWgG8= Message-ID: <3d221eaf-0d8c-d192-996c-1e82dee70d21@xen0n.name> Date: Tue, 21 Sep 2021 00:24:52 +0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:94.0) Gecko/20100101 Thunderbird/94.0a1 Subject: Re: [PATCH 04/30] tcg/loongarch: Add generated instruction opcodes and encoding helpers Content-Language: en-US To: Richard Henderson , qemu-devel@nongnu.org References: <20210920080451.408655-1-git@xen0n.name> <20210920080451.408655-5-git@xen0n.name> <7f94f992-8d7d-ac50-2ab7-88c2b9cbb18f@linaro.org> From: WANG Xuerui In-Reply-To: <7f94f992-8d7d-ac50-2ab7-88c2b9cbb18f@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Host-Lookup-Failed: Reverse DNS lookup failed for 115.28.160.31 (failed) Received-SPF: pass client-ip=115.28.160.31; envelope-from=i.qemu@xen0n.name; helo=mailbox.box.xen0n.name X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Hi Richard, On 9/20/21 23:55, Richard Henderson wrote: > On 9/20/21 1:04 AM, WANG Xuerui wrote: >> Signed-off-by: WANG Xuerui >> --- >>   tcg/loongarch/tcg-insn-defs.c.inc | 1080 +++++++++++++++++++++++++++++ >>   1 file changed, 1080 insertions(+) >>   create mode 100644 tcg/loongarch/tcg-insn-defs.c.inc >> >> diff --git a/tcg/loongarch/tcg-insn-defs.c.inc >> b/tcg/loongarch/tcg-insn-defs.c.inc >> new file mode 100644 >> index 0000000000..413f7ffc12 >> --- /dev/null >> +++ b/tcg/loongarch/tcg-insn-defs.c.inc >> @@ -0,0 +1,1080 @@ >> +/* SPDX-License-Identifier: MIT */ >> +/* >> + * LoongArch instruction formats, opcodes, and encoders for TCG use. >> + * >> + * Code generated by genqemutcgdefs from >> + *https://github.com/loongson-community/loongarch-opcodes, >> + * from commit bb5234081663faaefb6b921a7848b18e19519890. >> + * DO NOT EDIT. >> + */ >> + > > Acked-by: Richard Henderson > > >> +static int32_t encode_d_slot(LoongArchInsn opc, uint32_t d) >> +    __attribute__((unused)); >> + >> +static int32_t encode_d_slot(LoongArchInsn opc, uint32_t d) > > Just an FYI: you can add the attribute directly to the function > definition like so > > static int32_t __attribute__((unused)) > encode_d_slot(LoongArchInsn opc, uint32_t d) > { >    ... > } > Fine; I always struggle to remember the correct placement of attributes! I'll try to adjust that in loongarch-opcodes repo. If I can arrive at something that doesn't need prototypes and builds cleanly, I'll replace the code here and shave off maybe 100 lines (because currently we use 88 insns). > > r~