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Tue, 16 Nov 2021 03:17:54 -0800 From: Shubhrajyoti Datta To: CC: , , , Raviteja Narayanam , Shubhrajyoti Datta Subject: [PATCH 2/2] serial: pl011: Add support for Xilinx Uart Date: Tue, 16 Nov 2021 16:47:46 +0530 Message-ID: <3d24a1f6dedd70794fd08f9b4f85a7d362d835d4.1637061057.git.shubhrajyoti.datta@xilinx.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: a8e70c96-bf03-4ac3-d7d5-08d9a8f2bcd8 X-MS-TrafficTypeDiagnostic: DM6PR02MB5498: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:5236; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: arqnzpoSr593LaVSU7a6nKIaYmC6J5n25To6PkTnXpi/IlswBA7wk+jBarf08A4padzUXA34pWvoucqwE08olVUnHv5QC9KfLBhf1upQqbjIUrC3DLFERMkG3gEv7MojluzrT3FzEFIizIT2E+weCh+tRzyIvhXhTmLOInAlpCHH9vocb5Er4lzFwOjxQaMP/uT0WZJbHzZof836k/EdXZdNkbUMVZ2Wzbo+YajD37qVmkx86BRACOankSyIJYKiR+IkuynZYt5br/R7d+ezPZ3DuJQjdD0SIGt/R2TnOOyy/Egs+VKznk/23YzcMSClcVyWuppO35IJODfE5JerqCRy7YFLy+e80iPKsdy4RdmolYqTkeAMEfDgNwh6krIImxlJ0GTOvcm92/kJ74D6dMVRAxJa1sMlBLG/TwGmSiDim01E6mJqoD0L/0CifWMLAqkHFsEQfAOzxHs9A/7BXpSC6Bt9TzRcduA27NUhwdAg4sZMyxSWo6/gOLn9FzE69CRucAnk3THhyk2RSEdbxQ5Iv567DUUoOReH+XohG6f8hvSe9INqevSoaA/WVoDQ7iacGBY9oU27UJzgXRyl02W6vqaf3xwQXWypriBpC23qqhkFidEJDQTxy9UpFuUe4CsCG9pxZ1uVPNUZFdEXF6f4Jujh7otgvjDG8xYiYrd/bJHC/p+wg3K1IBEIG/stLKmYePnBjijK8n16JMD3MkvFd1OPKNYY7PJmmd4a7vU= X-Forefront-Antispam-Report: CIP:149.199.62.198;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:xsj-pvapexch01.xlnx.xilinx.com;PTR:unknown-62-198.xilinx.com;CAT:NONE;SFS:(46966006)(36840700001)(7636003)(7696005)(44832011)(508600001)(8676002)(2616005)(54906003)(36756003)(336012)(9786002)(5660300002)(4326008)(426003)(6666004)(356005)(6916009)(36860700001)(83380400001)(107886003)(47076005)(186003)(82310400003)(26005)(8936002)(316002)(2906002)(70586007)(36906005)(70206006)(102446001);DIR:OUT;SFP:1101; X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Nov 2021 11:17:55.2196 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a8e70c96-bf03-4ac3-d7d5-08d9a8f2bcd8 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.62.198];Helo=[xsj-pvapexch01.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: BN1NAM02FT020.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR02MB5498 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Raviteja Narayanam The xilinx uart used in Versal SOC follows arm pl011 implementation with just a minor change in data bus width. The minimum data transaction width in Versal SOC is 32-bit as specified in the TRM (Chapter 39: Transaction attributes). Pl011 defaults to 16-bit in the driver. So, add the xilinx uart as platform device with properties specified in 'vendor_data' structure. Signed-off-by: Raviteja Narayanam Signed-off-by: Shubhrajyoti Datta --- drivers/tty/serial/amba-pl011.c | 33 +++++++++++++++++++++++++++++++-- 1 file changed, 31 insertions(+), 2 deletions(-) diff --git a/drivers/tty/serial/amba-pl011.c b/drivers/tty/serial/amba-pl011.c index d361cd84ff8c..278255a45ad9 100644 --- a/drivers/tty/serial/amba-pl011.c +++ b/drivers/tty/serial/amba-pl011.c @@ -124,6 +124,21 @@ static const struct vendor_data vendor_sbsa = { .fixed_options = true, }; +static const struct vendor_data vendor_xlnx = { + .reg_offset = pl011_std_offsets, + .ifls = UART011_IFLS_RX4_8 | UART011_IFLS_TX4_8, + .fr_busy = UART01x_FR_BUSY, + .fr_dsr = UART01x_FR_DSR, + .fr_cts = UART01x_FR_CTS, + .fr_ri = UART011_FR_RI, + .access_32b = true, + .oversampling = false, + .dma_threshold = false, + .cts_event_workaround = false, + .always_enabled = true, + .fixed_options = false, +}; + #ifdef CONFIG_ACPI_SPCR_TABLE static const struct vendor_data vendor_qdt_qdf2400_e44 = { .reg_offset = pl011_std_offsets, @@ -2628,6 +2643,7 @@ static int __init pl011_early_console_setup(struct earlycon_device *device, } OF_EARLYCON_DECLARE(pl011, "arm,pl011", pl011_early_console_setup); OF_EARLYCON_DECLARE(pl011, "arm,sbsa-uart", pl011_early_console_setup); +OF_EARLYCON_DECLARE(pl011, "arm,xlnx-uart", pl011_early_console_setup); /* * On Qualcomm Datacenter Technologies QDF2400 SOCs affected by @@ -2872,6 +2888,7 @@ static int sbsa_uart_probe(struct platform_device *pdev) { struct uart_amba_port *uap; struct resource *r; + int xlnx_uart = 0; int portnr, ret; int baudrate; @@ -2882,6 +2899,7 @@ static int sbsa_uart_probe(struct platform_device *pdev) if (pdev->dev.of_node) { struct device_node *np = pdev->dev.of_node; + xlnx_uart = of_device_is_compatible(np, "arm,xlnx-uart"); ret = of_property_read_u32(np, "current-speed", &baudrate); if (ret) return ret; @@ -2911,13 +2929,23 @@ static int sbsa_uart_probe(struct platform_device *pdev) #endif uap->vendor = &vendor_sbsa; + uap->port.ops = &sbsa_uart_pops; + + if (xlnx_uart) { + uap->vendor = &vendor_xlnx; + uap->clk = devm_clk_get(&pdev->dev, NULL); + if (IS_ERR(uap->clk)) + return PTR_ERR(uap->clk); + + uap->port.ops = &amba_pl011_pops; + } + uap->reg_offset = uap->vendor->reg_offset; uap->fifosize = 32; uap->port.iotype = uap->vendor->access_32b ? UPIO_MEM32 : UPIO_MEM; - uap->port.ops = &sbsa_uart_pops; uap->fixed_baud = baudrate; - snprintf(uap->type, sizeof(uap->type), "SBSA"); + snprintf(uap->type, sizeof(uap->type), "%s\n", (xlnx_uart ? "xlnx_uart" : "SBSA")); r = platform_get_resource(pdev, IORESOURCE_MEM, 0); @@ -2941,6 +2969,7 @@ static int sbsa_uart_remove(struct platform_device *pdev) static const struct of_device_id sbsa_uart_of_match[] = { { .compatible = "arm,sbsa-uart", }, + { .compatible = "arm,xlnx-uart", }, {}, }; MODULE_DEVICE_TABLE(of, sbsa_uart_of_match); -- 2.25.1