From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0EBCBC433EF for ; Thu, 21 Oct 2021 11:47:24 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E7BA260FD9 for ; Thu, 21 Oct 2021 11:47:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230383AbhJULti (ORCPT ); Thu, 21 Oct 2021 07:49:38 -0400 Received: from esa.microchip.iphmx.com ([68.232.153.233]:35080 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229765AbhJULth (ORCPT ); Thu, 21 Oct 2021 07:49:37 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1634816841; x=1666352841; h=subject:to:cc:references:from:message-id:date: mime-version:in-reply-to:content-transfer-encoding; bh=p+VO7ithOuP0XnGZg+W3xd0diUiv+mQ77fVNQVDV3jU=; b=L9vcPFUupbWsX4J12U9EA5lbp82nbb4BeeUfQ23qQ5HEEVepSZBC33DI eEsgPEJ9O+SlBTtgYNsGaSNJW93zAJIbq5iert5xRMKCce6QtajnL+RXZ 3i9UdjApp1bAPjWltMh5yKqQ0oR0Auuni4Rw7cRJBPvLL5rr/fHfyGHd5 nmx7qepf7GhdzKdSd8fB808t1ss11Sg6E+g0P8i9rbbdhiHRFS55AZLzf AmXyfQKHY2xxdt/dqGiYkhj3+DiIyrablu1/WaudxOqqJLpo+qNv6KiSi ckFXoPL+hPvEvMuUh/Fi7YvjOZ0UrfjJ+gX6cZtuHMlCHCgIq/QefHjgV Q==; IronPort-SDR: RgqHskO2oQGEMsN1uyJsqOgybAkMqhCKZWAJItUnpXIiuFMVOetI/aD6rNhvP+snoPvJ/7gCTT cEsbk/Na8kYgaI7YbN1tuUTkivBq5y75dClVD56x3Vi+z1D2UQyp8GOa0D+6oQ7FGAe4Bg9mnx SoZ0JIxZhqUTN7TK3RrXTuR4REc/EWNhLoPHv1x0GY9qGatUpMPfEtC12/gsMDLkLtssd67l3F +rTpaP0btExGsnkXPj39AUPv8h8bc5Ym+tnPYg1NCO9/Ny9/gGVwda9Hj0RlLGlj9gReQH7rtZ Dcex0BENudHRXBPboLsz1feL X-IronPort-AV: E=Sophos;i="5.87,169,1631602800"; d="scan'208";a="140598015" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa5.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 21 Oct 2021 04:47:21 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.87.72) by chn-vm-ex02.mchp-main.com (10.10.87.72) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.14; Thu, 21 Oct 2021 04:47:21 -0700 Received: from [10.159.245.112] (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2176.14 via Frontend Transport; Thu, 21 Oct 2021 04:47:19 -0700 Subject: Re: [PATCH 0/3] ARM: dts: at91: enable leftover IPs To: Claudiu Beznea , , , CC: , , References: <20211020094656.3343242-1-claudiu.beznea@microchip.com> From: Nicolas Ferre Organization: microchip Message-ID: <3e0c9bdb-f224-3c0b-cb11-c089185824d1@microchip.com> Date: Thu, 21 Oct 2021 13:47:19 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.11.0 MIME-Version: 1.0 In-Reply-To: <20211020094656.3343242-1-claudiu.beznea@microchip.com> Content-Type: text/plain; charset="windows-1252"; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 20/10/2021 at 11:46, Claudiu Beznea wrote: > Hi, > > The following series add DT nodes for TCB and RTC blocks on SAMA7G5. > > Thank you, > Claudiu Beznea For whole series: Acked-by: Nicolas Ferre Queued in at91-dt for 5.16. I plan to send a PR tomorrow. Best regards, Nicolas > Claudiu Beznea (2): > ARM: dts: at91: sama7g5: add tcb nodes > ARM: dts: at91: sama7g5-ek: use blocks 0 and 1 of TCB0 as cs and ce > > Eugen Hristev (1): > ARM: dts: at91: sama7g5: add rtc node > > arch/arm/boot/dts/at91-sama7g5ek.dts | 12 ++++++++++++ > arch/arm/boot/dts/sama7g5.dtsi | 27 +++++++++++++++++++++++++++ > 2 files changed, 39 insertions(+) > -- Nicolas Ferre From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E754EC433F5 for ; Thu, 21 Oct 2021 11:48:58 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A910A611CE for ; Thu, 21 Oct 2021 11:48:58 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org A910A611CE Authentication-Results: mail.kernel.org; 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d="scan'208";a="140598015" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa5.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 21 Oct 2021 04:47:21 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.87.72) by chn-vm-ex02.mchp-main.com (10.10.87.72) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.14; Thu, 21 Oct 2021 04:47:21 -0700 Received: from [10.159.245.112] (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2176.14 via Frontend Transport; Thu, 21 Oct 2021 04:47:19 -0700 Subject: Re: [PATCH 0/3] ARM: dts: at91: enable leftover IPs To: Claudiu Beznea , , , CC: , , References: <20211020094656.3343242-1-claudiu.beznea@microchip.com> From: Nicolas Ferre Organization: microchip Message-ID: <3e0c9bdb-f224-3c0b-cb11-c089185824d1@microchip.com> Date: Thu, 21 Oct 2021 13:47:19 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.11.0 MIME-Version: 1.0 In-Reply-To: <20211020094656.3343242-1-claudiu.beznea@microchip.com> Content-Language: en-US X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211021_044723_962592_A2CDD6AA X-CRM114-Status: GOOD ( 13.07 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 20/10/2021 at 11:46, Claudiu Beznea wrote: > Hi, > > The following series add DT nodes for TCB and RTC blocks on SAMA7G5. > > Thank you, > Claudiu Beznea For whole series: Acked-by: Nicolas Ferre Queued in at91-dt for 5.16. I plan to send a PR tomorrow. Best regards, Nicolas > Claudiu Beznea (2): > ARM: dts: at91: sama7g5: add tcb nodes > ARM: dts: at91: sama7g5-ek: use blocks 0 and 1 of TCB0 as cs and ce > > Eugen Hristev (1): > ARM: dts: at91: sama7g5: add rtc node > > arch/arm/boot/dts/at91-sama7g5ek.dts | 12 ++++++++++++ > arch/arm/boot/dts/sama7g5.dtsi | 27 +++++++++++++++++++++++++++ > 2 files changed, 39 insertions(+) > -- Nicolas Ferre _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel