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[2.143.78.206]) by smtp.gmail.com with ESMTPSA id l2sm4012303wmi.1.2021.09.05.01.11.47 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 05 Sep 2021 01:11:48 -0700 (PDT) Subject: Re: [PATCH v10 03/16] target/riscv: clwz must ignore high bits (use shift-left & changed logic) To: Philipp Tomsich , qemu-devel@nongnu.org References: <20210904203516.2570119-1-philipp.tomsich@vrull.eu> <20210904203516.2570119-4-philipp.tomsich@vrull.eu> From: Richard Henderson Message-ID: <3e608998-3270-cf41-66b5-32158db99de0@linaro.org> Date: Sun, 5 Sep 2021 10:11:44 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.13.0 MIME-Version: 1.0 In-Reply-To: <20210904203516.2570119-4-philipp.tomsich@vrull.eu> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -58 X-Spam_score: -5.9 X-Spam_bar: ----- X-Spam_report: (-5.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-3.832, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kito Cheng , Alistair Francis Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 9/4/21 10:35 PM, Philipp Tomsich wrote: > Assume clzw being executed on a register that is not sign-extended, such > as for the following sequence that uses (1ULL << 63) | 392 as the operand > to clzw: > bseti a2, zero, 63 > addi a2, a2, 392 > clzw a3, a2 > The correct result of clzw would be 23, but the current implementation > returns -32 (as it performs a 64bit clz, which results in 0 leading zero > bits, and then subtracts 32). > > Fix this by changing the implementation to: > 1. shift the original register up by 32 > 2. performs a target-length (64bit) clz > 3. return 32 if no bits are set > > Signed-off-by: Philipp Tomsich > --- > > Changes in v10: > - New patch, fixing correctnes for clzw called on a register with undefined > (as in: not properly sign-extended) upper bits. But we have return gen_unary(ctx, a, EXT_ZERO, gen_clzw); should *not* be undefined. Ah, what's missing is ctx->w = true; within trans_clzw to cause the extend to take effect. There are a few other "w" functions that are missing that set, though they use EXT_NONE so there is no visible bug, it would probably be best to set w anyway. r~