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[69.222.133.165]) by smtp.googlemail.com with ESMTPSA id l131sm2825201ywc.0.2019.05.23.11.03.57 (version=TLS1_3 cipher=AEAD-AES128-GCM-SHA256 bits=128/128); Thu, 23 May 2019 11:03:57 -0700 (PDT) To: Richard Henderson , =?UTF-8?Q?Alex_Benn=c3=a9e?= References: <20190517224450.15566-1-jan.bobek@gmail.com> <87v9y5gvfq.fsf@zen.linaroharston> <233da7c2-baed-face-16e8-af7a06d642c5@gmail.com> <0d863686-435b-e3f6-e358-926591bbd7d3@linaro.org> From: Jan Bobek Openpgp: preference=signencrypt Autocrypt: addr=jan.bobek@gmail.com; prefer-encrypt=mutual; keydata= mQINBFbeakcBEACzYOxOXdeT3Ns+5fdSqZFODAb3VXBKQ9DL7ooxLQRhvAx6rKXP/ZkBD7eg q8DJuvx6FbH227wpX+JZQawtolRJO+BTOuyU4ANPn3LGQHNtI78VhjafK7/Geb/9J6mTLl+P iS1EpLjKFbaLQboOaVVCPOHfLJOMNm5Ks9iHVKPQcUWUnroZdm55MIWjRw+wYGpmLD/R+FK/ Cm1fS3j+tu9VYFoEFZmwW//PYzmEtYHpwXA6dOWEd12cu2208/JcEHYBl0Z6Oga0xAk2OxU5 BOELuewGLuSiWik4z594GLVleC2NMnr3gUPl1y8ADrKzQwYmPgytIdsQ0tkV5rK9R1XTk03e ZLViYWJt5dgea+jGWcHPKPfLln53V4nCbwklGFLJQDMo8hL82bjJ7x9bsXoAnkPxJgYHgsM0 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X-Received-From: 2607:f8b0:4864:20::c33 X-Content-Filtered-By: Mailman/MimeDel 2.1.21 Subject: Re: [Qemu-devel] [RISU v2 00/11] Support for i386/x86_64 with vector extensions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" This is an OpenPGP/MIME signed message (RFC 4880 and 3156) --uStn0J5Uu8jbNXG08xXWHntSxVXxZtBHn From: Jan Bobek To: Richard Henderson , =?UTF-8?Q?Alex_Benn=c3=a9e?= Cc: qemu-devel@nongnu.org Message-ID: <3e9ec904-62f4-1886-7d33-1903e795adf0@gmail.com> Subject: Re: [RISU v2 00/11] Support for i386/x86_64 with vector extensions References: <20190517224450.15566-1-jan.bobek@gmail.com> <87v9y5gvfq.fsf@zen.linaroharston> <233da7c2-baed-face-16e8-af7a06d642c5@gmail.com> <0d863686-435b-e3f6-e358-926591bbd7d3@linaro.org> In-Reply-To: <0d863686-435b-e3f6-e358-926591bbd7d3@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable On 5/21/19 12:49 PM, Richard Henderson wrote: > SSE2 is a mandatory part of the x86_64 ABI. >=20 > I sincerely doubt we care about testing 32-bit that does not have SSE, = but even > then this patch set will not fail, as the kernel will not include the S= SE > registers into the signal frame. It would be the actual test cases for= SSE > instructions that would SIGILL when run on a 32-bit guest w/o SSE. Fair enough. I had no idea that SSE2 is mandatory in x86_64, that's good to know. Let's keep the SSE default then. > No, the assert is really an assert, because we have also masked the --x= features > value against the set of features stored in the signal frame. If the k= ernel > reports a feature in the signal frame for which there is no cpuid leaf,= then > something is very confused somewhere. Ah, I see. Makes complete sense. > I am not sure that we can validate that the features in the signal fram= e match > the --xfeatures value, because I *think* that features are omitted from= the > XSAVE data structure when they are in init state. E.g. when we have no= t yet > exercised the feature. >=20 > This caveat is definitely true of ARM SVE, and I found that if I assert= ed that > all of the SVE state was in the signal frame that the generated RISU te= st which > uses memory would fail the 1st checkpoint, because no SVE instructions = had yet > been executed. >=20 > A careful reading of the XSAVE documentation, plus some experimentation= , is > definitely required. Maybe hand-craft a test case using XRSTOR, giving= it a > save area that specifies all features to be reset to init state. tl;dr Richard is exactly right; a component may be missing from the XSAVE region if it's in the "initial configuration." I'd just leave it as it is now: it appears everything more advanced than the SSE state is in the initial configuration when the test image starts executing. It won't show up until there's instructions which actually touch it, but by then we get a SIGILL if the HW doesn't support it. Long story: The Intel manual definitely has a notion of "init optimization," in addition to "modified optimization." Vol. 1, Section 13.6 "Processor Tracking of XSAVE Managed State" says: The XSAVEOPT, XSAVEC, and XSAVES instructions use two optimizations to reduce the amount of data that they write to memory. They avoid writing data for any state component known to be in its initial configuration (the init optimization). In addition, if either XSAVEOPT or XSAVES is using the same XSAVE area as that used by the most recent execution of XRSTOR or XRSTORS, it may avoid writing data for any state component whose configuration is known not to have been modified since then (the modified optimization). (XSAVE does not use these optimizations, and XSAVEC does not use the modified optimization.) So, XSAVE does not use any optimizations, whereas all other XSAVE variants use at least the init optimization. Furthermore, The following notation describes the state of the init and modified optimizations: * XINUSE denotes the state-component bitmap corresponding to the init optimization. If XINUSE[i] =3D 0, state component i is known to be in its initial configuration; otherwise XINUSE[i] =3D 1. It is possible for XINUSE[i] to be 1 even when state component i is in its initial configuration. On a processor that does not support the init optimization, XINUSE[i] is always 1 for every value of i. [...] The processor does not need to detect "return" to the initial configuration; this makes more sense once it's clear what the initial configuration is: The following items specify the initial configuration each state component (for the purposes of defining the XINUSE bitmap): * SSE state. In 64-bit mode, SSE state is in its initial configuration if each of XMM0=E2=80=93XMM15 is 0. Outside 64-bit mode= , SSE state is in its initial configuration if each of XMM0=E2=80=93XMM7 is= 0. [...] * AVX state. In 64-bit mode, AVX state is in its initial configuration if each of YMM0_H=E2=80=93YMM15_H is 0. Outside 64-bit = mode, AVX state is in its initial configuration if each of YMM0_H=E2=80=93Y= MM7_H is 0. [...] [...] No surprise here; the initial configuration is just all zeros. I ran some experiments on my laptop's Intel(R) Core(TM) i5-4210U to find out what actually happens. This CPU supports AVX (but not AVX-512) and doesn't support XSAVEC, so I only looked at XSAVE and XSAVEOPT (XSAVES is kernel-mode only). I found out that: 1. both XSAVE and XSAVEOPT do not include the AVX state if it is in the initial configuration (not only XSAVEOPT), 2. return to initial configuration is not detected, i.e. the AVX state is included even though it has been set to all zeros via vxorps, 3. the AVX state can be brought back to the initial configuration via XRSTOR with the AVX component removed. Cheers, -Jan --uStn0J5Uu8jbNXG08xXWHntSxVXxZtBHn Content-Type: application/pgp-signature; name="signature.asc" Content-Description: OpenPGP digital signature Content-Disposition: attachment; filename="signature.asc" -----BEGIN PGP SIGNATURE----- iQIzBAEBCgAdFiEESPYOqtMR3qRZrEutZeg2ldrjNs8FAlzm4IcACgkQZeg2ldrj Ns9L5xAAnW6Bc8Ni88E0R5J0AHsZX+2npp4g7L9j/QN4x3oWlook2qTF/XtmpAZl P9Pd7Tvun+t1VGJ1esP2OhkIGO9A/wx5dGGw3YnkByz67B4MCMdd/7B/FwQ4UA4h iLgZNwDwX97JWjzHA5vTT8+ElC0cmkerpzjkd3z/bzM+Lfhu2OAFY408w4WJkbqu nJ8WUcHivncOVeFtyNldCrQzbLeLBlr8am5B6muo5SCpa8iI8LkW0NJIjHydG1rq RueqqfOqNB04DdLj/WTZXdYtLwXndd4seAUm1KHC5dUWq/8u1Oj4kAZShXkDOStE 63EeclUip2xLGQzA+T4V5CLYFHqWjoKj0+XEcwsGx7UXPXOGZas/ST8cJ9HPhdFu TbR+3c0a296d25rJS3rG1XyBmZj9JYDDP39VCle7tCtCx8Zw2ANjxKklLViUYYnq DJOPIyqRW/SPf0rOZIfMzTmq7TcpcZ1XGxrAhI6I7oKiLLnLEMv0bPeC0y0oV4sr 6O1dQlOzPirT+PeFuvve7ll1lSSjFZMTFdU9OOQlnlx3ecQHBLgUO7yoSwMhyzvy CSY0ohqhBPU0tNOIqSDnTibVbqqpb+gJ0vAaAqubn1KkrvWnRPyrtmLWvh/4c7tf K75JDy5h81L1SGKT7FQje6B3gDnYtLlBS5HFO4PWa+ShVFJo7Jw= =3e70 -----END PGP SIGNATURE----- --uStn0J5Uu8jbNXG08xXWHntSxVXxZtBHn--