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[91.14.161.181]) by smtp.gmail.com with ESMTPSA id b16sm4389540wrp.82.2021.09.22.23.43.02 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 22 Sep 2021 23:43:02 -0700 (PDT) Subject: Re: [PATCH 00/66] Move to IP driven device enumeration To: Alex Deucher Cc: Alex Deucher , amd-gfx list References: <20210921180725.1985552-1-alexander.deucher@amd.com> <54e06b10-1921-5791-75a8-38a0041ef569@gmail.com> From: =?UTF-8?Q?Christian_K=c3=b6nig?= Message-ID: <3eb3d8b9-7087-19dd-2762-c9afde6b1a6b@gmail.com> Date: Thu, 23 Sep 2021 08:43:01 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.13.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Content-Language: en-US X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" Am 22.09.21 um 22:25 schrieb Alex Deucher: > On Wed, Sep 22, 2021 at 3:54 AM Christian König > wrote: >> [SNIP] >> Comment for patch #32: >> >> Maybe adjust the commit subject, otherwise somebody could think it's a >> revert the the previous patch. > I was thinking I could just apply 31 independently of what happens to > this patch set. I meant to split it out as a separate bug fix patch, > but it got lost in the other patches. Good point. I suggest to just push it to amd-staging-drm-next ASAP and not consider it part of this set any more. >> Comment on patch #51, #52 and #61: >> >> That looks just a little bit questionable. Could we clean that up or >> would that be to much churn for little gain? > What did you have in mind? As I mentioned in the reply to Lijo, the > IP discovery table uses a mix of separate HWIDs and multiple instances > of the same HWID to handle instancing. Patch #52 adds something like: "adev->ip_versions[hw_ip + ip->number_instance] =..." While patch #61 then cleans that up towards: "adev->ip_versions[hw_ip][ip->number_instance] =..." It would be nice to have some clean concept which handles all of the hw_ip oddies gracefully in the first place. And then add what you wrote to Lijo as comment somewhere as well. Not a must have, but I think it would make things a bit cleaner and more review- and maintain-able. >> Comment on patch #63: >> >>> case IP_VERSION(7, 2, 0): >>> - amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block); >>> + if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev))) >>> + amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block); >> Checking the IP version and then the chip type looks questionable. I >> have an idea where this comes from, but please confirm with a comment. > It's just because SR-IOV is only enabled on certain asics and that is > the way the old code looked. I guess I could drop the asic_type > checks. We'd never end up in with amdgpu_sriov_vf() returning true on > a asic without SR-IOV support in the first place. Yeah, either that our just add something like "SRIOV is only enabled on certain asics" as comment. Christian. > > Alex >