From mboxrd@z Thu Jan 1 00:00:00 1970 From: Robin Murphy Subject: Re: [PATCH 1/7] iommu/arm-smmu: add Nvidia SMMUv2 implementation Date: Mon, 2 Sep 2019 14:39:56 +0100 Message-ID: <3f2cbbe2-f6d7-07e3-3fef-18af518dedef@arm.com> References: <1567118827-26358-1-git-send-email-vdumpa@nvidia.com> <1567118827-26358-2-git-send-email-vdumpa@nvidia.com> <2ae9e0c4-6916-b005-f4bd-29e06d2056c6@arm.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii"; Format="flowed" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: Content-Language: en-GB List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: iommu-bounces-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org Errors-To: iommu-bounces-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org To: Krishna Reddy Cc: Timo Alho , Thierry Reding , Mikko Perttunen , "linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" , "will.deacon-5wv7dgnIgG8@public.gmane.org" , "iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org" , Pritesh Raithatha , "Thomas Zeng (SW-TEGRA)" , Sachin Nikam , "linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" , Yu-Huan Hsu , Juha Tukkinen , Alexander Van Brunt , "linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org" List-Id: linux-tegra@vger.kernel.org On 30/08/2019 19:16, Krishna Reddy wrote: >>> +ARM_SMMU_MATCH_DATA(nvidia_smmuv2, ARM_SMMU_V2, NVIDIA_SMMUV2); > >> From the previous discussions, I got the impression that other than the 'novel' way they're integrated, the actual SMMU implementations were unmodified Arm MMU-500s. Is that the case, or have I misread something? > > The ARM MMU-500 implementation is unmodified. It is the way the are integrated and used together(for interleaved accesses) is different from regular ARM MMU-500. > I have added it to get the model number and to be able differentiate the SMMU implementation in arm-smmu-impl.c. In that case, I would rather keep smmu->model representing the MMU-500 microarchitecture - since you'll still want to pick up errata workarounds etc. for that - and detect the Tegra integration via an explicit of_device_is_compatible() check in arm_smmu_impl_init(). For comparison, under ACPI we'd probably have to detect integration details by looking at table headers, separately from the IORT "Model" field, so I'd prefer if the DT vs. ACPI handling didn't diverge more than necessary. Of course, that immediately opens the question of how best to combine arm_mmu500_impl with nsmmu_impl, but hey, one step at a time :) Robin. From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.2 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7DDACC3A5A7 for ; Mon, 2 Sep 2019 13:40:06 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 61C2521883 for ; Mon, 2 Sep 2019 13:40:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731487AbfIBNkF (ORCPT ); Mon, 2 Sep 2019 09:40:05 -0400 Received: from foss.arm.com ([217.140.110.172]:54764 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731454AbfIBNkC (ORCPT ); Mon, 2 Sep 2019 09:40:02 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D16C7337; Mon, 2 Sep 2019 06:40:01 -0700 (PDT) Received: from [10.1.197.57] (e110467-lin.cambridge.arm.com [10.1.197.57]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 6C16B3F59C; Mon, 2 Sep 2019 06:39:57 -0700 (PDT) Subject: Re: [PATCH 1/7] iommu/arm-smmu: add Nvidia SMMUv2 implementation To: Krishna Reddy Cc: Sachin Nikam , "Thomas Zeng (SW-TEGRA)" , Juha Tukkinen , Mikko Perttunen , Pritesh Raithatha , "iommu@lists.linux-foundation.org" , "linux-kernel@vger.kernel.org" , Timo Alho , Yu-Huan Hsu , "linux-tegra@vger.kernel.org" , Thierry Reding , Alexander Van Brunt , "linux-arm-kernel@lists.infradead.org" , "will.deacon@arm.com" , "joro@8bytes.org" References: <1567118827-26358-1-git-send-email-vdumpa@nvidia.com> <1567118827-26358-2-git-send-email-vdumpa@nvidia.com> <2ae9e0c4-6916-b005-f4bd-29e06d2056c6@arm.com> From: Robin Murphy Message-ID: <3f2cbbe2-f6d7-07e3-3fef-18af518dedef@arm.com> Date: Mon, 2 Sep 2019 14:39:56 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.6.1 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-GB Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 30/08/2019 19:16, Krishna Reddy wrote: >>> +ARM_SMMU_MATCH_DATA(nvidia_smmuv2, ARM_SMMU_V2, NVIDIA_SMMUV2); > >> From the previous discussions, I got the impression that other than the 'novel' way they're integrated, the actual SMMU implementations were unmodified Arm MMU-500s. Is that the case, or have I misread something? > > The ARM MMU-500 implementation is unmodified. It is the way the are integrated and used together(for interleaved accesses) is different from regular ARM MMU-500. > I have added it to get the model number and to be able differentiate the SMMU implementation in arm-smmu-impl.c. In that case, I would rather keep smmu->model representing the MMU-500 microarchitecture - since you'll still want to pick up errata workarounds etc. for that - and detect the Tegra integration via an explicit of_device_is_compatible() check in arm_smmu_impl_init(). For comparison, under ACPI we'd probably have to detect integration details by looking at table headers, separately from the IORT "Model" field, so I'd prefer if the DT vs. ACPI handling didn't diverge more than necessary. Of course, that immediately opens the question of how best to combine arm_mmu500_impl with nsmmu_impl, but hey, one step at a time :) Robin. From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.2 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 86B03C3A59E for ; Mon, 2 Sep 2019 13:40:05 +0000 (UTC) Received: from mail.linuxfoundation.org (mail.linuxfoundation.org [140.211.169.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 667E4216C8 for ; Mon, 2 Sep 2019 13:40:05 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 667E4216C8 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=iommu-bounces@lists.linux-foundation.org Received: from mail.linux-foundation.org (localhost [127.0.0.1]) by mail.linuxfoundation.org (Postfix) with ESMTP id 38CA2E9D; Mon, 2 Sep 2019 13:40:05 +0000 (UTC) Received: from smtp1.linuxfoundation.org (smtp1.linux-foundation.org [172.17.192.35]) by mail.linuxfoundation.org (Postfix) with ESMTPS id 62F2EE70 for ; Mon, 2 Sep 2019 13:40:03 +0000 (UTC) X-Greylist: domain auto-whitelisted by SQLgrey-1.7.6 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp1.linuxfoundation.org (Postfix) with ESMTP id 38DF2709 for ; Mon, 2 Sep 2019 13:40:02 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D16C7337; Mon, 2 Sep 2019 06:40:01 -0700 (PDT) Received: from [10.1.197.57] (e110467-lin.cambridge.arm.com [10.1.197.57]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 6C16B3F59C; Mon, 2 Sep 2019 06:39:57 -0700 (PDT) Subject: Re: [PATCH 1/7] iommu/arm-smmu: add Nvidia SMMUv2 implementation To: Krishna Reddy References: <1567118827-26358-1-git-send-email-vdumpa@nvidia.com> <1567118827-26358-2-git-send-email-vdumpa@nvidia.com> <2ae9e0c4-6916-b005-f4bd-29e06d2056c6@arm.com> From: Robin Murphy Message-ID: <3f2cbbe2-f6d7-07e3-3fef-18af518dedef@arm.com> Date: Mon, 2 Sep 2019 14:39:56 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.6.1 MIME-Version: 1.0 In-Reply-To: Content-Language: en-GB Cc: Timo Alho , Thierry Reding , Mikko Perttunen , "linux-kernel@vger.kernel.org" , "will.deacon@arm.com" , "iommu@lists.linux-foundation.org" , Pritesh Raithatha , "Thomas Zeng \(SW-TEGRA\)" , Sachin Nikam , "linux-tegra@vger.kernel.org" , Yu-Huan Hsu , Juha Tukkinen , Alexander Van Brunt , "linux-arm-kernel@lists.infradead.org" X-BeenThere: iommu@lists.linux-foundation.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: Development issues for Linux IOMMU support List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: iommu-bounces@lists.linux-foundation.org Errors-To: iommu-bounces@lists.linux-foundation.org On 30/08/2019 19:16, Krishna Reddy wrote: >>> +ARM_SMMU_MATCH_DATA(nvidia_smmuv2, ARM_SMMU_V2, NVIDIA_SMMUV2); > >> From the previous discussions, I got the impression that other than the 'novel' way they're integrated, the actual SMMU implementations were unmodified Arm MMU-500s. Is that the case, or have I misread something? > > The ARM MMU-500 implementation is unmodified. It is the way the are integrated and used together(for interleaved accesses) is different from regular ARM MMU-500. > I have added it to get the model number and to be able differentiate the SMMU implementation in arm-smmu-impl.c. In that case, I would rather keep smmu->model representing the MMU-500 microarchitecture - since you'll still want to pick up errata workarounds etc. for that - and detect the Tegra integration via an explicit of_device_is_compatible() check in arm_smmu_impl_init(). For comparison, under ACPI we'd probably have to detect integration details by looking at table headers, separately from the IORT "Model" field, so I'd prefer if the DT vs. ACPI handling didn't diverge more than necessary. Of course, that immediately opens the question of how best to combine arm_mmu500_impl with nsmmu_impl, but hey, one step at a time :) Robin. _______________________________________________ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.2 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 323A1C3A59E for ; Mon, 2 Sep 2019 13:44:01 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 0601A216C8 for ; Mon, 2 Sep 2019 13:44:01 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="MTjL/pR0" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 0601A216C8 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender:Content-Type: Content-Transfer-Encoding:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:Date:Message-ID:From: References:To:Subject:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=lpdM+8eQIpneHS5rBBDMW75zZl+zCxegbsdAXoMHJ8A=; b=MTjL/pR01ti62nYtzsfm4n5yC XUPkZNExxlAJt8aDX+uKNIxukFO7B0apYVfllGVkgAJkTACdxcNmL7yxuBqdxilvpRqniO4P1Qij2 WGotTc/nD4s42l20LoiKy3DHGSnVP2Q2Q0CzLRLnsnEQRSz7wQwUzaNbvs1PFVH2gamvwj1N9ECeQ odaH2a62fNvwRDY6oOQFDpjbMMipLY8NOo5dOMv3bUwuwr3ZEb13oMGkiKdcUdWoZY8Ja55hyMl/y g0cGxOlFV2xhudwYmIOAiyBY/FzpkLNuPcQO9etBFW85urakloQSwMFBOdfQ2efy3gWnbxIw8Ihuc avrTSXgJw==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92 #3 (Red Hat Linux)) id 1i4mce-0007ok-3j; Mon, 02 Sep 2019 13:43:56 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.92 #3 (Red Hat Linux)) id 1i4mYs-0002WZ-D1 for linux-arm-kernel@lists.infradead.org; Mon, 02 Sep 2019 13:40:05 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D16C7337; Mon, 2 Sep 2019 06:40:01 -0700 (PDT) Received: from [10.1.197.57] (e110467-lin.cambridge.arm.com [10.1.197.57]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 6C16B3F59C; Mon, 2 Sep 2019 06:39:57 -0700 (PDT) Subject: Re: [PATCH 1/7] iommu/arm-smmu: add Nvidia SMMUv2 implementation To: Krishna Reddy References: <1567118827-26358-1-git-send-email-vdumpa@nvidia.com> <1567118827-26358-2-git-send-email-vdumpa@nvidia.com> <2ae9e0c4-6916-b005-f4bd-29e06d2056c6@arm.com> From: Robin Murphy Message-ID: <3f2cbbe2-f6d7-07e3-3fef-18af518dedef@arm.com> Date: Mon, 2 Sep 2019 14:39:56 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.6.1 MIME-Version: 1.0 In-Reply-To: Content-Language: en-GB X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190902_064002_587000_83681DD2 X-CRM114-Status: GOOD ( 14.66 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Timo Alho , Thierry Reding , Mikko Perttunen , "linux-kernel@vger.kernel.org" , "joro@8bytes.org" , "will.deacon@arm.com" , "iommu@lists.linux-foundation.org" , Pritesh Raithatha , "Thomas Zeng \(SW-TEGRA\)" , Sachin Nikam , "linux-tegra@vger.kernel.org" , Yu-Huan Hsu , Juha Tukkinen , Alexander Van Brunt , "linux-arm-kernel@lists.infradead.org" Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 30/08/2019 19:16, Krishna Reddy wrote: >>> +ARM_SMMU_MATCH_DATA(nvidia_smmuv2, ARM_SMMU_V2, NVIDIA_SMMUV2); > >> From the previous discussions, I got the impression that other than the 'novel' way they're integrated, the actual SMMU implementations were unmodified Arm MMU-500s. Is that the case, or have I misread something? > > The ARM MMU-500 implementation is unmodified. It is the way the are integrated and used together(for interleaved accesses) is different from regular ARM MMU-500. > I have added it to get the model number and to be able differentiate the SMMU implementation in arm-smmu-impl.c. In that case, I would rather keep smmu->model representing the MMU-500 microarchitecture - since you'll still want to pick up errata workarounds etc. for that - and detect the Tegra integration via an explicit of_device_is_compatible() check in arm_smmu_impl_init(). For comparison, under ACPI we'd probably have to detect integration details by looking at table headers, separately from the IORT "Model" field, so I'd prefer if the DT vs. ACPI handling didn't diverge more than necessary. Of course, that immediately opens the question of how best to combine arm_mmu500_impl with nsmmu_impl, but hey, one step at a time :) Robin. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel