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From: Patrick DELAUNAY <patrick.delaunay@st.com>
To: u-boot@lists.denx.de
Subject: [PATCH 2/2] [RFC] clk: stm32mp1: Handle SoC speed grade configs
Date: Wed, 13 May 2020 12:23:37 +0000	[thread overview]
Message-ID: <3f2db76ce23042a6a0c2066b95a91510@SFHDAG6NODE3.st.com> (raw)
In-Reply-To: <1e976268-91b4-9f3b-8455-a91a39df6cdb@denx.de>

Hi Marek,

> From: Marek Vasut <marex@denx.de>
> Sent: mercredi 13 mai 2020 12:53
> 
> On 5/13/20 11:12 AM, Patrick DELAUNAY wrote:
> > Dear Marek,
> >
> >> From: Marek Vasut <marex@denx.de>
> >> Sent: mardi 12 mai 2020 19:07
> >>
> >> There are two speed grades of the STM32MP1, the A/C and D/F, the
> >> former can run up to 650 MHz, the later at up to 800 MHz. Allow
> >> specifying PLL config for both in the DT, so that it is possible to
> >> cater for boards which can be populated with either SoC.
> >>
> >> Signed-off-by: Marek Vasut <marex@denx.de>
> >> Cc: Patrick Delaunay <patrick.delaunay@st.com>
> >> Cc: Patrice Chotard <patrice.chotard@st.com>
> >> ---
> >>  drivers/clk/clk_stm32mp1.c | 30 ++++++++++++++++++++++++++----
> >>  1 file changed, 26 insertions(+), 4 deletions(-)
> >>

[...]

> >
> > The 2 speed grade will be supported with OPP information and HW
> > support,present in kernel device tree (upstream in progress)
> >
> > I port this patch in U-Boot with:
> > http://patchwork.ozlabs.org/project/uboot/patch/20200421171123.2.Id362
> > 0aec4deb419f1c1a5876b865556e86d3aba1 at changeid/
> >
> >
> > Please check the full serie
> > stm32mp1: use OPP information for PLL1 settings in SPL
> > http://patchwork.ozlabs.org/project/uboot/list/?series=171767
> >
> > PLL1 settings are now computed in SPL and no more read from DT.
> 
> That's even better, nice, thanks !
> 
> btw. does the D/F 800 MHz always set BIT(7) in the CPU ID , while the A/C 650
> MHz part never does ? Maybe you can use that to discern the speed grades
> instead of listing all the parts ...

Yes but the meaning of RPN (the part of CPU IP) is undocumented... 
And BIT(7) could be no more be valid for next products.

So I prefer use the documented value of Device Part Number (RPN) as a fixed value.
 
For example:

Bits 7:0 RPN_coding[7:0]:
0x00: STM32MP157Cx
0x01: STM32MP157Ax
0x80: STM32MP157Fx
0x81: STM32MP157Dx
Others: Reserved

And it is also requested by ST marketing team
(don't code on RPN bit decoding).

Even if I agree: it is more elegant than my switch case.

> --
> Best regards,
> Marek Vasut

Regards

Patrick

  reply	other threads:[~2020-05-13 12:23 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-05-12 17:07 [PATCH 1/2] [RFC] ARM: stm32: Make bsec available in SPL Marek Vasut
2020-05-12 17:07 ` [PATCH 2/2] [RFC] clk: stm32mp1: Handle SoC speed grade configs Marek Vasut
2020-05-13  9:12   ` Patrick DELAUNAY
2020-05-13 10:52     ` Marek Vasut
2020-05-13 12:23       ` Patrick DELAUNAY [this message]
2020-05-13 12:38         ` Marek Vasut
2020-06-14 15:23     ` Marek Vasut
2020-05-13  9:05 ` [PATCH 1/2] [RFC] ARM: stm32: Make bsec available in SPL Patrick DELAUNAY

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