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[120.151.179.201]) by smtp.gmail.com with ESMTPSA id j4sm1347696pjv.46.2022.01.25.15.34.24 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 25 Jan 2022 15:34:26 -0800 (PST) Subject: Re: [PATCH 2/2] target/arm: Bail out early on 0-length tlb range invalidate To: Peter Maydell References: <20220110164754.1066025-1-idan.horowitz@gmail.com> <20220110164754.1066025-2-idan.horowitz@gmail.com> <0f211c09-4b4d-2c82-cff6-64711563c6d8@linaro.org> From: Richard Henderson Message-ID: <3f89816f-5e59-bac5-01bc-d9cc73d15927@linaro.org> Date: Wed, 26 Jan 2022 10:34:20 +1100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.14.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::1032 (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::1032; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1032.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pbonzini@redhat.com, qemu-arm@nongnu.org, Idan Horowitz , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 1/26/22 9:06 AM, Peter Maydell wrote: > On Tue, 25 Jan 2022 at 22:05, Richard Henderson > wrote: >> >> On 1/11/22 3:47 AM, Idan Horowitz wrote: >>> If the given range specifies no addresses to be flushed there's no reason >>> to schedule a function on all CPUs that does nothing. >>> >>> Signed-off-by: Idan Horowitz >>> --- >>> target/arm/helper.c | 4 ++++ >>> 1 file changed, 4 insertions(+) >>> >>> diff --git a/target/arm/helper.c b/target/arm/helper.c >>> index cfca0f5ba6..1e819835c2 100644 >>> --- a/target/arm/helper.c >>> +++ b/target/arm/helper.c >>> @@ -4564,6 +4564,10 @@ static void do_rvae_write(CPUARMState *env, uint64_t value, >>> length = tlbi_aa64_range_get_length(env, value); >>> bits = tlbbits_for_regime(env, one_idx, baseaddr); >>> >>> + if (length == 0) { >>> + return; >>> + } >>> + >>> if (synced) { >>> tlb_flush_range_by_mmuidx_all_cpus_synced(env_cpu(env), >>> baseaddr, >>> >> >> Looks good. I guess we could sort the extractions above so that we do >> >> length = ...; >> if (length == 0) { >> return; >> } >> >> addr = ... >> bits = ... >> >> Either way, >> Reviewed-by: Richard Henderson > > Should we handle this in the tlb_flush_* functions themselves, > or is it just Arm that has to fix up a special case of "actually > the length is zero" ? Hmm. Probably should handle this in tlb_*, yes. So far, Arm is the only user regardless. r~