* [PATCH for-6.2 00/25] arm: Get rid of system_clock_scale global
@ 2021-08-12 9:33 Peter Maydell
2021-08-12 9:33 ` [PATCH for-6.2 01/25] arm: Move M-profile RAS register block into its own device Peter Maydell
` (24 more replies)
0 siblings, 25 replies; 91+ messages in thread
From: Peter Maydell @ 2021-08-12 9:33 UTC (permalink / raw)
To: qemu-arm, qemu-devel
Cc: Damien Hedde, Luc Michel, Alistair Francis, Subbaraya Sundeep,
Joel Stanley, Alexandre Iooss
This is mostly a (big) refactoring to use Clocks instead of a global.
Review of the new multiplier/divider functionality I've added to the
Clock API would also be interesting. If you're a maintainer for an
M-profile board that isn't covered by 'make check-acceptance' then
I'd appreciate it if you have time to test that this series didn't
accidentally break your board...
The Arm v7M systick timer can run off one of two clocks
(guest-selectable by writing the SYST_CSR.CLKSOURCE control
register bit):
* the main CPU clock
* a separate 'reference clock' which the SoC and board may
or may not wire up
Currently we model this as:
* the global variable system_clock_scale is set to the period in ns
of the CPU clock by the board or SoC level code
* the reference clock is a fixed 1MHz, hardcoded in armv7m_systick.c
This is very old code, dating back to the first v7M support in 2007.
We now have a Clock API, so we can model clocks using something a bit
more complicat^Wsophisticated than a global variable.
The series starts with some refactoring to move the creation of
various sub-devices including the systick timers out of the nvic
object and into the 'armv7m' container object. The NVIC was doing some
of this for historical reasons, but it makes more sense to have all of
the "create subdevices and map them into the right place in the
peripheral region of the address space" be in one place. This also
means that when we start wiring Clocks up we don't have to go via the
NVIC to get from the armv7m object to the systick timers.
We then add clock inputs to the systick device, which are initially
ignored. Subsequent patches wire up those clock inputs in SoC and
board level code. Once all the boards have wired up their clocks, we
can change the systick device to use those instead of the
system_clock_scale global. Finally we can delete all the places
setting the global.
For some of the boards the systick reference clock is a fixed
multiple/division of the CPU clock. To support this, the "clock:
Provide builtin multiplier/divider" patch enhances the Clock API to
let you configure a Clock such that all its children are run at a
given ratio of the parent clock.
For the different boards I have taken a variety of approaches:
* sometimes the refclk frequency was easy to determine from
the SoC docs, and the patches implement that, changing the
behaviour from the old 1MHz fixed refclk. This is in
effect a very minor bugfix.
* in a few cases I couldn't determine the refclk frequency, so
I have implemented those boards to retain the old 1MHz
value, as at least no-behavioural-change
* some SoCs don't wire up the refclk at all; with this series
we will correctly implement that (the SYST_CSR.CLKSOURCE control
register bit in the systick device is then read-only), so
again a minor bugfix
In some SoCs the refclk should theoretically be guest-programmable; we
didn't implement that before and we still don't. I've put in a few
comments noting this missing feature where relevant.
The other user of the system_clock_scale global is the GPTM timer in
the stellaris board, so there's a patch converting that to also use
Clock input.
There are also a few patches implementing minor cleanups I noticed
along the way that I felt would be in the way if I didn't fix them up
first.
NB: this series is a migration compat break for all the M-profile
boards, because it adds Clock objects to vmstate structs.
I've tested this with 'make check-acceptance', which tests the
emcraft-sf2 board, and I've run some stellaris and various MPS images
I have locally. Other affected boards (microbit, netduino2,
netduinoplus2, stm32vldiscovery) are untested (though 'make check'
confirms that they at least don't crash on startup...). Testing from
maintainers of those boards would be appreciated.
thanks
-- PMM
Peter Maydell (25):
arm: Move M-profile RAS register block into its own device
arm: Move systick device creation from NVIC to ARMv7M object
arm: Move system PPB container handling to armv7m
hw/timer/armv7m_systick: Add usual QEMU interface comment
hw/timer/armv7m_systick: Add input clocks
hw/arm/armv7m: Create input clocks
armsse: Wire up systick cpuclk clock
hw/arm/mps2.c: Connect up armv7m clocks
clock: Provide builtin multiplier/divider
hw/arm: Don't allocate separate MemoryRegions in stm32 SoC realize
hw/arm/stm32f100: Wire up sysclk and refclk
hw/arm/stm32f205: Wire up sysclk and refclk
hw/arm/stm32f405: Wire up sysclk and refclk
hw/arm/stm32vldiscovery: Delete trailing blank line
hw/arm/nrf51: Wire up sysclk
hw/arm/stellaris: split stellaris_sys_init()
hw/arm/stellaris: Wire sysclk up to armv7m
hw/arm/msf2_soc: Don't allocate separate MemoryRegions
hw/arm/msf2: Use Clock input to MSF2_SOC instead of m3clk property
hw/arm/msf2-soc: Wire up refclk
hw/timer/armv7m_systick: Use clock inputs instead of
system_clock_scale
hw/arm/stellaris: Fix code style issues in GPTM code
hw/arm/stellaris: Split stellaris-gptm into its own file
hw/timer/stellaris-gptm: Use Clock input instead of system_clock_scale
arm: Remove system_clock_scale global
docs/devel/clocks.rst | 23 ++
include/hw/arm/armv7m.h | 24 ++
include/hw/arm/msf2-soc.h | 8 +-
include/hw/arm/nrf51_soc.h | 2 +
include/hw/arm/stm32f100_soc.h | 8 +
include/hw/arm/stm32f205_soc.h | 8 +
include/hw/arm/stm32f405_soc.h | 3 +
include/hw/clock.h | 29 +++
include/hw/intc/armv7m_nvic.h | 8 -
include/hw/misc/armv7m_ras.h | 37 +++
include/hw/timer/armv7m_systick.h | 36 ++-
include/hw/timer/stellaris-gptm.h | 51 ++++
hw/arm/armsse.c | 20 +-
hw/arm/armv7m.c | 260 +++++++++++++++++++-
hw/arm/mps2.c | 17 +-
hw/arm/msf2-soc.c | 68 +++--
hw/arm/msf2-som.c | 7 +-
hw/arm/netduino2.c | 12 +-
hw/arm/netduinoplus2.c | 12 +-
hw/arm/nrf51_soc.c | 20 +-
hw/arm/stellaris.c | 396 ++++--------------------------
hw/arm/stm32f100_soc.c | 47 +++-
hw/arm/stm32f205_soc.c | 47 +++-
hw/arm/stm32f405_soc.c | 30 +++
hw/arm/stm32vldiscovery.c | 13 +-
hw/core/clock-vmstate.c | 24 +-
hw/core/clock.c | 29 ++-
hw/intc/armv7m_nvic.c | 274 +--------------------
hw/misc/armv7m_ras.c | 93 +++++++
hw/timer/armv7m_systick.c | 116 ++++++---
hw/timer/stellaris-gptm.c | 332 +++++++++++++++++++++++++
MAINTAINERS | 2 +
hw/arm/Kconfig | 1 +
hw/misc/meson.build | 2 +
hw/timer/Kconfig | 3 +
hw/timer/meson.build | 1 +
36 files changed, 1292 insertions(+), 771 deletions(-)
create mode 100644 include/hw/misc/armv7m_ras.h
create mode 100644 include/hw/timer/stellaris-gptm.h
create mode 100644 hw/misc/armv7m_ras.c
create mode 100644 hw/timer/stellaris-gptm.c
--
2.20.1
^ permalink raw reply [flat|nested] 91+ messages in thread
* [PATCH for-6.2 01/25] arm: Move M-profile RAS register block into its own device
2021-08-12 9:33 [PATCH for-6.2 00/25] arm: Get rid of system_clock_scale global Peter Maydell
@ 2021-08-12 9:33 ` Peter Maydell
2021-08-12 11:08 ` Alexandre IOOSS
` (3 more replies)
2021-08-12 9:33 ` [PATCH for-6.2 02/25] arm: Move systick device creation from NVIC to ARMv7M object Peter Maydell
` (23 subsequent siblings)
24 siblings, 4 replies; 91+ messages in thread
From: Peter Maydell @ 2021-08-12 9:33 UTC (permalink / raw)
To: qemu-arm, qemu-devel
Cc: Damien Hedde, Luc Michel, Alistair Francis, Subbaraya Sundeep,
Joel Stanley, Alexandre Iooss
Currently we implement the RAS register block within the NVIC device.
It isn't really very tightly coupled with the NVIC proper, so instead
move it out into a sysbus device of its own and have the top level
ARMv7M container create it and map it into memory at the right
address.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
include/hw/arm/armv7m.h | 2 +
include/hw/intc/armv7m_nvic.h | 1 -
include/hw/misc/armv7m_ras.h | 37 ++++++++++++++
hw/arm/armv7m.c | 12 +++++
hw/intc/armv7m_nvic.c | 56 ---------------------
hw/misc/armv7m_ras.c | 93 +++++++++++++++++++++++++++++++++++
MAINTAINERS | 2 +
hw/misc/meson.build | 2 +
8 files changed, 148 insertions(+), 57 deletions(-)
create mode 100644 include/hw/misc/armv7m_ras.h
create mode 100644 hw/misc/armv7m_ras.c
diff --git a/include/hw/arm/armv7m.h b/include/hw/arm/armv7m.h
index bc6733c5184..4cae0d7eeaa 100644
--- a/include/hw/arm/armv7m.h
+++ b/include/hw/arm/armv7m.h
@@ -12,6 +12,7 @@
#include "hw/sysbus.h"
#include "hw/intc/armv7m_nvic.h"
+#include "hw/misc/armv7m_ras.h"
#include "target/arm/idau.h"
#include "qom/object.h"
@@ -58,6 +59,7 @@ struct ARMv7MState {
NVICState nvic;
BitBandState bitband[ARMV7M_NUM_BITBANDS];
ARMCPU *cpu;
+ ARMv7MRAS ras;
/* MemoryRegion we pass to the CPU, with our devices layered on
* top of the ones the board provides in board_memory.
diff --git a/include/hw/intc/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h
index 39c71e15936..33b6d8810c7 100644
--- a/include/hw/intc/armv7m_nvic.h
+++ b/include/hw/intc/armv7m_nvic.h
@@ -83,7 +83,6 @@ struct NVICState {
MemoryRegion sysreg_ns_mem;
MemoryRegion systickmem;
MemoryRegion systick_ns_mem;
- MemoryRegion ras_mem;
MemoryRegion container;
MemoryRegion defaultmem;
diff --git a/include/hw/misc/armv7m_ras.h b/include/hw/misc/armv7m_ras.h
new file mode 100644
index 00000000000..f8773e65b14
--- /dev/null
+++ b/include/hw/misc/armv7m_ras.h
@@ -0,0 +1,37 @@
+/*
+ * Arm M-profile RAS block
+ *
+ * Copyright (c) 2021 Linaro Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 or
+ * (at your option) any later version.
+ */
+
+/*
+ * This is a model of the RAS register block of an M-profile CPU
+ * (the registers starting at 0xE0005000 with ERRFRn).
+ *
+ * QEMU interface:
+ * + sysbus MMIO region 0: the register bank
+ *
+ * The QEMU implementation currently provides "minimal RAS" only.
+ */
+
+#ifndef HW_MISC_ARMV7M_RAS_H
+#define HW_MISC_ARMV7M_RAS_H
+
+#include "hw/sysbus.h"
+
+#define TYPE_ARMV7M_RAS "armv7m-ras"
+OBJECT_DECLARE_SIMPLE_TYPE(ARMv7MRAS, ARMV7M_RAS)
+
+struct ARMv7MRAS {
+ /*< private >*/
+ SysBusDevice parent_obj;
+
+ /*< public >*/
+ MemoryRegion iomem;
+};
+
+#endif
diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c
index 9ce5c30cd5c..8964730d153 100644
--- a/hw/arm/armv7m.c
+++ b/hw/arm/armv7m.c
@@ -231,6 +231,18 @@ static void armv7m_realize(DeviceState *dev, Error **errp)
memory_region_add_subregion(&s->container, 0xe0000000,
sysbus_mmio_get_region(sbd, 0));
+ /* If the CPU has RAS support, create the RAS register block */
+ if (cpu_isar_feature(aa32_ras, s->cpu)) {
+ object_initialize_child(OBJECT(dev), "armv7m-ras",
+ &s->ras, TYPE_ARMV7M_RAS);
+ sbd = SYS_BUS_DEVICE(&s->ras);
+ if (!sysbus_realize(sbd, errp)) {
+ return;
+ }
+ memory_region_add_subregion_overlap(&s->container, 0xe0005000,
+ sysbus_mmio_get_region(sbd, 0), 1);
+ }
+
for (i = 0; i < ARRAY_SIZE(s->bitband); i++) {
if (s->enable_bitband) {
Object *obj = OBJECT(&s->bitband[i]);
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index 1e7ddcb94cb..a5975592dfa 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -2549,56 +2549,6 @@ static const MemoryRegionOps nvic_systick_ops = {
.endianness = DEVICE_NATIVE_ENDIAN,
};
-
-static MemTxResult ras_read(void *opaque, hwaddr addr,
- uint64_t *data, unsigned size,
- MemTxAttrs attrs)
-{
- if (attrs.user) {
- return MEMTX_ERROR;
- }
-
- switch (addr) {
- case 0xe10: /* ERRIIDR */
- /* architect field = Arm; product/variant/revision 0 */
- *data = 0x43b;
- break;
- case 0xfc8: /* ERRDEVID */
- /* Minimal RAS: we implement 0 error record indexes */
- *data = 0;
- break;
- default:
- qemu_log_mask(LOG_UNIMP, "Read RAS register offset 0x%x\n",
- (uint32_t)addr);
- *data = 0;
- break;
- }
- return MEMTX_OK;
-}
-
-static MemTxResult ras_write(void *opaque, hwaddr addr,
- uint64_t value, unsigned size,
- MemTxAttrs attrs)
-{
- if (attrs.user) {
- return MEMTX_ERROR;
- }
-
- switch (addr) {
- default:
- qemu_log_mask(LOG_UNIMP, "Write to RAS register offset 0x%x\n",
- (uint32_t)addr);
- break;
- }
- return MEMTX_OK;
-}
-
-static const MemoryRegionOps ras_ops = {
- .read_with_attrs = ras_read,
- .write_with_attrs = ras_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
-};
-
/*
* Unassigned portions of the PPB space are RAZ/WI for privileged
* accesses, and fault for non-privileged accesses.
@@ -2946,12 +2896,6 @@ static void armv7m_nvic_realize(DeviceState *dev, Error **errp)
&s->systick_ns_mem, 1);
}
- if (cpu_isar_feature(aa32_ras, s->cpu)) {
- memory_region_init_io(&s->ras_mem, OBJECT(s),
- &ras_ops, s, "nvic_ras", 0x1000);
- memory_region_add_subregion(&s->container, 0x5000, &s->ras_mem);
- }
-
sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->container);
}
diff --git a/hw/misc/armv7m_ras.c b/hw/misc/armv7m_ras.c
new file mode 100644
index 00000000000..a2b4f4b8dc8
--- /dev/null
+++ b/hw/misc/armv7m_ras.c
@@ -0,0 +1,93 @@
+/*
+ * Arm M-profile RAS block
+ *
+ * Copyright (c) 2021 Linaro Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 or
+ * (at your option) any later version.
+ */
+
+#include "qemu/osdep.h"
+#include "hw/misc/armv7m_ras.h"
+#include "qemu/log.h"
+
+static MemTxResult ras_read(void *opaque, hwaddr addr,
+ uint64_t *data, unsigned size,
+ MemTxAttrs attrs)
+{
+ if (attrs.user) {
+ return MEMTX_ERROR;
+ }
+
+ switch (addr) {
+ case 0xe10: /* ERRIIDR */
+ /* architect field = Arm; product/variant/revision 0 */
+ *data = 0x43b;
+ break;
+ case 0xfc8: /* ERRDEVID */
+ /* Minimal RAS: we implement 0 error record indexes */
+ *data = 0;
+ break;
+ default:
+ qemu_log_mask(LOG_UNIMP, "Read RAS register offset 0x%x\n",
+ (uint32_t)addr);
+ *data = 0;
+ break;
+ }
+ return MEMTX_OK;
+}
+
+static MemTxResult ras_write(void *opaque, hwaddr addr,
+ uint64_t value, unsigned size,
+ MemTxAttrs attrs)
+{
+ if (attrs.user) {
+ return MEMTX_ERROR;
+ }
+
+ switch (addr) {
+ default:
+ qemu_log_mask(LOG_UNIMP, "Write to RAS register offset 0x%x\n",
+ (uint32_t)addr);
+ break;
+ }
+ return MEMTX_OK;
+}
+
+static const MemoryRegionOps ras_ops = {
+ .read_with_attrs = ras_read,
+ .write_with_attrs = ras_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+};
+
+
+static void armv7m_ras_init(Object *obj)
+{
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
+ ARMv7MRAS *s = ARMV7M_RAS(obj);
+
+ memory_region_init_io(&s->iomem, obj, &ras_ops,
+ s, "armv7m-ras", 0x1000);
+ sysbus_init_mmio(sbd, &s->iomem);
+}
+
+static void armv7m_ras_class_init(ObjectClass *klass, void *data)
+{
+ /* This device has no state: no need for vmstate or reset */
+}
+
+static const TypeInfo armv7m_ras_info = {
+ .name = TYPE_ARMV7M_RAS,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(ARMv7MRAS),
+ .instance_init = armv7m_ras_init,
+ .class_init = armv7m_ras_class_init,
+};
+
+static void armv7m_ras_register_types(void)
+{
+ type_register_static(&armv7m_ras_info);
+}
+
+type_init(armv7m_ras_register_types);
diff --git a/MAINTAINERS b/MAINTAINERS
index 37b1a8e4428..3cac393bb48 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -617,6 +617,7 @@ F: hw/intc/gic_internal.h
F: hw/misc/a9scu.c
F: hw/misc/arm11scu.c
F: hw/misc/arm_l2x0.c
+F: hw/misc/armv7m_ras.c
F: hw/timer/a9gtimer*
F: hw/timer/arm*
F: include/hw/arm/arm*.h
@@ -626,6 +627,7 @@ F: include/hw/misc/arm11scu.h
F: include/hw/timer/a9gtimer.h
F: include/hw/timer/arm_mptimer.h
F: include/hw/timer/armv7m_systick.h
+F: include/hw/misc/armv7m_ras.h
F: tests/qtest/test-arm-mptimer.c
Exynos
diff --git a/hw/misc/meson.build b/hw/misc/meson.build
index a53b849a5a0..3f41a3a5b27 100644
--- a/hw/misc/meson.build
+++ b/hw/misc/meson.build
@@ -17,6 +17,8 @@ softmmu_ss.add(when: 'CONFIG_INTEGRATOR_DEBUG', if_true: files('arm_integrator_d
softmmu_ss.add(when: 'CONFIG_A9SCU', if_true: files('a9scu.c'))
softmmu_ss.add(when: 'CONFIG_ARM11SCU', if_true: files('arm11scu.c'))
+softmmu_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('armv7m_ras.c'))
+
# Mac devices
softmmu_ss.add(when: 'CONFIG_MOS6522', if_true: files('mos6522.c'))
--
2.20.1
^ permalink raw reply related [flat|nested] 91+ messages in thread
* [PATCH for-6.2 02/25] arm: Move systick device creation from NVIC to ARMv7M object
2021-08-12 9:33 [PATCH for-6.2 00/25] arm: Get rid of system_clock_scale global Peter Maydell
2021-08-12 9:33 ` [PATCH for-6.2 01/25] arm: Move M-profile RAS register block into its own device Peter Maydell
@ 2021-08-12 9:33 ` Peter Maydell
2021-08-13 1:23 ` Alistair Francis
2021-08-17 9:24 ` Luc Michel
2021-08-12 9:33 ` [PATCH for-6.2 03/25] arm: Move system PPB container handling to armv7m Peter Maydell
` (22 subsequent siblings)
24 siblings, 2 replies; 91+ messages in thread
From: Peter Maydell @ 2021-08-12 9:33 UTC (permalink / raw)
To: qemu-arm, qemu-devel
Cc: Damien Hedde, Luc Michel, Alistair Francis, Subbaraya Sundeep,
Joel Stanley, Alexandre Iooss
There's no particular reason why the NVIC should be owning the
SysTick device objects; move them into the ARMv7M container object
instead, as part of consolidating the "create the devices which are
built into an M-profile CPU and map them into their architected
locations in the address space" work into one place.
This involves temporarily creating a duplicate copy of the
nvic_sysreg_ns_ops struct and its read/write functions (renamed as
v7m_sysreg_ns_*), but we will delete the NVIC's copy of this code in
a subsequent patch.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
include/hw/arm/armv7m.h | 12 ++++
include/hw/intc/armv7m_nvic.h | 4 --
hw/arm/armv7m.c | 125 ++++++++++++++++++++++++++++++++++
hw/intc/armv7m_nvic.c | 73 --------------------
4 files changed, 137 insertions(+), 77 deletions(-)
diff --git a/include/hw/arm/armv7m.h b/include/hw/arm/armv7m.h
index 4cae0d7eeaa..360c35c5fb2 100644
--- a/include/hw/arm/armv7m.h
+++ b/include/hw/arm/armv7m.h
@@ -60,11 +60,23 @@ struct ARMv7MState {
BitBandState bitband[ARMV7M_NUM_BITBANDS];
ARMCPU *cpu;
ARMv7MRAS ras;
+ SysTickState systick[M_REG_NUM_BANKS];
/* MemoryRegion we pass to the CPU, with our devices layered on
* top of the ones the board provides in board_memory.
*/
MemoryRegion container;
+ /*
+ * MemoryRegion which passes the transaction to either the S or the
+ * NS systick device depending on the transaction attributes
+ */
+ MemoryRegion systickmem;
+ /*
+ * MemoryRegion which enforces the S/NS handling of the systick
+ * device NS alias region and passes the transaction to the
+ * NS systick device if appropriate.
+ */
+ MemoryRegion systick_ns_mem;
/* Properties */
char *cpu_type;
diff --git a/include/hw/intc/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h
index 33b6d8810c7..6a6a99090c7 100644
--- a/include/hw/intc/armv7m_nvic.h
+++ b/include/hw/intc/armv7m_nvic.h
@@ -81,16 +81,12 @@ struct NVICState {
MemoryRegion sysregmem;
MemoryRegion sysreg_ns_mem;
- MemoryRegion systickmem;
- MemoryRegion systick_ns_mem;
MemoryRegion container;
MemoryRegion defaultmem;
uint32_t num_irq;
qemu_irq excpout;
qemu_irq sysresetreq;
-
- SysTickState systick[M_REG_NUM_BANKS];
};
#endif
diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c
index 8964730d153..364ac069702 100644
--- a/hw/arm/armv7m.c
+++ b/hw/arm/armv7m.c
@@ -124,6 +124,85 @@ static const hwaddr bitband_output_addr[ARMV7M_NUM_BITBANDS] = {
0x22000000, 0x42000000
};
+static MemTxResult v7m_sysreg_ns_write(void *opaque, hwaddr addr,
+ uint64_t value, unsigned size,
+ MemTxAttrs attrs)
+{
+ MemoryRegion *mr = opaque;
+
+ if (attrs.secure) {
+ /* S accesses to the alias act like NS accesses to the real region */
+ attrs.secure = 0;
+ return memory_region_dispatch_write(mr, addr, value,
+ size_memop(size) | MO_TE, attrs);
+ } else {
+ /* NS attrs are RAZ/WI for privileged, and BusFault for user */
+ if (attrs.user) {
+ return MEMTX_ERROR;
+ }
+ return MEMTX_OK;
+ }
+}
+
+static MemTxResult v7m_sysreg_ns_read(void *opaque, hwaddr addr,
+ uint64_t *data, unsigned size,
+ MemTxAttrs attrs)
+{
+ MemoryRegion *mr = opaque;
+
+ if (attrs.secure) {
+ /* S accesses to the alias act like NS accesses to the real region */
+ attrs.secure = 0;
+ return memory_region_dispatch_read(mr, addr, data,
+ size_memop(size) | MO_TE, attrs);
+ } else {
+ /* NS attrs are RAZ/WI for privileged, and BusFault for user */
+ if (attrs.user) {
+ return MEMTX_ERROR;
+ }
+ *data = 0;
+ return MEMTX_OK;
+ }
+}
+
+static const MemoryRegionOps v7m_sysreg_ns_ops = {
+ .read_with_attrs = v7m_sysreg_ns_read,
+ .write_with_attrs = v7m_sysreg_ns_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+};
+
+static MemTxResult v7m_systick_write(void *opaque, hwaddr addr,
+ uint64_t value, unsigned size,
+ MemTxAttrs attrs)
+{
+ ARMv7MState *s = opaque;
+ MemoryRegion *mr;
+
+ /* Direct the access to the correct systick */
+ mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->systick[attrs.secure]), 0);
+ return memory_region_dispatch_write(mr, addr, value,
+ size_memop(size) | MO_TE, attrs);
+}
+
+static MemTxResult v7m_systick_read(void *opaque, hwaddr addr,
+ uint64_t *data, unsigned size,
+ MemTxAttrs attrs)
+{
+ ARMv7MState *s = opaque;
+ MemoryRegion *mr;
+
+ /* Direct the access to the correct systick */
+ mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->systick[attrs.secure]), 0);
+ return memory_region_dispatch_read(mr, addr, data, size_memop(size) | MO_TE,
+ attrs);
+}
+
+static const MemoryRegionOps v7m_systick_ops = {
+ .read_with_attrs = v7m_systick_read,
+ .write_with_attrs = v7m_systick_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+};
+
static void armv7m_instance_init(Object *obj)
{
ARMv7MState *s = ARMV7M(obj);
@@ -137,6 +216,13 @@ static void armv7m_instance_init(Object *obj)
object_property_add_alias(obj, "num-irq",
OBJECT(&s->nvic), "num-irq");
+ object_initialize_child(obj, "systick-reg-ns", &s->systick[M_REG_NS],
+ TYPE_SYSTICK);
+ /*
+ * We can't initialize the secure systick here, as we don't know
+ * yet if we need it.
+ */
+
for (i = 0; i < ARRAY_SIZE(s->bitband); i++) {
object_initialize_child(obj, "bitband[*]", &s->bitband[i],
TYPE_BITBAND);
@@ -231,6 +317,45 @@ static void armv7m_realize(DeviceState *dev, Error **errp)
memory_region_add_subregion(&s->container, 0xe0000000,
sysbus_mmio_get_region(sbd, 0));
+ /* Create and map the systick devices */
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->systick[M_REG_NS]), errp)) {
+ return;
+ }
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->systick[M_REG_NS]), 0,
+ qdev_get_gpio_in_named(DEVICE(&s->nvic),
+ "systick-trigger", M_REG_NS));
+
+ if (arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY)) {
+ /*
+ * We couldn't init the secure systick device in instance_init
+ * as we didn't know then if the CPU had the security extensions;
+ * so we have to do it here.
+ */
+ object_initialize_child(OBJECT(dev), "systick-reg-s",
+ &s->systick[M_REG_S], TYPE_SYSTICK);
+
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->systick[M_REG_S]), errp)) {
+ return;
+ }
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->systick[M_REG_S]), 0,
+ qdev_get_gpio_in_named(DEVICE(&s->nvic),
+ "systick-trigger", M_REG_S));
+ }
+
+ memory_region_init_io(&s->systickmem, OBJECT(s),
+ &v7m_systick_ops, s,
+ "v7m_systick", 0xe0);
+
+ memory_region_add_subregion_overlap(&s->container, 0xe000e010,
+ &s->systickmem, 1);
+ if (arm_feature(&s->cpu->env, ARM_FEATURE_V8)) {
+ memory_region_init_io(&s->systick_ns_mem, OBJECT(s),
+ &v7m_sysreg_ns_ops, &s->systickmem,
+ "v7m_systick_ns", 0xe0);
+ memory_region_add_subregion_overlap(&s->container, 0xe002e010,
+ &s->systick_ns_mem, 1);
+ }
+
/* If the CPU has RAS support, create the RAS register block */
if (cpu_isar_feature(aa32_ras, s->cpu)) {
object_initialize_child(OBJECT(dev), "armv7m-ras",
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index a5975592dfa..2b3e79a3da9 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -2517,38 +2517,6 @@ static const MemoryRegionOps nvic_sysreg_ns_ops = {
.endianness = DEVICE_NATIVE_ENDIAN,
};
-static MemTxResult nvic_systick_write(void *opaque, hwaddr addr,
- uint64_t value, unsigned size,
- MemTxAttrs attrs)
-{
- NVICState *s = opaque;
- MemoryRegion *mr;
-
- /* Direct the access to the correct systick */
- mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->systick[attrs.secure]), 0);
- return memory_region_dispatch_write(mr, addr, value,
- size_memop(size) | MO_TE, attrs);
-}
-
-static MemTxResult nvic_systick_read(void *opaque, hwaddr addr,
- uint64_t *data, unsigned size,
- MemTxAttrs attrs)
-{
- NVICState *s = opaque;
- MemoryRegion *mr;
-
- /* Direct the access to the correct systick */
- mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->systick[attrs.secure]), 0);
- return memory_region_dispatch_read(mr, addr, data, size_memop(size) | MO_TE,
- attrs);
-}
-
-static const MemoryRegionOps nvic_systick_ops = {
- .read_with_attrs = nvic_systick_read,
- .write_with_attrs = nvic_systick_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
-};
-
/*
* Unassigned portions of the PPB space are RAZ/WI for privileged
* accesses, and fault for non-privileged accesses.
@@ -2801,29 +2769,6 @@ static void armv7m_nvic_realize(DeviceState *dev, Error **errp)
s->num_prio_bits = arm_feature(&s->cpu->env, ARM_FEATURE_V7) ? 8 : 2;
- if (!sysbus_realize(SYS_BUS_DEVICE(&s->systick[M_REG_NS]), errp)) {
- return;
- }
- sysbus_connect_irq(SYS_BUS_DEVICE(&s->systick[M_REG_NS]), 0,
- qdev_get_gpio_in_named(dev, "systick-trigger",
- M_REG_NS));
-
- if (arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY)) {
- /* We couldn't init the secure systick device in instance_init
- * as we didn't know then if the CPU had the security extensions;
- * so we have to do it here.
- */
- object_initialize_child(OBJECT(dev), "systick-reg-s",
- &s->systick[M_REG_S], TYPE_SYSTICK);
-
- if (!sysbus_realize(SYS_BUS_DEVICE(&s->systick[M_REG_S]), errp)) {
- return;
- }
- sysbus_connect_irq(SYS_BUS_DEVICE(&s->systick[M_REG_S]), 0,
- qdev_get_gpio_in_named(dev, "systick-trigger",
- M_REG_S));
- }
-
/*
* This device provides a single sysbus memory region which
* represents the whole of the "System PPB" space. This is the
@@ -2877,23 +2822,11 @@ static void armv7m_nvic_realize(DeviceState *dev, Error **errp)
"nvic_sysregs", 0x1000);
memory_region_add_subregion(&s->container, 0xe000, &s->sysregmem);
- memory_region_init_io(&s->systickmem, OBJECT(s),
- &nvic_systick_ops, s,
- "nvic_systick", 0xe0);
-
- memory_region_add_subregion_overlap(&s->container, 0xe010,
- &s->systickmem, 1);
-
if (arm_feature(&s->cpu->env, ARM_FEATURE_V8)) {
memory_region_init_io(&s->sysreg_ns_mem, OBJECT(s),
&nvic_sysreg_ns_ops, &s->sysregmem,
"nvic_sysregs_ns", 0x1000);
memory_region_add_subregion(&s->container, 0x2e000, &s->sysreg_ns_mem);
- memory_region_init_io(&s->systick_ns_mem, OBJECT(s),
- &nvic_sysreg_ns_ops, &s->systickmem,
- "nvic_systick_ns", 0xe0);
- memory_region_add_subregion_overlap(&s->container, 0x2e010,
- &s->systick_ns_mem, 1);
}
sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->container);
@@ -2905,12 +2838,6 @@ static void armv7m_nvic_instance_init(Object *obj)
NVICState *nvic = NVIC(obj);
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
- object_initialize_child(obj, "systick-reg-ns", &nvic->systick[M_REG_NS],
- TYPE_SYSTICK);
- /* We can't initialize the secure systick here, as we don't know
- * yet if we need it.
- */
-
sysbus_init_irq(sbd, &nvic->excpout);
qdev_init_gpio_out_named(dev, &nvic->sysresetreq, "SYSRESETREQ", 1);
qdev_init_gpio_in_named(dev, nvic_systick_trigger, "systick-trigger",
--
2.20.1
^ permalink raw reply related [flat|nested] 91+ messages in thread
* [PATCH for-6.2 03/25] arm: Move system PPB container handling to armv7m
2021-08-12 9:33 [PATCH for-6.2 00/25] arm: Get rid of system_clock_scale global Peter Maydell
2021-08-12 9:33 ` [PATCH for-6.2 01/25] arm: Move M-profile RAS register block into its own device Peter Maydell
2021-08-12 9:33 ` [PATCH for-6.2 02/25] arm: Move systick device creation from NVIC to ARMv7M object Peter Maydell
@ 2021-08-12 9:33 ` Peter Maydell
2021-08-12 11:56 ` Alexandre IOOSS
2021-08-17 9:25 ` Luc Michel
2021-08-12 9:33 ` [PATCH for-6.2 04/25] hw/timer/armv7m_systick: Add usual QEMU interface comment Peter Maydell
` (21 subsequent siblings)
24 siblings, 2 replies; 91+ messages in thread
From: Peter Maydell @ 2021-08-12 9:33 UTC (permalink / raw)
To: qemu-arm, qemu-devel
Cc: Damien Hedde, Luc Michel, Alistair Francis, Subbaraya Sundeep,
Joel Stanley, Alexandre Iooss
Instead of having the NVIC device provide a single sysbus memory
region covering the whole of the "System PPB" space, which implements
the default behaviour for unimplemented ranges and provides the NS
alias window to the sysregs as well as the main sysreg MR, move this
handling to the container armv7m device. The NVIC now provides a
single memory region which just implements the system registers.
This consolidates all the handling of "map various devices in the
PPB" into the armv7m container where it belongs.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
include/hw/arm/armv7m.h | 4 +
include/hw/intc/armv7m_nvic.h | 3 -
hw/arm/armv7m.c | 100 ++++++++++++++++++++++-
hw/intc/armv7m_nvic.c | 145 +---------------------------------
4 files changed, 107 insertions(+), 145 deletions(-)
diff --git a/include/hw/arm/armv7m.h b/include/hw/arm/armv7m.h
index 360c35c5fb2..fe8b248a6c6 100644
--- a/include/hw/arm/armv7m.h
+++ b/include/hw/arm/armv7m.h
@@ -77,6 +77,10 @@ struct ARMv7MState {
* NS systick device if appropriate.
*/
MemoryRegion systick_ns_mem;
+ /* Ditto, for the sysregs region provided by the NVIC */
+ MemoryRegion sysreg_ns_mem;
+ /* MR providing default PPB behaviour */
+ MemoryRegion defaultmem;
/* Properties */
char *cpu_type;
diff --git a/include/hw/intc/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h
index 6a6a99090c7..0180c7b0ca1 100644
--- a/include/hw/intc/armv7m_nvic.h
+++ b/include/hw/intc/armv7m_nvic.h
@@ -80,9 +80,6 @@ struct NVICState {
int vectpending_prio; /* group prio of the exeception in vectpending */
MemoryRegion sysregmem;
- MemoryRegion sysreg_ns_mem;
- MemoryRegion container;
- MemoryRegion defaultmem;
uint32_t num_irq;
qemu_irq excpout;
diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c
index 364ac069702..7e7fb7a3ad3 100644
--- a/hw/arm/armv7m.c
+++ b/hw/arm/armv7m.c
@@ -18,6 +18,7 @@
#include "sysemu/reset.h"
#include "qemu/error-report.h"
#include "qemu/module.h"
+#include "qemu/log.h"
#include "target/arm/idau.h"
/* Bitbanded IO. Each word corresponds to a single bit. */
@@ -203,6 +204,43 @@ static const MemoryRegionOps v7m_systick_ops = {
.endianness = DEVICE_NATIVE_ENDIAN,
};
+/*
+ * Unassigned portions of the PPB space are RAZ/WI for privileged
+ * accesses, and fault for non-privileged accesses.
+ */
+static MemTxResult ppb_default_read(void *opaque, hwaddr addr,
+ uint64_t *data, unsigned size,
+ MemTxAttrs attrs)
+{
+ qemu_log_mask(LOG_UNIMP, "Read of unassigned area of PPB: offset 0x%x\n",
+ (uint32_t)addr);
+ if (attrs.user) {
+ return MEMTX_ERROR;
+ }
+ *data = 0;
+ return MEMTX_OK;
+}
+
+static MemTxResult ppb_default_write(void *opaque, hwaddr addr,
+ uint64_t value, unsigned size,
+ MemTxAttrs attrs)
+{
+ qemu_log_mask(LOG_UNIMP, "Write of unassigned area of PPB: offset 0x%x\n",
+ (uint32_t)addr);
+ if (attrs.user) {
+ return MEMTX_ERROR;
+ }
+ return MEMTX_OK;
+}
+
+static const MemoryRegionOps ppb_default_ops = {
+ .read_with_attrs = ppb_default_read,
+ .write_with_attrs = ppb_default_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+ .valid.min_access_size = 1,
+ .valid.max_access_size = 8,
+};
+
static void armv7m_instance_init(Object *obj)
{
ARMv7MState *s = ARMV7M(obj);
@@ -309,13 +347,73 @@ static void armv7m_realize(DeviceState *dev, Error **errp)
qdev_pass_gpios(DEVICE(&s->nvic), dev, "SYSRESETREQ");
qdev_pass_gpios(DEVICE(&s->nvic), dev, "NMI");
+ /*
+ * We map various devices into the continer MR at their architected
+ * addresses. In particular, we map everything corresponding to the
+ * "System PPB" space. This is the range from 0xe0000000 to 0xe00fffff
+ * and includes the NVIC, the System Control Space (system registers),
+ * the systick timer, and for CPUs with the Security extension an NS
+ * banked version of all of these.
+ *
+ * The default behaviour for unimplemented registers/ranges
+ * (for instance the Data Watchpoint and Trace unit at 0xe0001000)
+ * is to RAZ/WI for privileged access and BusFault for non-privileged
+ * access.
+ *
+ * The NVIC and System Control Space (SCS) starts at 0xe000e000
+ * and looks like this:
+ * 0x004 - ICTR
+ * 0x010 - 0xff - systick
+ * 0x100..0x7ec - NVIC
+ * 0x7f0..0xcff - Reserved
+ * 0xd00..0xd3c - SCS registers
+ * 0xd40..0xeff - Reserved or Not implemented
+ * 0xf00 - STIR
+ *
+ * Some registers within this space are banked between security states.
+ * In v8M there is a second range 0xe002e000..0xe002efff which is the
+ * NonSecure alias SCS; secure accesses to this behave like NS accesses
+ * to the main SCS range, and non-secure accesses (including when
+ * the security extension is not implemented) are RAZ/WI.
+ * Note that both the main SCS range and the alias range are defined
+ * to be exempt from memory attribution (R_BLJT) and so the memory
+ * transaction attribute always matches the current CPU security
+ * state (attrs.secure == env->v7m.secure). In the v7m_sysreg_ns_ops
+ * wrappers we change attrs.secure to indicate the NS access; so
+ * generally code determining which banked register to use should
+ * use attrs.secure; code determining actual behaviour of the system
+ * should use env->v7m.secure.
+ *
+ * Within the PPB space, some MRs overlap, and the priority
+ * of overlapping regions is:
+ * - default region (for RAZ/WI and BusFault) : -1
+ * - system register regions (provided by the NVIC) : 0
+ * - systick : 1
+ * This is because the systick device is a small block of registers
+ * in the middle of the other system control registers.
+ */
+
+ memory_region_init_io(&s->defaultmem, OBJECT(s), &ppb_default_ops, s,
+ "nvic-default", 0x100000);
+ memory_region_add_subregion_overlap(&s->container, 0xe0000000,
+ &s->defaultmem, -1);
+
/* Wire the NVIC up to the CPU */
sbd = SYS_BUS_DEVICE(&s->nvic);
sysbus_connect_irq(sbd, 0,
qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_IRQ));
- memory_region_add_subregion(&s->container, 0xe0000000,
+ memory_region_add_subregion(&s->container, 0xe000e000,
sysbus_mmio_get_region(sbd, 0));
+ if (arm_feature(&s->cpu->env, ARM_FEATURE_V8)) {
+ /* Create the NS alias region for the NVIC sysregs */
+ memory_region_init_io(&s->sysreg_ns_mem, OBJECT(s),
+ &v7m_sysreg_ns_ops,
+ sysbus_mmio_get_region(sbd, 0),
+ "nvic_sysregs_ns", 0x1000);
+ memory_region_add_subregion(&s->container, 0xe002e000,
+ &s->sysreg_ns_mem);
+ }
/* Create and map the systick devices */
if (!sysbus_realize(SYS_BUS_DEVICE(&s->systick[M_REG_NS]), errp)) {
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index 2b3e79a3da9..13df002ce4d 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -2470,90 +2470,6 @@ static const MemoryRegionOps nvic_sysreg_ops = {
.endianness = DEVICE_NATIVE_ENDIAN,
};
-static MemTxResult nvic_sysreg_ns_write(void *opaque, hwaddr addr,
- uint64_t value, unsigned size,
- MemTxAttrs attrs)
-{
- MemoryRegion *mr = opaque;
-
- if (attrs.secure) {
- /* S accesses to the alias act like NS accesses to the real region */
- attrs.secure = 0;
- return memory_region_dispatch_write(mr, addr, value,
- size_memop(size) | MO_TE, attrs);
- } else {
- /* NS attrs are RAZ/WI for privileged, and BusFault for user */
- if (attrs.user) {
- return MEMTX_ERROR;
- }
- return MEMTX_OK;
- }
-}
-
-static MemTxResult nvic_sysreg_ns_read(void *opaque, hwaddr addr,
- uint64_t *data, unsigned size,
- MemTxAttrs attrs)
-{
- MemoryRegion *mr = opaque;
-
- if (attrs.secure) {
- /* S accesses to the alias act like NS accesses to the real region */
- attrs.secure = 0;
- return memory_region_dispatch_read(mr, addr, data,
- size_memop(size) | MO_TE, attrs);
- } else {
- /* NS attrs are RAZ/WI for privileged, and BusFault for user */
- if (attrs.user) {
- return MEMTX_ERROR;
- }
- *data = 0;
- return MEMTX_OK;
- }
-}
-
-static const MemoryRegionOps nvic_sysreg_ns_ops = {
- .read_with_attrs = nvic_sysreg_ns_read,
- .write_with_attrs = nvic_sysreg_ns_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
-};
-
-/*
- * Unassigned portions of the PPB space are RAZ/WI for privileged
- * accesses, and fault for non-privileged accesses.
- */
-static MemTxResult ppb_default_read(void *opaque, hwaddr addr,
- uint64_t *data, unsigned size,
- MemTxAttrs attrs)
-{
- qemu_log_mask(LOG_UNIMP, "Read of unassigned area of PPB: offset 0x%x\n",
- (uint32_t)addr);
- if (attrs.user) {
- return MEMTX_ERROR;
- }
- *data = 0;
- return MEMTX_OK;
-}
-
-static MemTxResult ppb_default_write(void *opaque, hwaddr addr,
- uint64_t value, unsigned size,
- MemTxAttrs attrs)
-{
- qemu_log_mask(LOG_UNIMP, "Write of unassigned area of PPB: offset 0x%x\n",
- (uint32_t)addr);
- if (attrs.user) {
- return MEMTX_ERROR;
- }
- return MEMTX_OK;
-}
-
-static const MemoryRegionOps ppb_default_ops = {
- .read_with_attrs = ppb_default_read,
- .write_with_attrs = ppb_default_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
- .valid.min_access_size = 1,
- .valid.max_access_size = 8,
-};
-
static int nvic_post_load(void *opaque, int version_id)
{
NVICState *s = opaque;
@@ -2770,66 +2686,13 @@ static void armv7m_nvic_realize(DeviceState *dev, Error **errp)
s->num_prio_bits = arm_feature(&s->cpu->env, ARM_FEATURE_V7) ? 8 : 2;
/*
- * This device provides a single sysbus memory region which
- * represents the whole of the "System PPB" space. This is the
- * range from 0xe0000000 to 0xe00fffff and includes the NVIC,
- * the System Control Space (system registers), the systick timer,
- * and for CPUs with the Security extension an NS banked version
- * of all of these.
- *
- * The default behaviour for unimplemented registers/ranges
- * (for instance the Data Watchpoint and Trace unit at 0xe0001000)
- * is to RAZ/WI for privileged access and BusFault for non-privileged
- * access.
- *
- * The NVIC and System Control Space (SCS) starts at 0xe000e000
- * and looks like this:
- * 0x004 - ICTR
- * 0x010 - 0xff - systick
- * 0x100..0x7ec - NVIC
- * 0x7f0..0xcff - Reserved
- * 0xd00..0xd3c - SCS registers
- * 0xd40..0xeff - Reserved or Not implemented
- * 0xf00 - STIR
- *
- * Some registers within this space are banked between security states.
- * In v8M there is a second range 0xe002e000..0xe002efff which is the
- * NonSecure alias SCS; secure accesses to this behave like NS accesses
- * to the main SCS range, and non-secure accesses (including when
- * the security extension is not implemented) are RAZ/WI.
- * Note that both the main SCS range and the alias range are defined
- * to be exempt from memory attribution (R_BLJT) and so the memory
- * transaction attribute always matches the current CPU security
- * state (attrs.secure == env->v7m.secure). In the nvic_sysreg_ns_ops
- * wrappers we change attrs.secure to indicate the NS access; so
- * generally code determining which banked register to use should
- * use attrs.secure; code determining actual behaviour of the system
- * should use env->v7m.secure.
- *
- * The container covers the whole PPB space. Within it the priority
- * of overlapping regions is:
- * - default region (for RAZ/WI and BusFault) : -1
- * - system register regions : 0
- * - systick : 1
- * This is because the systick device is a small block of registers
- * in the middle of the other system control registers.
+ * This device provides a single memory region which covers the
+ * sysreg/NVIC registers from 0xE000E000 .. 0xE000EFFF, with the
+ * exception of the systick timer registers 0xE000E010 .. 0xE000E0FF.
*/
- memory_region_init(&s->container, OBJECT(s), "nvic", 0x100000);
- memory_region_init_io(&s->defaultmem, OBJECT(s), &ppb_default_ops, s,
- "nvic-default", 0x100000);
- memory_region_add_subregion_overlap(&s->container, 0, &s->defaultmem, -1);
memory_region_init_io(&s->sysregmem, OBJECT(s), &nvic_sysreg_ops, s,
"nvic_sysregs", 0x1000);
- memory_region_add_subregion(&s->container, 0xe000, &s->sysregmem);
-
- if (arm_feature(&s->cpu->env, ARM_FEATURE_V8)) {
- memory_region_init_io(&s->sysreg_ns_mem, OBJECT(s),
- &nvic_sysreg_ns_ops, &s->sysregmem,
- "nvic_sysregs_ns", 0x1000);
- memory_region_add_subregion(&s->container, 0x2e000, &s->sysreg_ns_mem);
- }
-
- sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->container);
+ sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->sysregmem);
}
static void armv7m_nvic_instance_init(Object *obj)
--
2.20.1
^ permalink raw reply related [flat|nested] 91+ messages in thread
* [PATCH for-6.2 04/25] hw/timer/armv7m_systick: Add usual QEMU interface comment
2021-08-12 9:33 [PATCH for-6.2 00/25] arm: Get rid of system_clock_scale global Peter Maydell
` (2 preceding siblings ...)
2021-08-12 9:33 ` [PATCH for-6.2 03/25] arm: Move system PPB container handling to armv7m Peter Maydell
@ 2021-08-12 9:33 ` Peter Maydell
2021-08-13 1:26 ` Alistair Francis
2021-08-17 9:29 ` Luc Michel
2021-08-12 9:33 ` [PATCH for-6.2 05/25] hw/timer/armv7m_systick: Add input clocks Peter Maydell
` (20 subsequent siblings)
24 siblings, 2 replies; 91+ messages in thread
From: Peter Maydell @ 2021-08-12 9:33 UTC (permalink / raw)
To: qemu-arm, qemu-devel
Cc: Damien Hedde, Luc Michel, Alistair Francis, Subbaraya Sundeep,
Joel Stanley, Alexandre Iooss
Add the usual-style QEMU interface comment documenting what
properties, etc, this device exposes.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
include/hw/timer/armv7m_systick.h | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/include/hw/timer/armv7m_systick.h b/include/hw/timer/armv7m_systick.h
index 84496faaf96..685fc5bc0d7 100644
--- a/include/hw/timer/armv7m_systick.h
+++ b/include/hw/timer/armv7m_systick.h
@@ -20,6 +20,13 @@
OBJECT_DECLARE_SIMPLE_TYPE(SysTickState, SYSTICK)
+/*
+ * QEMU interface:
+ * + sysbus MMIO region 0 is the register interface (covering
+ * the registers which are mapped at address 0xE000E010)
+ * + sysbus IRQ 0 is the interrupt line to the NVIC
+ */
+
struct SysTickState {
/*< private >*/
SysBusDevice parent_obj;
--
2.20.1
^ permalink raw reply related [flat|nested] 91+ messages in thread
* [PATCH for-6.2 05/25] hw/timer/armv7m_systick: Add input clocks
2021-08-12 9:33 [PATCH for-6.2 00/25] arm: Get rid of system_clock_scale global Peter Maydell
` (3 preceding siblings ...)
2021-08-12 9:33 ` [PATCH for-6.2 04/25] hw/timer/armv7m_systick: Add usual QEMU interface comment Peter Maydell
@ 2021-08-12 9:33 ` Peter Maydell
2021-08-13 1:27 ` Alistair Francis
2021-08-17 9:32 ` Luc Michel
2021-08-12 9:33 ` [PATCH for-6.2 06/25] hw/arm/armv7m: Create " Peter Maydell
` (19 subsequent siblings)
24 siblings, 2 replies; 91+ messages in thread
From: Peter Maydell @ 2021-08-12 9:33 UTC (permalink / raw)
To: qemu-arm, qemu-devel
Cc: Damien Hedde, Luc Michel, Alistair Francis, Subbaraya Sundeep,
Joel Stanley, Alexandre Iooss
The v7M systick timer can be programmed to run from either of
two clocks:
* an "external reference clock" (when SYST_CSR.CLKSOURCE == 0)
* the main CPU clock (when SYST_CSR.CLKSOURCE == 1)
Our implementation currently hardwires the external reference clock
to be 1MHz, and allows boards to set the main CPU clock frequency via
the global 'system_clock_scale'. (Most boards set that to a constant
value; the Stellaris boards allow the guest to reprogram it via the
board-specific RCC registers).
As the first step in converting this to use the Clock infrastructure,
add input clocks to the systick device for the reference clock and
the CPU clock. The device implementation ignores them; once we have
made all the users of the device correctly wire up the new Clocks we
will switch the implementation to use them and ignore the old
system_clock_scale.
This is a migration compat break for all M-profile boards, because of
the addition of the new clock objects to the vmstate struct.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
include/hw/timer/armv7m_systick.h | 7 +++++++
hw/timer/armv7m_systick.c | 10 ++++++++--
2 files changed, 15 insertions(+), 2 deletions(-)
diff --git a/include/hw/timer/armv7m_systick.h b/include/hw/timer/armv7m_systick.h
index 685fc5bc0d7..38adf8d274e 100644
--- a/include/hw/timer/armv7m_systick.h
+++ b/include/hw/timer/armv7m_systick.h
@@ -15,6 +15,7 @@
#include "hw/sysbus.h"
#include "qom/object.h"
#include "hw/ptimer.h"
+#include "hw/clock.h"
#define TYPE_SYSTICK "armv7m_systick"
@@ -25,6 +26,10 @@ OBJECT_DECLARE_SIMPLE_TYPE(SysTickState, SYSTICK)
* + sysbus MMIO region 0 is the register interface (covering
* the registers which are mapped at address 0xE000E010)
* + sysbus IRQ 0 is the interrupt line to the NVIC
+ * + Clock input "refclk" is the external reference clock
+ * (used when SYST_CSR.CLKSOURCE == 0)
+ * + Clock input "cpuclk" is the main CPU clock
+ * (used when SYST_CSR.CLKSOURCE == 1)
*/
struct SysTickState {
@@ -38,6 +43,8 @@ struct SysTickState {
ptimer_state *ptimer;
MemoryRegion iomem;
qemu_irq irq;
+ Clock *refclk;
+ Clock *cpuclk;
};
/*
diff --git a/hw/timer/armv7m_systick.c b/hw/timer/armv7m_systick.c
index 2f192011eb0..e43f74114e8 100644
--- a/hw/timer/armv7m_systick.c
+++ b/hw/timer/armv7m_systick.c
@@ -14,6 +14,7 @@
#include "migration/vmstate.h"
#include "hw/irq.h"
#include "hw/sysbus.h"
+#include "hw/qdev-clock.h"
#include "qemu/timer.h"
#include "qemu/log.h"
#include "qemu/module.h"
@@ -201,6 +202,9 @@ static void systick_instance_init(Object *obj)
memory_region_init_io(&s->iomem, obj, &systick_ops, s, "systick", 0xe0);
sysbus_init_mmio(sbd, &s->iomem);
sysbus_init_irq(sbd, &s->irq);
+
+ s->refclk = qdev_init_clock_in(DEVICE(obj), "refclk", NULL, NULL, 0);
+ s->cpuclk = qdev_init_clock_in(DEVICE(obj), "cpuclk", NULL, NULL, 0);
}
static void systick_realize(DeviceState *dev, Error **errp)
@@ -215,9 +219,11 @@ static void systick_realize(DeviceState *dev, Error **errp)
static const VMStateDescription vmstate_systick = {
.name = "armv7m_systick",
- .version_id = 2,
- .minimum_version_id = 2,
+ .version_id = 3,
+ .minimum_version_id = 3,
.fields = (VMStateField[]) {
+ VMSTATE_CLOCK(refclk, SysTickState),
+ VMSTATE_CLOCK(cpuclk, SysTickState),
VMSTATE_UINT32(control, SysTickState),
VMSTATE_INT64(tick, SysTickState),
VMSTATE_PTIMER(ptimer, SysTickState),
--
2.20.1
^ permalink raw reply related [flat|nested] 91+ messages in thread
* [PATCH for-6.2 06/25] hw/arm/armv7m: Create input clocks
2021-08-12 9:33 [PATCH for-6.2 00/25] arm: Get rid of system_clock_scale global Peter Maydell
` (4 preceding siblings ...)
2021-08-12 9:33 ` [PATCH for-6.2 05/25] hw/timer/armv7m_systick: Add input clocks Peter Maydell
@ 2021-08-12 9:33 ` Peter Maydell
2021-08-13 1:28 ` Alistair Francis
2021-08-17 9:34 ` Luc Michel
2021-08-12 9:33 ` [PATCH for-6.2 07/25] armsse: Wire up systick cpuclk clock Peter Maydell
` (18 subsequent siblings)
24 siblings, 2 replies; 91+ messages in thread
From: Peter Maydell @ 2021-08-12 9:33 UTC (permalink / raw)
To: qemu-arm, qemu-devel
Cc: Damien Hedde, Luc Michel, Alistair Francis, Subbaraya Sundeep,
Joel Stanley, Alexandre Iooss
Create input clocks on the armv7m container object which pass through
to the systick timers, so that users of the armv7m object can specify
the clocks being used.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
include/hw/arm/armv7m.h | 6 ++++++
hw/arm/armv7m.c | 23 +++++++++++++++++++++++
2 files changed, 29 insertions(+)
diff --git a/include/hw/arm/armv7m.h b/include/hw/arm/armv7m.h
index fe8b248a6c6..b7ba0ff409c 100644
--- a/include/hw/arm/armv7m.h
+++ b/include/hw/arm/armv7m.h
@@ -15,6 +15,7 @@
#include "hw/misc/armv7m_ras.h"
#include "target/arm/idau.h"
#include "qom/object.h"
+#include "hw/clock.h"
#define TYPE_BITBAND "ARM-bitband-memory"
OBJECT_DECLARE_SIMPLE_TYPE(BitBandState, BITBAND)
@@ -51,6 +52,8 @@ OBJECT_DECLARE_SIMPLE_TYPE(ARMv7MState, ARMV7M)
* + Property "vfp": enable VFP (forwarded to CPU object)
* + Property "dsp": enable DSP (forwarded to CPU object)
* + Property "enable-bitband": expose bitbanded IO
+ * + Clock input "refclk" is the external reference clock for the systick timers
+ * + Clock input "cpuclk" is the main CPU clock
*/
struct ARMv7MState {
/*< private >*/
@@ -82,6 +85,9 @@ struct ARMv7MState {
/* MR providing default PPB behaviour */
MemoryRegion defaultmem;
+ Clock *refclk;
+ Clock *cpuclk;
+
/* Properties */
char *cpu_type;
/* MemoryRegion the board provides to us (with its devices, RAM, etc) */
diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c
index 7e7fb7a3ad3..db1bfa98df0 100644
--- a/hw/arm/armv7m.c
+++ b/hw/arm/armv7m.c
@@ -14,12 +14,14 @@
#include "hw/arm/boot.h"
#include "hw/loader.h"
#include "hw/qdev-properties.h"
+#include "hw/qdev-clock.h"
#include "elf.h"
#include "sysemu/reset.h"
#include "qemu/error-report.h"
#include "qemu/module.h"
#include "qemu/log.h"
#include "target/arm/idau.h"
+#include "migration/vmstate.h"
/* Bitbanded IO. Each word corresponds to a single bit. */
@@ -265,6 +267,9 @@ static void armv7m_instance_init(Object *obj)
object_initialize_child(obj, "bitband[*]", &s->bitband[i],
TYPE_BITBAND);
}
+
+ s->refclk = qdev_init_clock_in(DEVICE(obj), "refclk", NULL, NULL, 0);
+ s->cpuclk = qdev_init_clock_in(DEVICE(obj), "cpuclk", NULL, NULL, 0);
}
static void armv7m_realize(DeviceState *dev, Error **errp)
@@ -416,6 +421,8 @@ static void armv7m_realize(DeviceState *dev, Error **errp)
}
/* Create and map the systick devices */
+ qdev_connect_clock_in(DEVICE(&s->systick[M_REG_NS]), "refclk", s->refclk);
+ qdev_connect_clock_in(DEVICE(&s->systick[M_REG_NS]), "cpuclk", s->cpuclk);
if (!sysbus_realize(SYS_BUS_DEVICE(&s->systick[M_REG_NS]), errp)) {
return;
}
@@ -431,6 +438,10 @@ static void armv7m_realize(DeviceState *dev, Error **errp)
*/
object_initialize_child(OBJECT(dev), "systick-reg-s",
&s->systick[M_REG_S], TYPE_SYSTICK);
+ qdev_connect_clock_in(DEVICE(&s->systick[M_REG_S]), "refclk",
+ s->refclk);
+ qdev_connect_clock_in(DEVICE(&s->systick[M_REG_S]), "cpuclk",
+ s->cpuclk);
if (!sysbus_realize(SYS_BUS_DEVICE(&s->systick[M_REG_S]), errp)) {
return;
@@ -504,11 +515,23 @@ static Property armv7m_properties[] = {
DEFINE_PROP_END_OF_LIST(),
};
+static const VMStateDescription vmstate_armv7m = {
+ .name = "armv7m",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_CLOCK(refclk, SysTickState),
+ VMSTATE_CLOCK(cpuclk, SysTickState),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
static void armv7m_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
dc->realize = armv7m_realize;
+ dc->vmsd = &vmstate_armv7m;
device_class_set_props(dc, armv7m_properties);
}
--
2.20.1
^ permalink raw reply related [flat|nested] 91+ messages in thread
* [PATCH for-6.2 07/25] armsse: Wire up systick cpuclk clock
2021-08-12 9:33 [PATCH for-6.2 00/25] arm: Get rid of system_clock_scale global Peter Maydell
` (5 preceding siblings ...)
2021-08-12 9:33 ` [PATCH for-6.2 06/25] hw/arm/armv7m: Create " Peter Maydell
@ 2021-08-12 9:33 ` Peter Maydell
2021-08-13 1:29 ` Alistair Francis
2021-08-17 9:36 ` Luc Michel
2021-08-12 9:33 ` [PATCH for-6.2 08/25] hw/arm/mps2.c: Connect up armv7m clocks Peter Maydell
` (17 subsequent siblings)
24 siblings, 2 replies; 91+ messages in thread
From: Peter Maydell @ 2021-08-12 9:33 UTC (permalink / raw)
To: qemu-arm, qemu-devel
Cc: Damien Hedde, Luc Michel, Alistair Francis, Subbaraya Sundeep,
Joel Stanley, Alexandre Iooss
Wire up the cpuclk for the systick devices to the SSE object's
existing mainclk clock.
We do not wire up the refclk because the SSE subsystems do not
provide a refclk. (This is documented in the IoTKit and SSE-200
TRMs; the SSE-300 TRM doesn't mention it but we assume it follows the
same approach.) When we update the systick device later to honour "no
refclk connected" this will fix a minor emulation inaccuracy for the
SSE-based boards.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/arm/armsse.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c
index a1456cb0f42..70b52c3d4b9 100644
--- a/hw/arm/armsse.c
+++ b/hw/arm/armsse.c
@@ -995,6 +995,9 @@ static void armsse_realize(DeviceState *dev, Error **errp)
int j;
char *gpioname;
+ qdev_connect_clock_in(cpudev, "cpuclk", s->mainclk);
+ /* The SSE subsystems do not wire up a systick refclk */
+
qdev_prop_set_uint32(cpudev, "num-irq", s->exp_numirq + NUM_SSE_IRQS);
/*
* In real hardware the initial Secure VTOR is set from the INITSVTOR*
--
2.20.1
^ permalink raw reply related [flat|nested] 91+ messages in thread
* [PATCH for-6.2 08/25] hw/arm/mps2.c: Connect up armv7m clocks
2021-08-12 9:33 [PATCH for-6.2 00/25] arm: Get rid of system_clock_scale global Peter Maydell
` (6 preceding siblings ...)
2021-08-12 9:33 ` [PATCH for-6.2 07/25] armsse: Wire up systick cpuclk clock Peter Maydell
@ 2021-08-12 9:33 ` Peter Maydell
2021-08-17 9:39 ` Luc Michel
2021-08-12 9:33 ` [PATCH for-6.2 09/25] clock: Provide builtin multiplier/divider Peter Maydell
` (16 subsequent siblings)
24 siblings, 1 reply; 91+ messages in thread
From: Peter Maydell @ 2021-08-12 9:33 UTC (permalink / raw)
To: qemu-arm, qemu-devel
Cc: Damien Hedde, Luc Michel, Alistair Francis, Subbaraya Sundeep,
Joel Stanley, Alexandre Iooss
Connect up the armv7m clocks on the mps2-an385/386/500/511.
Connect up the armv7m object's clocks on the MPS boards defined in
mps2.c. The documentation for these FPGA images doesn't specify what
systick reference clock is used (if any), so for the moment we
provide a 1MHz refclock, which will result in no behavioural change
from the current hardwired 1MHz clock implemented in
armv7m_systick.c:systick_scale().
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/arm/mps2.c | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c
index 81413b7133e..3671f49ad7b 100644
--- a/hw/arm/mps2.c
+++ b/hw/arm/mps2.c
@@ -86,6 +86,7 @@ struct MPS2MachineState {
CMSDKAPBWatchdog watchdog;
CMSDKAPBTimer timer[2];
Clock *sysclk;
+ Clock *refclk;
};
#define TYPE_MPS2_MACHINE "mps2"
@@ -99,6 +100,15 @@ OBJECT_DECLARE_TYPE(MPS2MachineState, MPS2MachineClass, MPS2_MACHINE)
/* Main SYSCLK frequency in Hz */
#define SYSCLK_FRQ 25000000
+/*
+ * The Application Notes don't say anything about how the
+ * systick reference clock is configured. (Quite possibly
+ * they don't have one at all.) This 1MHz clock matches the
+ * pre-existing behaviour that used to be hardcoded in the
+ * armv7m_systick implementation.
+ */
+#define REFCLK_FRQ (1 * 1000 * 1000)
+
/* Initialize the auxiliary RAM region @mr and map it into
* the memory map at @base.
*/
@@ -146,6 +156,9 @@ static void mps2_common_init(MachineState *machine)
mms->sysclk = clock_new(OBJECT(machine), "SYSCLK");
clock_set_hz(mms->sysclk, SYSCLK_FRQ);
+ mms->refclk = clock_new(OBJECT(machine), "REFCLK");
+ clock_set_hz(mms->refclk, REFCLK_FRQ);
+
/* The FPGA images have an odd combination of different RAMs,
* because in hardware they are different implementations and
* connected to different buses, giving varying performance/size
@@ -223,6 +236,8 @@ static void mps2_common_init(MachineState *machine)
default:
g_assert_not_reached();
}
+ qdev_connect_clock_in(armv7m, "cpuclk", mms->sysclk);
+ qdev_connect_clock_in(armv7m, "refclk", mms->refclk);
qdev_prop_set_string(armv7m, "cpu-type", machine->cpu_type);
qdev_prop_set_bit(armv7m, "enable-bitband", true);
object_property_set_link(OBJECT(&mms->armv7m), "memory",
--
2.20.1
^ permalink raw reply related [flat|nested] 91+ messages in thread
* [PATCH for-6.2 09/25] clock: Provide builtin multiplier/divider
2021-08-12 9:33 [PATCH for-6.2 00/25] arm: Get rid of system_clock_scale global Peter Maydell
` (7 preceding siblings ...)
2021-08-12 9:33 ` [PATCH for-6.2 08/25] hw/arm/mps2.c: Connect up armv7m clocks Peter Maydell
@ 2021-08-12 9:33 ` Peter Maydell
2021-08-12 12:08 ` Alexandre IOOSS
` (4 more replies)
2021-08-12 9:33 ` [PATCH for-6.2 10/25] hw/arm: Don't allocate separate MemoryRegions in stm32 SoC realize Peter Maydell
` (15 subsequent siblings)
24 siblings, 5 replies; 91+ messages in thread
From: Peter Maydell @ 2021-08-12 9:33 UTC (permalink / raw)
To: qemu-arm, qemu-devel
Cc: Damien Hedde, Luc Michel, Alistair Francis, Subbaraya Sundeep,
Joel Stanley, Alexandre Iooss
It is quite common for a clock tree to involve possibly programmable
clock multipliers or dividers, where the frequency of a clock is for
instance divided by 8 to produce a slower clock to feed to a
particular device.
Currently we provide no convenient mechanism for modelling this. You
can implement it by having an input Clock and an output Clock, and
manually setting the period of the output clock in the period-changed
callback of the input clock, but that's quite clunky.
This patch adds support in the Clock objects themselves for setting a
multiplier or divider. The effect of setting this on a clock is that
when the clock's period is changed, all the children of the clock are
set to period * multiplier / divider, rather than being set to the
same period as the parent clock.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
docs/devel/clocks.rst | 23 +++++++++++++++++++++++
include/hw/clock.h | 29 +++++++++++++++++++++++++++++
hw/core/clock-vmstate.c | 24 +++++++++++++++++++++++-
hw/core/clock.c | 29 +++++++++++++++++++++++++----
4 files changed, 100 insertions(+), 5 deletions(-)
diff --git a/docs/devel/clocks.rst b/docs/devel/clocks.rst
index 956bd147ea0..430fbd842e5 100644
--- a/docs/devel/clocks.rst
+++ b/docs/devel/clocks.rst
@@ -260,6 +260,29 @@ clocks get the new clock period value: *Clock 2*, *Clock 3* and *Clock 4*.
It is not possible to disconnect a clock or to change the clock connection
after it is connected.
+Clock multiplier and divider settings
+-------------------------------------
+
+By default, when clocks are connected together, the child
+clocks run with the same period as their source (parent) clock.
+The Clock API supports a built-in period multiplier/divider
+mechanism so you can configure a clock to make its children
+run at a different period from its own. If you call the
+``clock_set_mul_div()`` function you can specify the clock's
+multiplier and divider values. The children of that clock
+will all run with a period of ``parent_period * multiplier / divider``.
+For instance, if the clock has a frequency of 8MHz and you set its
+multiplier to 2 and its divider to 3, the child clocks will run
+at 12MHz.
+
+You can change the multiplier and divider of a clock at runtime,
+so you can use this to model clock controller devices which
+have guest-programmable frequency multipliers or dividers.
+
+Note that ``clock_set_mul_div()`` does not automatically call
+``clock_propagate()``. If you make a runtime change to the
+multiplier or divider you must call clock_propagate() yourself.a
+
Unconnected input clocks
------------------------
diff --git a/include/hw/clock.h b/include/hw/clock.h
index a7187eab95e..11f67fb9701 100644
--- a/include/hw/clock.h
+++ b/include/hw/clock.h
@@ -81,6 +81,10 @@ struct Clock {
void *callback_opaque;
unsigned int callback_events;
+ /* Ratio of the parent clock to run the child clocks at */
+ uint32_t multiplier;
+ uint32_t divider;
+
/* Clocks are organized in a clock tree */
Clock *source;
QLIST_HEAD(, Clock) children;
@@ -350,4 +354,29 @@ static inline bool clock_is_enabled(const Clock *clk)
*/
char *clock_display_freq(Clock *clk);
+/**
+ * clock_set_mul_div: set multiplier/divider for child clocks
+ * @clk: clock
+ * @multiplier: multiplier value
+ * @divider: divider value
+ *
+ * By default, a Clock's children will all run with the same period
+ * as their parent. This function allows you to adjust the multiplier
+ * and divider used to derive the child clock frequency.
+ * For example, setting a multiplier of 2 and a divider of 3
+ * will run child clocks with a period 2/3 of the parent clock,
+ * so if the parent clock is an 8MHz clock the children will
+ * be 12MHz.
+ *
+ * Setting the multiplier to 0 will stop the child clocks.
+ * Setting the divider to 0 is a programming error (diagnosed with
+ * an assertion failure).
+ * Setting a multiplier value that results in the child period
+ * overflowing is not diagnosed.
+ *
+ * Note that this function does not call clock_propagate(); the
+ * caller should do that if necessary.
+ */
+void clock_set_mul_div(Clock *clk, uint32_t multiplier, uint32_t divider);
+
#endif /* QEMU_HW_CLOCK_H */
diff --git a/hw/core/clock-vmstate.c b/hw/core/clock-vmstate.c
index 260b13fc2c8..07bb45d7ed4 100644
--- a/hw/core/clock-vmstate.c
+++ b/hw/core/clock-vmstate.c
@@ -14,6 +14,24 @@
#include "migration/vmstate.h"
#include "hw/clock.h"
+static bool muldiv_needed(void *opaque)
+{
+ Clock *clk = opaque;
+
+ return clk->multiplier != 1 || clk->divider != 1;
+}
+
+const VMStateDescription vmstate_muldiv = {
+ .name = "clock/muldiv",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .needed = muldiv_needed,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT32(multiplier, Clock),
+ VMSTATE_UINT32(divider, Clock),
+ },
+};
+
const VMStateDescription vmstate_clock = {
.name = "clock",
.version_id = 0,
@@ -21,5 +39,9 @@ const VMStateDescription vmstate_clock = {
.fields = (VMStateField[]) {
VMSTATE_UINT64(period, Clock),
VMSTATE_END_OF_LIST()
- }
+ },
+ .subsections = (const VMStateDescription*[]) {
+ &vmstate_muldiv,
+ NULL
+ },
};
diff --git a/hw/core/clock.c b/hw/core/clock.c
index fc5a99683f8..c371b9e977a 100644
--- a/hw/core/clock.c
+++ b/hw/core/clock.c
@@ -64,6 +64,15 @@ bool clock_set(Clock *clk, uint64_t period)
return true;
}
+static uint64_t clock_get_child_period(Clock *clk)
+{
+ /*
+ * Return the period to be used for child clocks, which is the parent
+ * clock period adjusted for for multiplier and divider effects.
+ */
+ return muldiv64(clk->period, clk->multiplier, clk->divider);
+}
+
static void clock_call_callback(Clock *clk, ClockEvent event)
{
/*
@@ -78,15 +87,16 @@ static void clock_call_callback(Clock *clk, ClockEvent event)
static void clock_propagate_period(Clock *clk, bool call_callbacks)
{
Clock *child;
+ uint64_t child_period = clock_get_child_period(clk);
QLIST_FOREACH(child, &clk->children, sibling) {
- if (child->period != clk->period) {
+ if (child->period != child_period) {
if (call_callbacks) {
clock_call_callback(child, ClockPreUpdate);
}
- child->period = clk->period;
+ child->period = child_period;
trace_clock_update(CLOCK_PATH(child), CLOCK_PATH(clk),
- CLOCK_PERIOD_TO_HZ(clk->period),
+ CLOCK_PERIOD_TO_HZ(child->period),
call_callbacks);
if (call_callbacks) {
clock_call_callback(child, ClockUpdate);
@@ -110,7 +120,7 @@ void clock_set_source(Clock *clk, Clock *src)
trace_clock_set_source(CLOCK_PATH(clk), CLOCK_PATH(src));
- clk->period = src->period;
+ clk->period = clock_get_child_period(src);
QLIST_INSERT_HEAD(&src->children, clk, sibling);
clk->source = src;
clock_propagate_period(clk, false);
@@ -133,10 +143,21 @@ char *clock_display_freq(Clock *clk)
return freq_to_str(clock_get_hz(clk));
}
+void clock_set_mul_div(Clock *clk, uint32_t multiplier, uint32_t divider)
+{
+ assert(divider != 0);
+
+ clk->multiplier = multiplier;
+ clk->divider = divider;
+}
+
static void clock_initfn(Object *obj)
{
Clock *clk = CLOCK(obj);
+ clk->multiplier = 1;
+ clk->divider = 1;
+
QLIST_INIT(&clk->children);
}
--
2.20.1
^ permalink raw reply related [flat|nested] 91+ messages in thread
* [PATCH for-6.2 10/25] hw/arm: Don't allocate separate MemoryRegions in stm32 SoC realize
2021-08-12 9:33 [PATCH for-6.2 00/25] arm: Get rid of system_clock_scale global Peter Maydell
` (8 preceding siblings ...)
2021-08-12 9:33 ` [PATCH for-6.2 09/25] clock: Provide builtin multiplier/divider Peter Maydell
@ 2021-08-12 9:33 ` Peter Maydell
2021-08-12 12:13 ` Alexandre IOOSS
` (2 more replies)
2021-08-12 9:33 ` [PATCH for-6.2 11/25] hw/arm/stm32f100: Wire up sysclk and refclk Peter Maydell
` (14 subsequent siblings)
24 siblings, 3 replies; 91+ messages in thread
From: Peter Maydell @ 2021-08-12 9:33 UTC (permalink / raw)
To: qemu-arm, qemu-devel
Cc: Damien Hedde, Luc Michel, Alistair Francis, Subbaraya Sundeep,
Joel Stanley, Alexandre Iooss
In the realize methods of the stm32f100 and stm32f205 SoC objects, we
call g_new() to create new MemoryRegion objjects for the sram, flash,
and flash_alias. This is unnecessary (and leaves open the
possibility of leaking the allocations if we exit from realize with
an error). Make these MemoryRegions member fields of the device
state struct instead, as stm32f405 already does.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
include/hw/arm/stm32f100_soc.h | 4 ++++
include/hw/arm/stm32f205_soc.h | 4 ++++
hw/arm/stm32f100_soc.c | 17 +++++++----------
hw/arm/stm32f205_soc.c | 17 +++++++----------
4 files changed, 22 insertions(+), 20 deletions(-)
diff --git a/include/hw/arm/stm32f100_soc.h b/include/hw/arm/stm32f100_soc.h
index 71bffcf4fd5..b7d71c6c634 100644
--- a/include/hw/arm/stm32f100_soc.h
+++ b/include/hw/arm/stm32f100_soc.h
@@ -52,6 +52,10 @@ struct STM32F100State {
STM32F2XXUsartState usart[STM_NUM_USARTS];
STM32F2XXSPIState spi[STM_NUM_SPIS];
+
+ MemoryRegion sram;
+ MemoryRegion flash;
+ MemoryRegion flash_alias;
};
#endif
diff --git a/include/hw/arm/stm32f205_soc.h b/include/hw/arm/stm32f205_soc.h
index 985ff63aa9e..75251494917 100644
--- a/include/hw/arm/stm32f205_soc.h
+++ b/include/hw/arm/stm32f205_soc.h
@@ -63,6 +63,10 @@ struct STM32F205State {
STM32F2XXSPIState spi[STM_NUM_SPIS];
qemu_or_irq *adc_irqs;
+
+ MemoryRegion sram;
+ MemoryRegion flash;
+ MemoryRegion flash_alias;
};
#endif
diff --git a/hw/arm/stm32f100_soc.c b/hw/arm/stm32f100_soc.c
index 0c4a5c66451..0be92b2c475 100644
--- a/hw/arm/stm32f100_soc.c
+++ b/hw/arm/stm32f100_soc.c
@@ -67,25 +67,22 @@ static void stm32f100_soc_realize(DeviceState *dev_soc, Error **errp)
int i;
MemoryRegion *system_memory = get_system_memory();
- MemoryRegion *sram = g_new(MemoryRegion, 1);
- MemoryRegion *flash = g_new(MemoryRegion, 1);
- MemoryRegion *flash_alias = g_new(MemoryRegion, 1);
/*
* Init flash region
* Flash starts at 0x08000000 and then is aliased to boot memory at 0x0
*/
- memory_region_init_rom(flash, OBJECT(dev_soc), "STM32F100.flash",
+ memory_region_init_rom(&s->flash, OBJECT(dev_soc), "STM32F100.flash",
FLASH_SIZE, &error_fatal);
- memory_region_init_alias(flash_alias, OBJECT(dev_soc),
- "STM32F100.flash.alias", flash, 0, FLASH_SIZE);
- memory_region_add_subregion(system_memory, FLASH_BASE_ADDRESS, flash);
- memory_region_add_subregion(system_memory, 0, flash_alias);
+ memory_region_init_alias(&s->flash_alias, OBJECT(dev_soc),
+ "STM32F100.flash.alias", &s->flash, 0, FLASH_SIZE);
+ memory_region_add_subregion(system_memory, FLASH_BASE_ADDRESS, &s->flash);
+ memory_region_add_subregion(system_memory, 0, &s->flash_alias);
/* Init SRAM region */
- memory_region_init_ram(sram, NULL, "STM32F100.sram", SRAM_SIZE,
+ memory_region_init_ram(&s->sram, NULL, "STM32F100.sram", SRAM_SIZE,
&error_fatal);
- memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, sram);
+ memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, &s->sram);
/* Init ARMv7m */
armv7m = DEVICE(&s->armv7m);
diff --git a/hw/arm/stm32f205_soc.c b/hw/arm/stm32f205_soc.c
index 9cd41bf56da..0bd215aebd7 100644
--- a/hw/arm/stm32f205_soc.c
+++ b/hw/arm/stm32f205_soc.c
@@ -84,21 +84,18 @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
int i;
MemoryRegion *system_memory = get_system_memory();
- MemoryRegion *sram = g_new(MemoryRegion, 1);
- MemoryRegion *flash = g_new(MemoryRegion, 1);
- MemoryRegion *flash_alias = g_new(MemoryRegion, 1);
- memory_region_init_rom(flash, OBJECT(dev_soc), "STM32F205.flash",
+ memory_region_init_rom(&s->flash, OBJECT(dev_soc), "STM32F205.flash",
FLASH_SIZE, &error_fatal);
- memory_region_init_alias(flash_alias, OBJECT(dev_soc),
- "STM32F205.flash.alias", flash, 0, FLASH_SIZE);
+ memory_region_init_alias(&s->flash_alias, OBJECT(dev_soc),
+ "STM32F205.flash.alias", &s->flash, 0, FLASH_SIZE);
- memory_region_add_subregion(system_memory, FLASH_BASE_ADDRESS, flash);
- memory_region_add_subregion(system_memory, 0, flash_alias);
+ memory_region_add_subregion(system_memory, FLASH_BASE_ADDRESS, &s->flash);
+ memory_region_add_subregion(system_memory, 0, &s->flash_alias);
- memory_region_init_ram(sram, NULL, "STM32F205.sram", SRAM_SIZE,
+ memory_region_init_ram(&s->sram, NULL, "STM32F205.sram", SRAM_SIZE,
&error_fatal);
- memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, sram);
+ memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, &s->sram);
armv7m = DEVICE(&s->armv7m);
qdev_prop_set_uint32(armv7m, "num-irq", 96);
--
2.20.1
^ permalink raw reply related [flat|nested] 91+ messages in thread
* [PATCH for-6.2 11/25] hw/arm/stm32f100: Wire up sysclk and refclk
2021-08-12 9:33 [PATCH for-6.2 00/25] arm: Get rid of system_clock_scale global Peter Maydell
` (9 preceding siblings ...)
2021-08-12 9:33 ` [PATCH for-6.2 10/25] hw/arm: Don't allocate separate MemoryRegions in stm32 SoC realize Peter Maydell
@ 2021-08-12 9:33 ` Peter Maydell
2021-08-13 1:36 ` Alistair Francis
` (2 more replies)
2021-08-12 9:33 ` [PATCH for-6.2 12/25] hw/arm/stm32f205: " Peter Maydell
` (13 subsequent siblings)
24 siblings, 3 replies; 91+ messages in thread
From: Peter Maydell @ 2021-08-12 9:33 UTC (permalink / raw)
To: qemu-arm, qemu-devel
Cc: Damien Hedde, Luc Michel, Alistair Francis, Subbaraya Sundeep,
Joel Stanley, Alexandre Iooss
Wire up the sysclk and refclk for the stm32f100 SoC. This SoC always
runs the systick refclk at 1/8 the frequency of the main CPU clock,
so the board code only needs to provide a single sysclk clock.
Because there is only one board using this SoC, we convert the SoC
and the board together, rather than splitting it into "add clock to
SoC; connect clock in board; add error check in SoC code that clock
is wired up".
When the systick device starts honouring its clock inputs, this will
fix an emulation inaccuracy in the stm32vldiscovery board where the
systick reference clock was running at 1MHz rather than 3MHz.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
include/hw/arm/stm32f100_soc.h | 4 ++++
hw/arm/stm32f100_soc.c | 30 ++++++++++++++++++++++++++++++
hw/arm/stm32vldiscovery.c | 12 +++++++-----
3 files changed, 41 insertions(+), 5 deletions(-)
diff --git a/include/hw/arm/stm32f100_soc.h b/include/hw/arm/stm32f100_soc.h
index b7d71c6c634..40cd415b284 100644
--- a/include/hw/arm/stm32f100_soc.h
+++ b/include/hw/arm/stm32f100_soc.h
@@ -29,6 +29,7 @@
#include "hw/ssi/stm32f2xx_spi.h"
#include "hw/arm/armv7m.h"
#include "qom/object.h"
+#include "hw/clock.h"
#define TYPE_STM32F100_SOC "stm32f100-soc"
OBJECT_DECLARE_SIMPLE_TYPE(STM32F100State, STM32F100_SOC)
@@ -56,6 +57,9 @@ struct STM32F100State {
MemoryRegion sram;
MemoryRegion flash;
MemoryRegion flash_alias;
+
+ Clock *sysclk;
+ Clock *refclk;
};
#endif
diff --git a/hw/arm/stm32f100_soc.c b/hw/arm/stm32f100_soc.c
index 0be92b2c475..f7b344ba9fb 100644
--- a/hw/arm/stm32f100_soc.c
+++ b/hw/arm/stm32f100_soc.c
@@ -30,6 +30,7 @@
#include "exec/address-spaces.h"
#include "hw/arm/stm32f100_soc.h"
#include "hw/qdev-properties.h"
+#include "hw/qdev-clock.h"
#include "hw/misc/unimp.h"
#include "sysemu/sysemu.h"
@@ -57,6 +58,9 @@ static void stm32f100_soc_initfn(Object *obj)
for (i = 0; i < STM_NUM_SPIS; i++) {
object_initialize_child(obj, "spi[*]", &s->spi[i], TYPE_STM32F2XX_SPI);
}
+
+ s->sysclk = qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0);
+ s->refclk = qdev_init_clock_in(DEVICE(s), "refclk", NULL, NULL, 0);
}
static void stm32f100_soc_realize(DeviceState *dev_soc, Error **errp)
@@ -68,6 +72,30 @@ static void stm32f100_soc_realize(DeviceState *dev_soc, Error **errp)
MemoryRegion *system_memory = get_system_memory();
+ /*
+ * We use s->refclk internally and only define it with qdev_init_clock_in()
+ * so it is correctly parented and not leaked on an init/deinit; it is not
+ * intended as an externally exposed clock.
+ */
+ if (clock_has_source(s->refclk)) {
+ error_setg(errp, "refclk clock must not be wired up by the board code");
+ return;
+ }
+
+ if (!clock_has_source(s->sysclk)) {
+ error_setg(errp, "sysclk clock must be wired up by the board code");
+ return;
+ }
+
+ /*
+ * TODO: ideally we should model the SoC RCC and its ability to
+ * change the sysclk frequency and define different sysclk sources.
+ */
+
+ /* The refclk always runs at frequency HCLK / 8 */
+ clock_set_mul_div(s->refclk, 8, 1);
+ clock_set_source(s->refclk, s->sysclk);
+
/*
* Init flash region
* Flash starts at 0x08000000 and then is aliased to boot memory at 0x0
@@ -89,6 +117,8 @@ static void stm32f100_soc_realize(DeviceState *dev_soc, Error **errp)
qdev_prop_set_uint32(armv7m, "num-irq", 61);
qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type);
qdev_prop_set_bit(armv7m, "enable-bitband", true);
+ qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk);
+ qdev_connect_clock_in(armv7m, "refclk", s->refclk);
object_property_set_link(OBJECT(&s->armv7m), "memory",
OBJECT(get_system_memory()), &error_abort);
if (!sysbus_realize(SYS_BUS_DEVICE(&s->armv7m), errp)) {
diff --git a/hw/arm/stm32vldiscovery.c b/hw/arm/stm32vldiscovery.c
index 7e8191ebf5f..07e401a818d 100644
--- a/hw/arm/stm32vldiscovery.c
+++ b/hw/arm/stm32vldiscovery.c
@@ -27,6 +27,7 @@
#include "qapi/error.h"
#include "hw/boards.h"
#include "hw/qdev-properties.h"
+#include "hw/qdev-clock.h"
#include "qemu/error-report.h"
#include "hw/arm/stm32f100_soc.h"
#include "hw/arm/boot.h"
@@ -39,16 +40,17 @@
static void stm32vldiscovery_init(MachineState *machine)
{
DeviceState *dev;
+ Clock *sysclk;
- /*
- * TODO: ideally we would model the SoC RCC and let it handle
- * system_clock_scale, including its ability to define different
- * possible SYSCLK sources.
- */
system_clock_scale = NANOSECONDS_PER_SECOND / SYSCLK_FRQ;
+ /* This clock doesn't need migration because it is fixed-frequency */
+ sysclk = clock_new(OBJECT(machine), "SYSCLK");
+ clock_set_hz(sysclk, SYSCLK_FRQ);
+
dev = qdev_new(TYPE_STM32F100_SOC);
qdev_prop_set_string(dev, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m3"));
+ qdev_connect_clock_in(dev, "sysclk", sysclk);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
armv7m_load_kernel(ARM_CPU(first_cpu),
--
2.20.1
^ permalink raw reply related [flat|nested] 91+ messages in thread
* [PATCH for-6.2 12/25] hw/arm/stm32f205: Wire up sysclk and refclk
2021-08-12 9:33 [PATCH for-6.2 00/25] arm: Get rid of system_clock_scale global Peter Maydell
` (10 preceding siblings ...)
2021-08-12 9:33 ` [PATCH for-6.2 11/25] hw/arm/stm32f100: Wire up sysclk and refclk Peter Maydell
@ 2021-08-12 9:33 ` Peter Maydell
2021-08-13 1:38 ` Alistair Francis
` (2 more replies)
2021-08-12 9:33 ` [PATCH for-6.2 13/25] hw/arm/stm32f405: " Peter Maydell
` (12 subsequent siblings)
24 siblings, 3 replies; 91+ messages in thread
From: Peter Maydell @ 2021-08-12 9:33 UTC (permalink / raw)
To: qemu-arm, qemu-devel
Cc: Damien Hedde, Luc Michel, Alistair Francis, Subbaraya Sundeep,
Joel Stanley, Alexandre Iooss
Wire up the sysclk and refclk for the stm32f205 SoC. This SoC always
runs the systick refclk at 1/8 the frequency of the main CPU clock,
so the board code only needs to provide a single sysclk clock.
Because there is only one board using this SoC, we convert the SoC
and the board together, rather than splitting it into "add clock to
SoC; connect clock in board; add error check in SoC code that clock
is wired up".
When the systick device starts honouring its clock inputs, this will
fix an emulation inaccuracy in the netduino2 board where the systick
reference clock was running at 1MHz rather than 15MHz.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
include/hw/arm/stm32f205_soc.h | 4 ++++
hw/arm/netduino2.c | 12 +++++++-----
hw/arm/stm32f205_soc.c | 30 ++++++++++++++++++++++++++++++
3 files changed, 41 insertions(+), 5 deletions(-)
diff --git a/include/hw/arm/stm32f205_soc.h b/include/hw/arm/stm32f205_soc.h
index 75251494917..849d3ed8891 100644
--- a/include/hw/arm/stm32f205_soc.h
+++ b/include/hw/arm/stm32f205_soc.h
@@ -32,6 +32,7 @@
#include "hw/or-irq.h"
#include "hw/ssi/stm32f2xx_spi.h"
#include "hw/arm/armv7m.h"
+#include "hw/clock.h"
#include "qom/object.h"
#define TYPE_STM32F205_SOC "stm32f205-soc"
@@ -67,6 +68,9 @@ struct STM32F205State {
MemoryRegion sram;
MemoryRegion flash;
MemoryRegion flash_alias;
+
+ Clock *sysclk;
+ Clock *refclk;
};
#endif
diff --git a/hw/arm/netduino2.c b/hw/arm/netduino2.c
index 1733b71507c..b5c0ba23ee5 100644
--- a/hw/arm/netduino2.c
+++ b/hw/arm/netduino2.c
@@ -26,6 +26,7 @@
#include "qapi/error.h"
#include "hw/boards.h"
#include "hw/qdev-properties.h"
+#include "hw/qdev-clock.h"
#include "qemu/error-report.h"
#include "hw/arm/stm32f205_soc.h"
#include "hw/arm/boot.h"
@@ -36,16 +37,17 @@
static void netduino2_init(MachineState *machine)
{
DeviceState *dev;
+ Clock *sysclk;
- /*
- * TODO: ideally we would model the SoC RCC and let it handle
- * system_clock_scale, including its ability to define different
- * possible SYSCLK sources.
- */
system_clock_scale = NANOSECONDS_PER_SECOND / SYSCLK_FRQ;
+ /* This clock doesn't need migration because it is fixed-frequency */
+ sysclk = clock_new(OBJECT(machine), "SYSCLK");
+ clock_set_hz(sysclk, SYSCLK_FRQ);
+
dev = qdev_new(TYPE_STM32F205_SOC);
qdev_prop_set_string(dev, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m3"));
+ qdev_connect_clock_in(dev, "sysclk", sysclk);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename,
diff --git a/hw/arm/stm32f205_soc.c b/hw/arm/stm32f205_soc.c
index 0bd215aebd7..c6b75a381d9 100644
--- a/hw/arm/stm32f205_soc.c
+++ b/hw/arm/stm32f205_soc.c
@@ -29,6 +29,7 @@
#include "exec/address-spaces.h"
#include "hw/arm/stm32f205_soc.h"
#include "hw/qdev-properties.h"
+#include "hw/qdev-clock.h"
#include "sysemu/sysemu.h"
/* At the moment only Timer 2 to 5 are modelled */
@@ -74,6 +75,9 @@ static void stm32f205_soc_initfn(Object *obj)
for (i = 0; i < STM_NUM_SPIS; i++) {
object_initialize_child(obj, "spi[*]", &s->spi[i], TYPE_STM32F2XX_SPI);
}
+
+ s->sysclk = qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0);
+ s->refclk = qdev_init_clock_in(DEVICE(s), "refclk", NULL, NULL, 0);
}
static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
@@ -85,6 +89,30 @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
MemoryRegion *system_memory = get_system_memory();
+ /*
+ * We use s->refclk internally and only define it with qdev_init_clock_in()
+ * so it is correctly parented and not leaked on an init/deinit; it is not
+ * intended as an externally exposed clock.
+ */
+ if (clock_has_source(s->refclk)) {
+ error_setg(errp, "refclk clock must not be wired up by the board code");
+ return;
+ }
+
+ if (!clock_has_source(s->sysclk)) {
+ error_setg(errp, "sysclk clock must be wired up by the board code");
+ return;
+ }
+
+ /*
+ * TODO: ideally we should model the SoC RCC and its ability to
+ * change the sysclk frequency and define different sysclk sources.
+ */
+
+ /* The refclk always runs at frequency HCLK / 8 */
+ clock_set_mul_div(s->refclk, 8, 1);
+ clock_set_source(s->refclk, s->sysclk);
+
memory_region_init_rom(&s->flash, OBJECT(dev_soc), "STM32F205.flash",
FLASH_SIZE, &error_fatal);
memory_region_init_alias(&s->flash_alias, OBJECT(dev_soc),
@@ -101,6 +129,8 @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
qdev_prop_set_uint32(armv7m, "num-irq", 96);
qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type);
qdev_prop_set_bit(armv7m, "enable-bitband", true);
+ qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk);
+ qdev_connect_clock_in(armv7m, "refclk", s->refclk);
object_property_set_link(OBJECT(&s->armv7m), "memory",
OBJECT(get_system_memory()), &error_abort);
if (!sysbus_realize(SYS_BUS_DEVICE(&s->armv7m), errp)) {
--
2.20.1
^ permalink raw reply related [flat|nested] 91+ messages in thread
* [PATCH for-6.2 13/25] hw/arm/stm32f405: Wire up sysclk and refclk
2021-08-12 9:33 [PATCH for-6.2 00/25] arm: Get rid of system_clock_scale global Peter Maydell
` (11 preceding siblings ...)
2021-08-12 9:33 ` [PATCH for-6.2 12/25] hw/arm/stm32f205: " Peter Maydell
@ 2021-08-12 9:33 ` Peter Maydell
2021-08-13 1:37 ` Alistair Francis
` (2 more replies)
2021-08-12 9:33 ` [PATCH for-6.2 14/25] hw/arm/stm32vldiscovery: Delete trailing blank line Peter Maydell
` (11 subsequent siblings)
24 siblings, 3 replies; 91+ messages in thread
From: Peter Maydell @ 2021-08-12 9:33 UTC (permalink / raw)
To: qemu-arm, qemu-devel
Cc: Damien Hedde, Luc Michel, Alistair Francis, Subbaraya Sundeep,
Joel Stanley, Alexandre Iooss
Wire up the sysclk and refclk for the stm32f405 SoC. This SoC always
runs the systick refclk at 1/8 the frequency of the main CPU clock,
so the board code only needs to provide a single sysclk clock.
Because there is only one board using this SoC, we convert the SoC
and the board together, rather than splitting it into "add clock to
SoC; connect clock in board; add error check in SoC code that clock
is wired up".
When the systick device starts honouring its clock inputs, this will
fix an emulation inaccuracy in the netduinoplus2 board where the
systick reference clock was running at 1MHz rather than 21MHz.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
include/hw/arm/stm32f405_soc.h | 3 +++
hw/arm/netduinoplus2.c | 12 +++++++-----
hw/arm/stm32f405_soc.c | 30 ++++++++++++++++++++++++++++++
3 files changed, 40 insertions(+), 5 deletions(-)
diff --git a/include/hw/arm/stm32f405_soc.h b/include/hw/arm/stm32f405_soc.h
index 347105e709b..5bb0c8d5697 100644
--- a/include/hw/arm/stm32f405_soc.h
+++ b/include/hw/arm/stm32f405_soc.h
@@ -68,6 +68,9 @@ struct STM32F405State {
MemoryRegion sram;
MemoryRegion flash;
MemoryRegion flash_alias;
+
+ Clock *sysclk;
+ Clock *refclk;
};
#endif
diff --git a/hw/arm/netduinoplus2.c b/hw/arm/netduinoplus2.c
index d3ad7a2b675..a5a8999cc8c 100644
--- a/hw/arm/netduinoplus2.c
+++ b/hw/arm/netduinoplus2.c
@@ -26,6 +26,7 @@
#include "qapi/error.h"
#include "hw/boards.h"
#include "hw/qdev-properties.h"
+#include "hw/qdev-clock.h"
#include "qemu/error-report.h"
#include "hw/arm/stm32f405_soc.h"
#include "hw/arm/boot.h"
@@ -36,16 +37,17 @@
static void netduinoplus2_init(MachineState *machine)
{
DeviceState *dev;
+ Clock *sysclk;
- /*
- * TODO: ideally we would model the SoC RCC and let it handle
- * system_clock_scale, including its ability to define different
- * possible SYSCLK sources.
- */
system_clock_scale = NANOSECONDS_PER_SECOND / SYSCLK_FRQ;
+ /* This clock doesn't need migration because it is fixed-frequency */
+ sysclk = clock_new(OBJECT(machine), "SYSCLK");
+ clock_set_hz(sysclk, SYSCLK_FRQ);
+
dev = qdev_new(TYPE_STM32F405_SOC);
qdev_prop_set_string(dev, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m4"));
+ qdev_connect_clock_in(dev, "sysclk", sysclk);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
armv7m_load_kernel(ARM_CPU(first_cpu),
diff --git a/hw/arm/stm32f405_soc.c b/hw/arm/stm32f405_soc.c
index cb04c111987..0019b7f4785 100644
--- a/hw/arm/stm32f405_soc.c
+++ b/hw/arm/stm32f405_soc.c
@@ -28,6 +28,7 @@
#include "exec/address-spaces.h"
#include "sysemu/sysemu.h"
#include "hw/arm/stm32f405_soc.h"
+#include "hw/qdev-clock.h"
#include "hw/misc/unimp.h"
#define SYSCFG_ADD 0x40013800
@@ -80,6 +81,9 @@ static void stm32f405_soc_initfn(Object *obj)
}
object_initialize_child(obj, "exti", &s->exti, TYPE_STM32F4XX_EXTI);
+
+ s->sysclk = qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0);
+ s->refclk = qdev_init_clock_in(DEVICE(s), "refclk", NULL, NULL, 0);
}
static void stm32f405_soc_realize(DeviceState *dev_soc, Error **errp)
@@ -91,6 +95,30 @@ static void stm32f405_soc_realize(DeviceState *dev_soc, Error **errp)
Error *err = NULL;
int i;
+ /*
+ * We use s->refclk internally and only define it with qdev_init_clock_in()
+ * so it is correctly parented and not leaked on an init/deinit; it is not
+ * intended as an externally exposed clock.
+ */
+ if (clock_has_source(s->refclk)) {
+ error_setg(errp, "refclk clock must not be wired up by the board code");
+ return;
+ }
+
+ if (!clock_has_source(s->sysclk)) {
+ error_setg(errp, "sysclk clock must be wired up by the board code");
+ return;
+ }
+
+ /*
+ * TODO: ideally we should model the SoC RCC and its ability to
+ * change the sysclk frequency and define different sysclk sources.
+ */
+
+ /* The refclk always runs at frequency HCLK / 8 */
+ clock_set_mul_div(s->refclk, 8, 1);
+ clock_set_source(s->refclk, s->sysclk);
+
memory_region_init_rom(&s->flash, OBJECT(dev_soc), "STM32F405.flash",
FLASH_SIZE, &err);
if (err != NULL) {
@@ -116,6 +144,8 @@ static void stm32f405_soc_realize(DeviceState *dev_soc, Error **errp)
qdev_prop_set_uint32(armv7m, "num-irq", 96);
qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type);
qdev_prop_set_bit(armv7m, "enable-bitband", true);
+ qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk);
+ qdev_connect_clock_in(armv7m, "refclk", s->refclk);
object_property_set_link(OBJECT(&s->armv7m), "memory",
OBJECT(system_memory), &error_abort);
if (!sysbus_realize(SYS_BUS_DEVICE(&s->armv7m), errp)) {
--
2.20.1
^ permalink raw reply related [flat|nested] 91+ messages in thread
* [PATCH for-6.2 14/25] hw/arm/stm32vldiscovery: Delete trailing blank line
2021-08-12 9:33 [PATCH for-6.2 00/25] arm: Get rid of system_clock_scale global Peter Maydell
` (12 preceding siblings ...)
2021-08-12 9:33 ` [PATCH for-6.2 13/25] hw/arm/stm32f405: " Peter Maydell
@ 2021-08-12 9:33 ` Peter Maydell
2021-08-12 12:27 ` Alexandre IOOSS
` (2 more replies)
2021-08-12 9:33 ` [PATCH for-6.2 15/25] hw/arm/nrf51: Wire up sysclk Peter Maydell
` (10 subsequent siblings)
24 siblings, 3 replies; 91+ messages in thread
From: Peter Maydell @ 2021-08-12 9:33 UTC (permalink / raw)
To: qemu-arm, qemu-devel
Cc: Damien Hedde, Luc Michel, Alistair Francis, Subbaraya Sundeep,
Joel Stanley, Alexandre Iooss
Delete the trailing blank line at the end of the source file.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/arm/stm32vldiscovery.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/hw/arm/stm32vldiscovery.c b/hw/arm/stm32vldiscovery.c
index 07e401a818d..9b79004703b 100644
--- a/hw/arm/stm32vldiscovery.c
+++ b/hw/arm/stm32vldiscovery.c
@@ -65,4 +65,3 @@ static void stm32vldiscovery_machine_init(MachineClass *mc)
}
DEFINE_MACHINE("stm32vldiscovery", stm32vldiscovery_machine_init)
-
--
2.20.1
^ permalink raw reply related [flat|nested] 91+ messages in thread
* [PATCH for-6.2 15/25] hw/arm/nrf51: Wire up sysclk
2021-08-12 9:33 [PATCH for-6.2 00/25] arm: Get rid of system_clock_scale global Peter Maydell
` (13 preceding siblings ...)
2021-08-12 9:33 ` [PATCH for-6.2 14/25] hw/arm/stm32vldiscovery: Delete trailing blank line Peter Maydell
@ 2021-08-12 9:33 ` Peter Maydell
2021-08-14 9:06 ` Alexandre IOOSS
2021-08-12 9:33 ` [PATCH for-6.2 16/25] hw/arm/stellaris: split stellaris_sys_init() Peter Maydell
` (9 subsequent siblings)
24 siblings, 1 reply; 91+ messages in thread
From: Peter Maydell @ 2021-08-12 9:33 UTC (permalink / raw)
To: qemu-arm, qemu-devel
Cc: Damien Hedde, Luc Michel, Alistair Francis, Subbaraya Sundeep,
Joel Stanley, Alexandre Iooss
Wire up the sysclk input to the armv7m object.
Strictly this SoC should not have a systick device at all, but our
armv7m container object doesn't currently support disabling the
systick device. For the moment, add a TODO comment, but note that
this is why we aren't wiring up a refclk (no need for one).
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
include/hw/arm/nrf51_soc.h | 2 ++
hw/arm/nrf51_soc.c | 20 ++++++++++++++++++++
2 files changed, 22 insertions(+)
diff --git a/include/hw/arm/nrf51_soc.h b/include/hw/arm/nrf51_soc.h
index f8a6725b775..e52a56e75e0 100644
--- a/include/hw/arm/nrf51_soc.h
+++ b/include/hw/arm/nrf51_soc.h
@@ -17,6 +17,7 @@
#include "hw/gpio/nrf51_gpio.h"
#include "hw/nvram/nrf51_nvm.h"
#include "hw/timer/nrf51_timer.h"
+#include "hw/clock.h"
#include "qom/object.h"
#define TYPE_NRF51_SOC "nrf51-soc"
@@ -50,6 +51,7 @@ struct NRF51State {
MemoryRegion container;
+ Clock *sysclk;
};
#endif
diff --git a/hw/arm/nrf51_soc.c b/hw/arm/nrf51_soc.c
index 9407c2f268b..e3e849a32b1 100644
--- a/hw/arm/nrf51_soc.c
+++ b/hw/arm/nrf51_soc.c
@@ -12,6 +12,7 @@
#include "qapi/error.h"
#include "hw/arm/boot.h"
#include "hw/sysbus.h"
+#include "hw/qdev-clock.h"
#include "hw/misc/unimp.h"
#include "qemu/log.h"
@@ -66,6 +67,23 @@ static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp)
return;
}
+ /*
+ * HCLK on this SoC is fixed, so we set up sysclk ourselves and
+ * the board shouldn't connect it.
+ */
+ if (clock_has_source(s->sysclk)) {
+ error_setg(errp, "sysclk clock must not be wired up by the board code");
+ return;
+ }
+ /* This clock doesn't need migration because it is fixed-frequency */
+ clock_set_hz(s->sysclk, HCLK_FRQ);
+ qdev_connect_clock_in(DEVICE(&s->cpu), "cpuclk", s->sysclk);
+ /*
+ * This SoC has no systick device, so don't connect refclk.
+ * TODO: model the lack of systick (currently the armv7m object
+ * will always provide one).
+ */
+
system_clock_scale = NANOSECONDS_PER_SECOND / HCLK_FRQ;
object_property_set_link(OBJECT(&s->cpu), "memory", OBJECT(&s->container),
@@ -191,6 +209,8 @@ static void nrf51_soc_init(Object *obj)
TYPE_NRF51_TIMER);
}
+
+ s->sysclk = qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0);
}
static Property nrf51_soc_properties[] = {
--
2.20.1
^ permalink raw reply related [flat|nested] 91+ messages in thread
* [PATCH for-6.2 16/25] hw/arm/stellaris: split stellaris_sys_init()
2021-08-12 9:33 [PATCH for-6.2 00/25] arm: Get rid of system_clock_scale global Peter Maydell
` (14 preceding siblings ...)
2021-08-12 9:33 ` [PATCH for-6.2 15/25] hw/arm/nrf51: Wire up sysclk Peter Maydell
@ 2021-08-12 9:33 ` Peter Maydell
2021-08-14 9:10 ` Alexandre IOOSS
2021-08-12 9:33 ` [PATCH for-6.2 17/25] hw/arm/stellaris: Wire sysclk up to armv7m Peter Maydell
` (8 subsequent siblings)
24 siblings, 1 reply; 91+ messages in thread
From: Peter Maydell @ 2021-08-12 9:33 UTC (permalink / raw)
To: qemu-arm, qemu-devel
Cc: Damien Hedde, Luc Michel, Alistair Francis, Subbaraya Sundeep,
Joel Stanley, Alexandre Iooss
Currently the stellaris_sys_init() function creates the
TYPE_STELLARIS_SYS object, sets its properties, realizes it, maps its
MMIO region and connects its IRQ. In order to support wiring the
sysclk up to the armv7m object, we need to split this function apart,
because to connect the clock output of the STELLARIS_SYS object to
the armv7m object we need to create the STELLARIS_SYS object before
the armv7m object, but we can't wire up the IRQ until after we've
created the armv7m object.
Remove the stellaris_sys_init() function, and instead put the
create/configure/realize parts before we create the armv7m object and
the mmio/irq connection parts afterwards.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/arm/stellaris.c | 56 +++++++++++++++++++++-------------------------
1 file changed, 25 insertions(+), 31 deletions(-)
diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
index ad48cf26058..bf24abd44fd 100644
--- a/hw/arm/stellaris.c
+++ b/hw/arm/stellaris.c
@@ -755,33 +755,6 @@ static void stellaris_sys_instance_init(Object *obj)
s->sysclk = qdev_init_clock_out(DEVICE(s), "SYSCLK");
}
-static DeviceState *stellaris_sys_init(uint32_t base, qemu_irq irq,
- stellaris_board_info *board,
- uint8_t *macaddr)
-{
- DeviceState *dev = qdev_new(TYPE_STELLARIS_SYS);
- SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
-
- /* Most devices come preprogrammed with a MAC address in the user data. */
- qdev_prop_set_uint32(dev, "user0",
- macaddr[0] | (macaddr[1] << 8) | (macaddr[2] << 16));
- qdev_prop_set_uint32(dev, "user1",
- macaddr[3] | (macaddr[4] << 8) | (macaddr[5] << 16));
- qdev_prop_set_uint32(dev, "did0", board->did0);
- qdev_prop_set_uint32(dev, "did1", board->did1);
- qdev_prop_set_uint32(dev, "dc0", board->dc0);
- qdev_prop_set_uint32(dev, "dc1", board->dc1);
- qdev_prop_set_uint32(dev, "dc2", board->dc2);
- qdev_prop_set_uint32(dev, "dc3", board->dc3);
- qdev_prop_set_uint32(dev, "dc4", board->dc4);
-
- sysbus_realize_and_unref(sbd, &error_fatal);
- sysbus_mmio_map(sbd, 0, base);
- sysbus_connect_irq(sbd, 0, irq);
-
- return dev;
-}
-
/* I2C controller. */
#define TYPE_STELLARIS_I2C "stellaris-i2c"
@@ -1349,6 +1322,7 @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
DeviceState *ssys_dev;
int i;
int j;
+ uint8_t *macaddr;
MemoryRegion *sram = g_new(MemoryRegion, 1);
MemoryRegion *flash = g_new(MemoryRegion, 1);
@@ -1366,6 +1340,26 @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
&error_fatal);
memory_region_add_subregion(system_memory, 0x20000000, sram);
+ /*
+ * Create the system-registers object early, because we will
+ * need its sysclk output.
+ */
+ ssys_dev = qdev_new(TYPE_STELLARIS_SYS);
+ /* Most devices come preprogrammed with a MAC address in the user data. */
+ macaddr = nd_table[0].macaddr.a;
+ qdev_prop_set_uint32(ssys_dev, "user0",
+ macaddr[0] | (macaddr[1] << 8) | (macaddr[2] << 16));
+ qdev_prop_set_uint32(ssys_dev, "user1",
+ macaddr[3] | (macaddr[4] << 8) | (macaddr[5] << 16));
+ qdev_prop_set_uint32(ssys_dev, "did0", board->did0);
+ qdev_prop_set_uint32(ssys_dev, "did1", board->did1);
+ qdev_prop_set_uint32(ssys_dev, "dc0", board->dc0);
+ qdev_prop_set_uint32(ssys_dev, "dc1", board->dc1);
+ qdev_prop_set_uint32(ssys_dev, "dc2", board->dc2);
+ qdev_prop_set_uint32(ssys_dev, "dc3", board->dc3);
+ qdev_prop_set_uint32(ssys_dev, "dc4", board->dc4);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(ssys_dev), &error_fatal);
+
nvic = qdev_new(TYPE_ARMV7M);
qdev_prop_set_uint32(nvic, "num-irq", NUM_IRQ_LINES);
qdev_prop_set_string(nvic, "cpu-type", ms->cpu_type);
@@ -1375,6 +1369,10 @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
/* This will exit with an error if the user passed us a bad cpu_type */
sysbus_realize_and_unref(SYS_BUS_DEVICE(nvic), &error_fatal);
+ /* Now we can wire up the IRQ and MMIO of the system registers */
+ sysbus_mmio_map(SYS_BUS_DEVICE(ssys_dev), 0, 0x400fe000);
+ sysbus_connect_irq(SYS_BUS_DEVICE(ssys_dev), 0, qdev_get_gpio_in(nvic, 28));
+
if (board->dc1 & (1 << 16)) {
dev = sysbus_create_varargs(TYPE_STELLARIS_ADC, 0x40038000,
qdev_get_gpio_in(nvic, 14),
@@ -1397,10 +1395,6 @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
}
}
- ssys_dev = stellaris_sys_init(0x400fe000, qdev_get_gpio_in(nvic, 28),
- board, nd_table[0].macaddr.a);
-
-
if (board->dc1 & (1 << 3)) { /* watchdog present */
dev = qdev_new(TYPE_LUMINARY_WATCHDOG);
--
2.20.1
^ permalink raw reply related [flat|nested] 91+ messages in thread
* [PATCH for-6.2 17/25] hw/arm/stellaris: Wire sysclk up to armv7m
2021-08-12 9:33 [PATCH for-6.2 00/25] arm: Get rid of system_clock_scale global Peter Maydell
` (15 preceding siblings ...)
2021-08-12 9:33 ` [PATCH for-6.2 16/25] hw/arm/stellaris: split stellaris_sys_init() Peter Maydell
@ 2021-08-12 9:33 ` Peter Maydell
2021-08-14 9:12 ` Alexandre IOOSS
2021-08-12 9:33 ` [PATCH for-6.2 18/25] hw/arm/msf2_soc: Don't allocate separate MemoryRegions Peter Maydell
` (7 subsequent siblings)
24 siblings, 1 reply; 91+ messages in thread
From: Peter Maydell @ 2021-08-12 9:33 UTC (permalink / raw)
To: qemu-arm, qemu-devel
Cc: Damien Hedde, Luc Michel, Alistair Francis, Subbaraya Sundeep,
Joel Stanley, Alexandre Iooss
Connect the sysclk to the armv7m object. This board's SoC does not
connect up the systick reference clock, so we don't need to connect a
refclk.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/arm/stellaris.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
index bf24abd44fd..8c8bd39e2fe 100644
--- a/hw/arm/stellaris.c
+++ b/hw/arm/stellaris.c
@@ -1322,7 +1322,7 @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
DeviceState *ssys_dev;
int i;
int j;
- uint8_t *macaddr;
+ const uint8_t *macaddr;
MemoryRegion *sram = g_new(MemoryRegion, 1);
MemoryRegion *flash = g_new(MemoryRegion, 1);
@@ -1364,6 +1364,9 @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
qdev_prop_set_uint32(nvic, "num-irq", NUM_IRQ_LINES);
qdev_prop_set_string(nvic, "cpu-type", ms->cpu_type);
qdev_prop_set_bit(nvic, "enable-bitband", true);
+ qdev_connect_clock_in(nvic, "cpuclk",
+ qdev_get_clock_out(ssys_dev, "SYSCLK"));
+ /* This SoC does not connect the systick reference clock */
object_property_set_link(OBJECT(nvic), "memory",
OBJECT(get_system_memory()), &error_abort);
/* This will exit with an error if the user passed us a bad cpu_type */
--
2.20.1
^ permalink raw reply related [flat|nested] 91+ messages in thread
* [PATCH for-6.2 18/25] hw/arm/msf2_soc: Don't allocate separate MemoryRegions
2021-08-12 9:33 [PATCH for-6.2 00/25] arm: Get rid of system_clock_scale global Peter Maydell
` (16 preceding siblings ...)
2021-08-12 9:33 ` [PATCH for-6.2 17/25] hw/arm/stellaris: Wire sysclk up to armv7m Peter Maydell
@ 2021-08-12 9:33 ` Peter Maydell
2021-08-14 9:13 ` Alexandre IOOSS
2021-08-12 9:33 ` [PATCH for-6.2 19/25] hw/arm/msf2: Use Clock input to MSF2_SOC instead of m3clk property Peter Maydell
` (6 subsequent siblings)
24 siblings, 1 reply; 91+ messages in thread
From: Peter Maydell @ 2021-08-12 9:33 UTC (permalink / raw)
To: qemu-arm, qemu-devel
Cc: Damien Hedde, Luc Michel, Alistair Francis, Subbaraya Sundeep,
Joel Stanley, Alexandre Iooss
In the realize method of the msf2-soc SoC object, we call g_new() to
create new MemoryRegion objects for the nvm, nvm_alias, and sram.
This is unnecessary; make these MemoryRegions member fields of the
device state struct instead.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
include/hw/arm/msf2-soc.h | 4 ++++
hw/arm/msf2-soc.c | 17 +++++++----------
2 files changed, 11 insertions(+), 10 deletions(-)
diff --git a/include/hw/arm/msf2-soc.h b/include/hw/arm/msf2-soc.h
index d4061846855..38e10ce20aa 100644
--- a/include/hw/arm/msf2-soc.h
+++ b/include/hw/arm/msf2-soc.h
@@ -65,6 +65,10 @@ struct MSF2State {
MSSTimerState timer;
MSSSpiState spi[MSF2_NUM_SPIS];
MSF2EmacState emac;
+
+ MemoryRegion nvm;
+ MemoryRegion nvm_alias;
+ MemoryRegion sram;
};
#endif
diff --git a/hw/arm/msf2-soc.c b/hw/arm/msf2-soc.c
index 5cfe7caf834..f36788054b3 100644
--- a/hw/arm/msf2-soc.c
+++ b/hw/arm/msf2-soc.c
@@ -83,11 +83,8 @@ static void m2sxxx_soc_realize(DeviceState *dev_soc, Error **errp)
int i;
MemoryRegion *system_memory = get_system_memory();
- MemoryRegion *nvm = g_new(MemoryRegion, 1);
- MemoryRegion *nvm_alias = g_new(MemoryRegion, 1);
- MemoryRegion *sram = g_new(MemoryRegion, 1);
- memory_region_init_rom(nvm, OBJECT(dev_soc), "MSF2.eNVM", s->envm_size,
+ memory_region_init_rom(&s->nvm, OBJECT(dev_soc), "MSF2.eNVM", s->envm_size,
&error_fatal);
/*
* On power-on, the eNVM region 0x60000000 is automatically
@@ -95,15 +92,15 @@ static void m2sxxx_soc_realize(DeviceState *dev_soc, Error **errp)
* start address (0x0). We do not support remapping other eNVM,
* eSRAM and DDR regions by guest(via Sysreg) currently.
*/
- memory_region_init_alias(nvm_alias, OBJECT(dev_soc), "MSF2.eNVM", nvm, 0,
- s->envm_size);
+ memory_region_init_alias(&s->nvm_alias, OBJECT(dev_soc), "MSF2.eNVM",
+ &s->nvm, 0, s->envm_size);
- memory_region_add_subregion(system_memory, ENVM_BASE_ADDRESS, nvm);
- memory_region_add_subregion(system_memory, 0, nvm_alias);
+ memory_region_add_subregion(system_memory, ENVM_BASE_ADDRESS, &s->nvm);
+ memory_region_add_subregion(system_memory, 0, &s->nvm_alias);
- memory_region_init_ram(sram, NULL, "MSF2.eSRAM", s->esram_size,
+ memory_region_init_ram(&s->sram, NULL, "MSF2.eSRAM", s->esram_size,
&error_fatal);
- memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, sram);
+ memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, &s->sram);
armv7m = DEVICE(&s->armv7m);
qdev_prop_set_uint32(armv7m, "num-irq", 81);
--
2.20.1
^ permalink raw reply related [flat|nested] 91+ messages in thread
* [PATCH for-6.2 19/25] hw/arm/msf2: Use Clock input to MSF2_SOC instead of m3clk property
2021-08-12 9:33 [PATCH for-6.2 00/25] arm: Get rid of system_clock_scale global Peter Maydell
` (17 preceding siblings ...)
2021-08-12 9:33 ` [PATCH for-6.2 18/25] hw/arm/msf2_soc: Don't allocate separate MemoryRegions Peter Maydell
@ 2021-08-12 9:33 ` Peter Maydell
2021-08-14 9:20 ` Alexandre IOOSS
2021-08-12 9:33 ` [PATCH for-6.2 20/25] hw/arm/msf2-soc: Wire up refclk Peter Maydell
` (5 subsequent siblings)
24 siblings, 1 reply; 91+ messages in thread
From: Peter Maydell @ 2021-08-12 9:33 UTC (permalink / raw)
To: qemu-arm, qemu-devel
Cc: Damien Hedde, Luc Michel, Alistair Francis, Subbaraya Sundeep,
Joel Stanley, Alexandre Iooss
Instead of passing the MSF2 SoC an integer property specifying the
CPU clock rate, pass it a Clock instead. This lets us wire that
clock up to the armv7m object.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
include/hw/arm/msf2-soc.h | 3 ++-
hw/arm/msf2-soc.c | 28 +++++++++++++++++-----------
hw/arm/msf2-som.c | 7 ++++++-
3 files changed, 25 insertions(+), 13 deletions(-)
diff --git a/include/hw/arm/msf2-soc.h b/include/hw/arm/msf2-soc.h
index 38e10ce20aa..01f904cec47 100644
--- a/include/hw/arm/msf2-soc.h
+++ b/include/hw/arm/msf2-soc.h
@@ -30,6 +30,7 @@
#include "hw/misc/msf2-sysreg.h"
#include "hw/ssi/mss-spi.h"
#include "hw/net/msf2-emac.h"
+#include "hw/clock.h"
#include "qom/object.h"
#define TYPE_MSF2_SOC "msf2-soc"
@@ -57,7 +58,7 @@ struct MSF2State {
uint64_t envm_size;
uint64_t esram_size;
- uint32_t m3clk;
+ Clock *m3clk;
uint8_t apb0div;
uint8_t apb1div;
diff --git a/hw/arm/msf2-soc.c b/hw/arm/msf2-soc.c
index f36788054b3..0a1e594aee6 100644
--- a/hw/arm/msf2-soc.c
+++ b/hw/arm/msf2-soc.c
@@ -29,6 +29,7 @@
#include "hw/char/serial.h"
#include "hw/arm/msf2-soc.h"
#include "hw/misc/unimp.h"
+#include "hw/qdev-clock.h"
#include "sysemu/sysemu.h"
#define MSF2_TIMER_BASE 0x40004000
@@ -73,6 +74,8 @@ static void m2sxxx_soc_initfn(Object *obj)
}
object_initialize_child(obj, "emac", &s->emac, TYPE_MSS_EMAC);
+
+ s->m3clk = qdev_init_clock_in(DEVICE(obj), "m3clk", NULL, NULL, 0);
}
static void m2sxxx_soc_realize(DeviceState *dev_soc, Error **errp)
@@ -84,6 +87,11 @@ static void m2sxxx_soc_realize(DeviceState *dev_soc, Error **errp)
MemoryRegion *system_memory = get_system_memory();
+ if (!clock_has_source(s->m3clk)) {
+ error_setg(errp, "m3clk must be wired up by the board code");
+ return;
+ }
+
memory_region_init_rom(&s->nvm, OBJECT(dev_soc), "MSF2.eNVM", s->envm_size,
&error_fatal);
/*
@@ -106,19 +114,14 @@ static void m2sxxx_soc_realize(DeviceState *dev_soc, Error **errp)
qdev_prop_set_uint32(armv7m, "num-irq", 81);
qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type);
qdev_prop_set_bit(armv7m, "enable-bitband", true);
+ qdev_connect_clock_in(armv7m, "cpuclk", s->m3clk);
object_property_set_link(OBJECT(&s->armv7m), "memory",
OBJECT(get_system_memory()), &error_abort);
if (!sysbus_realize(SYS_BUS_DEVICE(&s->armv7m), errp)) {
return;
}
- if (!s->m3clk) {
- error_setg(errp, "Invalid m3clk value");
- error_append_hint(errp, "m3clk can not be zero\n");
- return;
- }
-
- system_clock_scale = NANOSECONDS_PER_SECOND / s->m3clk;
+ system_clock_scale = clock_ticks_to_ns(s->m3clk, 1);
for (i = 0; i < MSF2_NUM_UARTS; i++) {
if (serial_hd(i)) {
@@ -129,8 +132,13 @@ static void m2sxxx_soc_realize(DeviceState *dev_soc, Error **errp)
}
dev = DEVICE(&s->timer);
- /* APB0 clock is the timer input clock */
- qdev_prop_set_uint32(dev, "clock-frequency", s->m3clk / s->apb0div);
+ /*
+ * APB0 clock is the timer input clock.
+ * TODO: ideally the MSF2 timer device should use a Clock rather than a
+ * clock-frequency integer property.
+ */
+ qdev_prop_set_uint32(dev, "clock-frequency",
+ clock_get_hz(s->m3clk) / s->apb0div);
if (!sysbus_realize(SYS_BUS_DEVICE(&s->timer), errp)) {
return;
}
@@ -207,8 +215,6 @@ static Property m2sxxx_soc_properties[] = {
DEFINE_PROP_UINT64("eNVM-size", MSF2State, envm_size, MSF2_ENVM_MAX_SIZE),
DEFINE_PROP_UINT64("eSRAM-size", MSF2State, esram_size,
MSF2_ESRAM_MAX_SIZE),
- /* Libero GUI shows 100Mhz as default for clocks */
- DEFINE_PROP_UINT32("m3clk", MSF2State, m3clk, 100 * 1000000),
/* default divisors in Libero GUI */
DEFINE_PROP_UINT8("apb0div", MSF2State, apb0div, 2),
DEFINE_PROP_UINT8("apb1div", MSF2State, apb1div, 2),
diff --git a/hw/arm/msf2-som.c b/hw/arm/msf2-som.c
index 343ec977c07..396e8b99138 100644
--- a/hw/arm/msf2-som.c
+++ b/hw/arm/msf2-som.c
@@ -29,6 +29,7 @@
#include "hw/boards.h"
#include "hw/qdev-properties.h"
#include "hw/arm/boot.h"
+#include "hw/qdev-clock.h"
#include "exec/address-spaces.h"
#include "hw/arm/msf2-soc.h"
@@ -49,6 +50,7 @@ static void emcraft_sf2_s2s010_init(MachineState *machine)
BusState *spi_bus;
MemoryRegion *sysmem = get_system_memory();
MemoryRegion *ddr = g_new(MemoryRegion, 1);
+ Clock *m3clk;
if (strcmp(machine->cpu_type, mc->default_cpu_type) != 0) {
error_report("This board can only be used with CPU %s",
@@ -72,7 +74,10 @@ static void emcraft_sf2_s2s010_init(MachineState *machine)
* in Libero. CPU clock is divided by APB0 and APB1 divisors for
* peripherals. Emcraft's SoM kit comes with these settings by default.
*/
- qdev_prop_set_uint32(dev, "m3clk", 142 * 1000000);
+ /* This clock doesn't need migration because it is fixed-frequency */
+ m3clk = clock_new(OBJECT(machine), "m3clk");
+ clock_set_hz(m3clk, 142 * 1000000);
+ qdev_connect_clock_in(dev, "m3clk", m3clk);
qdev_prop_set_uint32(dev, "apb0div", 2);
qdev_prop_set_uint32(dev, "apb1div", 2);
--
2.20.1
^ permalink raw reply related [flat|nested] 91+ messages in thread
* [PATCH for-6.2 20/25] hw/arm/msf2-soc: Wire up refclk
2021-08-12 9:33 [PATCH for-6.2 00/25] arm: Get rid of system_clock_scale global Peter Maydell
` (18 preceding siblings ...)
2021-08-12 9:33 ` [PATCH for-6.2 19/25] hw/arm/msf2: Use Clock input to MSF2_SOC instead of m3clk property Peter Maydell
@ 2021-08-12 9:33 ` Peter Maydell
2021-08-17 15:05 ` Damien Hedde
2021-08-12 9:33 ` [PATCH for-6.2 21/25] hw/timer/armv7m_systick: Use clock inputs instead of system_clock_scale Peter Maydell
` (4 subsequent siblings)
24 siblings, 1 reply; 91+ messages in thread
From: Peter Maydell @ 2021-08-12 9:33 UTC (permalink / raw)
To: qemu-arm, qemu-devel
Cc: Damien Hedde, Luc Michel, Alistair Francis, Subbaraya Sundeep,
Joel Stanley, Alexandre Iooss
Wire up the refclk for the msf2 SoC. This SoC runs the refclk at a
frequency which is programmably either /4, /8, /16 or /32 of the main
CPU clock. We don't currently model the register which allows the
guest to set the divisor, so implement the refclk as a fixed /32 of
the CPU clock (which is the value of the divisor at reset).
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
include/hw/arm/msf2-soc.h | 1 +
hw/arm/msf2-soc.c | 23 +++++++++++++++++++++++
2 files changed, 24 insertions(+)
diff --git a/include/hw/arm/msf2-soc.h b/include/hw/arm/msf2-soc.h
index 01f904cec47..ce417a6266a 100644
--- a/include/hw/arm/msf2-soc.h
+++ b/include/hw/arm/msf2-soc.h
@@ -59,6 +59,7 @@ struct MSF2State {
uint64_t esram_size;
Clock *m3clk;
+ Clock *refclk;
uint8_t apb0div;
uint8_t apb1div;
diff --git a/hw/arm/msf2-soc.c b/hw/arm/msf2-soc.c
index 0a1e594aee6..dbc6d936a76 100644
--- a/hw/arm/msf2-soc.c
+++ b/hw/arm/msf2-soc.c
@@ -76,6 +76,7 @@ static void m2sxxx_soc_initfn(Object *obj)
object_initialize_child(obj, "emac", &s->emac, TYPE_MSS_EMAC);
s->m3clk = qdev_init_clock_in(DEVICE(obj), "m3clk", NULL, NULL, 0);
+ s->refclk = qdev_init_clock_in(DEVICE(obj), "refclk", NULL, NULL, 0);
}
static void m2sxxx_soc_realize(DeviceState *dev_soc, Error **errp)
@@ -92,6 +93,27 @@ static void m2sxxx_soc_realize(DeviceState *dev_soc, Error **errp)
return;
}
+ /*
+ * We use s->refclk internally and only define it with qdev_init_clock_in()
+ * so it is correctly parented and not leaked on an init/deinit; it is not
+ * intended as an externally exposed clock.
+ */
+ if (clock_has_source(s->refclk)) {
+ error_setg(errp, "refclk must not be wired up by the board code");
+ return;
+ }
+
+ /*
+ * TODO: ideally we should model the SoC SYSTICK_CR register at 0xe0042038,
+ * which allows the guest to program the divisor between the m3clk and
+ * the systick refclk to either /4, /8, /16 or /32, as well as setting
+ * the value the guest can read in the STCALIB register. Currently we
+ * implement the divisor as a fixed /32, which matches the reset value
+ * of SYSTICK_CR.
+ */
+ clock_set_mul_div(s->refclk, 32, 1);
+ clock_set_source(s->refclk, s->m3clk);
+
memory_region_init_rom(&s->nvm, OBJECT(dev_soc), "MSF2.eNVM", s->envm_size,
&error_fatal);
/*
@@ -115,6 +137,7 @@ static void m2sxxx_soc_realize(DeviceState *dev_soc, Error **errp)
qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type);
qdev_prop_set_bit(armv7m, "enable-bitband", true);
qdev_connect_clock_in(armv7m, "cpuclk", s->m3clk);
+ qdev_connect_clock_in(armv7m, "refclk", s->refclk);
object_property_set_link(OBJECT(&s->armv7m), "memory",
OBJECT(get_system_memory()), &error_abort);
if (!sysbus_realize(SYS_BUS_DEVICE(&s->armv7m), errp)) {
--
2.20.1
^ permalink raw reply related [flat|nested] 91+ messages in thread
* [PATCH for-6.2 21/25] hw/timer/armv7m_systick: Use clock inputs instead of system_clock_scale
2021-08-12 9:33 [PATCH for-6.2 00/25] arm: Get rid of system_clock_scale global Peter Maydell
` (19 preceding siblings ...)
2021-08-12 9:33 ` [PATCH for-6.2 20/25] hw/arm/msf2-soc: Wire up refclk Peter Maydell
@ 2021-08-12 9:33 ` Peter Maydell
2021-08-17 15:55 ` Damien Hedde
2021-08-12 9:33 ` [PATCH for-6.2 22/25] hw/arm/stellaris: Fix code style issues in GPTM code Peter Maydell
` (3 subsequent siblings)
24 siblings, 1 reply; 91+ messages in thread
From: Peter Maydell @ 2021-08-12 9:33 UTC (permalink / raw)
To: qemu-arm, qemu-devel
Cc: Damien Hedde, Luc Michel, Alistair Francis, Subbaraya Sundeep,
Joel Stanley, Alexandre Iooss
Now that all users of the systick devices wire up the clock inputs,
use those instead of the system_clock_scale and the hardwired 1MHz
value for the reference clock.
This will fix various board models where we were incorrectly
providing a 1MHz reference clock instead of some other value or
instead of providing no reference clock at all.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/timer/armv7m_systick.c | 110 ++++++++++++++++++++++++++++----------
1 file changed, 82 insertions(+), 28 deletions(-)
diff --git a/hw/timer/armv7m_systick.c b/hw/timer/armv7m_systick.c
index e43f74114e8..39cca206cfd 100644
--- a/hw/timer/armv7m_systick.c
+++ b/hw/timer/armv7m_systick.c
@@ -18,25 +18,29 @@
#include "qemu/timer.h"
#include "qemu/log.h"
#include "qemu/module.h"
+#include "qapi/error.h"
#include "trace.h"
-/* qemu timers run at 1GHz. We want something closer to 1MHz. */
-#define SYSTICK_SCALE 1000ULL
-
#define SYSTICK_ENABLE (1 << 0)
#define SYSTICK_TICKINT (1 << 1)
#define SYSTICK_CLKSOURCE (1 << 2)
#define SYSTICK_COUNTFLAG (1 << 16)
+#define SYSCALIB_NOREF (1U << 31)
+#define SYSCALIB_SKEW (1U << 30)
+
int system_clock_scale;
-/* Conversion factor from qemu timer to SysTick frequencies. */
-static inline int64_t systick_scale(SysTickState *s)
+static void systick_set_period_from_clock(SysTickState *s)
{
+ /*
+ * Set the ptimer period from whichever clock is selected.
+ * Must be called from within a ptimer transaction block.
+ */
if (s->control & SYSTICK_CLKSOURCE) {
- return system_clock_scale;
+ ptimer_set_period_from_clock(s->ptimer, s->cpuclk, 1);
} else {
- return 1000;
+ ptimer_set_period_from_clock(s->ptimer, s->refclk, 1);
}
}
@@ -83,7 +87,27 @@ static MemTxResult systick_read(void *opaque, hwaddr addr, uint64_t *data,
val = ptimer_get_count(s->ptimer);
break;
case 0xc: /* SysTick Calibration Value. */
- val = 10000;
+ /*
+ * In real hardware it is possible to make this register report
+ * a different value from what the reference clock is actually
+ * running at. We don't model that (which usually happens due
+ * to integration errors in the real hardware) and instead always
+ * report the theoretical correct value as described in the
+ * knowledgebase article at
+ * https://developer.arm.com/documentation/ka001325/latest
+ * If necessary, we could implement an extra QOM property on this
+ * device to force the STCALIB value to something different from
+ * the "correct" value.
+ */
+ if (!clock_has_source(s->refclk)) {
+ val = SYSCALIB_NOREF;
+ break;
+ }
+ val = clock_ns_to_ticks(s->refclk, 10 * SCALE_MS) - 1;
+ if (clock_ticks_to_ns(s->refclk, val + 1) != 10 * SCALE_MS) {
+ /* report that tick count does not yield exactly 10ms */
+ val |= SYSCALIB_SKEW;
+ }
break;
default:
val = 0;
@@ -115,6 +139,11 @@ static MemTxResult systick_write(void *opaque, hwaddr addr,
{
uint32_t oldval;
+ if (!clock_has_source(s->refclk)) {
+ /* This bit is always 1 if there is no external refclk */
+ value |= SYSTICK_CLKSOURCE;
+ }
+
ptimer_transaction_begin(s->ptimer);
oldval = s->control;
s->control &= 0xfffffff8;
@@ -122,19 +151,14 @@ static MemTxResult systick_write(void *opaque, hwaddr addr,
if ((oldval ^ value) & SYSTICK_ENABLE) {
if (value & SYSTICK_ENABLE) {
- /*
- * Always reload the period in case board code has
- * changed system_clock_scale. If we ever replace that
- * global with a more sensible API then we might be able
- * to set the period only when it actually changes.
- */
- ptimer_set_period(s->ptimer, systick_scale(s));
ptimer_run(s->ptimer, 0);
} else {
ptimer_stop(s->ptimer);
}
- } else if ((oldval ^ value) & SYSTICK_CLKSOURCE) {
- ptimer_set_period(s->ptimer, systick_scale(s));
+ }
+
+ if ((oldval ^ value) & SYSTICK_CLKSOURCE) {
+ systick_set_period_from_clock(s);
}
ptimer_transaction_commit(s->ptimer);
break;
@@ -177,20 +201,42 @@ static void systick_reset(DeviceState *dev)
{
SysTickState *s = SYSTICK(dev);
- /*
- * Forgetting to set system_clock_scale is always a board code
- * bug. We can't check this earlier because for some boards
- * (like stellaris) it is not yet configured at the point where
- * the systick device is realized.
- */
- assert(system_clock_scale != 0);
-
ptimer_transaction_begin(s->ptimer);
s->control = 0;
+ if (!clock_has_source(s->refclk)) {
+ /* This bit is always 1 if there is no external refclk */
+ s->control |= SYSTICK_CLKSOURCE;
+ }
ptimer_stop(s->ptimer);
ptimer_set_count(s->ptimer, 0);
ptimer_set_limit(s->ptimer, 0, 0);
- ptimer_set_period(s->ptimer, systick_scale(s));
+ systick_set_period_from_clock(s);
+ ptimer_transaction_commit(s->ptimer);
+}
+
+static void systick_cpuclk_update(void *opaque, ClockEvent event)
+{
+ SysTickState *s = SYSTICK(opaque);
+
+ if (!(s->control & SYSTICK_CLKSOURCE)) {
+ /* currently using refclk, we can ignore cpuclk changes */
+ }
+
+ ptimer_transaction_begin(s->ptimer);
+ ptimer_set_period_from_clock(s->ptimer, s->cpuclk, 1);
+ ptimer_transaction_commit(s->ptimer);
+}
+
+static void systick_refclk_update(void *opaque, ClockEvent event)
+{
+ SysTickState *s = SYSTICK(opaque);
+
+ if (s->control & SYSTICK_CLKSOURCE) {
+ /* currently using cpuclk, we can ignore refclk changes */
+ }
+
+ ptimer_transaction_begin(s->ptimer);
+ ptimer_set_period_from_clock(s->ptimer, s->refclk, 1);
ptimer_transaction_commit(s->ptimer);
}
@@ -203,8 +249,10 @@ static void systick_instance_init(Object *obj)
sysbus_init_mmio(sbd, &s->iomem);
sysbus_init_irq(sbd, &s->irq);
- s->refclk = qdev_init_clock_in(DEVICE(obj), "refclk", NULL, NULL, 0);
- s->cpuclk = qdev_init_clock_in(DEVICE(obj), "cpuclk", NULL, NULL, 0);
+ s->refclk = qdev_init_clock_in(DEVICE(obj), "refclk",
+ systick_refclk_update, s, ClockUpdate);
+ s->cpuclk = qdev_init_clock_in(DEVICE(obj), "cpuclk",
+ systick_cpuclk_update, s, ClockUpdate);
}
static void systick_realize(DeviceState *dev, Error **errp)
@@ -215,6 +263,12 @@ static void systick_realize(DeviceState *dev, Error **errp)
PTIMER_POLICY_NO_COUNTER_ROUND_DOWN |
PTIMER_POLICY_NO_IMMEDIATE_RELOAD |
PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT);
+
+ if (!clock_has_source(s->cpuclk)) {
+ error_setg(errp, "systick: cpuclk must be connected");
+ return;
+ }
+ /* It's OK not to connect the refclk */
}
static const VMStateDescription vmstate_systick = {
--
2.20.1
^ permalink raw reply related [flat|nested] 91+ messages in thread
* [PATCH for-6.2 22/25] hw/arm/stellaris: Fix code style issues in GPTM code
2021-08-12 9:33 [PATCH for-6.2 00/25] arm: Get rid of system_clock_scale global Peter Maydell
` (20 preceding siblings ...)
2021-08-12 9:33 ` [PATCH for-6.2 21/25] hw/timer/armv7m_systick: Use clock inputs instead of system_clock_scale Peter Maydell
@ 2021-08-12 9:33 ` Peter Maydell
2021-08-14 9:26 ` Alexandre IOOSS
2021-08-12 9:33 ` [PATCH for-6.2 23/25] hw/arm/stellaris: Split stellaris-gptm into its own file Peter Maydell
` (2 subsequent siblings)
24 siblings, 1 reply; 91+ messages in thread
From: Peter Maydell @ 2021-08-12 9:33 UTC (permalink / raw)
To: qemu-arm, qemu-devel
Cc: Damien Hedde, Luc Michel, Alistair Francis, Subbaraya Sundeep,
Joel Stanley, Alexandre Iooss
Fix the code style issues in the Stellaris general purpose timer
module code, so that when we move it to a different file in a
following patch checkpatch doesn't complain.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/arm/stellaris.c | 13 ++++++++-----
1 file changed, 8 insertions(+), 5 deletions(-)
diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
index 8c8bd39e2fe..a32c567ce11 100644
--- a/hw/arm/stellaris.c
+++ b/hw/arm/stellaris.c
@@ -97,10 +97,11 @@ static void gptm_stop(gptm_state *s, int n)
static void gptm_reload(gptm_state *s, int n, int reset)
{
int64_t tick;
- if (reset)
+ if (reset) {
tick = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
- else
+ } else {
tick = s->tick[n];
+ }
if (s->config == 0) {
/* 32-bit CountDown. */
@@ -227,9 +228,11 @@ static void gptm_write(void *opaque, hwaddr offset,
gptm_state *s = (gptm_state *)opaque;
uint32_t oldval;
- /* The timers should be disabled before changing the configuration.
- We take advantage of this and defer everything until the timer
- is enabled. */
+ /*
+ * The timers should be disabled before changing the configuration.
+ * We take advantage of this and defer everything until the timer
+ * is enabled.
+ */
switch (offset) {
case 0x00: /* CFG */
s->config = value;
--
2.20.1
^ permalink raw reply related [flat|nested] 91+ messages in thread
* [PATCH for-6.2 23/25] hw/arm/stellaris: Split stellaris-gptm into its own file
2021-08-12 9:33 [PATCH for-6.2 00/25] arm: Get rid of system_clock_scale global Peter Maydell
` (21 preceding siblings ...)
2021-08-12 9:33 ` [PATCH for-6.2 22/25] hw/arm/stellaris: Fix code style issues in GPTM code Peter Maydell
@ 2021-08-12 9:33 ` Peter Maydell
2021-08-17 15:59 ` Damien Hedde
2021-08-12 9:33 ` [PATCH for-6.2 24/25] hw/timer/stellaris-gptm: Use Clock input instead of system_clock_scale Peter Maydell
2021-08-12 9:33 ` [PATCH for-6.2 25/25] arm: Remove system_clock_scale global Peter Maydell
24 siblings, 1 reply; 91+ messages in thread
From: Peter Maydell @ 2021-08-12 9:33 UTC (permalink / raw)
To: qemu-arm, qemu-devel
Cc: Damien Hedde, Luc Michel, Alistair Francis, Subbaraya Sundeep,
Joel Stanley, Alexandre Iooss
The implementation of the Stellaris general purpose timer module
device stellaris-gptm is currently in the same source file as the
board model. Split it out into its own source file in hw/timer.
Apart from the new file comment headers and the Kconfig and
meson.build changes, this is just code movement.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
include/hw/timer/stellaris-gptm.h | 48 +++++
hw/arm/stellaris.c | 321 +-----------------------------
hw/timer/stellaris-gptm.c | 314 +++++++++++++++++++++++++++++
hw/arm/Kconfig | 1 +
hw/timer/Kconfig | 3 +
hw/timer/meson.build | 1 +
6 files changed, 368 insertions(+), 320 deletions(-)
create mode 100644 include/hw/timer/stellaris-gptm.h
create mode 100644 hw/timer/stellaris-gptm.c
diff --git a/include/hw/timer/stellaris-gptm.h b/include/hw/timer/stellaris-gptm.h
new file mode 100644
index 00000000000..b8fa43c94bf
--- /dev/null
+++ b/include/hw/timer/stellaris-gptm.h
@@ -0,0 +1,48 @@
+/*
+ * Luminary Micro Stellaris General Purpose Timer Module
+ *
+ * Copyright (c) 2006 CodeSourcery.
+ * Written by Paul Brook
+ *
+ * This code is licensed under the GPL.
+ */
+
+#ifndef HW_TIMER_STELLARIS_GPTM_H
+#define HW_TIMER_STELLARIS_GPTM_H
+
+#include "qom/object.h"
+#include "hw/sysbus.h"
+#include "hw/irq.h"
+
+#define TYPE_STELLARIS_GPTM "stellaris-gptm"
+OBJECT_DECLARE_SIMPLE_TYPE(gptm_state, STELLARIS_GPTM)
+
+/*
+ * QEMU interface:
+ * + sysbus MMIO region 0: register bank
+ * + sysbus IRQ 0: timer interrupt
+ * + unnamed GPIO output 0: trigger output for the ADC
+ */
+struct gptm_state {
+ SysBusDevice parent_obj;
+
+ MemoryRegion iomem;
+ uint32_t config;
+ uint32_t mode[2];
+ uint32_t control;
+ uint32_t state;
+ uint32_t mask;
+ uint32_t load[2];
+ uint32_t match[2];
+ uint32_t prescale[2];
+ uint32_t match_prescale[2];
+ uint32_t rtc;
+ int64_t tick[2];
+ struct gptm_state *opaque[2];
+ QEMUTimer *timer[2];
+ /* The timers have an alternate output used to trigger the ADC. */
+ qemu_irq trigger;
+ qemu_irq irq;
+};
+
+#endif
diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
index a32c567ce11..8c547f146a9 100644
--- a/hw/arm/stellaris.c
+++ b/hw/arm/stellaris.c
@@ -26,6 +26,7 @@
#include "hw/watchdog/cmsdk-apb-watchdog.h"
#include "migration/vmstate.h"
#include "hw/misc/unimp.h"
+#include "hw/timer/stellaris-gptm.h"
#include "hw/qdev-clock.h"
#include "qom/object.h"
@@ -55,309 +56,6 @@ typedef const struct {
uint32_t peripherals;
} stellaris_board_info;
-/* General purpose timer module. */
-
-#define TYPE_STELLARIS_GPTM "stellaris-gptm"
-OBJECT_DECLARE_SIMPLE_TYPE(gptm_state, STELLARIS_GPTM)
-
-struct gptm_state {
- SysBusDevice parent_obj;
-
- MemoryRegion iomem;
- uint32_t config;
- uint32_t mode[2];
- uint32_t control;
- uint32_t state;
- uint32_t mask;
- uint32_t load[2];
- uint32_t match[2];
- uint32_t prescale[2];
- uint32_t match_prescale[2];
- uint32_t rtc;
- int64_t tick[2];
- struct gptm_state *opaque[2];
- QEMUTimer *timer[2];
- /* The timers have an alternate output used to trigger the ADC. */
- qemu_irq trigger;
- qemu_irq irq;
-};
-
-static void gptm_update_irq(gptm_state *s)
-{
- int level;
- level = (s->state & s->mask) != 0;
- qemu_set_irq(s->irq, level);
-}
-
-static void gptm_stop(gptm_state *s, int n)
-{
- timer_del(s->timer[n]);
-}
-
-static void gptm_reload(gptm_state *s, int n, int reset)
-{
- int64_t tick;
- if (reset) {
- tick = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
- } else {
- tick = s->tick[n];
- }
-
- if (s->config == 0) {
- /* 32-bit CountDown. */
- uint32_t count;
- count = s->load[0] | (s->load[1] << 16);
- tick += (int64_t)count * system_clock_scale;
- } else if (s->config == 1) {
- /* 32-bit RTC. 1Hz tick. */
- tick += NANOSECONDS_PER_SECOND;
- } else if (s->mode[n] == 0xa) {
- /* PWM mode. Not implemented. */
- } else {
- qemu_log_mask(LOG_UNIMP,
- "GPTM: 16-bit timer mode unimplemented: 0x%x\n",
- s->mode[n]);
- return;
- }
- s->tick[n] = tick;
- timer_mod(s->timer[n], tick);
-}
-
-static void gptm_tick(void *opaque)
-{
- gptm_state **p = (gptm_state **)opaque;
- gptm_state *s;
- int n;
-
- s = *p;
- n = p - s->opaque;
- if (s->config == 0) {
- s->state |= 1;
- if ((s->control & 0x20)) {
- /* Output trigger. */
- qemu_irq_pulse(s->trigger);
- }
- if (s->mode[0] & 1) {
- /* One-shot. */
- s->control &= ~1;
- } else {
- /* Periodic. */
- gptm_reload(s, 0, 0);
- }
- } else if (s->config == 1) {
- /* RTC. */
- uint32_t match;
- s->rtc++;
- match = s->match[0] | (s->match[1] << 16);
- if (s->rtc > match)
- s->rtc = 0;
- if (s->rtc == 0) {
- s->state |= 8;
- }
- gptm_reload(s, 0, 0);
- } else if (s->mode[n] == 0xa) {
- /* PWM mode. Not implemented. */
- } else {
- qemu_log_mask(LOG_UNIMP,
- "GPTM: 16-bit timer mode unimplemented: 0x%x\n",
- s->mode[n]);
- }
- gptm_update_irq(s);
-}
-
-static uint64_t gptm_read(void *opaque, hwaddr offset,
- unsigned size)
-{
- gptm_state *s = (gptm_state *)opaque;
-
- switch (offset) {
- case 0x00: /* CFG */
- return s->config;
- case 0x04: /* TAMR */
- return s->mode[0];
- case 0x08: /* TBMR */
- return s->mode[1];
- case 0x0c: /* CTL */
- return s->control;
- case 0x18: /* IMR */
- return s->mask;
- case 0x1c: /* RIS */
- return s->state;
- case 0x20: /* MIS */
- return s->state & s->mask;
- case 0x24: /* CR */
- return 0;
- case 0x28: /* TAILR */
- return s->load[0] | ((s->config < 4) ? (s->load[1] << 16) : 0);
- case 0x2c: /* TBILR */
- return s->load[1];
- case 0x30: /* TAMARCHR */
- return s->match[0] | ((s->config < 4) ? (s->match[1] << 16) : 0);
- case 0x34: /* TBMATCHR */
- return s->match[1];
- case 0x38: /* TAPR */
- return s->prescale[0];
- case 0x3c: /* TBPR */
- return s->prescale[1];
- case 0x40: /* TAPMR */
- return s->match_prescale[0];
- case 0x44: /* TBPMR */
- return s->match_prescale[1];
- case 0x48: /* TAR */
- if (s->config == 1) {
- return s->rtc;
- }
- qemu_log_mask(LOG_UNIMP,
- "GPTM: read of TAR but timer read not supported\n");
- return 0;
- case 0x4c: /* TBR */
- qemu_log_mask(LOG_UNIMP,
- "GPTM: read of TBR but timer read not supported\n");
- return 0;
- default:
- qemu_log_mask(LOG_GUEST_ERROR,
- "GPTM: read at bad offset 0x02%" HWADDR_PRIx "\n",
- offset);
- return 0;
- }
-}
-
-static void gptm_write(void *opaque, hwaddr offset,
- uint64_t value, unsigned size)
-{
- gptm_state *s = (gptm_state *)opaque;
- uint32_t oldval;
-
- /*
- * The timers should be disabled before changing the configuration.
- * We take advantage of this and defer everything until the timer
- * is enabled.
- */
- switch (offset) {
- case 0x00: /* CFG */
- s->config = value;
- break;
- case 0x04: /* TAMR */
- s->mode[0] = value;
- break;
- case 0x08: /* TBMR */
- s->mode[1] = value;
- break;
- case 0x0c: /* CTL */
- oldval = s->control;
- s->control = value;
- /* TODO: Implement pause. */
- if ((oldval ^ value) & 1) {
- if (value & 1) {
- gptm_reload(s, 0, 1);
- } else {
- gptm_stop(s, 0);
- }
- }
- if (((oldval ^ value) & 0x100) && s->config >= 4) {
- if (value & 0x100) {
- gptm_reload(s, 1, 1);
- } else {
- gptm_stop(s, 1);
- }
- }
- break;
- case 0x18: /* IMR */
- s->mask = value & 0x77;
- gptm_update_irq(s);
- break;
- case 0x24: /* CR */
- s->state &= ~value;
- break;
- case 0x28: /* TAILR */
- s->load[0] = value & 0xffff;
- if (s->config < 4) {
- s->load[1] = value >> 16;
- }
- break;
- case 0x2c: /* TBILR */
- s->load[1] = value & 0xffff;
- break;
- case 0x30: /* TAMARCHR */
- s->match[0] = value & 0xffff;
- if (s->config < 4) {
- s->match[1] = value >> 16;
- }
- break;
- case 0x34: /* TBMATCHR */
- s->match[1] = value >> 16;
- break;
- case 0x38: /* TAPR */
- s->prescale[0] = value;
- break;
- case 0x3c: /* TBPR */
- s->prescale[1] = value;
- break;
- case 0x40: /* TAPMR */
- s->match_prescale[0] = value;
- break;
- case 0x44: /* TBPMR */
- s->match_prescale[0] = value;
- break;
- default:
- qemu_log_mask(LOG_GUEST_ERROR,
- "GPTM: write at bad offset 0x02%" HWADDR_PRIx "\n",
- offset);
- }
- gptm_update_irq(s);
-}
-
-static const MemoryRegionOps gptm_ops = {
- .read = gptm_read,
- .write = gptm_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
-};
-
-static const VMStateDescription vmstate_stellaris_gptm = {
- .name = "stellaris_gptm",
- .version_id = 1,
- .minimum_version_id = 1,
- .fields = (VMStateField[]) {
- VMSTATE_UINT32(config, gptm_state),
- VMSTATE_UINT32_ARRAY(mode, gptm_state, 2),
- VMSTATE_UINT32(control, gptm_state),
- VMSTATE_UINT32(state, gptm_state),
- VMSTATE_UINT32(mask, gptm_state),
- VMSTATE_UNUSED(8),
- VMSTATE_UINT32_ARRAY(load, gptm_state, 2),
- VMSTATE_UINT32_ARRAY(match, gptm_state, 2),
- VMSTATE_UINT32_ARRAY(prescale, gptm_state, 2),
- VMSTATE_UINT32_ARRAY(match_prescale, gptm_state, 2),
- VMSTATE_UINT32(rtc, gptm_state),
- VMSTATE_INT64_ARRAY(tick, gptm_state, 2),
- VMSTATE_TIMER_PTR_ARRAY(timer, gptm_state, 2),
- VMSTATE_END_OF_LIST()
- }
-};
-
-static void stellaris_gptm_init(Object *obj)
-{
- DeviceState *dev = DEVICE(obj);
- gptm_state *s = STELLARIS_GPTM(obj);
- SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
-
- sysbus_init_irq(sbd, &s->irq);
- qdev_init_gpio_out(dev, &s->trigger, 1);
-
- memory_region_init_io(&s->iomem, obj, &gptm_ops, s,
- "gptm", 0x1000);
- sysbus_init_mmio(sbd, &s->iomem);
-
- s->opaque[0] = s->opaque[1] = s;
-}
-
-static void stellaris_gptm_realize(DeviceState *dev, Error **errp)
-{
- gptm_state *s = STELLARIS_GPTM(dev);
- s->timer[0] = timer_new_ns(QEMU_CLOCK_VIRTUAL, gptm_tick, &s->opaque[0]);
- s->timer[1] = timer_new_ns(QEMU_CLOCK_VIRTUAL, gptm_tick, &s->opaque[1]);
-}
-
/* System controller. */
#define TYPE_STELLARIS_SYS "stellaris-sys"
@@ -1642,22 +1340,6 @@ static const TypeInfo stellaris_i2c_info = {
.class_init = stellaris_i2c_class_init,
};
-static void stellaris_gptm_class_init(ObjectClass *klass, void *data)
-{
- DeviceClass *dc = DEVICE_CLASS(klass);
-
- dc->vmsd = &vmstate_stellaris_gptm;
- dc->realize = stellaris_gptm_realize;
-}
-
-static const TypeInfo stellaris_gptm_info = {
- .name = TYPE_STELLARIS_GPTM,
- .parent = TYPE_SYS_BUS_DEVICE,
- .instance_size = sizeof(gptm_state),
- .instance_init = stellaris_gptm_init,
- .class_init = stellaris_gptm_class_init,
-};
-
static void stellaris_adc_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
@@ -1696,7 +1378,6 @@ static const TypeInfo stellaris_sys_info = {
static void stellaris_register_types(void)
{
type_register_static(&stellaris_i2c_info);
- type_register_static(&stellaris_gptm_info);
type_register_static(&stellaris_adc_info);
type_register_static(&stellaris_sys_info);
}
diff --git a/hw/timer/stellaris-gptm.c b/hw/timer/stellaris-gptm.c
new file mode 100644
index 00000000000..7846fe5f84e
--- /dev/null
+++ b/hw/timer/stellaris-gptm.c
@@ -0,0 +1,314 @@
+/*
+ * Luminary Micro Stellaris General Purpose Timer Module
+ *
+ * Copyright (c) 2006 CodeSourcery.
+ * Written by Paul Brook
+ *
+ * This code is licensed under the GPL.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/log.h"
+#include "qemu/timer.h"
+#include "migration/vmstate.h"
+#include "hw/timer/stellaris-gptm.h"
+#include "hw/timer/armv7m_systick.h" /* Needed only for system_clock_scale */
+
+static void gptm_update_irq(gptm_state *s)
+{
+ int level;
+ level = (s->state & s->mask) != 0;
+ qemu_set_irq(s->irq, level);
+}
+
+static void gptm_stop(gptm_state *s, int n)
+{
+ timer_del(s->timer[n]);
+}
+
+static void gptm_reload(gptm_state *s, int n, int reset)
+{
+ int64_t tick;
+ if (reset) {
+ tick = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
+ } else {
+ tick = s->tick[n];
+ }
+
+ if (s->config == 0) {
+ /* 32-bit CountDown. */
+ uint32_t count;
+ count = s->load[0] | (s->load[1] << 16);
+ tick += (int64_t)count * system_clock_scale;
+ } else if (s->config == 1) {
+ /* 32-bit RTC. 1Hz tick. */
+ tick += NANOSECONDS_PER_SECOND;
+ } else if (s->mode[n] == 0xa) {
+ /* PWM mode. Not implemented. */
+ } else {
+ qemu_log_mask(LOG_UNIMP,
+ "GPTM: 16-bit timer mode unimplemented: 0x%x\n",
+ s->mode[n]);
+ return;
+ }
+ s->tick[n] = tick;
+ timer_mod(s->timer[n], tick);
+}
+
+static void gptm_tick(void *opaque)
+{
+ gptm_state **p = (gptm_state **)opaque;
+ gptm_state *s;
+ int n;
+
+ s = *p;
+ n = p - s->opaque;
+ if (s->config == 0) {
+ s->state |= 1;
+ if ((s->control & 0x20)) {
+ /* Output trigger. */
+ qemu_irq_pulse(s->trigger);
+ }
+ if (s->mode[0] & 1) {
+ /* One-shot. */
+ s->control &= ~1;
+ } else {
+ /* Periodic. */
+ gptm_reload(s, 0, 0);
+ }
+ } else if (s->config == 1) {
+ /* RTC. */
+ uint32_t match;
+ s->rtc++;
+ match = s->match[0] | (s->match[1] << 16);
+ if (s->rtc > match)
+ s->rtc = 0;
+ if (s->rtc == 0) {
+ s->state |= 8;
+ }
+ gptm_reload(s, 0, 0);
+ } else if (s->mode[n] == 0xa) {
+ /* PWM mode. Not implemented. */
+ } else {
+ qemu_log_mask(LOG_UNIMP,
+ "GPTM: 16-bit timer mode unimplemented: 0x%x\n",
+ s->mode[n]);
+ }
+ gptm_update_irq(s);
+}
+
+static uint64_t gptm_read(void *opaque, hwaddr offset,
+ unsigned size)
+{
+ gptm_state *s = (gptm_state *)opaque;
+
+ switch (offset) {
+ case 0x00: /* CFG */
+ return s->config;
+ case 0x04: /* TAMR */
+ return s->mode[0];
+ case 0x08: /* TBMR */
+ return s->mode[1];
+ case 0x0c: /* CTL */
+ return s->control;
+ case 0x18: /* IMR */
+ return s->mask;
+ case 0x1c: /* RIS */
+ return s->state;
+ case 0x20: /* MIS */
+ return s->state & s->mask;
+ case 0x24: /* CR */
+ return 0;
+ case 0x28: /* TAILR */
+ return s->load[0] | ((s->config < 4) ? (s->load[1] << 16) : 0);
+ case 0x2c: /* TBILR */
+ return s->load[1];
+ case 0x30: /* TAMARCHR */
+ return s->match[0] | ((s->config < 4) ? (s->match[1] << 16) : 0);
+ case 0x34: /* TBMATCHR */
+ return s->match[1];
+ case 0x38: /* TAPR */
+ return s->prescale[0];
+ case 0x3c: /* TBPR */
+ return s->prescale[1];
+ case 0x40: /* TAPMR */
+ return s->match_prescale[0];
+ case 0x44: /* TBPMR */
+ return s->match_prescale[1];
+ case 0x48: /* TAR */
+ if (s->config == 1) {
+ return s->rtc;
+ }
+ qemu_log_mask(LOG_UNIMP,
+ "GPTM: read of TAR but timer read not supported\n");
+ return 0;
+ case 0x4c: /* TBR */
+ qemu_log_mask(LOG_UNIMP,
+ "GPTM: read of TBR but timer read not supported\n");
+ return 0;
+ default:
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "GPTM: read at bad offset 0x02%" HWADDR_PRIx "\n",
+ offset);
+ return 0;
+ }
+}
+
+static void gptm_write(void *opaque, hwaddr offset,
+ uint64_t value, unsigned size)
+{
+ gptm_state *s = (gptm_state *)opaque;
+ uint32_t oldval;
+
+ /*
+ * The timers should be disabled before changing the configuration.
+ * We take advantage of this and defer everything until the timer
+ * is enabled.
+ */
+ switch (offset) {
+ case 0x00: /* CFG */
+ s->config = value;
+ break;
+ case 0x04: /* TAMR */
+ s->mode[0] = value;
+ break;
+ case 0x08: /* TBMR */
+ s->mode[1] = value;
+ break;
+ case 0x0c: /* CTL */
+ oldval = s->control;
+ s->control = value;
+ /* TODO: Implement pause. */
+ if ((oldval ^ value) & 1) {
+ if (value & 1) {
+ gptm_reload(s, 0, 1);
+ } else {
+ gptm_stop(s, 0);
+ }
+ }
+ if (((oldval ^ value) & 0x100) && s->config >= 4) {
+ if (value & 0x100) {
+ gptm_reload(s, 1, 1);
+ } else {
+ gptm_stop(s, 1);
+ }
+ }
+ break;
+ case 0x18: /* IMR */
+ s->mask = value & 0x77;
+ gptm_update_irq(s);
+ break;
+ case 0x24: /* CR */
+ s->state &= ~value;
+ break;
+ case 0x28: /* TAILR */
+ s->load[0] = value & 0xffff;
+ if (s->config < 4) {
+ s->load[1] = value >> 16;
+ }
+ break;
+ case 0x2c: /* TBILR */
+ s->load[1] = value & 0xffff;
+ break;
+ case 0x30: /* TAMARCHR */
+ s->match[0] = value & 0xffff;
+ if (s->config < 4) {
+ s->match[1] = value >> 16;
+ }
+ break;
+ case 0x34: /* TBMATCHR */
+ s->match[1] = value >> 16;
+ break;
+ case 0x38: /* TAPR */
+ s->prescale[0] = value;
+ break;
+ case 0x3c: /* TBPR */
+ s->prescale[1] = value;
+ break;
+ case 0x40: /* TAPMR */
+ s->match_prescale[0] = value;
+ break;
+ case 0x44: /* TBPMR */
+ s->match_prescale[0] = value;
+ break;
+ default:
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "GPTM: write at bad offset 0x02%" HWADDR_PRIx "\n",
+ offset);
+ }
+ gptm_update_irq(s);
+}
+
+static const MemoryRegionOps gptm_ops = {
+ .read = gptm_read,
+ .write = gptm_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+};
+
+static const VMStateDescription vmstate_stellaris_gptm = {
+ .name = "stellaris_gptm",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT32(config, gptm_state),
+ VMSTATE_UINT32_ARRAY(mode, gptm_state, 2),
+ VMSTATE_UINT32(control, gptm_state),
+ VMSTATE_UINT32(state, gptm_state),
+ VMSTATE_UINT32(mask, gptm_state),
+ VMSTATE_UNUSED(8),
+ VMSTATE_UINT32_ARRAY(load, gptm_state, 2),
+ VMSTATE_UINT32_ARRAY(match, gptm_state, 2),
+ VMSTATE_UINT32_ARRAY(prescale, gptm_state, 2),
+ VMSTATE_UINT32_ARRAY(match_prescale, gptm_state, 2),
+ VMSTATE_UINT32(rtc, gptm_state),
+ VMSTATE_INT64_ARRAY(tick, gptm_state, 2),
+ VMSTATE_TIMER_PTR_ARRAY(timer, gptm_state, 2),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static void stellaris_gptm_init(Object *obj)
+{
+ DeviceState *dev = DEVICE(obj);
+ gptm_state *s = STELLARIS_GPTM(obj);
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
+
+ sysbus_init_irq(sbd, &s->irq);
+ qdev_init_gpio_out(dev, &s->trigger, 1);
+
+ memory_region_init_io(&s->iomem, obj, &gptm_ops, s,
+ "gptm", 0x1000);
+ sysbus_init_mmio(sbd, &s->iomem);
+
+ s->opaque[0] = s->opaque[1] = s;
+}
+
+static void stellaris_gptm_realize(DeviceState *dev, Error **errp)
+{
+ gptm_state *s = STELLARIS_GPTM(dev);
+ s->timer[0] = timer_new_ns(QEMU_CLOCK_VIRTUAL, gptm_tick, &s->opaque[0]);
+ s->timer[1] = timer_new_ns(QEMU_CLOCK_VIRTUAL, gptm_tick, &s->opaque[1]);
+}
+
+static void stellaris_gptm_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->vmsd = &vmstate_stellaris_gptm;
+ dc->realize = stellaris_gptm_realize;
+}
+
+static const TypeInfo stellaris_gptm_info = {
+ .name = TYPE_STELLARIS_GPTM,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(gptm_state),
+ .instance_init = stellaris_gptm_init,
+ .class_init = stellaris_gptm_class_init,
+};
+
+static void stellaris_gptm_register_types(void)
+{
+ type_register_static(&stellaris_gptm_info);
+}
+
+type_init(stellaris_gptm_register_types)
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index 4ba0aca0676..a261b6f13bd 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -237,6 +237,7 @@ config STELLARIS
select SSI_SD
select STELLARIS_INPUT
select STELLARIS_ENET # ethernet
+ select STELLARIS_GPTM # general purpose timer module
select UNIMP
config STM32VLDISCOVERY
diff --git a/hw/timer/Kconfig b/hw/timer/Kconfig
index bac25117155..1e73da7e120 100644
--- a/hw/timer/Kconfig
+++ b/hw/timer/Kconfig
@@ -52,5 +52,8 @@ config SSE_COUNTER
config SSE_TIMER
bool
+config STELLARIS_GPTM
+ bool
+
config AVR_TIMER16
bool
diff --git a/hw/timer/meson.build b/hw/timer/meson.build
index 1aa3cd22844..e67478a8f10 100644
--- a/hw/timer/meson.build
+++ b/hw/timer/meson.build
@@ -31,6 +31,7 @@ softmmu_ss.add(when: 'CONFIG_SH_TIMER', if_true: files('sh_timer.c'))
softmmu_ss.add(when: 'CONFIG_SLAVIO', if_true: files('slavio_timer.c'))
softmmu_ss.add(when: 'CONFIG_SSE_COUNTER', if_true: files('sse-counter.c'))
softmmu_ss.add(when: 'CONFIG_SSE_TIMER', if_true: files('sse-timer.c'))
+softmmu_ss.add(when: 'CONFIG_STELLARIS_GPTM', if_true: files('stellaris-gptm.c'))
softmmu_ss.add(when: 'CONFIG_STM32F2XX_TIMER', if_true: files('stm32f2xx_timer.c'))
softmmu_ss.add(when: 'CONFIG_XILINX', if_true: files('xilinx_timer.c'))
specific_ss.add(when: 'CONFIG_IBEX', if_true: files('ibex_timer.c'))
--
2.20.1
^ permalink raw reply related [flat|nested] 91+ messages in thread
* [PATCH for-6.2 24/25] hw/timer/stellaris-gptm: Use Clock input instead of system_clock_scale
2021-08-12 9:33 [PATCH for-6.2 00/25] arm: Get rid of system_clock_scale global Peter Maydell
` (22 preceding siblings ...)
2021-08-12 9:33 ` [PATCH for-6.2 23/25] hw/arm/stellaris: Split stellaris-gptm into its own file Peter Maydell
@ 2021-08-12 9:33 ` Peter Maydell
2021-08-18 12:03 ` Damien Hedde
2021-08-12 9:33 ` [PATCH for-6.2 25/25] arm: Remove system_clock_scale global Peter Maydell
24 siblings, 1 reply; 91+ messages in thread
From: Peter Maydell @ 2021-08-12 9:33 UTC (permalink / raw)
To: qemu-arm, qemu-devel
Cc: Damien Hedde, Luc Michel, Alistair Francis, Subbaraya Sundeep,
Joel Stanley, Alexandre Iooss
The stellaris-gptm timer currently uses system_clock_scale for one of
its timer modes where the timer runs at the CPU clock rate. Make it
use a Clock input instead.
We don't try to make the timer handle changes in the clock frequency
while the downcounter is running. This is not a change in behaviour
from the previous system_clock_scale implementation -- we will pick
up the new frequency only when the downcounter hits zero. Handling
dynamic clock changes when the counter is running would require state
that the current gptm implementation doesn't have.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
As noted in the comment, ideally we would convert the device to use
ptimer for its downcounter, which supports frequency changes while
the counter is running and would also allow reading the timer value.
But I don't want to make and test that change to a minor timer device
in a board model I wouldn't recommend anybody actually use; this
series is long enough as it is...
---
include/hw/timer/stellaris-gptm.h | 3 +++
hw/arm/stellaris.c | 12 +++++++++---
hw/timer/stellaris-gptm.c | 26 ++++++++++++++++++++++----
3 files changed, 34 insertions(+), 7 deletions(-)
diff --git a/include/hw/timer/stellaris-gptm.h b/include/hw/timer/stellaris-gptm.h
index b8fa43c94bf..fde1fc6f0c7 100644
--- a/include/hw/timer/stellaris-gptm.h
+++ b/include/hw/timer/stellaris-gptm.h
@@ -13,6 +13,7 @@
#include "qom/object.h"
#include "hw/sysbus.h"
#include "hw/irq.h"
+#include "hw/clock.h"
#define TYPE_STELLARIS_GPTM "stellaris-gptm"
OBJECT_DECLARE_SIMPLE_TYPE(gptm_state, STELLARIS_GPTM)
@@ -22,6 +23,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(gptm_state, STELLARIS_GPTM)
* + sysbus MMIO region 0: register bank
* + sysbus IRQ 0: timer interrupt
* + unnamed GPIO output 0: trigger output for the ADC
+ * + Clock input "clk": the 32-bit countdown timer runs at this speed
*/
struct gptm_state {
SysBusDevice parent_obj;
@@ -43,6 +45,7 @@ struct gptm_state {
/* The timers have an alternate output used to trigger the ADC. */
qemu_irq trigger;
qemu_irq irq;
+ Clock *clk;
};
#endif
diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
index 8c547f146a9..3e7d1dabad1 100644
--- a/hw/arm/stellaris.c
+++ b/hw/arm/stellaris.c
@@ -1090,9 +1090,15 @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
}
for (i = 0; i < 4; i++) {
if (board->dc2 & (0x10000 << i)) {
- dev = sysbus_create_simple(TYPE_STELLARIS_GPTM,
- 0x40030000 + i * 0x1000,
- qdev_get_gpio_in(nvic, timer_irq[i]));
+ SysBusDevice *sbd;
+
+ dev = qdev_new(TYPE_STELLARIS_GPTM);
+ sbd = SYS_BUS_DEVICE(dev);
+ qdev_connect_clock_in(dev, "clk",
+ qdev_get_clock_out(ssys_dev, "SYSCLK"));
+ sysbus_realize_and_unref(sbd, &error_fatal);
+ sysbus_mmio_map(sbd, 0, 0x40030000 + i * 0x1000);
+ sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(nvic, timer_irq[i]));
/* TODO: This is incorrect, but we get away with it because
the ADC output is only ever pulsed. */
qdev_connect_gpio_out(dev, 0, adc);
diff --git a/hw/timer/stellaris-gptm.c b/hw/timer/stellaris-gptm.c
index 7846fe5f84e..fd71c79be48 100644
--- a/hw/timer/stellaris-gptm.c
+++ b/hw/timer/stellaris-gptm.c
@@ -10,9 +10,10 @@
#include "qemu/osdep.h"
#include "qemu/log.h"
#include "qemu/timer.h"
+#include "qapi/error.h"
#include "migration/vmstate.h"
+#include "hw/qdev-clock.h"
#include "hw/timer/stellaris-gptm.h"
-#include "hw/timer/armv7m_systick.h" /* Needed only for system_clock_scale */
static void gptm_update_irq(gptm_state *s)
{
@@ -39,7 +40,7 @@ static void gptm_reload(gptm_state *s, int n, int reset)
/* 32-bit CountDown. */
uint32_t count;
count = s->load[0] | (s->load[1] << 16);
- tick += (int64_t)count * system_clock_scale;
+ tick += clock_ticks_to_ns(s->clk, count);
} else if (s->config == 1) {
/* 32-bit RTC. 1Hz tick. */
tick += NANOSECONDS_PER_SECOND;
@@ -247,8 +248,8 @@ static const MemoryRegionOps gptm_ops = {
static const VMStateDescription vmstate_stellaris_gptm = {
.name = "stellaris_gptm",
- .version_id = 1,
- .minimum_version_id = 1,
+ .version_id = 2,
+ .minimum_version_id = 2,
.fields = (VMStateField[]) {
VMSTATE_UINT32(config, gptm_state),
VMSTATE_UINT32_ARRAY(mode, gptm_state, 2),
@@ -263,6 +264,7 @@ static const VMStateDescription vmstate_stellaris_gptm = {
VMSTATE_UINT32(rtc, gptm_state),
VMSTATE_INT64_ARRAY(tick, gptm_state, 2),
VMSTATE_TIMER_PTR_ARRAY(timer, gptm_state, 2),
+ VMSTATE_CLOCK(clk, gptm_state),
VMSTATE_END_OF_LIST()
}
};
@@ -281,11 +283,27 @@ static void stellaris_gptm_init(Object *obj)
sysbus_init_mmio(sbd, &s->iomem);
s->opaque[0] = s->opaque[1] = s;
+
+ /*
+ * TODO: in an ideal world we would model the effects of changing
+ * the input clock frequency while the countdown timer is active.
+ * The best way to do this would be to convert the device to use
+ * ptimer instead of hand-rolling its own timer. This would also
+ * make it easy to implement reading the current count from the
+ * TAR and TBR registers.
+ */
+ s->clk = qdev_init_clock_in(dev, "clk", NULL, NULL, 0);
}
static void stellaris_gptm_realize(DeviceState *dev, Error **errp)
{
gptm_state *s = STELLARIS_GPTM(dev);
+
+ if (!clock_has_source(s->clk)) {
+ error_setg(errp, "stellaris-gptm: clk must be connected");
+ return;
+ }
+
s->timer[0] = timer_new_ns(QEMU_CLOCK_VIRTUAL, gptm_tick, &s->opaque[0]);
s->timer[1] = timer_new_ns(QEMU_CLOCK_VIRTUAL, gptm_tick, &s->opaque[1]);
}
--
2.20.1
^ permalink raw reply related [flat|nested] 91+ messages in thread
* [PATCH for-6.2 25/25] arm: Remove system_clock_scale global
2021-08-12 9:33 [PATCH for-6.2 00/25] arm: Get rid of system_clock_scale global Peter Maydell
` (23 preceding siblings ...)
2021-08-12 9:33 ` [PATCH for-6.2 24/25] hw/timer/stellaris-gptm: Use Clock input instead of system_clock_scale Peter Maydell
@ 2021-08-12 9:33 ` Peter Maydell
2021-08-13 5:08 ` Alistair Francis
24 siblings, 1 reply; 91+ messages in thread
From: Peter Maydell @ 2021-08-12 9:33 UTC (permalink / raw)
To: qemu-arm, qemu-devel
Cc: Damien Hedde, Luc Michel, Alistair Francis, Subbaraya Sundeep,
Joel Stanley, Alexandre Iooss
All the devices that used to use system_clock_scale have now been
converted to use Clock inputs instead, so the global is no longer
needed; remove it and all the code that sets it.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
include/hw/timer/armv7m_systick.h | 22 ----------------------
hw/arm/armsse.c | 17 +----------------
hw/arm/mps2.c | 2 --
hw/arm/msf2-soc.c | 2 --
hw/arm/netduino2.c | 2 --
hw/arm/netduinoplus2.c | 2 --
hw/arm/nrf51_soc.c | 2 --
hw/arm/stellaris.c | 7 ++++---
hw/arm/stm32vldiscovery.c | 2 --
hw/timer/armv7m_systick.c | 2 --
10 files changed, 5 insertions(+), 55 deletions(-)
diff --git a/include/hw/timer/armv7m_systick.h b/include/hw/timer/armv7m_systick.h
index 38adf8d274e..ee09b138810 100644
--- a/include/hw/timer/armv7m_systick.h
+++ b/include/hw/timer/armv7m_systick.h
@@ -47,26 +47,4 @@ struct SysTickState {
Clock *cpuclk;
};
-/*
- * Multiplication factor to convert from system clock ticks to qemu timer
- * ticks. This should be set (by board code, usually) to a value
- * equal to NANOSECONDS_PER_SECOND / frq, where frq is the clock frequency
- * in Hz of the CPU.
- *
- * This value is used by the systick device when it is running in
- * its "use the CPU clock" mode (ie when SYST_CSR.CLKSOURCE == 1) to
- * set how fast the timer should tick.
- *
- * TODO: we should refactor this so that rather than using a global
- * we use a device property or something similar. This is complicated
- * because (a) the property would need to be plumbed through from the
- * board code down through various layers to the systick device
- * and (b) the property needs to be modifiable after realize, because
- * the stellaris board uses this to implement the behaviour where the
- * guest can reprogram the PLL registers to downclock the CPU, and the
- * systick device needs to react accordingly. Possibly this should
- * be deferred until we have a good API for modelling clock trees.
- */
-extern int system_clock_scale;
-
#endif
diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c
index 70b52c3d4b9..aecdeb9815a 100644
--- a/hw/arm/armsse.c
+++ b/hw/arm/armsse.c
@@ -689,17 +689,6 @@ static void armsse_forward_sec_resp_cfg(ARMSSE *s)
qdev_connect_gpio_out(dev_splitter, 2, s->sec_resp_cfg_in);
}
-static void armsse_mainclk_update(void *opaque, ClockEvent event)
-{
- ARMSSE *s = ARM_SSE(opaque);
-
- /*
- * Set system_clock_scale from our Clock input; this is what
- * controls the tick rate of the CPU SysTick timer.
- */
- system_clock_scale = clock_ticks_to_ns(s->mainclk, 1);
-}
-
static void armsse_init(Object *obj)
{
ARMSSE *s = ARM_SSE(obj);
@@ -711,8 +700,7 @@ static void armsse_init(Object *obj)
assert(info->sram_banks <= MAX_SRAM_BANKS);
assert(info->num_cpus <= SSE_MAX_CPUS);
- s->mainclk = qdev_init_clock_in(DEVICE(s), "MAINCLK",
- armsse_mainclk_update, s, ClockUpdate);
+ s->mainclk = qdev_init_clock_in(DEVICE(s), "MAINCLK", NULL, NULL, 0);
s->s32kclk = qdev_init_clock_in(DEVICE(s), "S32KCLK", NULL, NULL, 0);
memory_region_init(&s->container, obj, "armsse-container", UINT64_MAX);
@@ -1654,9 +1642,6 @@ static void armsse_realize(DeviceState *dev, Error **errp)
* devices in the ARMSSE.
*/
sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->container);
-
- /* Set initial system_clock_scale from MAINCLK */
- armsse_mainclk_update(s, ClockUpdate);
}
static void armsse_idau_check(IDAUInterface *ii, uint32_t address,
diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c
index 3671f49ad7b..4634aa1a1ca 100644
--- a/hw/arm/mps2.c
+++ b/hw/arm/mps2.c
@@ -439,8 +439,6 @@ static void mps2_common_init(MachineState *machine)
qdev_get_gpio_in(armv7m,
mmc->fpga_type == FPGA_AN511 ? 47 : 13));
- system_clock_scale = NANOSECONDS_PER_SECOND / SYSCLK_FRQ;
-
armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename,
0x400000);
}
diff --git a/hw/arm/msf2-soc.c b/hw/arm/msf2-soc.c
index dbc6d936a76..b5fe9f364d5 100644
--- a/hw/arm/msf2-soc.c
+++ b/hw/arm/msf2-soc.c
@@ -144,8 +144,6 @@ static void m2sxxx_soc_realize(DeviceState *dev_soc, Error **errp)
return;
}
- system_clock_scale = clock_ticks_to_ns(s->m3clk, 1);
-
for (i = 0; i < MSF2_NUM_UARTS; i++) {
if (serial_hd(i)) {
serial_mm_init(get_system_memory(), uart_addr[i], 2,
diff --git a/hw/arm/netduino2.c b/hw/arm/netduino2.c
index b5c0ba23ee5..3365da11bf7 100644
--- a/hw/arm/netduino2.c
+++ b/hw/arm/netduino2.c
@@ -39,8 +39,6 @@ static void netduino2_init(MachineState *machine)
DeviceState *dev;
Clock *sysclk;
- system_clock_scale = NANOSECONDS_PER_SECOND / SYSCLK_FRQ;
-
/* This clock doesn't need migration because it is fixed-frequency */
sysclk = clock_new(OBJECT(machine), "SYSCLK");
clock_set_hz(sysclk, SYSCLK_FRQ);
diff --git a/hw/arm/netduinoplus2.c b/hw/arm/netduinoplus2.c
index a5a8999cc8c..76cea8e4891 100644
--- a/hw/arm/netduinoplus2.c
+++ b/hw/arm/netduinoplus2.c
@@ -39,8 +39,6 @@ static void netduinoplus2_init(MachineState *machine)
DeviceState *dev;
Clock *sysclk;
- system_clock_scale = NANOSECONDS_PER_SECOND / SYSCLK_FRQ;
-
/* This clock doesn't need migration because it is fixed-frequency */
sysclk = clock_new(OBJECT(machine), "SYSCLK");
clock_set_hz(sysclk, SYSCLK_FRQ);
diff --git a/hw/arm/nrf51_soc.c b/hw/arm/nrf51_soc.c
index e3e849a32b1..34da0d62f00 100644
--- a/hw/arm/nrf51_soc.c
+++ b/hw/arm/nrf51_soc.c
@@ -84,8 +84,6 @@ static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp)
* will always provide one).
*/
- system_clock_scale = NANOSECONDS_PER_SECOND / HCLK_FRQ;
-
object_property_set_link(OBJECT(&s->cpu), "memory", OBJECT(&s->container),
&error_abort);
if (!sysbus_realize(SYS_BUS_DEVICE(&s->cpu), errp)) {
diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
index 3e7d1dabad1..78827ace6b8 100644
--- a/hw/arm/stellaris.c
+++ b/hw/arm/stellaris.c
@@ -263,17 +263,18 @@ static bool ssys_use_rcc2(ssys_state *s)
*/
static void ssys_calculate_system_clock(ssys_state *s, bool propagate_clock)
{
+ int period_ns;
/*
* SYSDIV field specifies divisor: 0 == /1, 1 == /2, etc. Input
* clock is 200MHz, which is a period of 5 ns. Dividing the clock
* frequency by X is the same as multiplying the period by X.
*/
if (ssys_use_rcc2(s)) {
- system_clock_scale = 5 * (((s->rcc2 >> 23) & 0x3f) + 1);
+ period_ns = 5 * (((s->rcc2 >> 23) & 0x3f) + 1);
} else {
- system_clock_scale = 5 * (((s->rcc >> 23) & 0xf) + 1);
+ period_ns = 5 * (((s->rcc >> 23) & 0xf) + 1);
}
- clock_set_ns(s->sysclk, system_clock_scale);
+ clock_set_ns(s->sysclk, period_ns);
if (propagate_clock) {
clock_propagate(s->sysclk);
}
diff --git a/hw/arm/stm32vldiscovery.c b/hw/arm/stm32vldiscovery.c
index 9b79004703b..04036da3ee0 100644
--- a/hw/arm/stm32vldiscovery.c
+++ b/hw/arm/stm32vldiscovery.c
@@ -42,8 +42,6 @@ static void stm32vldiscovery_init(MachineState *machine)
DeviceState *dev;
Clock *sysclk;
- system_clock_scale = NANOSECONDS_PER_SECOND / SYSCLK_FRQ;
-
/* This clock doesn't need migration because it is fixed-frequency */
sysclk = clock_new(OBJECT(machine), "SYSCLK");
clock_set_hz(sysclk, SYSCLK_FRQ);
diff --git a/hw/timer/armv7m_systick.c b/hw/timer/armv7m_systick.c
index 39cca206cfd..9f92830968b 100644
--- a/hw/timer/armv7m_systick.c
+++ b/hw/timer/armv7m_systick.c
@@ -29,8 +29,6 @@
#define SYSCALIB_NOREF (1U << 31)
#define SYSCALIB_SKEW (1U << 30)
-int system_clock_scale;
-
static void systick_set_period_from_clock(SysTickState *s)
{
/*
--
2.20.1
^ permalink raw reply related [flat|nested] 91+ messages in thread
* Re: [PATCH for-6.2 01/25] arm: Move M-profile RAS register block into its own device
2021-08-12 9:33 ` [PATCH for-6.2 01/25] arm: Move M-profile RAS register block into its own device Peter Maydell
@ 2021-08-12 11:08 ` Alexandre IOOSS
2021-08-12 11:09 ` Peter Maydell
2021-08-13 0:59 ` Alistair Francis
` (2 subsequent siblings)
3 siblings, 1 reply; 91+ messages in thread
From: Alexandre IOOSS @ 2021-08-12 11:08 UTC (permalink / raw)
To: Peter Maydell, qemu-arm, qemu-devel
Cc: Damien Hedde, Alistair Francis, Luc Michel, Joel Stanley,
Subbaraya Sundeep
[-- Attachment #1.1: Type: text/plain, Size: 11355 bytes --]
On 8/12/21 11:33 AM, Peter Maydell wrote:
> Currently we implement the RAS register block within the NVIC device.
> It isn't really very tightly coupled with the NVIC proper, so instead
> move it out into a sysbus device of its own and have the top level
> ARMv7M container create it and map it into memory at the right
> address.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
> include/hw/arm/armv7m.h | 2 +
> include/hw/intc/armv7m_nvic.h | 1 -
> include/hw/misc/armv7m_ras.h | 37 ++++++++++++++
> hw/arm/armv7m.c | 12 +++++
> hw/intc/armv7m_nvic.c | 56 ---------------------
> hw/misc/armv7m_ras.c | 93 +++++++++++++++++++++++++++++++++++
> MAINTAINERS | 2 +
> hw/misc/meson.build | 2 +
> 8 files changed, 148 insertions(+), 57 deletions(-)
> create mode 100644 include/hw/misc/armv7m_ras.h
> create mode 100644 hw/misc/armv7m_ras.c
>
> diff --git a/include/hw/arm/armv7m.h b/include/hw/arm/armv7m.h
> index bc6733c5184..4cae0d7eeaa 100644
> --- a/include/hw/arm/armv7m.h
> +++ b/include/hw/arm/armv7m.h
> @@ -12,6 +12,7 @@
>
> #include "hw/sysbus.h"
> #include "hw/intc/armv7m_nvic.h"
> +#include "hw/misc/armv7m_ras.h"
> #include "target/arm/idau.h"
> #include "qom/object.h"
>
> @@ -58,6 +59,7 @@ struct ARMv7MState {
> NVICState nvic;
> BitBandState bitband[ARMV7M_NUM_BITBANDS];
> ARMCPU *cpu;
> + ARMv7MRAS ras;
>
> /* MemoryRegion we pass to the CPU, with our devices layered on
> * top of the ones the board provides in board_memory.
> diff --git a/include/hw/intc/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h
> index 39c71e15936..33b6d8810c7 100644
> --- a/include/hw/intc/armv7m_nvic.h
> +++ b/include/hw/intc/armv7m_nvic.h
> @@ -83,7 +83,6 @@ struct NVICState {
> MemoryRegion sysreg_ns_mem;
> MemoryRegion systickmem;
> MemoryRegion systick_ns_mem;
> - MemoryRegion ras_mem;
> MemoryRegion container;
> MemoryRegion defaultmem;
>
> diff --git a/include/hw/misc/armv7m_ras.h b/include/hw/misc/armv7m_ras.h
> new file mode 100644
> index 00000000000..f8773e65b14
> --- /dev/null
> +++ b/include/hw/misc/armv7m_ras.h
> @@ -0,0 +1,37 @@
> +/*
> + * Arm M-profile RAS block
> + *
> + * Copyright (c) 2021 Linaro Limited
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 or
> + * (at your option) any later version.
> + */
Maybe it would be a good idea here to change to "Arm M-profile RAS
(Reliability, Availability, and Serviceability) block" to define the
acronym at least once in the device code?
> +
> +/*
> + * This is a model of the RAS register block of an M-profile CPU
> + * (the registers starting at 0xE0005000 with ERRFRn).
> + *
> + * QEMU interface:
> + * + sysbus MMIO region 0: the register bank
> + *
> + * The QEMU implementation currently provides "minimal RAS" only.
> + */
> +
> +#ifndef HW_MISC_ARMV7M_RAS_H
> +#define HW_MISC_ARMV7M_RAS_H
> +
> +#include "hw/sysbus.h"
> +
> +#define TYPE_ARMV7M_RAS "armv7m-ras"
> +OBJECT_DECLARE_SIMPLE_TYPE(ARMv7MRAS, ARMV7M_RAS)
> +
> +struct ARMv7MRAS {
> + /*< private >*/
> + SysBusDevice parent_obj;
> +
> + /*< public >*/
> + MemoryRegion iomem;
> +};
> +
> +#endif
> diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c
> index 9ce5c30cd5c..8964730d153 100644
> --- a/hw/arm/armv7m.c
> +++ b/hw/arm/armv7m.c
> @@ -231,6 +231,18 @@ static void armv7m_realize(DeviceState *dev, Error **errp)
> memory_region_add_subregion(&s->container, 0xe0000000,
> sysbus_mmio_get_region(sbd, 0));
>
> + /* If the CPU has RAS support, create the RAS register block */
> + if (cpu_isar_feature(aa32_ras, s->cpu)) {
> + object_initialize_child(OBJECT(dev), "armv7m-ras",
> + &s->ras, TYPE_ARMV7M_RAS);
> + sbd = SYS_BUS_DEVICE(&s->ras);
> + if (!sysbus_realize(sbd, errp)) {
> + return;
> + }
> + memory_region_add_subregion_overlap(&s->container, 0xe0005000,
> + sysbus_mmio_get_region(sbd, 0), 1);
> + }
> +
> for (i = 0; i < ARRAY_SIZE(s->bitband); i++) {
> if (s->enable_bitband) {
> Object *obj = OBJECT(&s->bitband[i]);
> diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
> index 1e7ddcb94cb..a5975592dfa 100644
> --- a/hw/intc/armv7m_nvic.c
> +++ b/hw/intc/armv7m_nvic.c
> @@ -2549,56 +2549,6 @@ static const MemoryRegionOps nvic_systick_ops = {
> .endianness = DEVICE_NATIVE_ENDIAN,
> };
>
> -
> -static MemTxResult ras_read(void *opaque, hwaddr addr,
> - uint64_t *data, unsigned size,
> - MemTxAttrs attrs)
> -{
> - if (attrs.user) {
> - return MEMTX_ERROR;
> - }
> -
> - switch (addr) {
> - case 0xe10: /* ERRIIDR */
> - /* architect field = Arm; product/variant/revision 0 */
> - *data = 0x43b;
> - break;
> - case 0xfc8: /* ERRDEVID */
> - /* Minimal RAS: we implement 0 error record indexes */
> - *data = 0;
> - break;
> - default:
> - qemu_log_mask(LOG_UNIMP, "Read RAS register offset 0x%x\n",
> - (uint32_t)addr);
> - *data = 0;
> - break;
> - }
> - return MEMTX_OK;
> -}
> -
> -static MemTxResult ras_write(void *opaque, hwaddr addr,
> - uint64_t value, unsigned size,
> - MemTxAttrs attrs)
> -{
> - if (attrs.user) {
> - return MEMTX_ERROR;
> - }
> -
> - switch (addr) {
> - default:
> - qemu_log_mask(LOG_UNIMP, "Write to RAS register offset 0x%x\n",
> - (uint32_t)addr);
> - break;
> - }
> - return MEMTX_OK;
> -}
> -
> -static const MemoryRegionOps ras_ops = {
> - .read_with_attrs = ras_read,
> - .write_with_attrs = ras_write,
> - .endianness = DEVICE_NATIVE_ENDIAN,
> -};
> -
> /*
> * Unassigned portions of the PPB space are RAZ/WI for privileged
> * accesses, and fault for non-privileged accesses.
> @@ -2946,12 +2896,6 @@ static void armv7m_nvic_realize(DeviceState *dev, Error **errp)
> &s->systick_ns_mem, 1);
> }
>
> - if (cpu_isar_feature(aa32_ras, s->cpu)) {
> - memory_region_init_io(&s->ras_mem, OBJECT(s),
> - &ras_ops, s, "nvic_ras", 0x1000);
> - memory_region_add_subregion(&s->container, 0x5000, &s->ras_mem);
> - }
> -
> sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->container);
> }
>
> diff --git a/hw/misc/armv7m_ras.c b/hw/misc/armv7m_ras.c
> new file mode 100644
> index 00000000000..a2b4f4b8dc8
> --- /dev/null
> +++ b/hw/misc/armv7m_ras.c
> @@ -0,0 +1,93 @@
> +/*
> + * Arm M-profile RAS block
> + *
> + * Copyright (c) 2021 Linaro Limited
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 or
> + * (at your option) any later version.
> + */
> +
> +#include "qemu/osdep.h"
> +#include "hw/misc/armv7m_ras.h"
> +#include "qemu/log.h"
> +
> +static MemTxResult ras_read(void *opaque, hwaddr addr,
> + uint64_t *data, unsigned size,
> + MemTxAttrs attrs)
> +{
> + if (attrs.user) {
> + return MEMTX_ERROR;
> + }
> +
> + switch (addr) {
> + case 0xe10: /* ERRIIDR */
> + /* architect field = Arm; product/variant/revision 0 */
> + *data = 0x43b;
> + break;
> + case 0xfc8: /* ERRDEVID */
> + /* Minimal RAS: we implement 0 error record indexes */
> + *data = 0;
> + break;
> + default:
> + qemu_log_mask(LOG_UNIMP, "Read RAS register offset 0x%x\n",
> + (uint32_t)addr);
> + *data = 0;
> + break;
> + }
> + return MEMTX_OK;
> +}
> +
> +static MemTxResult ras_write(void *opaque, hwaddr addr,
> + uint64_t value, unsigned size,
> + MemTxAttrs attrs)
> +{
> + if (attrs.user) {
> + return MEMTX_ERROR;
> + }
> +
> + switch (addr) {
> + default:
> + qemu_log_mask(LOG_UNIMP, "Write to RAS register offset 0x%x\n",
> + (uint32_t)addr);
> + break;
> + }
> + return MEMTX_OK;
> +}
> +
> +static const MemoryRegionOps ras_ops = {
> + .read_with_attrs = ras_read,
> + .write_with_attrs = ras_write,
> + .endianness = DEVICE_NATIVE_ENDIAN,
> +};
> +
> +
> +static void armv7m_ras_init(Object *obj)
> +{
> + SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
> + ARMv7MRAS *s = ARMV7M_RAS(obj);
> +
> + memory_region_init_io(&s->iomem, obj, &ras_ops,
> + s, "armv7m-ras", 0x1000);
> + sysbus_init_mmio(sbd, &s->iomem);
> +}
> +
> +static void armv7m_ras_class_init(ObjectClass *klass, void *data)
> +{
> + /* This device has no state: no need for vmstate or reset */
> +}
> +
> +static const TypeInfo armv7m_ras_info = {
> + .name = TYPE_ARMV7M_RAS,
> + .parent = TYPE_SYS_BUS_DEVICE,
> + .instance_size = sizeof(ARMv7MRAS),
> + .instance_init = armv7m_ras_init,
> + .class_init = armv7m_ras_class_init,
> +};
Pure curiosity: is `.class_init` defined because it needs to be defined
or is it only a good practise in QEMU code to always define it?
> +
> +static void armv7m_ras_register_types(void)
> +{
> + type_register_static(&armv7m_ras_info);
> +}
> +
> +type_init(armv7m_ras_register_types);
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 37b1a8e4428..3cac393bb48 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -617,6 +617,7 @@ F: hw/intc/gic_internal.h
> F: hw/misc/a9scu.c
> F: hw/misc/arm11scu.c
> F: hw/misc/arm_l2x0.c
> +F: hw/misc/armv7m_ras.c
> F: hw/timer/a9gtimer*
> F: hw/timer/arm*
> F: include/hw/arm/arm*.h
> @@ -626,6 +627,7 @@ F: include/hw/misc/arm11scu.h
> F: include/hw/timer/a9gtimer.h
> F: include/hw/timer/arm_mptimer.h
> F: include/hw/timer/armv7m_systick.h
> +F: include/hw/misc/armv7m_ras.h
> F: tests/qtest/test-arm-mptimer.c
>
> Exynos
> diff --git a/hw/misc/meson.build b/hw/misc/meson.build
> index a53b849a5a0..3f41a3a5b27 100644
> --- a/hw/misc/meson.build
> +++ b/hw/misc/meson.build
> @@ -17,6 +17,8 @@ softmmu_ss.add(when: 'CONFIG_INTEGRATOR_DEBUG', if_true: files('arm_integrator_d
> softmmu_ss.add(when: 'CONFIG_A9SCU', if_true: files('a9scu.c'))
> softmmu_ss.add(when: 'CONFIG_ARM11SCU', if_true: files('arm11scu.c'))
>
> +softmmu_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('armv7m_ras.c'))
> +
> # Mac devices
> softmmu_ss.add(when: 'CONFIG_MOS6522', if_true: files('mos6522.c'))
>
>
Looks good to me! My review is weak because I am still new to QEMU codebase.
Reviewed-by: Alexandre Iooss <erdnaxe@crans.org>
-- Alexandre
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^ permalink raw reply [flat|nested] 91+ messages in thread
* Re: [PATCH for-6.2 01/25] arm: Move M-profile RAS register block into its own device
2021-08-12 11:08 ` Alexandre IOOSS
@ 2021-08-12 11:09 ` Peter Maydell
0 siblings, 0 replies; 91+ messages in thread
From: Peter Maydell @ 2021-08-12 11:09 UTC (permalink / raw)
To: Alexandre IOOSS
Cc: Damien Hedde, Luc Michel, Alistair Francis, QEMU Developers,
Subbaraya Sundeep, qemu-arm, Joel Stanley
On Thu, 12 Aug 2021 at 12:08, Alexandre IOOSS <erdnaxe@crans.org> wrote:
>
>
>
> On 8/12/21 11:33 AM, Peter Maydell wrote:
> > Currently we implement the RAS register block within the NVIC device.
> > It isn't really very tightly coupled with the NVIC proper, so instead
> > move it out into a sysbus device of its own and have the top level
> > ARMv7M container create it and map it into memory at the right
> > address.
> >
> > Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> > ---
> > include/hw/arm/armv7m.h | 2 +
> > include/hw/intc/armv7m_nvic.h | 1 -
> > include/hw/misc/armv7m_ras.h | 37 ++++++++++++++
> > hw/arm/armv7m.c | 12 +++++
> > hw/intc/armv7m_nvic.c | 56 ---------------------
> > hw/misc/armv7m_ras.c | 93 +++++++++++++++++++++++++++++++++++
> > MAINTAINERS | 2 +
> > hw/misc/meson.build | 2 +
> > 8 files changed, 148 insertions(+), 57 deletions(-)
> > create mode 100644 include/hw/misc/armv7m_ras.h
> > create mode 100644 hw/misc/armv7m_ras.c
> >
> > diff --git a/include/hw/arm/armv7m.h b/include/hw/arm/armv7m.h
> > index bc6733c5184..4cae0d7eeaa 100644
> > --- a/include/hw/arm/armv7m.h
> > +++ b/include/hw/arm/armv7m.h
> > @@ -12,6 +12,7 @@
> >
> > #include "hw/sysbus.h"
> > #include "hw/intc/armv7m_nvic.h"
> > +#include "hw/misc/armv7m_ras.h"
> > #include "target/arm/idau.h"
> > #include "qom/object.h"
> >
> > @@ -58,6 +59,7 @@ struct ARMv7MState {
> > NVICState nvic;
> > BitBandState bitband[ARMV7M_NUM_BITBANDS];
> > ARMCPU *cpu;
> > + ARMv7MRAS ras;
> >
> > /* MemoryRegion we pass to the CPU, with our devices layered on
> > * top of the ones the board provides in board_memory.
> > diff --git a/include/hw/intc/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h
> > index 39c71e15936..33b6d8810c7 100644
> > --- a/include/hw/intc/armv7m_nvic.h
> > +++ b/include/hw/intc/armv7m_nvic.h
> > @@ -83,7 +83,6 @@ struct NVICState {
> > MemoryRegion sysreg_ns_mem;
> > MemoryRegion systickmem;
> > MemoryRegion systick_ns_mem;
> > - MemoryRegion ras_mem;
> > MemoryRegion container;
> > MemoryRegion defaultmem;
> >
> > diff --git a/include/hw/misc/armv7m_ras.h b/include/hw/misc/armv7m_ras.h
> > new file mode 100644
> > index 00000000000..f8773e65b14
> > --- /dev/null
> > +++ b/include/hw/misc/armv7m_ras.h
> > @@ -0,0 +1,37 @@
> > +/*
> > + * Arm M-profile RAS block
> > + *
> > + * Copyright (c) 2021 Linaro Limited
> > + *
> > + * This program is free software; you can redistribute it and/or modify
> > + * it under the terms of the GNU General Public License version 2 or
> > + * (at your option) any later version.
> > + */
>
> Maybe it would be a good idea here to change to "Arm M-profile RAS
> (Reliability, Availability, and Serviceability) block" to define the
> acronym at least once in the device code?
Yeah, we could perhaps put a comment in there somewhere.
Though really you need to look in the spec to understand
what the block is doing, at which point you'll find out what
the register block is for.
> > +static void armv7m_ras_class_init(ObjectClass *klass, void *data)
> > +{
> > + /* This device has no state: no need for vmstate or reset */
> > +}
> > +
> > +static const TypeInfo armv7m_ras_info = {
> > + .name = TYPE_ARMV7M_RAS,
> > + .parent = TYPE_SYS_BUS_DEVICE,
> > + .instance_size = sizeof(ARMv7MRAS),
> > + .instance_init = armv7m_ras_init,
> > + .class_init = armv7m_ras_class_init,
> > +};
>
> Pure curiosity: is `.class_init` defined because it needs to be defined
> or is it only a good practise in QEMU code to always define it?
It's optional, and in this case it's only there because it makes
a place to put the comment, I guess.
-- PMM
^ permalink raw reply [flat|nested] 91+ messages in thread
* Re: [PATCH for-6.2 03/25] arm: Move system PPB container handling to armv7m
2021-08-12 9:33 ` [PATCH for-6.2 03/25] arm: Move system PPB container handling to armv7m Peter Maydell
@ 2021-08-12 11:56 ` Alexandre IOOSS
2021-08-17 9:25 ` Luc Michel
1 sibling, 0 replies; 91+ messages in thread
From: Alexandre IOOSS @ 2021-08-12 11:56 UTC (permalink / raw)
To: Peter Maydell, qemu-arm, qemu-devel
Cc: Damien Hedde, Alistair Francis, Luc Michel, Joel Stanley,
Subbaraya Sundeep
[-- Attachment #1.1: Type: text/plain, Size: 15355 bytes --]
On 8/12/21 11:33 AM, Peter Maydell wrote:
> Instead of having the NVIC device provide a single sysbus memory
> region covering the whole of the "System PPB" space, which implements
> the default behaviour for unimplemented ranges and provides the NS
> alias window to the sysregs as well as the main sysreg MR, move this
> handling to the container armv7m device. The NVIC now provides a
> single memory region which just implements the system registers.
> This consolidates all the handling of "map various devices in the
> PPB" into the armv7m container where it belongs.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
> include/hw/arm/armv7m.h | 4 +
> include/hw/intc/armv7m_nvic.h | 3 -
> hw/arm/armv7m.c | 100 ++++++++++++++++++++++-
> hw/intc/armv7m_nvic.c | 145 +---------------------------------
> 4 files changed, 107 insertions(+), 145 deletions(-)
>
> diff --git a/include/hw/arm/armv7m.h b/include/hw/arm/armv7m.h
> index 360c35c5fb2..fe8b248a6c6 100644
> --- a/include/hw/arm/armv7m.h
> +++ b/include/hw/arm/armv7m.h
> @@ -77,6 +77,10 @@ struct ARMv7MState {
> * NS systick device if appropriate.
> */
> MemoryRegion systick_ns_mem;
> + /* Ditto, for the sysregs region provided by the NVIC */
> + MemoryRegion sysreg_ns_mem;
> + /* MR providing default PPB behaviour */
> + MemoryRegion defaultmem;
>
> /* Properties */
> char *cpu_type;
> diff --git a/include/hw/intc/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h
> index 6a6a99090c7..0180c7b0ca1 100644
> --- a/include/hw/intc/armv7m_nvic.h
> +++ b/include/hw/intc/armv7m_nvic.h
> @@ -80,9 +80,6 @@ struct NVICState {
> int vectpending_prio; /* group prio of the exeception in vectpending */
>
> MemoryRegion sysregmem;
> - MemoryRegion sysreg_ns_mem;
> - MemoryRegion container;
> - MemoryRegion defaultmem;
>
> uint32_t num_irq;
> qemu_irq excpout;
> diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c
> index 364ac069702..7e7fb7a3ad3 100644
> --- a/hw/arm/armv7m.c
> +++ b/hw/arm/armv7m.c
> @@ -18,6 +18,7 @@
> #include "sysemu/reset.h"
> #include "qemu/error-report.h"
> #include "qemu/module.h"
> +#include "qemu/log.h"
> #include "target/arm/idau.h"
>
> /* Bitbanded IO. Each word corresponds to a single bit. */
> @@ -203,6 +204,43 @@ static const MemoryRegionOps v7m_systick_ops = {
> .endianness = DEVICE_NATIVE_ENDIAN,
> };
>
> +/*
> + * Unassigned portions of the PPB space are RAZ/WI for privileged
> + * accesses, and fault for non-privileged accesses.
> + */
> +static MemTxResult ppb_default_read(void *opaque, hwaddr addr,
> + uint64_t *data, unsigned size,
> + MemTxAttrs attrs)
> +{
> + qemu_log_mask(LOG_UNIMP, "Read of unassigned area of PPB: offset 0x%x\n",
> + (uint32_t)addr);
> + if (attrs.user) {
> + return MEMTX_ERROR;
> + }
> + *data = 0;
> + return MEMTX_OK;
> +}
> +
> +static MemTxResult ppb_default_write(void *opaque, hwaddr addr,
> + uint64_t value, unsigned size,
> + MemTxAttrs attrs)
> +{
> + qemu_log_mask(LOG_UNIMP, "Write of unassigned area of PPB: offset 0x%x\n",
> + (uint32_t)addr);
> + if (attrs.user) {
> + return MEMTX_ERROR;
> + }
> + return MEMTX_OK;
> +}
> +
> +static const MemoryRegionOps ppb_default_ops = {
> + .read_with_attrs = ppb_default_read,
> + .write_with_attrs = ppb_default_write,
> + .endianness = DEVICE_NATIVE_ENDIAN,
> + .valid.min_access_size = 1,
> + .valid.max_access_size = 8,
> +};
> +
> static void armv7m_instance_init(Object *obj)
> {
> ARMv7MState *s = ARMV7M(obj);
> @@ -309,13 +347,73 @@ static void armv7m_realize(DeviceState *dev, Error **errp)
> qdev_pass_gpios(DEVICE(&s->nvic), dev, "SYSRESETREQ");
> qdev_pass_gpios(DEVICE(&s->nvic), dev, "NMI");
>
> + /*
> + * We map various devices into the continer MR at their architected
> + * addresses. In particular, we map everything corresponding to the
> + * "System PPB" space. This is the range from 0xe0000000 to 0xe00fffff
> + * and includes the NVIC, the System Control Space (system registers),
> + * the systick timer, and for CPUs with the Security extension an NS
> + * banked version of all of these.
I believe there is a typo: "continer". Is it "container"?
> + *
> + * The default behaviour for unimplemented registers/ranges
> + * (for instance the Data Watchpoint and Trace unit at 0xe0001000)
> + * is to RAZ/WI for privileged access and BusFault for non-privileged
> + * access.
> + *
> + * The NVIC and System Control Space (SCS) starts at 0xe000e000
> + * and looks like this:
> + * 0x004 - ICTR
> + * 0x010 - 0xff - systick
> + * 0x100..0x7ec - NVIC
> + * 0x7f0..0xcff - Reserved
> + * 0xd00..0xd3c - SCS registers
> + * 0xd40..0xeff - Reserved or Not implemented
> + * 0xf00 - STIR
> + *
> + * Some registers within this space are banked between security states.
> + * In v8M there is a second range 0xe002e000..0xe002efff which is the
> + * NonSecure alias SCS; secure accesses to this behave like NS accesses
> + * to the main SCS range, and non-secure accesses (including when
> + * the security extension is not implemented) are RAZ/WI.
> + * Note that both the main SCS range and the alias range are defined
> + * to be exempt from memory attribution (R_BLJT) and so the memory
> + * transaction attribute always matches the current CPU security
> + * state (attrs.secure == env->v7m.secure). In the v7m_sysreg_ns_ops
> + * wrappers we change attrs.secure to indicate the NS access; so
> + * generally code determining which banked register to use should
> + * use attrs.secure; code determining actual behaviour of the system
> + * should use env->v7m.secure.
> + *
> + * Within the PPB space, some MRs overlap, and the priority
> + * of overlapping regions is:
> + * - default region (for RAZ/WI and BusFault) : -1
> + * - system register regions (provided by the NVIC) : 0
> + * - systick : 1
> + * This is because the systick device is a small block of registers
> + * in the middle of the other system control registers.
> + */
> +
> + memory_region_init_io(&s->defaultmem, OBJECT(s), &ppb_default_ops, s,
> + "nvic-default", 0x100000);
> + memory_region_add_subregion_overlap(&s->container, 0xe0000000,
> + &s->defaultmem, -1);
> +
> /* Wire the NVIC up to the CPU */
> sbd = SYS_BUS_DEVICE(&s->nvic);
> sysbus_connect_irq(sbd, 0,
> qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_IRQ));
>
> - memory_region_add_subregion(&s->container, 0xe0000000,
> + memory_region_add_subregion(&s->container, 0xe000e000,
> sysbus_mmio_get_region(sbd, 0));
> + if (arm_feature(&s->cpu->env, ARM_FEATURE_V8)) {
> + /* Create the NS alias region for the NVIC sysregs */
> + memory_region_init_io(&s->sysreg_ns_mem, OBJECT(s),
> + &v7m_sysreg_ns_ops,
> + sysbus_mmio_get_region(sbd, 0),
> + "nvic_sysregs_ns", 0x1000);
> + memory_region_add_subregion(&s->container, 0xe002e000,
> + &s->sysreg_ns_mem);
> + }
>
> /* Create and map the systick devices */
> if (!sysbus_realize(SYS_BUS_DEVICE(&s->systick[M_REG_NS]), errp)) {
> diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
> index 2b3e79a3da9..13df002ce4d 100644
> --- a/hw/intc/armv7m_nvic.c
> +++ b/hw/intc/armv7m_nvic.c
> @@ -2470,90 +2470,6 @@ static const MemoryRegionOps nvic_sysreg_ops = {
> .endianness = DEVICE_NATIVE_ENDIAN,
> };
>
> -static MemTxResult nvic_sysreg_ns_write(void *opaque, hwaddr addr,
> - uint64_t value, unsigned size,
> - MemTxAttrs attrs)
> -{
> - MemoryRegion *mr = opaque;
> -
> - if (attrs.secure) {
> - /* S accesses to the alias act like NS accesses to the real region */
> - attrs.secure = 0;
> - return memory_region_dispatch_write(mr, addr, value,
> - size_memop(size) | MO_TE, attrs);
> - } else {
> - /* NS attrs are RAZ/WI for privileged, and BusFault for user */
> - if (attrs.user) {
> - return MEMTX_ERROR;
> - }
> - return MEMTX_OK;
> - }
> -}
> -
> -static MemTxResult nvic_sysreg_ns_read(void *opaque, hwaddr addr,
> - uint64_t *data, unsigned size,
> - MemTxAttrs attrs)
> -{
> - MemoryRegion *mr = opaque;
> -
> - if (attrs.secure) {
> - /* S accesses to the alias act like NS accesses to the real region */
> - attrs.secure = 0;
> - return memory_region_dispatch_read(mr, addr, data,
> - size_memop(size) | MO_TE, attrs);
> - } else {
> - /* NS attrs are RAZ/WI for privileged, and BusFault for user */
> - if (attrs.user) {
> - return MEMTX_ERROR;
> - }
> - *data = 0;
> - return MEMTX_OK;
> - }
> -}
> -
> -static const MemoryRegionOps nvic_sysreg_ns_ops = {
> - .read_with_attrs = nvic_sysreg_ns_read,
> - .write_with_attrs = nvic_sysreg_ns_write,
> - .endianness = DEVICE_NATIVE_ENDIAN,
> -};
> -
> -/*
> - * Unassigned portions of the PPB space are RAZ/WI for privileged
> - * accesses, and fault for non-privileged accesses.
> - */
> -static MemTxResult ppb_default_read(void *opaque, hwaddr addr,
> - uint64_t *data, unsigned size,
> - MemTxAttrs attrs)
> -{
> - qemu_log_mask(LOG_UNIMP, "Read of unassigned area of PPB: offset 0x%x\n",
> - (uint32_t)addr);
> - if (attrs.user) {
> - return MEMTX_ERROR;
> - }
> - *data = 0;
> - return MEMTX_OK;
> -}
> -
> -static MemTxResult ppb_default_write(void *opaque, hwaddr addr,
> - uint64_t value, unsigned size,
> - MemTxAttrs attrs)
> -{
> - qemu_log_mask(LOG_UNIMP, "Write of unassigned area of PPB: offset 0x%x\n",
> - (uint32_t)addr);
> - if (attrs.user) {
> - return MEMTX_ERROR;
> - }
> - return MEMTX_OK;
> -}
> -
> -static const MemoryRegionOps ppb_default_ops = {
> - .read_with_attrs = ppb_default_read,
> - .write_with_attrs = ppb_default_write,
> - .endianness = DEVICE_NATIVE_ENDIAN,
> - .valid.min_access_size = 1,
> - .valid.max_access_size = 8,
> -};
> -
> static int nvic_post_load(void *opaque, int version_id)
> {
> NVICState *s = opaque;
> @@ -2770,66 +2686,13 @@ static void armv7m_nvic_realize(DeviceState *dev, Error **errp)
> s->num_prio_bits = arm_feature(&s->cpu->env, ARM_FEATURE_V7) ? 8 : 2;
>
> /*
> - * This device provides a single sysbus memory region which
> - * represents the whole of the "System PPB" space. This is the
> - * range from 0xe0000000 to 0xe00fffff and includes the NVIC,
> - * the System Control Space (system registers), the systick timer,
> - * and for CPUs with the Security extension an NS banked version
> - * of all of these.
> - *
> - * The default behaviour for unimplemented registers/ranges
> - * (for instance the Data Watchpoint and Trace unit at 0xe0001000)
> - * is to RAZ/WI for privileged access and BusFault for non-privileged
> - * access.
> - *
> - * The NVIC and System Control Space (SCS) starts at 0xe000e000
> - * and looks like this:
> - * 0x004 - ICTR
> - * 0x010 - 0xff - systick
> - * 0x100..0x7ec - NVIC
> - * 0x7f0..0xcff - Reserved
> - * 0xd00..0xd3c - SCS registers
> - * 0xd40..0xeff - Reserved or Not implemented
> - * 0xf00 - STIR
> - *
> - * Some registers within this space are banked between security states.
> - * In v8M there is a second range 0xe002e000..0xe002efff which is the
> - * NonSecure alias SCS; secure accesses to this behave like NS accesses
> - * to the main SCS range, and non-secure accesses (including when
> - * the security extension is not implemented) are RAZ/WI.
> - * Note that both the main SCS range and the alias range are defined
> - * to be exempt from memory attribution (R_BLJT) and so the memory
> - * transaction attribute always matches the current CPU security
> - * state (attrs.secure == env->v7m.secure). In the nvic_sysreg_ns_ops
> - * wrappers we change attrs.secure to indicate the NS access; so
> - * generally code determining which banked register to use should
> - * use attrs.secure; code determining actual behaviour of the system
> - * should use env->v7m.secure.
> - *
> - * The container covers the whole PPB space. Within it the priority
> - * of overlapping regions is:
> - * - default region (for RAZ/WI and BusFault) : -1
> - * - system register regions : 0
> - * - systick : 1
> - * This is because the systick device is a small block of registers
> - * in the middle of the other system control registers.
> + * This device provides a single memory region which covers the
> + * sysreg/NVIC registers from 0xE000E000 .. 0xE000EFFF, with the
> + * exception of the systick timer registers 0xE000E010 .. 0xE000E0FF.
> */
> - memory_region_init(&s->container, OBJECT(s), "nvic", 0x100000);
> - memory_region_init_io(&s->defaultmem, OBJECT(s), &ppb_default_ops, s,
> - "nvic-default", 0x100000);
> - memory_region_add_subregion_overlap(&s->container, 0, &s->defaultmem, -1);
> memory_region_init_io(&s->sysregmem, OBJECT(s), &nvic_sysreg_ops, s,
> "nvic_sysregs", 0x1000);
> - memory_region_add_subregion(&s->container, 0xe000, &s->sysregmem);
> -
> - if (arm_feature(&s->cpu->env, ARM_FEATURE_V8)) {
> - memory_region_init_io(&s->sysreg_ns_mem, OBJECT(s),
> - &nvic_sysreg_ns_ops, &s->sysregmem,
> - "nvic_sysregs_ns", 0x1000);
> - memory_region_add_subregion(&s->container, 0x2e000, &s->sysreg_ns_mem);
> - }
> -
> - sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->container);
> + sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->sysregmem);
> }
>
> static void armv7m_nvic_instance_init(Object *obj)
>
My review is week because I am new to this codebase.
Reviewed-by: Alexandre Iooss <erdnaxe@crans.org>
Thanks,
-- Alexandre
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^ permalink raw reply [flat|nested] 91+ messages in thread
* Re: [PATCH for-6.2 09/25] clock: Provide builtin multiplier/divider
2021-08-12 9:33 ` [PATCH for-6.2 09/25] clock: Provide builtin multiplier/divider Peter Maydell
@ 2021-08-12 12:08 ` Alexandre IOOSS
2021-08-12 12:22 ` Peter Maydell
2021-08-13 1:33 ` Alistair Francis
` (3 subsequent siblings)
4 siblings, 1 reply; 91+ messages in thread
From: Alexandre IOOSS @ 2021-08-12 12:08 UTC (permalink / raw)
To: Peter Maydell, qemu-arm, qemu-devel
Cc: Damien Hedde, Alistair Francis, Luc Michel, Joel Stanley,
Subbaraya Sundeep
[-- Attachment #1.1: Type: text/plain, Size: 8548 bytes --]
On 8/12/21 11:33 AM, Peter Maydell wrote:
> It is quite common for a clock tree to involve possibly programmable
> clock multipliers or dividers, where the frequency of a clock is for
> instance divided by 8 to produce a slower clock to feed to a
> particular device.
>
> Currently we provide no convenient mechanism for modelling this. You
> can implement it by having an input Clock and an output Clock, and
> manually setting the period of the output clock in the period-changed
> callback of the input clock, but that's quite clunky.
>
> This patch adds support in the Clock objects themselves for setting a
> multiplier or divider. The effect of setting this on a clock is that
> when the clock's period is changed, all the children of the clock are
> set to period * multiplier / divider, rather than being set to the
> same period as the parent clock.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
> docs/devel/clocks.rst | 23 +++++++++++++++++++++++
> include/hw/clock.h | 29 +++++++++++++++++++++++++++++
> hw/core/clock-vmstate.c | 24 +++++++++++++++++++++++-
> hw/core/clock.c | 29 +++++++++++++++++++++++++----
> 4 files changed, 100 insertions(+), 5 deletions(-)
>
> diff --git a/docs/devel/clocks.rst b/docs/devel/clocks.rst
> index 956bd147ea0..430fbd842e5 100644
> --- a/docs/devel/clocks.rst
> +++ b/docs/devel/clocks.rst
> @@ -260,6 +260,29 @@ clocks get the new clock period value: *Clock 2*, *Clock 3* and *Clock 4*.
> It is not possible to disconnect a clock or to change the clock connection
> after it is connected.
>
> +Clock multiplier and divider settings
> +-------------------------------------
> +
> +By default, when clocks are connected together, the child
> +clocks run with the same period as their source (parent) clock.
> +The Clock API supports a built-in period multiplier/divider
> +mechanism so you can configure a clock to make its children
> +run at a different period from its own. If you call the
> +``clock_set_mul_div()`` function you can specify the clock's
> +multiplier and divider values. The children of that clock
> +will all run with a period of ``parent_period * multiplier / divider``.
> +For instance, if the clock has a frequency of 8MHz and you set its
> +multiplier to 2 and its divider to 3, the child clocks will run
> +at 12MHz.
> +
> +You can change the multiplier and divider of a clock at runtime,
> +so you can use this to model clock controller devices which
> +have guest-programmable frequency multipliers or dividers.
This looks nice!
Does this imply that if I am going to implement the STM32 RCC (Reset and
Clock Controller) device, then I should use this new feature?
> +
> +Note that ``clock_set_mul_div()`` does not automatically call
> +``clock_propagate()``. If you make a runtime change to the
> +multiplier or divider you must call clock_propagate() yourself.a
> +
> Unconnected input clocks
> ------------------------
>
> diff --git a/include/hw/clock.h b/include/hw/clock.h
> index a7187eab95e..11f67fb9701 100644
> --- a/include/hw/clock.h
> +++ b/include/hw/clock.h
> @@ -81,6 +81,10 @@ struct Clock {
> void *callback_opaque;
> unsigned int callback_events;
>
> + /* Ratio of the parent clock to run the child clocks at */
> + uint32_t multiplier;
> + uint32_t divider;
> +
> /* Clocks are organized in a clock tree */
> Clock *source;
> QLIST_HEAD(, Clock) children;
> @@ -350,4 +354,29 @@ static inline bool clock_is_enabled(const Clock *clk)
> */
> char *clock_display_freq(Clock *clk);
>
> +/**
> + * clock_set_mul_div: set multiplier/divider for child clocks
> + * @clk: clock
> + * @multiplier: multiplier value
> + * @divider: divider value
> + *
> + * By default, a Clock's children will all run with the same period
> + * as their parent. This function allows you to adjust the multiplier
> + * and divider used to derive the child clock frequency.
> + * For example, setting a multiplier of 2 and a divider of 3
> + * will run child clocks with a period 2/3 of the parent clock,
> + * so if the parent clock is an 8MHz clock the children will
> + * be 12MHz.
> + *
> + * Setting the multiplier to 0 will stop the child clocks.
> + * Setting the divider to 0 is a programming error (diagnosed with
> + * an assertion failure).
> + * Setting a multiplier value that results in the child period
> + * overflowing is not diagnosed.
> + *
> + * Note that this function does not call clock_propagate(); the
> + * caller should do that if necessary.
> + */
> +void clock_set_mul_div(Clock *clk, uint32_t multiplier, uint32_t divider);
> +
> #endif /* QEMU_HW_CLOCK_H */
> diff --git a/hw/core/clock-vmstate.c b/hw/core/clock-vmstate.c
> index 260b13fc2c8..07bb45d7ed4 100644
> --- a/hw/core/clock-vmstate.c
> +++ b/hw/core/clock-vmstate.c
> @@ -14,6 +14,24 @@
> #include "migration/vmstate.h"
> #include "hw/clock.h"
>
> +static bool muldiv_needed(void *opaque)
> +{
> + Clock *clk = opaque;
> +
> + return clk->multiplier != 1 || clk->divider != 1;
> +}
> +
> +const VMStateDescription vmstate_muldiv = {
> + .name = "clock/muldiv",
> + .version_id = 1,
> + .minimum_version_id = 1,
> + .needed = muldiv_needed,
> + .fields = (VMStateField[]) {
> + VMSTATE_UINT32(multiplier, Clock),
> + VMSTATE_UINT32(divider, Clock),
> + },
> +};
> +
> const VMStateDescription vmstate_clock = {
> .name = "clock",
> .version_id = 0,
> @@ -21,5 +39,9 @@ const VMStateDescription vmstate_clock = {
> .fields = (VMStateField[]) {
> VMSTATE_UINT64(period, Clock),
> VMSTATE_END_OF_LIST()
> - }
> + },
> + .subsections = (const VMStateDescription*[]) {
> + &vmstate_muldiv,
> + NULL
> + },
> };
> diff --git a/hw/core/clock.c b/hw/core/clock.c
> index fc5a99683f8..c371b9e977a 100644
> --- a/hw/core/clock.c
> +++ b/hw/core/clock.c
> @@ -64,6 +64,15 @@ bool clock_set(Clock *clk, uint64_t period)
> return true;
> }
>
> +static uint64_t clock_get_child_period(Clock *clk)
> +{
> + /*
> + * Return the period to be used for child clocks, which is the parent
> + * clock period adjusted for for multiplier and divider effects.
> + */
> + return muldiv64(clk->period, clk->multiplier, clk->divider);
> +}
> +
> static void clock_call_callback(Clock *clk, ClockEvent event)
> {
> /*
> @@ -78,15 +87,16 @@ static void clock_call_callback(Clock *clk, ClockEvent event)
> static void clock_propagate_period(Clock *clk, bool call_callbacks)
> {
> Clock *child;
> + uint64_t child_period = clock_get_child_period(clk);
>
> QLIST_FOREACH(child, &clk->children, sibling) {
> - if (child->period != clk->period) {
> + if (child->period != child_period) {
> if (call_callbacks) {
> clock_call_callback(child, ClockPreUpdate);
> }
> - child->period = clk->period;
> + child->period = child_period;
> trace_clock_update(CLOCK_PATH(child), CLOCK_PATH(clk),
> - CLOCK_PERIOD_TO_HZ(clk->period),
> + CLOCK_PERIOD_TO_HZ(child->period),
> call_callbacks);
> if (call_callbacks) {
> clock_call_callback(child, ClockUpdate);
> @@ -110,7 +120,7 @@ void clock_set_source(Clock *clk, Clock *src)
>
> trace_clock_set_source(CLOCK_PATH(clk), CLOCK_PATH(src));
>
> - clk->period = src->period;
> + clk->period = clock_get_child_period(src);
> QLIST_INSERT_HEAD(&src->children, clk, sibling);
> clk->source = src;
> clock_propagate_period(clk, false);
> @@ -133,10 +143,21 @@ char *clock_display_freq(Clock *clk)
> return freq_to_str(clock_get_hz(clk));
> }
>
> +void clock_set_mul_div(Clock *clk, uint32_t multiplier, uint32_t divider)
> +{
> + assert(divider != 0);
> +
> + clk->multiplier = multiplier;
> + clk->divider = divider;
> +}
> +
> static void clock_initfn(Object *obj)
> {
> Clock *clk = CLOCK(obj);
>
> + clk->multiplier = 1;
> + clk->divider = 1;
> +
> QLIST_INIT(&clk->children);
> }
>
>
Reviewed-by: Alexandre Iooss <erdnaxe@crans.org>
Thanks,
-- Alexandre
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^ permalink raw reply [flat|nested] 91+ messages in thread
* Re: [PATCH for-6.2 10/25] hw/arm: Don't allocate separate MemoryRegions in stm32 SoC realize
2021-08-12 9:33 ` [PATCH for-6.2 10/25] hw/arm: Don't allocate separate MemoryRegions in stm32 SoC realize Peter Maydell
@ 2021-08-12 12:13 ` Alexandre IOOSS
2021-08-12 12:27 ` Peter Maydell
2021-08-13 1:34 ` Alistair Francis
2021-08-17 9:41 ` Luc Michel
2 siblings, 1 reply; 91+ messages in thread
From: Alexandre IOOSS @ 2021-08-12 12:13 UTC (permalink / raw)
To: Peter Maydell, qemu-arm, qemu-devel
Cc: Damien Hedde, Alistair Francis, Luc Michel, Joel Stanley,
Subbaraya Sundeep
[-- Attachment #1.1: Type: text/plain, Size: 5665 bytes --]
On 8/12/21 11:33 AM, Peter Maydell wrote:
> In the realize methods of the stm32f100 and stm32f205 SoC objects, we
> call g_new() to create new MemoryRegion objjects for the sram, flash,
> and flash_alias. This is unnecessary (and leaves open the
> possibility of leaking the allocations if we exit from realize with
> an error). Make these MemoryRegions member fields of the device
> state struct instead, as stm32f405 already does.
There is a typo in "objjects".
This is something I had issue understanding as I was seeing both
patterns in the codebase, thank you for making this clear.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
> include/hw/arm/stm32f100_soc.h | 4 ++++
> include/hw/arm/stm32f205_soc.h | 4 ++++
> hw/arm/stm32f100_soc.c | 17 +++++++----------
> hw/arm/stm32f205_soc.c | 17 +++++++----------
> 4 files changed, 22 insertions(+), 20 deletions(-)
>
> diff --git a/include/hw/arm/stm32f100_soc.h b/include/hw/arm/stm32f100_soc.h
> index 71bffcf4fd5..b7d71c6c634 100644
> --- a/include/hw/arm/stm32f100_soc.h
> +++ b/include/hw/arm/stm32f100_soc.h
> @@ -52,6 +52,10 @@ struct STM32F100State {
>
> STM32F2XXUsartState usart[STM_NUM_USARTS];
> STM32F2XXSPIState spi[STM_NUM_SPIS];
> +
> + MemoryRegion sram;
> + MemoryRegion flash;
> + MemoryRegion flash_alias;
> };
>
> #endif
> diff --git a/include/hw/arm/stm32f205_soc.h b/include/hw/arm/stm32f205_soc.h
> index 985ff63aa9e..75251494917 100644
> --- a/include/hw/arm/stm32f205_soc.h
> +++ b/include/hw/arm/stm32f205_soc.h
> @@ -63,6 +63,10 @@ struct STM32F205State {
> STM32F2XXSPIState spi[STM_NUM_SPIS];
>
> qemu_or_irq *adc_irqs;
> +
> + MemoryRegion sram;
> + MemoryRegion flash;
> + MemoryRegion flash_alias;
> };
>
> #endif
> diff --git a/hw/arm/stm32f100_soc.c b/hw/arm/stm32f100_soc.c
> index 0c4a5c66451..0be92b2c475 100644
> --- a/hw/arm/stm32f100_soc.c
> +++ b/hw/arm/stm32f100_soc.c
> @@ -67,25 +67,22 @@ static void stm32f100_soc_realize(DeviceState *dev_soc, Error **errp)
> int i;
>
> MemoryRegion *system_memory = get_system_memory();
> - MemoryRegion *sram = g_new(MemoryRegion, 1);
> - MemoryRegion *flash = g_new(MemoryRegion, 1);
> - MemoryRegion *flash_alias = g_new(MemoryRegion, 1);
>
> /*
> * Init flash region
> * Flash starts at 0x08000000 and then is aliased to boot memory at 0x0
> */
> - memory_region_init_rom(flash, OBJECT(dev_soc), "STM32F100.flash",
> + memory_region_init_rom(&s->flash, OBJECT(dev_soc), "STM32F100.flash",
> FLASH_SIZE, &error_fatal);
> - memory_region_init_alias(flash_alias, OBJECT(dev_soc),
> - "STM32F100.flash.alias", flash, 0, FLASH_SIZE);
> - memory_region_add_subregion(system_memory, FLASH_BASE_ADDRESS, flash);
> - memory_region_add_subregion(system_memory, 0, flash_alias);
> + memory_region_init_alias(&s->flash_alias, OBJECT(dev_soc),
> + "STM32F100.flash.alias", &s->flash, 0, FLASH_SIZE);
> + memory_region_add_subregion(system_memory, FLASH_BASE_ADDRESS, &s->flash);
> + memory_region_add_subregion(system_memory, 0, &s->flash_alias);
>
> /* Init SRAM region */
> - memory_region_init_ram(sram, NULL, "STM32F100.sram", SRAM_SIZE,
> + memory_region_init_ram(&s->sram, NULL, "STM32F100.sram", SRAM_SIZE,
> &error_fatal);
> - memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, sram);
> + memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, &s->sram);
>
> /* Init ARMv7m */
> armv7m = DEVICE(&s->armv7m);
> diff --git a/hw/arm/stm32f205_soc.c b/hw/arm/stm32f205_soc.c
> index 9cd41bf56da..0bd215aebd7 100644
> --- a/hw/arm/stm32f205_soc.c
> +++ b/hw/arm/stm32f205_soc.c
> @@ -84,21 +84,18 @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
> int i;
>
> MemoryRegion *system_memory = get_system_memory();
> - MemoryRegion *sram = g_new(MemoryRegion, 1);
> - MemoryRegion *flash = g_new(MemoryRegion, 1);
> - MemoryRegion *flash_alias = g_new(MemoryRegion, 1);
>
> - memory_region_init_rom(flash, OBJECT(dev_soc), "STM32F205.flash",
> + memory_region_init_rom(&s->flash, OBJECT(dev_soc), "STM32F205.flash",
> FLASH_SIZE, &error_fatal);
> - memory_region_init_alias(flash_alias, OBJECT(dev_soc),
> - "STM32F205.flash.alias", flash, 0, FLASH_SIZE);
> + memory_region_init_alias(&s->flash_alias, OBJECT(dev_soc),
> + "STM32F205.flash.alias", &s->flash, 0, FLASH_SIZE);
>
> - memory_region_add_subregion(system_memory, FLASH_BASE_ADDRESS, flash);
> - memory_region_add_subregion(system_memory, 0, flash_alias);
> + memory_region_add_subregion(system_memory, FLASH_BASE_ADDRESS, &s->flash);
> + memory_region_add_subregion(system_memory, 0, &s->flash_alias);
>
> - memory_region_init_ram(sram, NULL, "STM32F205.sram", SRAM_SIZE,
> + memory_region_init_ram(&s->sram, NULL, "STM32F205.sram", SRAM_SIZE,
> &error_fatal);
> - memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, sram);
> + memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, &s->sram);
>
> armv7m = DEVICE(&s->armv7m);
> qdev_prop_set_uint32(armv7m, "num-irq", 96);
>
Reviewed-by: Alexandre Iooss <erdnaxe@crans.org>
Thanks,
-- Alexandre
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^ permalink raw reply [flat|nested] 91+ messages in thread
* Re: [PATCH for-6.2 09/25] clock: Provide builtin multiplier/divider
2021-08-12 12:08 ` Alexandre IOOSS
@ 2021-08-12 12:22 ` Peter Maydell
0 siblings, 0 replies; 91+ messages in thread
From: Peter Maydell @ 2021-08-12 12:22 UTC (permalink / raw)
To: Alexandre IOOSS
Cc: Damien Hedde, Luc Michel, Alistair Francis, QEMU Developers,
Subbaraya Sundeep, qemu-arm, Joel Stanley
On Thu, 12 Aug 2021 at 13:08, Alexandre IOOSS <erdnaxe@crans.org> wrote:
>
>
> On 8/12/21 11:33 AM, Peter Maydell wrote:
> > It is quite common for a clock tree to involve possibly programmable
> > clock multipliers or dividers, where the frequency of a clock is for
> > instance divided by 8 to produce a slower clock to feed to a
> > particular device.
> >
> > Currently we provide no convenient mechanism for modelling this. You
> > can implement it by having an input Clock and an output Clock, and
> > manually setting the period of the output clock in the period-changed
> > callback of the input clock, but that's quite clunky.
> >
> > This patch adds support in the Clock objects themselves for setting a
> > multiplier or divider. The effect of setting this on a clock is that
> > when the clock's period is changed, all the children of the clock are
> > set to period * multiplier / divider, rather than being set to the
> > same period as the parent clock.
> >
> > Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> > ---
> > docs/devel/clocks.rst | 23 +++++++++++++++++++++++
> > include/hw/clock.h | 29 +++++++++++++++++++++++++++++
> > hw/core/clock-vmstate.c | 24 +++++++++++++++++++++++-
> > hw/core/clock.c | 29 +++++++++++++++++++++++++----
> > 4 files changed, 100 insertions(+), 5 deletions(-)
> >
> > diff --git a/docs/devel/clocks.rst b/docs/devel/clocks.rst
> > index 956bd147ea0..430fbd842e5 100644
> > --- a/docs/devel/clocks.rst
> > +++ b/docs/devel/clocks.rst
> > @@ -260,6 +260,29 @@ clocks get the new clock period value: *Clock 2*, *Clock 3* and *Clock 4*.
> > It is not possible to disconnect a clock or to change the clock connection
> > after it is connected.
> >
> > +Clock multiplier and divider settings
> > +-------------------------------------
> > +
> > +By default, when clocks are connected together, the child
> > +clocks run with the same period as their source (parent) clock.
> > +The Clock API supports a built-in period multiplier/divider
> > +mechanism so you can configure a clock to make its children
> > +run at a different period from its own. If you call the
> > +``clock_set_mul_div()`` function you can specify the clock's
> > +multiplier and divider values. The children of that clock
> > +will all run with a period of ``parent_period * multiplier / divider``.
> > +For instance, if the clock has a frequency of 8MHz and you set its
> > +multiplier to 2 and its divider to 3, the child clocks will run
> > +at 12MHz.
> > +
> > +You can change the multiplier and divider of a clock at runtime,
> > +so you can use this to model clock controller devices which
> > +have guest-programmable frequency multipliers or dividers.
>
> This looks nice!
> Does this imply that if I am going to implement the STM32 RCC (Reset and
> Clock Controller) device, then I should use this new feature?
I haven't looked at the RCC spec in detail, but yeah, I'd expect
that you'd have a device with one (or perhaps more) input clocks
and a lot of output clocks, and as the guest writes to registers
that set divider/multiplier settings you'd use clock_set_mul_div()
to configure the appropriate output clocks.
-- PMM
^ permalink raw reply [flat|nested] 91+ messages in thread
* Re: [PATCH for-6.2 14/25] hw/arm/stm32vldiscovery: Delete trailing blank line
2021-08-12 9:33 ` [PATCH for-6.2 14/25] hw/arm/stm32vldiscovery: Delete trailing blank line Peter Maydell
@ 2021-08-12 12:27 ` Alexandre IOOSS
2021-08-13 1:39 ` Alistair Francis
2021-08-17 9:48 ` Luc Michel
2 siblings, 0 replies; 91+ messages in thread
From: Alexandre IOOSS @ 2021-08-12 12:27 UTC (permalink / raw)
To: Peter Maydell, qemu-arm, qemu-devel
Cc: Damien Hedde, Alistair Francis, Luc Michel, Joel Stanley,
Subbaraya Sundeep
[-- Attachment #1.1: Type: text/plain, Size: 690 bytes --]
On 8/12/21 11:33 AM, Peter Maydell wrote:
> Delete the trailing blank line at the end of the source file.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
> hw/arm/stm32vldiscovery.c | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git a/hw/arm/stm32vldiscovery.c b/hw/arm/stm32vldiscovery.c
> index 07e401a818d..9b79004703b 100644
> --- a/hw/arm/stm32vldiscovery.c
> +++ b/hw/arm/stm32vldiscovery.c
> @@ -65,4 +65,3 @@ static void stm32vldiscovery_machine_init(MachineClass *mc)
> }
>
> DEFINE_MACHINE("stm32vldiscovery", stm32vldiscovery_machine_init)
> -
>
Reviewed-by: Alexandre Iooss <erdnaxe@crans.org>
Thanks,
-- Alexandre
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^ permalink raw reply [flat|nested] 91+ messages in thread
* Re: [PATCH for-6.2 10/25] hw/arm: Don't allocate separate MemoryRegions in stm32 SoC realize
2021-08-12 12:13 ` Alexandre IOOSS
@ 2021-08-12 12:27 ` Peter Maydell
2021-08-15 16:37 ` Philippe Mathieu-Daudé
0 siblings, 1 reply; 91+ messages in thread
From: Peter Maydell @ 2021-08-12 12:27 UTC (permalink / raw)
To: Alexandre IOOSS
Cc: Damien Hedde, Luc Michel, Alistair Francis, QEMU Developers,
Subbaraya Sundeep, qemu-arm, Joel Stanley
On Thu, 12 Aug 2021 at 13:13, Alexandre IOOSS <erdnaxe@crans.org> wrote:
>
> On 8/12/21 11:33 AM, Peter Maydell wrote:
> > In the realize methods of the stm32f100 and stm32f205 SoC objects, we
> > call g_new() to create new MemoryRegion objjects for the sram, flash,
> > and flash_alias. This is unnecessary (and leaves open the
> > possibility of leaking the allocations if we exit from realize with
> > an error). Make these MemoryRegions member fields of the device
> > state struct instead, as stm32f405 already does.
>
> There is a typo in "objjects".
>
> This is something I had issue understanding as I was seeing both
> patterns in the codebase, thank you for making this clear.
Basically if there's a struct that the MemoryRegion can live
in then that's the best place for it. For some board-level code
where we haven't needed to subclass MachineState there is no
convenient struct, so we just g_new(). In a few places like this
one the board-code pattern has been copied into an SoC object.
-- PMM
^ permalink raw reply [flat|nested] 91+ messages in thread
* Re: [PATCH for-6.2 01/25] arm: Move M-profile RAS register block into its own device
2021-08-12 9:33 ` [PATCH for-6.2 01/25] arm: Move M-profile RAS register block into its own device Peter Maydell
2021-08-12 11:08 ` Alexandre IOOSS
@ 2021-08-13 0:59 ` Alistair Francis
2021-08-15 17:30 ` Philippe Mathieu-Daudé
2021-08-17 8:25 ` Luc Michel
3 siblings, 0 replies; 91+ messages in thread
From: Alistair Francis @ 2021-08-13 0:59 UTC (permalink / raw)
To: Peter Maydell
Cc: Damien Hedde, Luc Michel, Alistair Francis,
qemu-devel@nongnu.org Developers, Subbaraya Sundeep, qemu-arm,
Joel Stanley, Alexandre Iooss
On Thu, Aug 12, 2021 at 7:34 PM Peter Maydell <peter.maydell@linaro.org> wrote:
>
> Currently we implement the RAS register block within the NVIC device.
> It isn't really very tightly coupled with the NVIC proper, so instead
> move it out into a sysbus device of its own and have the top level
> ARMv7M container create it and map it into memory at the right
> address.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> include/hw/arm/armv7m.h | 2 +
> include/hw/intc/armv7m_nvic.h | 1 -
> include/hw/misc/armv7m_ras.h | 37 ++++++++++++++
> hw/arm/armv7m.c | 12 +++++
> hw/intc/armv7m_nvic.c | 56 ---------------------
> hw/misc/armv7m_ras.c | 93 +++++++++++++++++++++++++++++++++++
> MAINTAINERS | 2 +
> hw/misc/meson.build | 2 +
> 8 files changed, 148 insertions(+), 57 deletions(-)
> create mode 100644 include/hw/misc/armv7m_ras.h
> create mode 100644 hw/misc/armv7m_ras.c
>
> diff --git a/include/hw/arm/armv7m.h b/include/hw/arm/armv7m.h
> index bc6733c5184..4cae0d7eeaa 100644
> --- a/include/hw/arm/armv7m.h
> +++ b/include/hw/arm/armv7m.h
> @@ -12,6 +12,7 @@
>
> #include "hw/sysbus.h"
> #include "hw/intc/armv7m_nvic.h"
> +#include "hw/misc/armv7m_ras.h"
> #include "target/arm/idau.h"
> #include "qom/object.h"
>
> @@ -58,6 +59,7 @@ struct ARMv7MState {
> NVICState nvic;
> BitBandState bitband[ARMV7M_NUM_BITBANDS];
> ARMCPU *cpu;
> + ARMv7MRAS ras;
>
> /* MemoryRegion we pass to the CPU, with our devices layered on
> * top of the ones the board provides in board_memory.
> diff --git a/include/hw/intc/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h
> index 39c71e15936..33b6d8810c7 100644
> --- a/include/hw/intc/armv7m_nvic.h
> +++ b/include/hw/intc/armv7m_nvic.h
> @@ -83,7 +83,6 @@ struct NVICState {
> MemoryRegion sysreg_ns_mem;
> MemoryRegion systickmem;
> MemoryRegion systick_ns_mem;
> - MemoryRegion ras_mem;
> MemoryRegion container;
> MemoryRegion defaultmem;
>
> diff --git a/include/hw/misc/armv7m_ras.h b/include/hw/misc/armv7m_ras.h
> new file mode 100644
> index 00000000000..f8773e65b14
> --- /dev/null
> +++ b/include/hw/misc/armv7m_ras.h
> @@ -0,0 +1,37 @@
> +/*
> + * Arm M-profile RAS block
> + *
> + * Copyright (c) 2021 Linaro Limited
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 or
> + * (at your option) any later version.
> + */
> +
> +/*
> + * This is a model of the RAS register block of an M-profile CPU
> + * (the registers starting at 0xE0005000 with ERRFRn).
> + *
> + * QEMU interface:
> + * + sysbus MMIO region 0: the register bank
> + *
> + * The QEMU implementation currently provides "minimal RAS" only.
> + */
> +
> +#ifndef HW_MISC_ARMV7M_RAS_H
> +#define HW_MISC_ARMV7M_RAS_H
> +
> +#include "hw/sysbus.h"
> +
> +#define TYPE_ARMV7M_RAS "armv7m-ras"
> +OBJECT_DECLARE_SIMPLE_TYPE(ARMv7MRAS, ARMV7M_RAS)
> +
> +struct ARMv7MRAS {
> + /*< private >*/
> + SysBusDevice parent_obj;
> +
> + /*< public >*/
> + MemoryRegion iomem;
> +};
> +
> +#endif
> diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c
> index 9ce5c30cd5c..8964730d153 100644
> --- a/hw/arm/armv7m.c
> +++ b/hw/arm/armv7m.c
> @@ -231,6 +231,18 @@ static void armv7m_realize(DeviceState *dev, Error **errp)
> memory_region_add_subregion(&s->container, 0xe0000000,
> sysbus_mmio_get_region(sbd, 0));
>
> + /* If the CPU has RAS support, create the RAS register block */
> + if (cpu_isar_feature(aa32_ras, s->cpu)) {
> + object_initialize_child(OBJECT(dev), "armv7m-ras",
> + &s->ras, TYPE_ARMV7M_RAS);
> + sbd = SYS_BUS_DEVICE(&s->ras);
> + if (!sysbus_realize(sbd, errp)) {
> + return;
> + }
> + memory_region_add_subregion_overlap(&s->container, 0xe0005000,
> + sysbus_mmio_get_region(sbd, 0), 1);
> + }
> +
> for (i = 0; i < ARRAY_SIZE(s->bitband); i++) {
> if (s->enable_bitband) {
> Object *obj = OBJECT(&s->bitband[i]);
> diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
> index 1e7ddcb94cb..a5975592dfa 100644
> --- a/hw/intc/armv7m_nvic.c
> +++ b/hw/intc/armv7m_nvic.c
> @@ -2549,56 +2549,6 @@ static const MemoryRegionOps nvic_systick_ops = {
> .endianness = DEVICE_NATIVE_ENDIAN,
> };
>
> -
> -static MemTxResult ras_read(void *opaque, hwaddr addr,
> - uint64_t *data, unsigned size,
> - MemTxAttrs attrs)
> -{
> - if (attrs.user) {
> - return MEMTX_ERROR;
> - }
> -
> - switch (addr) {
> - case 0xe10: /* ERRIIDR */
> - /* architect field = Arm; product/variant/revision 0 */
> - *data = 0x43b;
> - break;
> - case 0xfc8: /* ERRDEVID */
> - /* Minimal RAS: we implement 0 error record indexes */
> - *data = 0;
> - break;
> - default:
> - qemu_log_mask(LOG_UNIMP, "Read RAS register offset 0x%x\n",
> - (uint32_t)addr);
> - *data = 0;
> - break;
> - }
> - return MEMTX_OK;
> -}
> -
> -static MemTxResult ras_write(void *opaque, hwaddr addr,
> - uint64_t value, unsigned size,
> - MemTxAttrs attrs)
> -{
> - if (attrs.user) {
> - return MEMTX_ERROR;
> - }
> -
> - switch (addr) {
> - default:
> - qemu_log_mask(LOG_UNIMP, "Write to RAS register offset 0x%x\n",
> - (uint32_t)addr);
> - break;
> - }
> - return MEMTX_OK;
> -}
> -
> -static const MemoryRegionOps ras_ops = {
> - .read_with_attrs = ras_read,
> - .write_with_attrs = ras_write,
> - .endianness = DEVICE_NATIVE_ENDIAN,
> -};
> -
> /*
> * Unassigned portions of the PPB space are RAZ/WI for privileged
> * accesses, and fault for non-privileged accesses.
> @@ -2946,12 +2896,6 @@ static void armv7m_nvic_realize(DeviceState *dev, Error **errp)
> &s->systick_ns_mem, 1);
> }
>
> - if (cpu_isar_feature(aa32_ras, s->cpu)) {
> - memory_region_init_io(&s->ras_mem, OBJECT(s),
> - &ras_ops, s, "nvic_ras", 0x1000);
> - memory_region_add_subregion(&s->container, 0x5000, &s->ras_mem);
> - }
> -
> sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->container);
> }
>
> diff --git a/hw/misc/armv7m_ras.c b/hw/misc/armv7m_ras.c
> new file mode 100644
> index 00000000000..a2b4f4b8dc8
> --- /dev/null
> +++ b/hw/misc/armv7m_ras.c
> @@ -0,0 +1,93 @@
> +/*
> + * Arm M-profile RAS block
> + *
> + * Copyright (c) 2021 Linaro Limited
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 or
> + * (at your option) any later version.
> + */
> +
> +#include "qemu/osdep.h"
> +#include "hw/misc/armv7m_ras.h"
> +#include "qemu/log.h"
> +
> +static MemTxResult ras_read(void *opaque, hwaddr addr,
> + uint64_t *data, unsigned size,
> + MemTxAttrs attrs)
> +{
> + if (attrs.user) {
> + return MEMTX_ERROR;
> + }
> +
> + switch (addr) {
> + case 0xe10: /* ERRIIDR */
> + /* architect field = Arm; product/variant/revision 0 */
> + *data = 0x43b;
> + break;
> + case 0xfc8: /* ERRDEVID */
> + /* Minimal RAS: we implement 0 error record indexes */
> + *data = 0;
> + break;
> + default:
> + qemu_log_mask(LOG_UNIMP, "Read RAS register offset 0x%x\n",
> + (uint32_t)addr);
> + *data = 0;
> + break;
> + }
> + return MEMTX_OK;
> +}
> +
> +static MemTxResult ras_write(void *opaque, hwaddr addr,
> + uint64_t value, unsigned size,
> + MemTxAttrs attrs)
> +{
> + if (attrs.user) {
> + return MEMTX_ERROR;
> + }
> +
> + switch (addr) {
> + default:
> + qemu_log_mask(LOG_UNIMP, "Write to RAS register offset 0x%x\n",
> + (uint32_t)addr);
> + break;
> + }
> + return MEMTX_OK;
> +}
> +
> +static const MemoryRegionOps ras_ops = {
> + .read_with_attrs = ras_read,
> + .write_with_attrs = ras_write,
> + .endianness = DEVICE_NATIVE_ENDIAN,
> +};
> +
> +
> +static void armv7m_ras_init(Object *obj)
> +{
> + SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
> + ARMv7MRAS *s = ARMV7M_RAS(obj);
> +
> + memory_region_init_io(&s->iomem, obj, &ras_ops,
> + s, "armv7m-ras", 0x1000);
> + sysbus_init_mmio(sbd, &s->iomem);
> +}
> +
> +static void armv7m_ras_class_init(ObjectClass *klass, void *data)
> +{
> + /* This device has no state: no need for vmstate or reset */
> +}
> +
> +static const TypeInfo armv7m_ras_info = {
> + .name = TYPE_ARMV7M_RAS,
> + .parent = TYPE_SYS_BUS_DEVICE,
> + .instance_size = sizeof(ARMv7MRAS),
> + .instance_init = armv7m_ras_init,
> + .class_init = armv7m_ras_class_init,
> +};
> +
> +static void armv7m_ras_register_types(void)
> +{
> + type_register_static(&armv7m_ras_info);
> +}
> +
> +type_init(armv7m_ras_register_types);
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 37b1a8e4428..3cac393bb48 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -617,6 +617,7 @@ F: hw/intc/gic_internal.h
> F: hw/misc/a9scu.c
> F: hw/misc/arm11scu.c
> F: hw/misc/arm_l2x0.c
> +F: hw/misc/armv7m_ras.c
> F: hw/timer/a9gtimer*
> F: hw/timer/arm*
> F: include/hw/arm/arm*.h
> @@ -626,6 +627,7 @@ F: include/hw/misc/arm11scu.h
> F: include/hw/timer/a9gtimer.h
> F: include/hw/timer/arm_mptimer.h
> F: include/hw/timer/armv7m_systick.h
> +F: include/hw/misc/armv7m_ras.h
> F: tests/qtest/test-arm-mptimer.c
>
> Exynos
> diff --git a/hw/misc/meson.build b/hw/misc/meson.build
> index a53b849a5a0..3f41a3a5b27 100644
> --- a/hw/misc/meson.build
> +++ b/hw/misc/meson.build
> @@ -17,6 +17,8 @@ softmmu_ss.add(when: 'CONFIG_INTEGRATOR_DEBUG', if_true: files('arm_integrator_d
> softmmu_ss.add(when: 'CONFIG_A9SCU', if_true: files('a9scu.c'))
> softmmu_ss.add(when: 'CONFIG_ARM11SCU', if_true: files('arm11scu.c'))
>
> +softmmu_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('armv7m_ras.c'))
> +
> # Mac devices
> softmmu_ss.add(when: 'CONFIG_MOS6522', if_true: files('mos6522.c'))
>
> --
> 2.20.1
>
>
^ permalink raw reply [flat|nested] 91+ messages in thread
* Re: [PATCH for-6.2 02/25] arm: Move systick device creation from NVIC to ARMv7M object
2021-08-12 9:33 ` [PATCH for-6.2 02/25] arm: Move systick device creation from NVIC to ARMv7M object Peter Maydell
@ 2021-08-13 1:23 ` Alistair Francis
2021-08-17 9:24 ` Luc Michel
1 sibling, 0 replies; 91+ messages in thread
From: Alistair Francis @ 2021-08-13 1:23 UTC (permalink / raw)
To: Peter Maydell
Cc: Damien Hedde, Luc Michel, Alistair Francis,
qemu-devel@nongnu.org Developers, Subbaraya Sundeep, qemu-arm,
Joel Stanley, Alexandre Iooss
On Thu, Aug 12, 2021 at 7:36 PM Peter Maydell <peter.maydell@linaro.org> wrote:
>
> There's no particular reason why the NVIC should be owning the
> SysTick device objects; move them into the ARMv7M container object
> instead, as part of consolidating the "create the devices which are
> built into an M-profile CPU and map them into their architected
> locations in the address space" work into one place.
>
> This involves temporarily creating a duplicate copy of the
> nvic_sysreg_ns_ops struct and its read/write functions (renamed as
> v7m_sysreg_ns_*), but we will delete the NVIC's copy of this code in
> a subsequent patch.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> include/hw/arm/armv7m.h | 12 ++++
> include/hw/intc/armv7m_nvic.h | 4 --
> hw/arm/armv7m.c | 125 ++++++++++++++++++++++++++++++++++
> hw/intc/armv7m_nvic.c | 73 --------------------
> 4 files changed, 137 insertions(+), 77 deletions(-)
>
> diff --git a/include/hw/arm/armv7m.h b/include/hw/arm/armv7m.h
> index 4cae0d7eeaa..360c35c5fb2 100644
> --- a/include/hw/arm/armv7m.h
> +++ b/include/hw/arm/armv7m.h
> @@ -60,11 +60,23 @@ struct ARMv7MState {
> BitBandState bitband[ARMV7M_NUM_BITBANDS];
> ARMCPU *cpu;
> ARMv7MRAS ras;
> + SysTickState systick[M_REG_NUM_BANKS];
>
> /* MemoryRegion we pass to the CPU, with our devices layered on
> * top of the ones the board provides in board_memory.
> */
> MemoryRegion container;
> + /*
> + * MemoryRegion which passes the transaction to either the S or the
> + * NS systick device depending on the transaction attributes
> + */
> + MemoryRegion systickmem;
> + /*
> + * MemoryRegion which enforces the S/NS handling of the systick
> + * device NS alias region and passes the transaction to the
> + * NS systick device if appropriate.
> + */
> + MemoryRegion systick_ns_mem;
>
> /* Properties */
> char *cpu_type;
> diff --git a/include/hw/intc/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h
> index 33b6d8810c7..6a6a99090c7 100644
> --- a/include/hw/intc/armv7m_nvic.h
> +++ b/include/hw/intc/armv7m_nvic.h
> @@ -81,16 +81,12 @@ struct NVICState {
>
> MemoryRegion sysregmem;
> MemoryRegion sysreg_ns_mem;
> - MemoryRegion systickmem;
> - MemoryRegion systick_ns_mem;
> MemoryRegion container;
> MemoryRegion defaultmem;
>
> uint32_t num_irq;
> qemu_irq excpout;
> qemu_irq sysresetreq;
> -
> - SysTickState systick[M_REG_NUM_BANKS];
> };
>
> #endif
> diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c
> index 8964730d153..364ac069702 100644
> --- a/hw/arm/armv7m.c
> +++ b/hw/arm/armv7m.c
> @@ -124,6 +124,85 @@ static const hwaddr bitband_output_addr[ARMV7M_NUM_BITBANDS] = {
> 0x22000000, 0x42000000
> };
>
> +static MemTxResult v7m_sysreg_ns_write(void *opaque, hwaddr addr,
> + uint64_t value, unsigned size,
> + MemTxAttrs attrs)
> +{
> + MemoryRegion *mr = opaque;
> +
> + if (attrs.secure) {
> + /* S accesses to the alias act like NS accesses to the real region */
> + attrs.secure = 0;
> + return memory_region_dispatch_write(mr, addr, value,
> + size_memop(size) | MO_TE, attrs);
> + } else {
> + /* NS attrs are RAZ/WI for privileged, and BusFault for user */
> + if (attrs.user) {
> + return MEMTX_ERROR;
> + }
> + return MEMTX_OK;
> + }
> +}
> +
> +static MemTxResult v7m_sysreg_ns_read(void *opaque, hwaddr addr,
> + uint64_t *data, unsigned size,
> + MemTxAttrs attrs)
> +{
> + MemoryRegion *mr = opaque;
> +
> + if (attrs.secure) {
> + /* S accesses to the alias act like NS accesses to the real region */
> + attrs.secure = 0;
> + return memory_region_dispatch_read(mr, addr, data,
> + size_memop(size) | MO_TE, attrs);
> + } else {
> + /* NS attrs are RAZ/WI for privileged, and BusFault for user */
> + if (attrs.user) {
> + return MEMTX_ERROR;
> + }
> + *data = 0;
> + return MEMTX_OK;
> + }
> +}
> +
> +static const MemoryRegionOps v7m_sysreg_ns_ops = {
> + .read_with_attrs = v7m_sysreg_ns_read,
> + .write_with_attrs = v7m_sysreg_ns_write,
> + .endianness = DEVICE_NATIVE_ENDIAN,
> +};
> +
> +static MemTxResult v7m_systick_write(void *opaque, hwaddr addr,
> + uint64_t value, unsigned size,
> + MemTxAttrs attrs)
> +{
> + ARMv7MState *s = opaque;
> + MemoryRegion *mr;
> +
> + /* Direct the access to the correct systick */
> + mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->systick[attrs.secure]), 0);
> + return memory_region_dispatch_write(mr, addr, value,
> + size_memop(size) | MO_TE, attrs);
> +}
> +
> +static MemTxResult v7m_systick_read(void *opaque, hwaddr addr,
> + uint64_t *data, unsigned size,
> + MemTxAttrs attrs)
> +{
> + ARMv7MState *s = opaque;
> + MemoryRegion *mr;
> +
> + /* Direct the access to the correct systick */
> + mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->systick[attrs.secure]), 0);
> + return memory_region_dispatch_read(mr, addr, data, size_memop(size) | MO_TE,
> + attrs);
> +}
> +
> +static const MemoryRegionOps v7m_systick_ops = {
> + .read_with_attrs = v7m_systick_read,
> + .write_with_attrs = v7m_systick_write,
> + .endianness = DEVICE_NATIVE_ENDIAN,
> +};
> +
> static void armv7m_instance_init(Object *obj)
> {
> ARMv7MState *s = ARMV7M(obj);
> @@ -137,6 +216,13 @@ static void armv7m_instance_init(Object *obj)
> object_property_add_alias(obj, "num-irq",
> OBJECT(&s->nvic), "num-irq");
>
> + object_initialize_child(obj, "systick-reg-ns", &s->systick[M_REG_NS],
> + TYPE_SYSTICK);
> + /*
> + * We can't initialize the secure systick here, as we don't know
> + * yet if we need it.
> + */
> +
> for (i = 0; i < ARRAY_SIZE(s->bitband); i++) {
> object_initialize_child(obj, "bitband[*]", &s->bitband[i],
> TYPE_BITBAND);
> @@ -231,6 +317,45 @@ static void armv7m_realize(DeviceState *dev, Error **errp)
> memory_region_add_subregion(&s->container, 0xe0000000,
> sysbus_mmio_get_region(sbd, 0));
>
> + /* Create and map the systick devices */
> + if (!sysbus_realize(SYS_BUS_DEVICE(&s->systick[M_REG_NS]), errp)) {
> + return;
> + }
> + sysbus_connect_irq(SYS_BUS_DEVICE(&s->systick[M_REG_NS]), 0,
> + qdev_get_gpio_in_named(DEVICE(&s->nvic),
> + "systick-trigger", M_REG_NS));
> +
> + if (arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY)) {
> + /*
> + * We couldn't init the secure systick device in instance_init
> + * as we didn't know then if the CPU had the security extensions;
> + * so we have to do it here.
> + */
> + object_initialize_child(OBJECT(dev), "systick-reg-s",
> + &s->systick[M_REG_S], TYPE_SYSTICK);
> +
> + if (!sysbus_realize(SYS_BUS_DEVICE(&s->systick[M_REG_S]), errp)) {
> + return;
> + }
> + sysbus_connect_irq(SYS_BUS_DEVICE(&s->systick[M_REG_S]), 0,
> + qdev_get_gpio_in_named(DEVICE(&s->nvic),
> + "systick-trigger", M_REG_S));
> + }
> +
> + memory_region_init_io(&s->systickmem, OBJECT(s),
> + &v7m_systick_ops, s,
> + "v7m_systick", 0xe0);
> +
> + memory_region_add_subregion_overlap(&s->container, 0xe000e010,
> + &s->systickmem, 1);
> + if (arm_feature(&s->cpu->env, ARM_FEATURE_V8)) {
> + memory_region_init_io(&s->systick_ns_mem, OBJECT(s),
> + &v7m_sysreg_ns_ops, &s->systickmem,
> + "v7m_systick_ns", 0xe0);
> + memory_region_add_subregion_overlap(&s->container, 0xe002e010,
> + &s->systick_ns_mem, 1);
> + }
> +
> /* If the CPU has RAS support, create the RAS register block */
> if (cpu_isar_feature(aa32_ras, s->cpu)) {
> object_initialize_child(OBJECT(dev), "armv7m-ras",
> diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
> index a5975592dfa..2b3e79a3da9 100644
> --- a/hw/intc/armv7m_nvic.c
> +++ b/hw/intc/armv7m_nvic.c
> @@ -2517,38 +2517,6 @@ static const MemoryRegionOps nvic_sysreg_ns_ops = {
> .endianness = DEVICE_NATIVE_ENDIAN,
> };
>
> -static MemTxResult nvic_systick_write(void *opaque, hwaddr addr,
> - uint64_t value, unsigned size,
> - MemTxAttrs attrs)
> -{
> - NVICState *s = opaque;
> - MemoryRegion *mr;
> -
> - /* Direct the access to the correct systick */
> - mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->systick[attrs.secure]), 0);
> - return memory_region_dispatch_write(mr, addr, value,
> - size_memop(size) | MO_TE, attrs);
> -}
> -
> -static MemTxResult nvic_systick_read(void *opaque, hwaddr addr,
> - uint64_t *data, unsigned size,
> - MemTxAttrs attrs)
> -{
> - NVICState *s = opaque;
> - MemoryRegion *mr;
> -
> - /* Direct the access to the correct systick */
> - mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->systick[attrs.secure]), 0);
> - return memory_region_dispatch_read(mr, addr, data, size_memop(size) | MO_TE,
> - attrs);
> -}
> -
> -static const MemoryRegionOps nvic_systick_ops = {
> - .read_with_attrs = nvic_systick_read,
> - .write_with_attrs = nvic_systick_write,
> - .endianness = DEVICE_NATIVE_ENDIAN,
> -};
> -
> /*
> * Unassigned portions of the PPB space are RAZ/WI for privileged
> * accesses, and fault for non-privileged accesses.
> @@ -2801,29 +2769,6 @@ static void armv7m_nvic_realize(DeviceState *dev, Error **errp)
>
> s->num_prio_bits = arm_feature(&s->cpu->env, ARM_FEATURE_V7) ? 8 : 2;
>
> - if (!sysbus_realize(SYS_BUS_DEVICE(&s->systick[M_REG_NS]), errp)) {
> - return;
> - }
> - sysbus_connect_irq(SYS_BUS_DEVICE(&s->systick[M_REG_NS]), 0,
> - qdev_get_gpio_in_named(dev, "systick-trigger",
> - M_REG_NS));
> -
> - if (arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY)) {
> - /* We couldn't init the secure systick device in instance_init
> - * as we didn't know then if the CPU had the security extensions;
> - * so we have to do it here.
> - */
> - object_initialize_child(OBJECT(dev), "systick-reg-s",
> - &s->systick[M_REG_S], TYPE_SYSTICK);
> -
> - if (!sysbus_realize(SYS_BUS_DEVICE(&s->systick[M_REG_S]), errp)) {
> - return;
> - }
> - sysbus_connect_irq(SYS_BUS_DEVICE(&s->systick[M_REG_S]), 0,
> - qdev_get_gpio_in_named(dev, "systick-trigger",
> - M_REG_S));
> - }
> -
> /*
> * This device provides a single sysbus memory region which
> * represents the whole of the "System PPB" space. This is the
> @@ -2877,23 +2822,11 @@ static void armv7m_nvic_realize(DeviceState *dev, Error **errp)
> "nvic_sysregs", 0x1000);
> memory_region_add_subregion(&s->container, 0xe000, &s->sysregmem);
>
> - memory_region_init_io(&s->systickmem, OBJECT(s),
> - &nvic_systick_ops, s,
> - "nvic_systick", 0xe0);
> -
> - memory_region_add_subregion_overlap(&s->container, 0xe010,
> - &s->systickmem, 1);
> -
> if (arm_feature(&s->cpu->env, ARM_FEATURE_V8)) {
> memory_region_init_io(&s->sysreg_ns_mem, OBJECT(s),
> &nvic_sysreg_ns_ops, &s->sysregmem,
> "nvic_sysregs_ns", 0x1000);
> memory_region_add_subregion(&s->container, 0x2e000, &s->sysreg_ns_mem);
> - memory_region_init_io(&s->systick_ns_mem, OBJECT(s),
> - &nvic_sysreg_ns_ops, &s->systickmem,
> - "nvic_systick_ns", 0xe0);
> - memory_region_add_subregion_overlap(&s->container, 0x2e010,
> - &s->systick_ns_mem, 1);
> }
>
> sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->container);
> @@ -2905,12 +2838,6 @@ static void armv7m_nvic_instance_init(Object *obj)
> NVICState *nvic = NVIC(obj);
> SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
>
> - object_initialize_child(obj, "systick-reg-ns", &nvic->systick[M_REG_NS],
> - TYPE_SYSTICK);
> - /* We can't initialize the secure systick here, as we don't know
> - * yet if we need it.
> - */
> -
> sysbus_init_irq(sbd, &nvic->excpout);
> qdev_init_gpio_out_named(dev, &nvic->sysresetreq, "SYSRESETREQ", 1);
> qdev_init_gpio_in_named(dev, nvic_systick_trigger, "systick-trigger",
> --
> 2.20.1
>
>
^ permalink raw reply [flat|nested] 91+ messages in thread
* Re: [PATCH for-6.2 04/25] hw/timer/armv7m_systick: Add usual QEMU interface comment
2021-08-12 9:33 ` [PATCH for-6.2 04/25] hw/timer/armv7m_systick: Add usual QEMU interface comment Peter Maydell
@ 2021-08-13 1:26 ` Alistair Francis
2021-08-17 9:29 ` Luc Michel
1 sibling, 0 replies; 91+ messages in thread
From: Alistair Francis @ 2021-08-13 1:26 UTC (permalink / raw)
To: Peter Maydell
Cc: Damien Hedde, Luc Michel, Alistair Francis,
qemu-devel@nongnu.org Developers, Subbaraya Sundeep, qemu-arm,
Joel Stanley, Alexandre Iooss
On Thu, Aug 12, 2021 at 7:34 PM Peter Maydell <peter.maydell@linaro.org> wrote:
>
> Add the usual-style QEMU interface comment documenting what
> properties, etc, this device exposes.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> include/hw/timer/armv7m_systick.h | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/include/hw/timer/armv7m_systick.h b/include/hw/timer/armv7m_systick.h
> index 84496faaf96..685fc5bc0d7 100644
> --- a/include/hw/timer/armv7m_systick.h
> +++ b/include/hw/timer/armv7m_systick.h
> @@ -20,6 +20,13 @@
>
> OBJECT_DECLARE_SIMPLE_TYPE(SysTickState, SYSTICK)
>
> +/*
> + * QEMU interface:
> + * + sysbus MMIO region 0 is the register interface (covering
> + * the registers which are mapped at address 0xE000E010)
> + * + sysbus IRQ 0 is the interrupt line to the NVIC
> + */
> +
> struct SysTickState {
> /*< private >*/
> SysBusDevice parent_obj;
> --
> 2.20.1
>
>
^ permalink raw reply [flat|nested] 91+ messages in thread
* Re: [PATCH for-6.2 05/25] hw/timer/armv7m_systick: Add input clocks
2021-08-12 9:33 ` [PATCH for-6.2 05/25] hw/timer/armv7m_systick: Add input clocks Peter Maydell
@ 2021-08-13 1:27 ` Alistair Francis
2021-08-17 9:32 ` Luc Michel
1 sibling, 0 replies; 91+ messages in thread
From: Alistair Francis @ 2021-08-13 1:27 UTC (permalink / raw)
To: Peter Maydell
Cc: Damien Hedde, Luc Michel, Alistair Francis,
qemu-devel@nongnu.org Developers, Subbaraya Sundeep, qemu-arm,
Joel Stanley, Alexandre Iooss
On Thu, Aug 12, 2021 at 7:36 PM Peter Maydell <peter.maydell@linaro.org> wrote:
>
> The v7M systick timer can be programmed to run from either of
> two clocks:
> * an "external reference clock" (when SYST_CSR.CLKSOURCE == 0)
> * the main CPU clock (when SYST_CSR.CLKSOURCE == 1)
>
> Our implementation currently hardwires the external reference clock
> to be 1MHz, and allows boards to set the main CPU clock frequency via
> the global 'system_clock_scale'. (Most boards set that to a constant
> value; the Stellaris boards allow the guest to reprogram it via the
> board-specific RCC registers).
>
> As the first step in converting this to use the Clock infrastructure,
> add input clocks to the systick device for the reference clock and
> the CPU clock. The device implementation ignores them; once we have
> made all the users of the device correctly wire up the new Clocks we
> will switch the implementation to use them and ignore the old
> system_clock_scale.
>
> This is a migration compat break for all M-profile boards, because of
> the addition of the new clock objects to the vmstate struct.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> include/hw/timer/armv7m_systick.h | 7 +++++++
> hw/timer/armv7m_systick.c | 10 ++++++++--
> 2 files changed, 15 insertions(+), 2 deletions(-)
>
> diff --git a/include/hw/timer/armv7m_systick.h b/include/hw/timer/armv7m_systick.h
> index 685fc5bc0d7..38adf8d274e 100644
> --- a/include/hw/timer/armv7m_systick.h
> +++ b/include/hw/timer/armv7m_systick.h
> @@ -15,6 +15,7 @@
> #include "hw/sysbus.h"
> #include "qom/object.h"
> #include "hw/ptimer.h"
> +#include "hw/clock.h"
>
> #define TYPE_SYSTICK "armv7m_systick"
>
> @@ -25,6 +26,10 @@ OBJECT_DECLARE_SIMPLE_TYPE(SysTickState, SYSTICK)
> * + sysbus MMIO region 0 is the register interface (covering
> * the registers which are mapped at address 0xE000E010)
> * + sysbus IRQ 0 is the interrupt line to the NVIC
> + * + Clock input "refclk" is the external reference clock
> + * (used when SYST_CSR.CLKSOURCE == 0)
> + * + Clock input "cpuclk" is the main CPU clock
> + * (used when SYST_CSR.CLKSOURCE == 1)
> */
>
> struct SysTickState {
> @@ -38,6 +43,8 @@ struct SysTickState {
> ptimer_state *ptimer;
> MemoryRegion iomem;
> qemu_irq irq;
> + Clock *refclk;
> + Clock *cpuclk;
> };
>
> /*
> diff --git a/hw/timer/armv7m_systick.c b/hw/timer/armv7m_systick.c
> index 2f192011eb0..e43f74114e8 100644
> --- a/hw/timer/armv7m_systick.c
> +++ b/hw/timer/armv7m_systick.c
> @@ -14,6 +14,7 @@
> #include "migration/vmstate.h"
> #include "hw/irq.h"
> #include "hw/sysbus.h"
> +#include "hw/qdev-clock.h"
> #include "qemu/timer.h"
> #include "qemu/log.h"
> #include "qemu/module.h"
> @@ -201,6 +202,9 @@ static void systick_instance_init(Object *obj)
> memory_region_init_io(&s->iomem, obj, &systick_ops, s, "systick", 0xe0);
> sysbus_init_mmio(sbd, &s->iomem);
> sysbus_init_irq(sbd, &s->irq);
> +
> + s->refclk = qdev_init_clock_in(DEVICE(obj), "refclk", NULL, NULL, 0);
> + s->cpuclk = qdev_init_clock_in(DEVICE(obj), "cpuclk", NULL, NULL, 0);
> }
>
> static void systick_realize(DeviceState *dev, Error **errp)
> @@ -215,9 +219,11 @@ static void systick_realize(DeviceState *dev, Error **errp)
>
> static const VMStateDescription vmstate_systick = {
> .name = "armv7m_systick",
> - .version_id = 2,
> - .minimum_version_id = 2,
> + .version_id = 3,
> + .minimum_version_id = 3,
> .fields = (VMStateField[]) {
> + VMSTATE_CLOCK(refclk, SysTickState),
> + VMSTATE_CLOCK(cpuclk, SysTickState),
> VMSTATE_UINT32(control, SysTickState),
> VMSTATE_INT64(tick, SysTickState),
> VMSTATE_PTIMER(ptimer, SysTickState),
> --
> 2.20.1
>
>
^ permalink raw reply [flat|nested] 91+ messages in thread
* Re: [PATCH for-6.2 06/25] hw/arm/armv7m: Create input clocks
2021-08-12 9:33 ` [PATCH for-6.2 06/25] hw/arm/armv7m: Create " Peter Maydell
@ 2021-08-13 1:28 ` Alistair Francis
2021-08-17 9:34 ` Luc Michel
1 sibling, 0 replies; 91+ messages in thread
From: Alistair Francis @ 2021-08-13 1:28 UTC (permalink / raw)
To: Peter Maydell
Cc: Damien Hedde, Luc Michel, Alistair Francis,
qemu-devel@nongnu.org Developers, Subbaraya Sundeep, qemu-arm,
Joel Stanley, Alexandre Iooss
On Thu, Aug 12, 2021 at 7:38 PM Peter Maydell <peter.maydell@linaro.org> wrote:
>
> Create input clocks on the armv7m container object which pass through
> to the systick timers, so that users of the armv7m object can specify
> the clocks being used.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> include/hw/arm/armv7m.h | 6 ++++++
> hw/arm/armv7m.c | 23 +++++++++++++++++++++++
> 2 files changed, 29 insertions(+)
>
> diff --git a/include/hw/arm/armv7m.h b/include/hw/arm/armv7m.h
> index fe8b248a6c6..b7ba0ff409c 100644
> --- a/include/hw/arm/armv7m.h
> +++ b/include/hw/arm/armv7m.h
> @@ -15,6 +15,7 @@
> #include "hw/misc/armv7m_ras.h"
> #include "target/arm/idau.h"
> #include "qom/object.h"
> +#include "hw/clock.h"
>
> #define TYPE_BITBAND "ARM-bitband-memory"
> OBJECT_DECLARE_SIMPLE_TYPE(BitBandState, BITBAND)
> @@ -51,6 +52,8 @@ OBJECT_DECLARE_SIMPLE_TYPE(ARMv7MState, ARMV7M)
> * + Property "vfp": enable VFP (forwarded to CPU object)
> * + Property "dsp": enable DSP (forwarded to CPU object)
> * + Property "enable-bitband": expose bitbanded IO
> + * + Clock input "refclk" is the external reference clock for the systick timers
> + * + Clock input "cpuclk" is the main CPU clock
> */
> struct ARMv7MState {
> /*< private >*/
> @@ -82,6 +85,9 @@ struct ARMv7MState {
> /* MR providing default PPB behaviour */
> MemoryRegion defaultmem;
>
> + Clock *refclk;
> + Clock *cpuclk;
> +
> /* Properties */
> char *cpu_type;
> /* MemoryRegion the board provides to us (with its devices, RAM, etc) */
> diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c
> index 7e7fb7a3ad3..db1bfa98df0 100644
> --- a/hw/arm/armv7m.c
> +++ b/hw/arm/armv7m.c
> @@ -14,12 +14,14 @@
> #include "hw/arm/boot.h"
> #include "hw/loader.h"
> #include "hw/qdev-properties.h"
> +#include "hw/qdev-clock.h"
> #include "elf.h"
> #include "sysemu/reset.h"
> #include "qemu/error-report.h"
> #include "qemu/module.h"
> #include "qemu/log.h"
> #include "target/arm/idau.h"
> +#include "migration/vmstate.h"
>
> /* Bitbanded IO. Each word corresponds to a single bit. */
>
> @@ -265,6 +267,9 @@ static void armv7m_instance_init(Object *obj)
> object_initialize_child(obj, "bitband[*]", &s->bitband[i],
> TYPE_BITBAND);
> }
> +
> + s->refclk = qdev_init_clock_in(DEVICE(obj), "refclk", NULL, NULL, 0);
> + s->cpuclk = qdev_init_clock_in(DEVICE(obj), "cpuclk", NULL, NULL, 0);
> }
>
> static void armv7m_realize(DeviceState *dev, Error **errp)
> @@ -416,6 +421,8 @@ static void armv7m_realize(DeviceState *dev, Error **errp)
> }
>
> /* Create and map the systick devices */
> + qdev_connect_clock_in(DEVICE(&s->systick[M_REG_NS]), "refclk", s->refclk);
> + qdev_connect_clock_in(DEVICE(&s->systick[M_REG_NS]), "cpuclk", s->cpuclk);
> if (!sysbus_realize(SYS_BUS_DEVICE(&s->systick[M_REG_NS]), errp)) {
> return;
> }
> @@ -431,6 +438,10 @@ static void armv7m_realize(DeviceState *dev, Error **errp)
> */
> object_initialize_child(OBJECT(dev), "systick-reg-s",
> &s->systick[M_REG_S], TYPE_SYSTICK);
> + qdev_connect_clock_in(DEVICE(&s->systick[M_REG_S]), "refclk",
> + s->refclk);
> + qdev_connect_clock_in(DEVICE(&s->systick[M_REG_S]), "cpuclk",
> + s->cpuclk);
>
> if (!sysbus_realize(SYS_BUS_DEVICE(&s->systick[M_REG_S]), errp)) {
> return;
> @@ -504,11 +515,23 @@ static Property armv7m_properties[] = {
> DEFINE_PROP_END_OF_LIST(),
> };
>
> +static const VMStateDescription vmstate_armv7m = {
> + .name = "armv7m",
> + .version_id = 1,
> + .minimum_version_id = 1,
> + .fields = (VMStateField[]) {
> + VMSTATE_CLOCK(refclk, SysTickState),
> + VMSTATE_CLOCK(cpuclk, SysTickState),
> + VMSTATE_END_OF_LIST()
> + }
> +};
> +
> static void armv7m_class_init(ObjectClass *klass, void *data)
> {
> DeviceClass *dc = DEVICE_CLASS(klass);
>
> dc->realize = armv7m_realize;
> + dc->vmsd = &vmstate_armv7m;
> device_class_set_props(dc, armv7m_properties);
> }
>
> --
> 2.20.1
>
>
^ permalink raw reply [flat|nested] 91+ messages in thread
* Re: [PATCH for-6.2 07/25] armsse: Wire up systick cpuclk clock
2021-08-12 9:33 ` [PATCH for-6.2 07/25] armsse: Wire up systick cpuclk clock Peter Maydell
@ 2021-08-13 1:29 ` Alistair Francis
2021-08-17 9:36 ` Luc Michel
1 sibling, 0 replies; 91+ messages in thread
From: Alistair Francis @ 2021-08-13 1:29 UTC (permalink / raw)
To: Peter Maydell
Cc: Damien Hedde, Luc Michel, Alistair Francis,
qemu-devel@nongnu.org Developers, Subbaraya Sundeep, qemu-arm,
Joel Stanley, Alexandre Iooss
On Thu, Aug 12, 2021 at 7:42 PM Peter Maydell <peter.maydell@linaro.org> wrote:
>
> Wire up the cpuclk for the systick devices to the SSE object's
> existing mainclk clock.
>
> We do not wire up the refclk because the SSE subsystems do not
> provide a refclk. (This is documented in the IoTKit and SSE-200
> TRMs; the SSE-300 TRM doesn't mention it but we assume it follows the
> same approach.) When we update the systick device later to honour "no
> refclk connected" this will fix a minor emulation inaccuracy for the
> SSE-based boards.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> hw/arm/armsse.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c
> index a1456cb0f42..70b52c3d4b9 100644
> --- a/hw/arm/armsse.c
> +++ b/hw/arm/armsse.c
> @@ -995,6 +995,9 @@ static void armsse_realize(DeviceState *dev, Error **errp)
> int j;
> char *gpioname;
>
> + qdev_connect_clock_in(cpudev, "cpuclk", s->mainclk);
> + /* The SSE subsystems do not wire up a systick refclk */
> +
> qdev_prop_set_uint32(cpudev, "num-irq", s->exp_numirq + NUM_SSE_IRQS);
> /*
> * In real hardware the initial Secure VTOR is set from the INITSVTOR*
> --
> 2.20.1
>
>
^ permalink raw reply [flat|nested] 91+ messages in thread
* Re: [PATCH for-6.2 09/25] clock: Provide builtin multiplier/divider
2021-08-12 9:33 ` [PATCH for-6.2 09/25] clock: Provide builtin multiplier/divider Peter Maydell
2021-08-12 12:08 ` Alexandre IOOSS
@ 2021-08-13 1:33 ` Alistair Francis
2021-08-15 16:32 ` Philippe Mathieu-Daudé
` (2 subsequent siblings)
4 siblings, 0 replies; 91+ messages in thread
From: Alistair Francis @ 2021-08-13 1:33 UTC (permalink / raw)
To: Peter Maydell
Cc: Damien Hedde, Luc Michel, Alistair Francis,
qemu-devel@nongnu.org Developers, Subbaraya Sundeep, qemu-arm,
Joel Stanley, Alexandre Iooss
On Thu, Aug 12, 2021 at 7:38 PM Peter Maydell <peter.maydell@linaro.org> wrote:
>
> It is quite common for a clock tree to involve possibly programmable
> clock multipliers or dividers, where the frequency of a clock is for
> instance divided by 8 to produce a slower clock to feed to a
> particular device.
>
> Currently we provide no convenient mechanism for modelling this. You
> can implement it by having an input Clock and an output Clock, and
> manually setting the period of the output clock in the period-changed
> callback of the input clock, but that's quite clunky.
>
> This patch adds support in the Clock objects themselves for setting a
> multiplier or divider. The effect of setting this on a clock is that
> when the clock's period is changed, all the children of the clock are
> set to period * multiplier / divider, rather than being set to the
> same period as the parent clock.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
> docs/devel/clocks.rst | 23 +++++++++++++++++++++++
> include/hw/clock.h | 29 +++++++++++++++++++++++++++++
> hw/core/clock-vmstate.c | 24 +++++++++++++++++++++++-
> hw/core/clock.c | 29 +++++++++++++++++++++++++----
> 4 files changed, 100 insertions(+), 5 deletions(-)
>
> diff --git a/docs/devel/clocks.rst b/docs/devel/clocks.rst
> index 956bd147ea0..430fbd842e5 100644
> --- a/docs/devel/clocks.rst
> +++ b/docs/devel/clocks.rst
> @@ -260,6 +260,29 @@ clocks get the new clock period value: *Clock 2*, *Clock 3* and *Clock 4*.
> It is not possible to disconnect a clock or to change the clock connection
> after it is connected.
>
> +Clock multiplier and divider settings
> +-------------------------------------
> +
> +By default, when clocks are connected together, the child
> +clocks run with the same period as their source (parent) clock.
> +The Clock API supports a built-in period multiplier/divider
> +mechanism so you can configure a clock to make its children
> +run at a different period from its own. If you call the
> +``clock_set_mul_div()`` function you can specify the clock's
> +multiplier and divider values. The children of that clock
> +will all run with a period of ``parent_period * multiplier / divider``.
> +For instance, if the clock has a frequency of 8MHz and you set its
> +multiplier to 2 and its divider to 3, the child clocks will run
> +at 12MHz.
> +
> +You can change the multiplier and divider of a clock at runtime,
> +so you can use this to model clock controller devices which
> +have guest-programmable frequency multipliers or dividers.
> +
> +Note that ``clock_set_mul_div()`` does not automatically call
> +``clock_propagate()``. If you make a runtime change to the
> +multiplier or divider you must call clock_propagate() yourself.a
You have an extra `a` here after the full stop.
Otherwise:
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> +
> Unconnected input clocks
> ------------------------
>
> diff --git a/include/hw/clock.h b/include/hw/clock.h
> index a7187eab95e..11f67fb9701 100644
> --- a/include/hw/clock.h
> +++ b/include/hw/clock.h
> @@ -81,6 +81,10 @@ struct Clock {
> void *callback_opaque;
> unsigned int callback_events;
>
> + /* Ratio of the parent clock to run the child clocks at */
> + uint32_t multiplier;
> + uint32_t divider;
> +
> /* Clocks are organized in a clock tree */
> Clock *source;
> QLIST_HEAD(, Clock) children;
> @@ -350,4 +354,29 @@ static inline bool clock_is_enabled(const Clock *clk)
> */
> char *clock_display_freq(Clock *clk);
>
> +/**
> + * clock_set_mul_div: set multiplier/divider for child clocks
> + * @clk: clock
> + * @multiplier: multiplier value
> + * @divider: divider value
> + *
> + * By default, a Clock's children will all run with the same period
> + * as their parent. This function allows you to adjust the multiplier
> + * and divider used to derive the child clock frequency.
> + * For example, setting a multiplier of 2 and a divider of 3
> + * will run child clocks with a period 2/3 of the parent clock,
> + * so if the parent clock is an 8MHz clock the children will
> + * be 12MHz.
> + *
> + * Setting the multiplier to 0 will stop the child clocks.
> + * Setting the divider to 0 is a programming error (diagnosed with
> + * an assertion failure).
> + * Setting a multiplier value that results in the child period
> + * overflowing is not diagnosed.
> + *
> + * Note that this function does not call clock_propagate(); the
> + * caller should do that if necessary.
> + */
> +void clock_set_mul_div(Clock *clk, uint32_t multiplier, uint32_t divider);
> +
> #endif /* QEMU_HW_CLOCK_H */
> diff --git a/hw/core/clock-vmstate.c b/hw/core/clock-vmstate.c
> index 260b13fc2c8..07bb45d7ed4 100644
> --- a/hw/core/clock-vmstate.c
> +++ b/hw/core/clock-vmstate.c
> @@ -14,6 +14,24 @@
> #include "migration/vmstate.h"
> #include "hw/clock.h"
>
> +static bool muldiv_needed(void *opaque)
> +{
> + Clock *clk = opaque;
> +
> + return clk->multiplier != 1 || clk->divider != 1;
> +}
> +
> +const VMStateDescription vmstate_muldiv = {
> + .name = "clock/muldiv",
> + .version_id = 1,
> + .minimum_version_id = 1,
> + .needed = muldiv_needed,
> + .fields = (VMStateField[]) {
> + VMSTATE_UINT32(multiplier, Clock),
> + VMSTATE_UINT32(divider, Clock),
> + },
> +};
> +
> const VMStateDescription vmstate_clock = {
> .name = "clock",
> .version_id = 0,
> @@ -21,5 +39,9 @@ const VMStateDescription vmstate_clock = {
> .fields = (VMStateField[]) {
> VMSTATE_UINT64(period, Clock),
> VMSTATE_END_OF_LIST()
> - }
> + },
> + .subsections = (const VMStateDescription*[]) {
> + &vmstate_muldiv,
> + NULL
> + },
> };
> diff --git a/hw/core/clock.c b/hw/core/clock.c
> index fc5a99683f8..c371b9e977a 100644
> --- a/hw/core/clock.c
> +++ b/hw/core/clock.c
> @@ -64,6 +64,15 @@ bool clock_set(Clock *clk, uint64_t period)
> return true;
> }
>
> +static uint64_t clock_get_child_period(Clock *clk)
> +{
> + /*
> + * Return the period to be used for child clocks, which is the parent
> + * clock period adjusted for for multiplier and divider effects.
> + */
> + return muldiv64(clk->period, clk->multiplier, clk->divider);
> +}
> +
> static void clock_call_callback(Clock *clk, ClockEvent event)
> {
> /*
> @@ -78,15 +87,16 @@ static void clock_call_callback(Clock *clk, ClockEvent event)
> static void clock_propagate_period(Clock *clk, bool call_callbacks)
> {
> Clock *child;
> + uint64_t child_period = clock_get_child_period(clk);
>
> QLIST_FOREACH(child, &clk->children, sibling) {
> - if (child->period != clk->period) {
> + if (child->period != child_period) {
> if (call_callbacks) {
> clock_call_callback(child, ClockPreUpdate);
> }
> - child->period = clk->period;
> + child->period = child_period;
> trace_clock_update(CLOCK_PATH(child), CLOCK_PATH(clk),
> - CLOCK_PERIOD_TO_HZ(clk->period),
> + CLOCK_PERIOD_TO_HZ(child->period),
> call_callbacks);
> if (call_callbacks) {
> clock_call_callback(child, ClockUpdate);
> @@ -110,7 +120,7 @@ void clock_set_source(Clock *clk, Clock *src)
>
> trace_clock_set_source(CLOCK_PATH(clk), CLOCK_PATH(src));
>
> - clk->period = src->period;
> + clk->period = clock_get_child_period(src);
> QLIST_INSERT_HEAD(&src->children, clk, sibling);
> clk->source = src;
> clock_propagate_period(clk, false);
> @@ -133,10 +143,21 @@ char *clock_display_freq(Clock *clk)
> return freq_to_str(clock_get_hz(clk));
> }
>
> +void clock_set_mul_div(Clock *clk, uint32_t multiplier, uint32_t divider)
> +{
> + assert(divider != 0);
> +
> + clk->multiplier = multiplier;
> + clk->divider = divider;
> +}
> +
> static void clock_initfn(Object *obj)
> {
> Clock *clk = CLOCK(obj);
>
> + clk->multiplier = 1;
> + clk->divider = 1;
> +
> QLIST_INIT(&clk->children);
> }
>
> --
> 2.20.1
>
>
^ permalink raw reply [flat|nested] 91+ messages in thread
* Re: [PATCH for-6.2 10/25] hw/arm: Don't allocate separate MemoryRegions in stm32 SoC realize
2021-08-12 9:33 ` [PATCH for-6.2 10/25] hw/arm: Don't allocate separate MemoryRegions in stm32 SoC realize Peter Maydell
2021-08-12 12:13 ` Alexandre IOOSS
@ 2021-08-13 1:34 ` Alistair Francis
2021-08-17 9:41 ` Luc Michel
2 siblings, 0 replies; 91+ messages in thread
From: Alistair Francis @ 2021-08-13 1:34 UTC (permalink / raw)
To: Peter Maydell
Cc: Damien Hedde, Luc Michel, Alistair Francis,
qemu-devel@nongnu.org Developers, Subbaraya Sundeep, qemu-arm,
Joel Stanley, Alexandre Iooss
On Thu, Aug 12, 2021 at 7:37 PM Peter Maydell <peter.maydell@linaro.org> wrote:
>
> In the realize methods of the stm32f100 and stm32f205 SoC objects, we
> call g_new() to create new MemoryRegion objjects for the sram, flash,
> and flash_alias. This is unnecessary (and leaves open the
> possibility of leaking the allocations if we exit from realize with
> an error). Make these MemoryRegions member fields of the device
> state struct instead, as stm32f405 already does.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> include/hw/arm/stm32f100_soc.h | 4 ++++
> include/hw/arm/stm32f205_soc.h | 4 ++++
> hw/arm/stm32f100_soc.c | 17 +++++++----------
> hw/arm/stm32f205_soc.c | 17 +++++++----------
> 4 files changed, 22 insertions(+), 20 deletions(-)
>
> diff --git a/include/hw/arm/stm32f100_soc.h b/include/hw/arm/stm32f100_soc.h
> index 71bffcf4fd5..b7d71c6c634 100644
> --- a/include/hw/arm/stm32f100_soc.h
> +++ b/include/hw/arm/stm32f100_soc.h
> @@ -52,6 +52,10 @@ struct STM32F100State {
>
> STM32F2XXUsartState usart[STM_NUM_USARTS];
> STM32F2XXSPIState spi[STM_NUM_SPIS];
> +
> + MemoryRegion sram;
> + MemoryRegion flash;
> + MemoryRegion flash_alias;
> };
>
> #endif
> diff --git a/include/hw/arm/stm32f205_soc.h b/include/hw/arm/stm32f205_soc.h
> index 985ff63aa9e..75251494917 100644
> --- a/include/hw/arm/stm32f205_soc.h
> +++ b/include/hw/arm/stm32f205_soc.h
> @@ -63,6 +63,10 @@ struct STM32F205State {
> STM32F2XXSPIState spi[STM_NUM_SPIS];
>
> qemu_or_irq *adc_irqs;
> +
> + MemoryRegion sram;
> + MemoryRegion flash;
> + MemoryRegion flash_alias;
> };
>
> #endif
> diff --git a/hw/arm/stm32f100_soc.c b/hw/arm/stm32f100_soc.c
> index 0c4a5c66451..0be92b2c475 100644
> --- a/hw/arm/stm32f100_soc.c
> +++ b/hw/arm/stm32f100_soc.c
> @@ -67,25 +67,22 @@ static void stm32f100_soc_realize(DeviceState *dev_soc, Error **errp)
> int i;
>
> MemoryRegion *system_memory = get_system_memory();
> - MemoryRegion *sram = g_new(MemoryRegion, 1);
> - MemoryRegion *flash = g_new(MemoryRegion, 1);
> - MemoryRegion *flash_alias = g_new(MemoryRegion, 1);
>
> /*
> * Init flash region
> * Flash starts at 0x08000000 and then is aliased to boot memory at 0x0
> */
> - memory_region_init_rom(flash, OBJECT(dev_soc), "STM32F100.flash",
> + memory_region_init_rom(&s->flash, OBJECT(dev_soc), "STM32F100.flash",
> FLASH_SIZE, &error_fatal);
> - memory_region_init_alias(flash_alias, OBJECT(dev_soc),
> - "STM32F100.flash.alias", flash, 0, FLASH_SIZE);
> - memory_region_add_subregion(system_memory, FLASH_BASE_ADDRESS, flash);
> - memory_region_add_subregion(system_memory, 0, flash_alias);
> + memory_region_init_alias(&s->flash_alias, OBJECT(dev_soc),
> + "STM32F100.flash.alias", &s->flash, 0, FLASH_SIZE);
> + memory_region_add_subregion(system_memory, FLASH_BASE_ADDRESS, &s->flash);
> + memory_region_add_subregion(system_memory, 0, &s->flash_alias);
>
> /* Init SRAM region */
> - memory_region_init_ram(sram, NULL, "STM32F100.sram", SRAM_SIZE,
> + memory_region_init_ram(&s->sram, NULL, "STM32F100.sram", SRAM_SIZE,
> &error_fatal);
> - memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, sram);
> + memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, &s->sram);
>
> /* Init ARMv7m */
> armv7m = DEVICE(&s->armv7m);
> diff --git a/hw/arm/stm32f205_soc.c b/hw/arm/stm32f205_soc.c
> index 9cd41bf56da..0bd215aebd7 100644
> --- a/hw/arm/stm32f205_soc.c
> +++ b/hw/arm/stm32f205_soc.c
> @@ -84,21 +84,18 @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
> int i;
>
> MemoryRegion *system_memory = get_system_memory();
> - MemoryRegion *sram = g_new(MemoryRegion, 1);
> - MemoryRegion *flash = g_new(MemoryRegion, 1);
> - MemoryRegion *flash_alias = g_new(MemoryRegion, 1);
>
> - memory_region_init_rom(flash, OBJECT(dev_soc), "STM32F205.flash",
> + memory_region_init_rom(&s->flash, OBJECT(dev_soc), "STM32F205.flash",
> FLASH_SIZE, &error_fatal);
> - memory_region_init_alias(flash_alias, OBJECT(dev_soc),
> - "STM32F205.flash.alias", flash, 0, FLASH_SIZE);
> + memory_region_init_alias(&s->flash_alias, OBJECT(dev_soc),
> + "STM32F205.flash.alias", &s->flash, 0, FLASH_SIZE);
>
> - memory_region_add_subregion(system_memory, FLASH_BASE_ADDRESS, flash);
> - memory_region_add_subregion(system_memory, 0, flash_alias);
> + memory_region_add_subregion(system_memory, FLASH_BASE_ADDRESS, &s->flash);
> + memory_region_add_subregion(system_memory, 0, &s->flash_alias);
>
> - memory_region_init_ram(sram, NULL, "STM32F205.sram", SRAM_SIZE,
> + memory_region_init_ram(&s->sram, NULL, "STM32F205.sram", SRAM_SIZE,
> &error_fatal);
> - memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, sram);
> + memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, &s->sram);
>
> armv7m = DEVICE(&s->armv7m);
> qdev_prop_set_uint32(armv7m, "num-irq", 96);
> --
> 2.20.1
>
>
^ permalink raw reply [flat|nested] 91+ messages in thread
* Re: [PATCH for-6.2 11/25] hw/arm/stm32f100: Wire up sysclk and refclk
2021-08-12 9:33 ` [PATCH for-6.2 11/25] hw/arm/stm32f100: Wire up sysclk and refclk Peter Maydell
@ 2021-08-13 1:36 ` Alistair Francis
2021-08-14 9:01 ` Alexandre IOOSS
2021-08-17 9:45 ` Luc Michel
2 siblings, 0 replies; 91+ messages in thread
From: Alistair Francis @ 2021-08-13 1:36 UTC (permalink / raw)
To: Peter Maydell
Cc: Damien Hedde, Luc Michel, Alistair Francis,
qemu-devel@nongnu.org Developers, Subbaraya Sundeep, qemu-arm,
Joel Stanley, Alexandre Iooss
On Thu, Aug 12, 2021 at 7:37 PM Peter Maydell <peter.maydell@linaro.org> wrote:
>
> Wire up the sysclk and refclk for the stm32f100 SoC. This SoC always
> runs the systick refclk at 1/8 the frequency of the main CPU clock,
> so the board code only needs to provide a single sysclk clock.
>
> Because there is only one board using this SoC, we convert the SoC
> and the board together, rather than splitting it into "add clock to
> SoC; connect clock in board; add error check in SoC code that clock
> is wired up".
>
> When the systick device starts honouring its clock inputs, this will
> fix an emulation inaccuracy in the stm32vldiscovery board where the
> systick reference clock was running at 1MHz rather than 3MHz.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> include/hw/arm/stm32f100_soc.h | 4 ++++
> hw/arm/stm32f100_soc.c | 30 ++++++++++++++++++++++++++++++
> hw/arm/stm32vldiscovery.c | 12 +++++++-----
> 3 files changed, 41 insertions(+), 5 deletions(-)
>
> diff --git a/include/hw/arm/stm32f100_soc.h b/include/hw/arm/stm32f100_soc.h
> index b7d71c6c634..40cd415b284 100644
> --- a/include/hw/arm/stm32f100_soc.h
> +++ b/include/hw/arm/stm32f100_soc.h
> @@ -29,6 +29,7 @@
> #include "hw/ssi/stm32f2xx_spi.h"
> #include "hw/arm/armv7m.h"
> #include "qom/object.h"
> +#include "hw/clock.h"
>
> #define TYPE_STM32F100_SOC "stm32f100-soc"
> OBJECT_DECLARE_SIMPLE_TYPE(STM32F100State, STM32F100_SOC)
> @@ -56,6 +57,9 @@ struct STM32F100State {
> MemoryRegion sram;
> MemoryRegion flash;
> MemoryRegion flash_alias;
> +
> + Clock *sysclk;
> + Clock *refclk;
> };
>
> #endif
> diff --git a/hw/arm/stm32f100_soc.c b/hw/arm/stm32f100_soc.c
> index 0be92b2c475..f7b344ba9fb 100644
> --- a/hw/arm/stm32f100_soc.c
> +++ b/hw/arm/stm32f100_soc.c
> @@ -30,6 +30,7 @@
> #include "exec/address-spaces.h"
> #include "hw/arm/stm32f100_soc.h"
> #include "hw/qdev-properties.h"
> +#include "hw/qdev-clock.h"
> #include "hw/misc/unimp.h"
> #include "sysemu/sysemu.h"
>
> @@ -57,6 +58,9 @@ static void stm32f100_soc_initfn(Object *obj)
> for (i = 0; i < STM_NUM_SPIS; i++) {
> object_initialize_child(obj, "spi[*]", &s->spi[i], TYPE_STM32F2XX_SPI);
> }
> +
> + s->sysclk = qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0);
> + s->refclk = qdev_init_clock_in(DEVICE(s), "refclk", NULL, NULL, 0);
> }
>
> static void stm32f100_soc_realize(DeviceState *dev_soc, Error **errp)
> @@ -68,6 +72,30 @@ static void stm32f100_soc_realize(DeviceState *dev_soc, Error **errp)
>
> MemoryRegion *system_memory = get_system_memory();
>
> + /*
> + * We use s->refclk internally and only define it with qdev_init_clock_in()
> + * so it is correctly parented and not leaked on an init/deinit; it is not
> + * intended as an externally exposed clock.
> + */
> + if (clock_has_source(s->refclk)) {
> + error_setg(errp, "refclk clock must not be wired up by the board code");
> + return;
> + }
> +
> + if (!clock_has_source(s->sysclk)) {
> + error_setg(errp, "sysclk clock must be wired up by the board code");
> + return;
> + }
> +
> + /*
> + * TODO: ideally we should model the SoC RCC and its ability to
> + * change the sysclk frequency and define different sysclk sources.
> + */
> +
> + /* The refclk always runs at frequency HCLK / 8 */
> + clock_set_mul_div(s->refclk, 8, 1);
> + clock_set_source(s->refclk, s->sysclk);
> +
> /*
> * Init flash region
> * Flash starts at 0x08000000 and then is aliased to boot memory at 0x0
> @@ -89,6 +117,8 @@ static void stm32f100_soc_realize(DeviceState *dev_soc, Error **errp)
> qdev_prop_set_uint32(armv7m, "num-irq", 61);
> qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type);
> qdev_prop_set_bit(armv7m, "enable-bitband", true);
> + qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk);
> + qdev_connect_clock_in(armv7m, "refclk", s->refclk);
> object_property_set_link(OBJECT(&s->armv7m), "memory",
> OBJECT(get_system_memory()), &error_abort);
> if (!sysbus_realize(SYS_BUS_DEVICE(&s->armv7m), errp)) {
> diff --git a/hw/arm/stm32vldiscovery.c b/hw/arm/stm32vldiscovery.c
> index 7e8191ebf5f..07e401a818d 100644
> --- a/hw/arm/stm32vldiscovery.c
> +++ b/hw/arm/stm32vldiscovery.c
> @@ -27,6 +27,7 @@
> #include "qapi/error.h"
> #include "hw/boards.h"
> #include "hw/qdev-properties.h"
> +#include "hw/qdev-clock.h"
> #include "qemu/error-report.h"
> #include "hw/arm/stm32f100_soc.h"
> #include "hw/arm/boot.h"
> @@ -39,16 +40,17 @@
> static void stm32vldiscovery_init(MachineState *machine)
> {
> DeviceState *dev;
> + Clock *sysclk;
>
> - /*
> - * TODO: ideally we would model the SoC RCC and let it handle
> - * system_clock_scale, including its ability to define different
> - * possible SYSCLK sources.
> - */
> system_clock_scale = NANOSECONDS_PER_SECOND / SYSCLK_FRQ;
>
> + /* This clock doesn't need migration because it is fixed-frequency */
> + sysclk = clock_new(OBJECT(machine), "SYSCLK");
> + clock_set_hz(sysclk, SYSCLK_FRQ);
> +
> dev = qdev_new(TYPE_STM32F100_SOC);
> qdev_prop_set_string(dev, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m3"));
> + qdev_connect_clock_in(dev, "sysclk", sysclk);
> sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
>
> armv7m_load_kernel(ARM_CPU(first_cpu),
> --
> 2.20.1
>
>
^ permalink raw reply [flat|nested] 91+ messages in thread
* Re: [PATCH for-6.2 13/25] hw/arm/stm32f405: Wire up sysclk and refclk
2021-08-12 9:33 ` [PATCH for-6.2 13/25] hw/arm/stm32f405: " Peter Maydell
@ 2021-08-13 1:37 ` Alistair Francis
2021-08-14 9:03 ` Alexandre IOOSS
2021-08-17 9:47 ` Luc Michel
2 siblings, 0 replies; 91+ messages in thread
From: Alistair Francis @ 2021-08-13 1:37 UTC (permalink / raw)
To: Peter Maydell
Cc: Damien Hedde, Luc Michel, Alistair Francis,
qemu-devel@nongnu.org Developers, Subbaraya Sundeep, qemu-arm,
Joel Stanley, Alexandre Iooss
On Thu, Aug 12, 2021 at 7:41 PM Peter Maydell <peter.maydell@linaro.org> wrote:
>
> Wire up the sysclk and refclk for the stm32f405 SoC. This SoC always
> runs the systick refclk at 1/8 the frequency of the main CPU clock,
> so the board code only needs to provide a single sysclk clock.
>
> Because there is only one board using this SoC, we convert the SoC
> and the board together, rather than splitting it into "add clock to
> SoC; connect clock in board; add error check in SoC code that clock
> is wired up".
>
> When the systick device starts honouring its clock inputs, this will
> fix an emulation inaccuracy in the netduinoplus2 board where the
> systick reference clock was running at 1MHz rather than 21MHz.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> include/hw/arm/stm32f405_soc.h | 3 +++
> hw/arm/netduinoplus2.c | 12 +++++++-----
> hw/arm/stm32f405_soc.c | 30 ++++++++++++++++++++++++++++++
> 3 files changed, 40 insertions(+), 5 deletions(-)
>
> diff --git a/include/hw/arm/stm32f405_soc.h b/include/hw/arm/stm32f405_soc.h
> index 347105e709b..5bb0c8d5697 100644
> --- a/include/hw/arm/stm32f405_soc.h
> +++ b/include/hw/arm/stm32f405_soc.h
> @@ -68,6 +68,9 @@ struct STM32F405State {
> MemoryRegion sram;
> MemoryRegion flash;
> MemoryRegion flash_alias;
> +
> + Clock *sysclk;
> + Clock *refclk;
> };
>
> #endif
> diff --git a/hw/arm/netduinoplus2.c b/hw/arm/netduinoplus2.c
> index d3ad7a2b675..a5a8999cc8c 100644
> --- a/hw/arm/netduinoplus2.c
> +++ b/hw/arm/netduinoplus2.c
> @@ -26,6 +26,7 @@
> #include "qapi/error.h"
> #include "hw/boards.h"
> #include "hw/qdev-properties.h"
> +#include "hw/qdev-clock.h"
> #include "qemu/error-report.h"
> #include "hw/arm/stm32f405_soc.h"
> #include "hw/arm/boot.h"
> @@ -36,16 +37,17 @@
> static void netduinoplus2_init(MachineState *machine)
> {
> DeviceState *dev;
> + Clock *sysclk;
>
> - /*
> - * TODO: ideally we would model the SoC RCC and let it handle
> - * system_clock_scale, including its ability to define different
> - * possible SYSCLK sources.
> - */
> system_clock_scale = NANOSECONDS_PER_SECOND / SYSCLK_FRQ;
>
> + /* This clock doesn't need migration because it is fixed-frequency */
> + sysclk = clock_new(OBJECT(machine), "SYSCLK");
> + clock_set_hz(sysclk, SYSCLK_FRQ);
> +
> dev = qdev_new(TYPE_STM32F405_SOC);
> qdev_prop_set_string(dev, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m4"));
> + qdev_connect_clock_in(dev, "sysclk", sysclk);
> sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
>
> armv7m_load_kernel(ARM_CPU(first_cpu),
> diff --git a/hw/arm/stm32f405_soc.c b/hw/arm/stm32f405_soc.c
> index cb04c111987..0019b7f4785 100644
> --- a/hw/arm/stm32f405_soc.c
> +++ b/hw/arm/stm32f405_soc.c
> @@ -28,6 +28,7 @@
> #include "exec/address-spaces.h"
> #include "sysemu/sysemu.h"
> #include "hw/arm/stm32f405_soc.h"
> +#include "hw/qdev-clock.h"
> #include "hw/misc/unimp.h"
>
> #define SYSCFG_ADD 0x40013800
> @@ -80,6 +81,9 @@ static void stm32f405_soc_initfn(Object *obj)
> }
>
> object_initialize_child(obj, "exti", &s->exti, TYPE_STM32F4XX_EXTI);
> +
> + s->sysclk = qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0);
> + s->refclk = qdev_init_clock_in(DEVICE(s), "refclk", NULL, NULL, 0);
> }
>
> static void stm32f405_soc_realize(DeviceState *dev_soc, Error **errp)
> @@ -91,6 +95,30 @@ static void stm32f405_soc_realize(DeviceState *dev_soc, Error **errp)
> Error *err = NULL;
> int i;
>
> + /*
> + * We use s->refclk internally and only define it with qdev_init_clock_in()
> + * so it is correctly parented and not leaked on an init/deinit; it is not
> + * intended as an externally exposed clock.
> + */
> + if (clock_has_source(s->refclk)) {
> + error_setg(errp, "refclk clock must not be wired up by the board code");
> + return;
> + }
> +
> + if (!clock_has_source(s->sysclk)) {
> + error_setg(errp, "sysclk clock must be wired up by the board code");
> + return;
> + }
> +
> + /*
> + * TODO: ideally we should model the SoC RCC and its ability to
> + * change the sysclk frequency and define different sysclk sources.
> + */
> +
> + /* The refclk always runs at frequency HCLK / 8 */
> + clock_set_mul_div(s->refclk, 8, 1);
> + clock_set_source(s->refclk, s->sysclk);
> +
> memory_region_init_rom(&s->flash, OBJECT(dev_soc), "STM32F405.flash",
> FLASH_SIZE, &err);
> if (err != NULL) {
> @@ -116,6 +144,8 @@ static void stm32f405_soc_realize(DeviceState *dev_soc, Error **errp)
> qdev_prop_set_uint32(armv7m, "num-irq", 96);
> qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type);
> qdev_prop_set_bit(armv7m, "enable-bitband", true);
> + qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk);
> + qdev_connect_clock_in(armv7m, "refclk", s->refclk);
> object_property_set_link(OBJECT(&s->armv7m), "memory",
> OBJECT(system_memory), &error_abort);
> if (!sysbus_realize(SYS_BUS_DEVICE(&s->armv7m), errp)) {
> --
> 2.20.1
>
>
^ permalink raw reply [flat|nested] 91+ messages in thread
* Re: [PATCH for-6.2 12/25] hw/arm/stm32f205: Wire up sysclk and refclk
2021-08-12 9:33 ` [PATCH for-6.2 12/25] hw/arm/stm32f205: " Peter Maydell
@ 2021-08-13 1:38 ` Alistair Francis
2021-08-14 9:02 ` Alexandre IOOSS
2021-08-17 9:47 ` Luc Michel
2 siblings, 0 replies; 91+ messages in thread
From: Alistair Francis @ 2021-08-13 1:38 UTC (permalink / raw)
To: Peter Maydell
Cc: Damien Hedde, Luc Michel, Alistair Francis,
qemu-devel@nongnu.org Developers, Subbaraya Sundeep, qemu-arm,
Joel Stanley, Alexandre Iooss
On Thu, Aug 12, 2021 at 7:38 PM Peter Maydell <peter.maydell@linaro.org> wrote:
>
> Wire up the sysclk and refclk for the stm32f205 SoC. This SoC always
> runs the systick refclk at 1/8 the frequency of the main CPU clock,
> so the board code only needs to provide a single sysclk clock.
>
> Because there is only one board using this SoC, we convert the SoC
> and the board together, rather than splitting it into "add clock to
> SoC; connect clock in board; add error check in SoC code that clock
> is wired up".
>
> When the systick device starts honouring its clock inputs, this will
> fix an emulation inaccuracy in the netduino2 board where the systick
> reference clock was running at 1MHz rather than 15MHz.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> include/hw/arm/stm32f205_soc.h | 4 ++++
> hw/arm/netduino2.c | 12 +++++++-----
> hw/arm/stm32f205_soc.c | 30 ++++++++++++++++++++++++++++++
> 3 files changed, 41 insertions(+), 5 deletions(-)
>
> diff --git a/include/hw/arm/stm32f205_soc.h b/include/hw/arm/stm32f205_soc.h
> index 75251494917..849d3ed8891 100644
> --- a/include/hw/arm/stm32f205_soc.h
> +++ b/include/hw/arm/stm32f205_soc.h
> @@ -32,6 +32,7 @@
> #include "hw/or-irq.h"
> #include "hw/ssi/stm32f2xx_spi.h"
> #include "hw/arm/armv7m.h"
> +#include "hw/clock.h"
> #include "qom/object.h"
>
> #define TYPE_STM32F205_SOC "stm32f205-soc"
> @@ -67,6 +68,9 @@ struct STM32F205State {
> MemoryRegion sram;
> MemoryRegion flash;
> MemoryRegion flash_alias;
> +
> + Clock *sysclk;
> + Clock *refclk;
> };
>
> #endif
> diff --git a/hw/arm/netduino2.c b/hw/arm/netduino2.c
> index 1733b71507c..b5c0ba23ee5 100644
> --- a/hw/arm/netduino2.c
> +++ b/hw/arm/netduino2.c
> @@ -26,6 +26,7 @@
> #include "qapi/error.h"
> #include "hw/boards.h"
> #include "hw/qdev-properties.h"
> +#include "hw/qdev-clock.h"
> #include "qemu/error-report.h"
> #include "hw/arm/stm32f205_soc.h"
> #include "hw/arm/boot.h"
> @@ -36,16 +37,17 @@
> static void netduino2_init(MachineState *machine)
> {
> DeviceState *dev;
> + Clock *sysclk;
>
> - /*
> - * TODO: ideally we would model the SoC RCC and let it handle
> - * system_clock_scale, including its ability to define different
> - * possible SYSCLK sources.
> - */
> system_clock_scale = NANOSECONDS_PER_SECOND / SYSCLK_FRQ;
>
> + /* This clock doesn't need migration because it is fixed-frequency */
> + sysclk = clock_new(OBJECT(machine), "SYSCLK");
> + clock_set_hz(sysclk, SYSCLK_FRQ);
> +
> dev = qdev_new(TYPE_STM32F205_SOC);
> qdev_prop_set_string(dev, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m3"));
> + qdev_connect_clock_in(dev, "sysclk", sysclk);
> sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
>
> armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename,
> diff --git a/hw/arm/stm32f205_soc.c b/hw/arm/stm32f205_soc.c
> index 0bd215aebd7..c6b75a381d9 100644
> --- a/hw/arm/stm32f205_soc.c
> +++ b/hw/arm/stm32f205_soc.c
> @@ -29,6 +29,7 @@
> #include "exec/address-spaces.h"
> #include "hw/arm/stm32f205_soc.h"
> #include "hw/qdev-properties.h"
> +#include "hw/qdev-clock.h"
> #include "sysemu/sysemu.h"
>
> /* At the moment only Timer 2 to 5 are modelled */
> @@ -74,6 +75,9 @@ static void stm32f205_soc_initfn(Object *obj)
> for (i = 0; i < STM_NUM_SPIS; i++) {
> object_initialize_child(obj, "spi[*]", &s->spi[i], TYPE_STM32F2XX_SPI);
> }
> +
> + s->sysclk = qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0);
> + s->refclk = qdev_init_clock_in(DEVICE(s), "refclk", NULL, NULL, 0);
> }
>
> static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
> @@ -85,6 +89,30 @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
>
> MemoryRegion *system_memory = get_system_memory();
>
> + /*
> + * We use s->refclk internally and only define it with qdev_init_clock_in()
> + * so it is correctly parented and not leaked on an init/deinit; it is not
> + * intended as an externally exposed clock.
> + */
> + if (clock_has_source(s->refclk)) {
> + error_setg(errp, "refclk clock must not be wired up by the board code");
> + return;
> + }
> +
> + if (!clock_has_source(s->sysclk)) {
> + error_setg(errp, "sysclk clock must be wired up by the board code");
> + return;
> + }
> +
> + /*
> + * TODO: ideally we should model the SoC RCC and its ability to
> + * change the sysclk frequency and define different sysclk sources.
> + */
> +
> + /* The refclk always runs at frequency HCLK / 8 */
> + clock_set_mul_div(s->refclk, 8, 1);
> + clock_set_source(s->refclk, s->sysclk);
> +
> memory_region_init_rom(&s->flash, OBJECT(dev_soc), "STM32F205.flash",
> FLASH_SIZE, &error_fatal);
> memory_region_init_alias(&s->flash_alias, OBJECT(dev_soc),
> @@ -101,6 +129,8 @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
> qdev_prop_set_uint32(armv7m, "num-irq", 96);
> qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type);
> qdev_prop_set_bit(armv7m, "enable-bitband", true);
> + qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk);
> + qdev_connect_clock_in(armv7m, "refclk", s->refclk);
> object_property_set_link(OBJECT(&s->armv7m), "memory",
> OBJECT(get_system_memory()), &error_abort);
> if (!sysbus_realize(SYS_BUS_DEVICE(&s->armv7m), errp)) {
> --
> 2.20.1
>
>
^ permalink raw reply [flat|nested] 91+ messages in thread
* Re: [PATCH for-6.2 14/25] hw/arm/stm32vldiscovery: Delete trailing blank line
2021-08-12 9:33 ` [PATCH for-6.2 14/25] hw/arm/stm32vldiscovery: Delete trailing blank line Peter Maydell
2021-08-12 12:27 ` Alexandre IOOSS
@ 2021-08-13 1:39 ` Alistair Francis
2021-08-17 9:48 ` Luc Michel
2 siblings, 0 replies; 91+ messages in thread
From: Alistair Francis @ 2021-08-13 1:39 UTC (permalink / raw)
To: Peter Maydell
Cc: Damien Hedde, Luc Michel, Alistair Francis,
qemu-devel@nongnu.org Developers, Subbaraya Sundeep, qemu-arm,
Joel Stanley, Alexandre Iooss
On Thu, Aug 12, 2021 at 7:44 PM Peter Maydell <peter.maydell@linaro.org> wrote:
>
> Delete the trailing blank line at the end of the source file.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> hw/arm/stm32vldiscovery.c | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git a/hw/arm/stm32vldiscovery.c b/hw/arm/stm32vldiscovery.c
> index 07e401a818d..9b79004703b 100644
> --- a/hw/arm/stm32vldiscovery.c
> +++ b/hw/arm/stm32vldiscovery.c
> @@ -65,4 +65,3 @@ static void stm32vldiscovery_machine_init(MachineClass *mc)
> }
>
> DEFINE_MACHINE("stm32vldiscovery", stm32vldiscovery_machine_init)
> -
> --
> 2.20.1
>
>
^ permalink raw reply [flat|nested] 91+ messages in thread
* Re: [PATCH for-6.2 25/25] arm: Remove system_clock_scale global
2021-08-12 9:33 ` [PATCH for-6.2 25/25] arm: Remove system_clock_scale global Peter Maydell
@ 2021-08-13 5:08 ` Alistair Francis
0 siblings, 0 replies; 91+ messages in thread
From: Alistair Francis @ 2021-08-13 5:08 UTC (permalink / raw)
To: Peter Maydell
Cc: Damien Hedde, Luc Michel, Alistair Francis,
qemu-devel@nongnu.org Developers, Subbaraya Sundeep, qemu-arm,
Joel Stanley, Alexandre Iooss
On Thu, Aug 12, 2021 at 7:52 PM Peter Maydell <peter.maydell@linaro.org> wrote:
>
> All the devices that used to use system_clock_scale have now been
> converted to use Clock inputs instead, so the global is no longer
> needed; remove it and all the code that sets it.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> include/hw/timer/armv7m_systick.h | 22 ----------------------
> hw/arm/armsse.c | 17 +----------------
> hw/arm/mps2.c | 2 --
> hw/arm/msf2-soc.c | 2 --
> hw/arm/netduino2.c | 2 --
> hw/arm/netduinoplus2.c | 2 --
> hw/arm/nrf51_soc.c | 2 --
> hw/arm/stellaris.c | 7 ++++---
> hw/arm/stm32vldiscovery.c | 2 --
> hw/timer/armv7m_systick.c | 2 --
> 10 files changed, 5 insertions(+), 55 deletions(-)
>
> diff --git a/include/hw/timer/armv7m_systick.h b/include/hw/timer/armv7m_systick.h
> index 38adf8d274e..ee09b138810 100644
> --- a/include/hw/timer/armv7m_systick.h
> +++ b/include/hw/timer/armv7m_systick.h
> @@ -47,26 +47,4 @@ struct SysTickState {
> Clock *cpuclk;
> };
>
> -/*
> - * Multiplication factor to convert from system clock ticks to qemu timer
> - * ticks. This should be set (by board code, usually) to a value
> - * equal to NANOSECONDS_PER_SECOND / frq, where frq is the clock frequency
> - * in Hz of the CPU.
> - *
> - * This value is used by the systick device when it is running in
> - * its "use the CPU clock" mode (ie when SYST_CSR.CLKSOURCE == 1) to
> - * set how fast the timer should tick.
> - *
> - * TODO: we should refactor this so that rather than using a global
> - * we use a device property or something similar. This is complicated
> - * because (a) the property would need to be plumbed through from the
> - * board code down through various layers to the systick device
> - * and (b) the property needs to be modifiable after realize, because
> - * the stellaris board uses this to implement the behaviour where the
> - * guest can reprogram the PLL registers to downclock the CPU, and the
> - * systick device needs to react accordingly. Possibly this should
> - * be deferred until we have a good API for modelling clock trees.
> - */
> -extern int system_clock_scale;
> -
> #endif
> diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c
> index 70b52c3d4b9..aecdeb9815a 100644
> --- a/hw/arm/armsse.c
> +++ b/hw/arm/armsse.c
> @@ -689,17 +689,6 @@ static void armsse_forward_sec_resp_cfg(ARMSSE *s)
> qdev_connect_gpio_out(dev_splitter, 2, s->sec_resp_cfg_in);
> }
>
> -static void armsse_mainclk_update(void *opaque, ClockEvent event)
> -{
> - ARMSSE *s = ARM_SSE(opaque);
> -
> - /*
> - * Set system_clock_scale from our Clock input; this is what
> - * controls the tick rate of the CPU SysTick timer.
> - */
> - system_clock_scale = clock_ticks_to_ns(s->mainclk, 1);
> -}
> -
> static void armsse_init(Object *obj)
> {
> ARMSSE *s = ARM_SSE(obj);
> @@ -711,8 +700,7 @@ static void armsse_init(Object *obj)
> assert(info->sram_banks <= MAX_SRAM_BANKS);
> assert(info->num_cpus <= SSE_MAX_CPUS);
>
> - s->mainclk = qdev_init_clock_in(DEVICE(s), "MAINCLK",
> - armsse_mainclk_update, s, ClockUpdate);
> + s->mainclk = qdev_init_clock_in(DEVICE(s), "MAINCLK", NULL, NULL, 0);
> s->s32kclk = qdev_init_clock_in(DEVICE(s), "S32KCLK", NULL, NULL, 0);
>
> memory_region_init(&s->container, obj, "armsse-container", UINT64_MAX);
> @@ -1654,9 +1642,6 @@ static void armsse_realize(DeviceState *dev, Error **errp)
> * devices in the ARMSSE.
> */
> sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->container);
> -
> - /* Set initial system_clock_scale from MAINCLK */
> - armsse_mainclk_update(s, ClockUpdate);
> }
>
> static void armsse_idau_check(IDAUInterface *ii, uint32_t address,
> diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c
> index 3671f49ad7b..4634aa1a1ca 100644
> --- a/hw/arm/mps2.c
> +++ b/hw/arm/mps2.c
> @@ -439,8 +439,6 @@ static void mps2_common_init(MachineState *machine)
> qdev_get_gpio_in(armv7m,
> mmc->fpga_type == FPGA_AN511 ? 47 : 13));
>
> - system_clock_scale = NANOSECONDS_PER_SECOND / SYSCLK_FRQ;
> -
> armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename,
> 0x400000);
> }
> diff --git a/hw/arm/msf2-soc.c b/hw/arm/msf2-soc.c
> index dbc6d936a76..b5fe9f364d5 100644
> --- a/hw/arm/msf2-soc.c
> +++ b/hw/arm/msf2-soc.c
> @@ -144,8 +144,6 @@ static void m2sxxx_soc_realize(DeviceState *dev_soc, Error **errp)
> return;
> }
>
> - system_clock_scale = clock_ticks_to_ns(s->m3clk, 1);
> -
> for (i = 0; i < MSF2_NUM_UARTS; i++) {
> if (serial_hd(i)) {
> serial_mm_init(get_system_memory(), uart_addr[i], 2,
> diff --git a/hw/arm/netduino2.c b/hw/arm/netduino2.c
> index b5c0ba23ee5..3365da11bf7 100644
> --- a/hw/arm/netduino2.c
> +++ b/hw/arm/netduino2.c
> @@ -39,8 +39,6 @@ static void netduino2_init(MachineState *machine)
> DeviceState *dev;
> Clock *sysclk;
>
> - system_clock_scale = NANOSECONDS_PER_SECOND / SYSCLK_FRQ;
> -
> /* This clock doesn't need migration because it is fixed-frequency */
> sysclk = clock_new(OBJECT(machine), "SYSCLK");
> clock_set_hz(sysclk, SYSCLK_FRQ);
> diff --git a/hw/arm/netduinoplus2.c b/hw/arm/netduinoplus2.c
> index a5a8999cc8c..76cea8e4891 100644
> --- a/hw/arm/netduinoplus2.c
> +++ b/hw/arm/netduinoplus2.c
> @@ -39,8 +39,6 @@ static void netduinoplus2_init(MachineState *machine)
> DeviceState *dev;
> Clock *sysclk;
>
> - system_clock_scale = NANOSECONDS_PER_SECOND / SYSCLK_FRQ;
> -
> /* This clock doesn't need migration because it is fixed-frequency */
> sysclk = clock_new(OBJECT(machine), "SYSCLK");
> clock_set_hz(sysclk, SYSCLK_FRQ);
> diff --git a/hw/arm/nrf51_soc.c b/hw/arm/nrf51_soc.c
> index e3e849a32b1..34da0d62f00 100644
> --- a/hw/arm/nrf51_soc.c
> +++ b/hw/arm/nrf51_soc.c
> @@ -84,8 +84,6 @@ static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp)
> * will always provide one).
> */
>
> - system_clock_scale = NANOSECONDS_PER_SECOND / HCLK_FRQ;
> -
> object_property_set_link(OBJECT(&s->cpu), "memory", OBJECT(&s->container),
> &error_abort);
> if (!sysbus_realize(SYS_BUS_DEVICE(&s->cpu), errp)) {
> diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
> index 3e7d1dabad1..78827ace6b8 100644
> --- a/hw/arm/stellaris.c
> +++ b/hw/arm/stellaris.c
> @@ -263,17 +263,18 @@ static bool ssys_use_rcc2(ssys_state *s)
> */
> static void ssys_calculate_system_clock(ssys_state *s, bool propagate_clock)
> {
> + int period_ns;
> /*
> * SYSDIV field specifies divisor: 0 == /1, 1 == /2, etc. Input
> * clock is 200MHz, which is a period of 5 ns. Dividing the clock
> * frequency by X is the same as multiplying the period by X.
> */
> if (ssys_use_rcc2(s)) {
> - system_clock_scale = 5 * (((s->rcc2 >> 23) & 0x3f) + 1);
> + period_ns = 5 * (((s->rcc2 >> 23) & 0x3f) + 1);
> } else {
> - system_clock_scale = 5 * (((s->rcc >> 23) & 0xf) + 1);
> + period_ns = 5 * (((s->rcc >> 23) & 0xf) + 1);
> }
> - clock_set_ns(s->sysclk, system_clock_scale);
> + clock_set_ns(s->sysclk, period_ns);
> if (propagate_clock) {
> clock_propagate(s->sysclk);
> }
> diff --git a/hw/arm/stm32vldiscovery.c b/hw/arm/stm32vldiscovery.c
> index 9b79004703b..04036da3ee0 100644
> --- a/hw/arm/stm32vldiscovery.c
> +++ b/hw/arm/stm32vldiscovery.c
> @@ -42,8 +42,6 @@ static void stm32vldiscovery_init(MachineState *machine)
> DeviceState *dev;
> Clock *sysclk;
>
> - system_clock_scale = NANOSECONDS_PER_SECOND / SYSCLK_FRQ;
> -
> /* This clock doesn't need migration because it is fixed-frequency */
> sysclk = clock_new(OBJECT(machine), "SYSCLK");
> clock_set_hz(sysclk, SYSCLK_FRQ);
> diff --git a/hw/timer/armv7m_systick.c b/hw/timer/armv7m_systick.c
> index 39cca206cfd..9f92830968b 100644
> --- a/hw/timer/armv7m_systick.c
> +++ b/hw/timer/armv7m_systick.c
> @@ -29,8 +29,6 @@
> #define SYSCALIB_NOREF (1U << 31)
> #define SYSCALIB_SKEW (1U << 30)
>
> -int system_clock_scale;
> -
> static void systick_set_period_from_clock(SysTickState *s)
> {
> /*
> --
> 2.20.1
>
>
^ permalink raw reply [flat|nested] 91+ messages in thread
* Re: [PATCH for-6.2 11/25] hw/arm/stm32f100: Wire up sysclk and refclk
2021-08-12 9:33 ` [PATCH for-6.2 11/25] hw/arm/stm32f100: Wire up sysclk and refclk Peter Maydell
2021-08-13 1:36 ` Alistair Francis
@ 2021-08-14 9:01 ` Alexandre IOOSS
2021-08-17 9:45 ` Luc Michel
2 siblings, 0 replies; 91+ messages in thread
From: Alexandre IOOSS @ 2021-08-14 9:01 UTC (permalink / raw)
To: Peter Maydell, qemu-arm, qemu-devel
Cc: Damien Hedde, Alistair Francis, Luc Michel, Joel Stanley,
Subbaraya Sundeep
[-- Attachment #1.1: Type: text/plain, Size: 833 bytes --]
On 8/12/21 11:33 AM, Peter Maydell wrote:
> Wire up the sysclk and refclk for the stm32f100 SoC. This SoC always
> runs the systick refclk at 1/8 the frequency of the main CPU clock,
> so the board code only needs to provide a single sysclk clock.
>
> Because there is only one board using this SoC, we convert the SoC
> and the board together, rather than splitting it into "add clock to
> SoC; connect clock in board; add error check in SoC code that clock
> is wired up".
>
> When the systick device starts honouring its clock inputs, this will
> fix an emulation inaccuracy in the stm32vldiscovery board where the
> systick reference clock was running at 1MHz rather than 3MHz.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alexandre Iooss <erdnaxe@crans.org>
-- Alexandre
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^ permalink raw reply [flat|nested] 91+ messages in thread
* Re: [PATCH for-6.2 12/25] hw/arm/stm32f205: Wire up sysclk and refclk
2021-08-12 9:33 ` [PATCH for-6.2 12/25] hw/arm/stm32f205: " Peter Maydell
2021-08-13 1:38 ` Alistair Francis
@ 2021-08-14 9:02 ` Alexandre IOOSS
2021-08-17 9:47 ` Luc Michel
2 siblings, 0 replies; 91+ messages in thread
From: Alexandre IOOSS @ 2021-08-14 9:02 UTC (permalink / raw)
To: Peter Maydell, qemu-arm, qemu-devel
Cc: Damien Hedde, Alistair Francis, Luc Michel, Joel Stanley,
Subbaraya Sundeep
[-- Attachment #1.1: Type: text/plain, Size: 827 bytes --]
On 8/12/21 11:33 AM, Peter Maydell wrote:
> Wire up the sysclk and refclk for the stm32f205 SoC. This SoC always
> runs the systick refclk at 1/8 the frequency of the main CPU clock,
> so the board code only needs to provide a single sysclk clock.
>
> Because there is only one board using this SoC, we convert the SoC
> and the board together, rather than splitting it into "add clock to
> SoC; connect clock in board; add error check in SoC code that clock
> is wired up".
>
> When the systick device starts honouring its clock inputs, this will
> fix an emulation inaccuracy in the netduino2 board where the systick
> reference clock was running at 1MHz rather than 15MHz.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alexandre Iooss <erdnaxe@crans.org>
-- Alexandre
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^ permalink raw reply [flat|nested] 91+ messages in thread
* Re: [PATCH for-6.2 13/25] hw/arm/stm32f405: Wire up sysclk and refclk
2021-08-12 9:33 ` [PATCH for-6.2 13/25] hw/arm/stm32f405: " Peter Maydell
2021-08-13 1:37 ` Alistair Francis
@ 2021-08-14 9:03 ` Alexandre IOOSS
2021-08-17 9:47 ` Luc Michel
2 siblings, 0 replies; 91+ messages in thread
From: Alexandre IOOSS @ 2021-08-14 9:03 UTC (permalink / raw)
To: Peter Maydell, qemu-arm, qemu-devel
Cc: Damien Hedde, Alistair Francis, Luc Michel, Joel Stanley,
Subbaraya Sundeep
[-- Attachment #1.1: Type: text/plain, Size: 831 bytes --]
On 8/12/21 11:33 AM, Peter Maydell wrote:
> Wire up the sysclk and refclk for the stm32f405 SoC. This SoC always
> runs the systick refclk at 1/8 the frequency of the main CPU clock,
> so the board code only needs to provide a single sysclk clock.
>
> Because there is only one board using this SoC, we convert the SoC
> and the board together, rather than splitting it into "add clock to
> SoC; connect clock in board; add error check in SoC code that clock
> is wired up".
>
> When the systick device starts honouring its clock inputs, this will
> fix an emulation inaccuracy in the netduinoplus2 board where the
> systick reference clock was running at 1MHz rather than 21MHz.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alexandre Iooss <erdnaxe@crans.org>
-- Alexandre
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^ permalink raw reply [flat|nested] 91+ messages in thread
* Re: [PATCH for-6.2 15/25] hw/arm/nrf51: Wire up sysclk
2021-08-12 9:33 ` [PATCH for-6.2 15/25] hw/arm/nrf51: Wire up sysclk Peter Maydell
@ 2021-08-14 9:06 ` Alexandre IOOSS
0 siblings, 0 replies; 91+ messages in thread
From: Alexandre IOOSS @ 2021-08-14 9:06 UTC (permalink / raw)
To: Peter Maydell, qemu-arm, qemu-devel
Cc: Damien Hedde, Alistair Francis, Luc Michel, Joel Stanley,
Subbaraya Sundeep
[-- Attachment #1.1: Type: text/plain, Size: 502 bytes --]
On 8/12/21 11:33 AM, Peter Maydell wrote:
> Wire up the sysclk input to the armv7m object.
>
> Strictly this SoC should not have a systick device at all, but our
> armv7m container object doesn't currently support disabling the
> systick device. For the moment, add a TODO comment, but note that
> this is why we aren't wiring up a refclk (no need for one).
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alexandre Iooss <erdnaxe@crans.org>
-- Alexandre
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^ permalink raw reply [flat|nested] 91+ messages in thread
* Re: [PATCH for-6.2 16/25] hw/arm/stellaris: split stellaris_sys_init()
2021-08-12 9:33 ` [PATCH for-6.2 16/25] hw/arm/stellaris: split stellaris_sys_init() Peter Maydell
@ 2021-08-14 9:10 ` Alexandre IOOSS
0 siblings, 0 replies; 91+ messages in thread
From: Alexandre IOOSS @ 2021-08-14 9:10 UTC (permalink / raw)
To: Peter Maydell, qemu-arm, qemu-devel
Cc: Damien Hedde, Alistair Francis, Luc Michel, Joel Stanley,
Subbaraya Sundeep
[-- Attachment #1.1: Type: text/plain, Size: 879 bytes --]
On 8/12/21 11:33 AM, Peter Maydell wrote:
> Currently the stellaris_sys_init() function creates the
> TYPE_STELLARIS_SYS object, sets its properties, realizes it, maps its
> MMIO region and connects its IRQ. In order to support wiring the
> sysclk up to the armv7m object, we need to split this function apart,
> because to connect the clock output of the STELLARIS_SYS object to
> the armv7m object we need to create the STELLARIS_SYS object before
> the armv7m object, but we can't wire up the IRQ until after we've
> created the armv7m object.
>
> Remove the stellaris_sys_init() function, and instead put the
> create/configure/realize parts before we create the armv7m object and
> the mmio/irq connection parts afterwards.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alexandre Iooss <erdnaxe@crans.org>
-- Alexandre
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^ permalink raw reply [flat|nested] 91+ messages in thread
* Re: [PATCH for-6.2 17/25] hw/arm/stellaris: Wire sysclk up to armv7m
2021-08-12 9:33 ` [PATCH for-6.2 17/25] hw/arm/stellaris: Wire sysclk up to armv7m Peter Maydell
@ 2021-08-14 9:12 ` Alexandre IOOSS
0 siblings, 0 replies; 91+ messages in thread
From: Alexandre IOOSS @ 2021-08-14 9:12 UTC (permalink / raw)
To: Peter Maydell, qemu-arm, qemu-devel
Cc: Damien Hedde, Alistair Francis, Luc Michel, Joel Stanley,
Subbaraya Sundeep
[-- Attachment #1.1: Type: text/plain, Size: 333 bytes --]
On 8/12/21 11:33 AM, Peter Maydell wrote:
> Connect the sysclk to the armv7m object. This board's SoC does not
> connect up the systick reference clock, so we don't need to connect a
> refclk.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alexandre Iooss <erdnaxe@crans.org>
-- Alexandre
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^ permalink raw reply [flat|nested] 91+ messages in thread
* Re: [PATCH for-6.2 18/25] hw/arm/msf2_soc: Don't allocate separate MemoryRegions
2021-08-12 9:33 ` [PATCH for-6.2 18/25] hw/arm/msf2_soc: Don't allocate separate MemoryRegions Peter Maydell
@ 2021-08-14 9:13 ` Alexandre IOOSS
0 siblings, 0 replies; 91+ messages in thread
From: Alexandre IOOSS @ 2021-08-14 9:13 UTC (permalink / raw)
To: Peter Maydell, qemu-arm, qemu-devel
Cc: Damien Hedde, Alistair Francis, Luc Michel, Joel Stanley,
Subbaraya Sundeep
[-- Attachment #1.1: Type: text/plain, Size: 423 bytes --]
On 8/12/21 11:33 AM, Peter Maydell wrote:
> In the realize method of the msf2-soc SoC object, we call g_new() to
> create new MemoryRegion objects for the nvm, nvm_alias, and sram.
> This is unnecessary; make these MemoryRegions member fields of the
> device state struct instead.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alexandre Iooss <erdnaxe@crans.org>
-- Alexandre
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^ permalink raw reply [flat|nested] 91+ messages in thread
* Re: [PATCH for-6.2 19/25] hw/arm/msf2: Use Clock input to MSF2_SOC instead of m3clk property
2021-08-12 9:33 ` [PATCH for-6.2 19/25] hw/arm/msf2: Use Clock input to MSF2_SOC instead of m3clk property Peter Maydell
@ 2021-08-14 9:20 ` Alexandre IOOSS
2021-08-14 10:11 ` Peter Maydell
0 siblings, 1 reply; 91+ messages in thread
From: Alexandre IOOSS @ 2021-08-14 9:20 UTC (permalink / raw)
To: Peter Maydell, qemu-arm, qemu-devel
Cc: Damien Hedde, Alistair Francis, Luc Michel, Joel Stanley,
Subbaraya Sundeep
[-- Attachment #1.1: Type: text/plain, Size: 6288 bytes --]
On 8/12/21 11:33 AM, Peter Maydell wrote:
> Instead of passing the MSF2 SoC an integer property specifying the
> CPU clock rate, pass it a Clock instead. This lets us wire that
> clock up to the armv7m object.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
> include/hw/arm/msf2-soc.h | 3 ++-
> hw/arm/msf2-soc.c | 28 +++++++++++++++++-----------
> hw/arm/msf2-som.c | 7 ++++++-
> 3 files changed, 25 insertions(+), 13 deletions(-)
>
> diff --git a/include/hw/arm/msf2-soc.h b/include/hw/arm/msf2-soc.h
> index 38e10ce20aa..01f904cec47 100644
> --- a/include/hw/arm/msf2-soc.h
> +++ b/include/hw/arm/msf2-soc.h
> @@ -30,6 +30,7 @@
> #include "hw/misc/msf2-sysreg.h"
> #include "hw/ssi/mss-spi.h"
> #include "hw/net/msf2-emac.h"
> +#include "hw/clock.h"
> #include "qom/object.h"
>
> #define TYPE_MSF2_SOC "msf2-soc"
> @@ -57,7 +58,7 @@ struct MSF2State {
> uint64_t envm_size;
> uint64_t esram_size;
>
> - uint32_t m3clk;
> + Clock *m3clk;
> uint8_t apb0div;
> uint8_t apb1div;
>
> diff --git a/hw/arm/msf2-soc.c b/hw/arm/msf2-soc.c
> index f36788054b3..0a1e594aee6 100644
> --- a/hw/arm/msf2-soc.c
> +++ b/hw/arm/msf2-soc.c
> @@ -29,6 +29,7 @@
> #include "hw/char/serial.h"
> #include "hw/arm/msf2-soc.h"
> #include "hw/misc/unimp.h"
> +#include "hw/qdev-clock.h"
> #include "sysemu/sysemu.h"
>
> #define MSF2_TIMER_BASE 0x40004000
> @@ -73,6 +74,8 @@ static void m2sxxx_soc_initfn(Object *obj)
> }
>
> object_initialize_child(obj, "emac", &s->emac, TYPE_MSS_EMAC);
> +
> + s->m3clk = qdev_init_clock_in(DEVICE(obj), "m3clk", NULL, NULL, 0);
> }
>
> static void m2sxxx_soc_realize(DeviceState *dev_soc, Error **errp)
> @@ -84,6 +87,11 @@ static void m2sxxx_soc_realize(DeviceState *dev_soc, Error **errp)
>
> MemoryRegion *system_memory = get_system_memory();
>
> + if (!clock_has_source(s->m3clk)) {
> + error_setg(errp, "m3clk must be wired up by the board code");
> + return;
> + }
> +
> memory_region_init_rom(&s->nvm, OBJECT(dev_soc), "MSF2.eNVM", s->envm_size,
> &error_fatal);
> /*
> @@ -106,19 +114,14 @@ static void m2sxxx_soc_realize(DeviceState *dev_soc, Error **errp)
> qdev_prop_set_uint32(armv7m, "num-irq", 81);
> qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type);
> qdev_prop_set_bit(armv7m, "enable-bitband", true);
> + qdev_connect_clock_in(armv7m, "cpuclk", s->m3clk);
> object_property_set_link(OBJECT(&s->armv7m), "memory",
> OBJECT(get_system_memory()), &error_abort);
> if (!sysbus_realize(SYS_BUS_DEVICE(&s->armv7m), errp)) {
> return;
> }
>
> - if (!s->m3clk) {
> - error_setg(errp, "Invalid m3clk value");
> - error_append_hint(errp, "m3clk can not be zero\n");
> - return;
> - }
> -
> - system_clock_scale = NANOSECONDS_PER_SECOND / s->m3clk;
> + system_clock_scale = clock_ticks_to_ns(s->m3clk, 1);
>
> for (i = 0; i < MSF2_NUM_UARTS; i++) {
> if (serial_hd(i)) {
> @@ -129,8 +132,13 @@ static void m2sxxx_soc_realize(DeviceState *dev_soc, Error **errp)
> }
>
> dev = DEVICE(&s->timer);
> - /* APB0 clock is the timer input clock */
> - qdev_prop_set_uint32(dev, "clock-frequency", s->m3clk / s->apb0div);
> + /*
> + * APB0 clock is the timer input clock.
> + * TODO: ideally the MSF2 timer device should use a Clock rather than a
> + * clock-frequency integer property.
> + */
> + qdev_prop_set_uint32(dev, "clock-frequency",
> + clock_get_hz(s->m3clk) / s->apb0div);
> if (!sysbus_realize(SYS_BUS_DEVICE(&s->timer), errp)) {
> return;
> }
> @@ -207,8 +215,6 @@ static Property m2sxxx_soc_properties[] = {
> DEFINE_PROP_UINT64("eNVM-size", MSF2State, envm_size, MSF2_ENVM_MAX_SIZE),
> DEFINE_PROP_UINT64("eSRAM-size", MSF2State, esram_size,
> MSF2_ESRAM_MAX_SIZE),
> - /* Libero GUI shows 100Mhz as default for clocks */
> - DEFINE_PROP_UINT32("m3clk", MSF2State, m3clk, 100 * 1000000),
> /* default divisors in Libero GUI */
> DEFINE_PROP_UINT8("apb0div", MSF2State, apb0div, 2),
> DEFINE_PROP_UINT8("apb1div", MSF2State, apb1div, 2),
> diff --git a/hw/arm/msf2-som.c b/hw/arm/msf2-som.c
> index 343ec977c07..396e8b99138 100644
> --- a/hw/arm/msf2-som.c
> +++ b/hw/arm/msf2-som.c
> @@ -29,6 +29,7 @@
> #include "hw/boards.h"
> #include "hw/qdev-properties.h"
> #include "hw/arm/boot.h"
> +#include "hw/qdev-clock.h"
> #include "exec/address-spaces.h"
> #include "hw/arm/msf2-soc.h"
>
> @@ -49,6 +50,7 @@ static void emcraft_sf2_s2s010_init(MachineState *machine)
> BusState *spi_bus;
> MemoryRegion *sysmem = get_system_memory();
> MemoryRegion *ddr = g_new(MemoryRegion, 1);
> + Clock *m3clk;
>
> if (strcmp(machine->cpu_type, mc->default_cpu_type) != 0) {
> error_report("This board can only be used with CPU %s",
> @@ -72,7 +74,10 @@ static void emcraft_sf2_s2s010_init(MachineState *machine)
> * in Libero. CPU clock is divided by APB0 and APB1 divisors for
> * peripherals. Emcraft's SoM kit comes with these settings by default.
> */
> - qdev_prop_set_uint32(dev, "m3clk", 142 * 1000000);
> + /* This clock doesn't need migration because it is fixed-frequency */
> + m3clk = clock_new(OBJECT(machine), "m3clk");
> + clock_set_hz(m3clk, 142 * 1000000);
Maybe something could be added in the commit message to say that M3_CLK
is changed from 100MHz to 142MHz. I do not know the SmartFusion2 but the
clocking guide seems to agree with 142MHz:
https://www.microsemi.com/document-portal/doc_download/132012-ug0449-smartfusion2-and-igloo2-clocking-resources-user-guide
> + qdev_connect_clock_in(dev, "m3clk", m3clk);
> qdev_prop_set_uint32(dev, "apb0div", 2);
> qdev_prop_set_uint32(dev, "apb1div", 2);
>
>
Reviewed-by: Alexandre Iooss <erdnaxe@crans.org>
Thanks,
-- Alexandre
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^ permalink raw reply [flat|nested] 91+ messages in thread
* Re: [PATCH for-6.2 22/25] hw/arm/stellaris: Fix code style issues in GPTM code
2021-08-12 9:33 ` [PATCH for-6.2 22/25] hw/arm/stellaris: Fix code style issues in GPTM code Peter Maydell
@ 2021-08-14 9:26 ` Alexandre IOOSS
0 siblings, 0 replies; 91+ messages in thread
From: Alexandre IOOSS @ 2021-08-14 9:26 UTC (permalink / raw)
To: Peter Maydell, qemu-arm, qemu-devel
Cc: Damien Hedde, Alistair Francis, Luc Michel, Joel Stanley,
Subbaraya Sundeep
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On 8/12/21 11:33 AM, Peter Maydell wrote:
> Fix the code style issues in the Stellaris general purpose timer
> module code, so that when we move it to a different file in a
> following patch checkpatch doesn't complain.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alexandre Iooss <erdnaxe@crans.org>
Thanks,
-- Alexandre
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^ permalink raw reply [flat|nested] 91+ messages in thread
* Re: [PATCH for-6.2 19/25] hw/arm/msf2: Use Clock input to MSF2_SOC instead of m3clk property
2021-08-14 9:20 ` Alexandre IOOSS
@ 2021-08-14 10:11 ` Peter Maydell
2021-08-14 10:47 ` Alexandre IOOSS
0 siblings, 1 reply; 91+ messages in thread
From: Peter Maydell @ 2021-08-14 10:11 UTC (permalink / raw)
To: Alexandre IOOSS
Cc: Damien Hedde, Luc Michel, Alistair Francis, QEMU Developers,
Subbaraya Sundeep, qemu-arm, Joel Stanley
On Sat, 14 Aug 2021 at 10:20, Alexandre IOOSS <erdnaxe@crans.org> wrote:
>
>
> On 8/12/21 11:33 AM, Peter Maydell wrote:
> > Instead of passing the MSF2 SoC an integer property specifying the
> > CPU clock rate, pass it a Clock instead. This lets us wire that
> > clock up to the armv7m object.
> >
> > Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> > @@ -72,7 +74,10 @@ static void emcraft_sf2_s2s010_init(MachineState *machine)
> > * in Libero. CPU clock is divided by APB0 and APB1 divisors for
> > * peripherals. Emcraft's SoM kit comes with these settings by default.
> > */
> > - qdev_prop_set_uint32(dev, "m3clk", 142 * 1000000);
> > + /* This clock doesn't need migration because it is fixed-frequency */
> > + m3clk = clock_new(OBJECT(machine), "m3clk");
> > + clock_set_hz(m3clk, 142 * 1000000);
>
> Maybe something could be added in the commit message to say that M3_CLK
> is changed from 100MHz to 142MHz.
I'm not sure what you mean here? This commit doesn't change the frequency:
we previously set the m3clk property to "142 * 1000000" and now we set the
clock's hz setting to the same thing.
The old m3clk property had a default value of 100 * 1000000, but nothing
ever used that because the only user of the device (this board code)
set the property explicitly to some value. With the new Clock-based
setup there is no default value at all, because the board code must
always connect a clock, and will set its frequency to whatever is
right for that board.
-- PMM
^ permalink raw reply [flat|nested] 91+ messages in thread
* Re: [PATCH for-6.2 19/25] hw/arm/msf2: Use Clock input to MSF2_SOC instead of m3clk property
2021-08-14 10:11 ` Peter Maydell
@ 2021-08-14 10:47 ` Alexandre IOOSS
0 siblings, 0 replies; 91+ messages in thread
From: Alexandre IOOSS @ 2021-08-14 10:47 UTC (permalink / raw)
To: Peter Maydell
Cc: Damien Hedde, Luc Michel, Alistair Francis, QEMU Developers,
Subbaraya Sundeep, qemu-arm, Joel Stanley
[-- Attachment #1.1: Type: text/plain, Size: 1357 bytes --]
On 8/14/21 12:11 PM, Peter Maydell wrote:
> On Sat, 14 Aug 2021 at 10:20, Alexandre IOOSS <erdnaxe@crans.org> wrote:
>>
>>
>> On 8/12/21 11:33 AM, Peter Maydell wrote:
>>> Instead of passing the MSF2 SoC an integer property specifying the
>>> CPU clock rate, pass it a Clock instead. This lets us wire that
>>> clock up to the armv7m object.
>>>
>>> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
>
>>> @@ -72,7 +74,10 @@ static void emcraft_sf2_s2s010_init(MachineState *machine)
>>> * in Libero. CPU clock is divided by APB0 and APB1 divisors for
>>> * peripherals. Emcraft's SoM kit comes with these settings by default.
>>> */
>>> - qdev_prop_set_uint32(dev, "m3clk", 142 * 1000000);
>>> + /* This clock doesn't need migration because it is fixed-frequency */
>>> + m3clk = clock_new(OBJECT(machine), "m3clk");
>>> + clock_set_hz(m3clk, 142 * 1000000);
>>
>> Maybe something could be added in the commit message to say that M3_CLK
>> is changed from 100MHz to 142MHz.
>
> I'm not sure what you mean here? This commit doesn't change the frequency:
> we previously set the m3clk property to "142 * 1000000" and now we set the
> clock's hz setting to the same thing.
My bad, I did not realize the board was already setting the frequency to
142MHz.
Thanks,
-- Alexandre
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^ permalink raw reply [flat|nested] 91+ messages in thread
* Re: [PATCH for-6.2 09/25] clock: Provide builtin multiplier/divider
2021-08-12 9:33 ` [PATCH for-6.2 09/25] clock: Provide builtin multiplier/divider Peter Maydell
2021-08-12 12:08 ` Alexandre IOOSS
2021-08-13 1:33 ` Alistair Francis
@ 2021-08-15 16:32 ` Philippe Mathieu-Daudé
2021-08-16 9:05 ` Peter Maydell
2021-08-15 21:27 ` Luc Michel
2021-08-17 9:59 ` Damien Hedde
4 siblings, 1 reply; 91+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-08-15 16:32 UTC (permalink / raw)
To: Peter Maydell, qemu-arm, qemu-devel
Cc: Damien Hedde, Luc Michel, Alistair Francis, Subbaraya Sundeep,
Joel Stanley, Alexandre Iooss
On 8/12/21 11:33 AM, Peter Maydell wrote:
> It is quite common for a clock tree to involve possibly programmable
> clock multipliers or dividers, where the frequency of a clock is for
> instance divided by 8 to produce a slower clock to feed to a
> particular device.
>
> Currently we provide no convenient mechanism for modelling this. You
> can implement it by having an input Clock and an output Clock, and
> manually setting the period of the output clock in the period-changed
> callback of the input clock, but that's quite clunky.
>
> This patch adds support in the Clock objects themselves for setting a
> multiplier or divider. The effect of setting this on a clock is that
> when the clock's period is changed, all the children of the clock are
> set to period * multiplier / divider, rather than being set to the
> same period as the parent clock.
This is super nice!
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
> docs/devel/clocks.rst | 23 +++++++++++++++++++++++
> include/hw/clock.h | 29 +++++++++++++++++++++++++++++
> hw/core/clock-vmstate.c | 24 +++++++++++++++++++++++-
> hw/core/clock.c | 29 +++++++++++++++++++++++++----
> 4 files changed, 100 insertions(+), 5 deletions(-)
> +void clock_set_mul_div(Clock *clk, uint32_t multiplier, uint32_t divider)
> +{
> + assert(divider != 0);
I only wonder if we shouldn't check clock_is_enabled() here.
Maybe not assert, but at least report a GUEST_ERROR?
Also a trace-event "mul: %u -> %u, div: %u -> %u" would be useful IMHO.
> + clk->multiplier = multiplier;
> + clk->divider = divider;
> +}
^ permalink raw reply [flat|nested] 91+ messages in thread
* Re: [PATCH for-6.2 10/25] hw/arm: Don't allocate separate MemoryRegions in stm32 SoC realize
2021-08-12 12:27 ` Peter Maydell
@ 2021-08-15 16:37 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 91+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-08-15 16:37 UTC (permalink / raw)
To: Peter Maydell, Alexandre IOOSS, Igor Mammedov
Cc: Damien Hedde, Luc Michel, Alistair Francis, QEMU Developers,
Subbaraya Sundeep, qemu-arm, Joel Stanley
On 8/12/21 2:27 PM, Peter Maydell wrote:
> On Thu, 12 Aug 2021 at 13:13, Alexandre IOOSS <erdnaxe@crans.org> wrote:
>>
>> On 8/12/21 11:33 AM, Peter Maydell wrote:
>>> In the realize methods of the stm32f100 and stm32f205 SoC objects, we
>>> call g_new() to create new MemoryRegion objjects for the sram, flash,
>>> and flash_alias. This is unnecessary (and leaves open the
>>> possibility of leaking the allocations if we exit from realize with
>>> an error). Make these MemoryRegions member fields of the device
>>> state struct instead, as stm32f405 already does.
>>
>> There is a typo in "objjects".
>>
>> This is something I had issue understanding as I was seeing both
>> patterns in the codebase, thank you for making this clear.
>
> Basically if there's a struct that the MemoryRegion can live
> in then that's the best place for it. For some board-level code
> where we haven't needed to subclass MachineState there is no
> convenient struct, so we just g_new(). In a few places like this
> one the board-code pattern has been copied into an SoC object.
FYI since more than 2 years now Igor recommends using DEFINE_TYPES()
for newer QOM style, which makes adding board-specific fields to
MachineState quite easy (see hw/avr/arduino.c or hw/arm/raspi.c).
^ permalink raw reply [flat|nested] 91+ messages in thread
* Re: [PATCH for-6.2 01/25] arm: Move M-profile RAS register block into its own device
2021-08-12 9:33 ` [PATCH for-6.2 01/25] arm: Move M-profile RAS register block into its own device Peter Maydell
2021-08-12 11:08 ` Alexandre IOOSS
2021-08-13 0:59 ` Alistair Francis
@ 2021-08-15 17:30 ` Philippe Mathieu-Daudé
2021-08-16 7:28 ` David Hildenbrand
2021-08-16 9:16 ` Peter Maydell
2021-08-17 8:25 ` Luc Michel
3 siblings, 2 replies; 91+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-08-15 17:30 UTC (permalink / raw)
To: Peter Maydell, qemu-arm, qemu-devel, Peter Xu, David Hildenbrand
Cc: Damien Hedde, Luc Michel, Alistair Francis, Subbaraya Sundeep,
Joel Stanley, Alexandre Iooss
+Peter/David
On 8/12/21 11:33 AM, Peter Maydell wrote:
> Currently we implement the RAS register block within the NVIC device.
> It isn't really very tightly coupled with the NVIC proper, so instead
> move it out into a sysbus device of its own and have the top level
> ARMv7M container create it and map it into memory at the right
> address.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
> include/hw/arm/armv7m.h | 2 +
> include/hw/intc/armv7m_nvic.h | 1 -
> include/hw/misc/armv7m_ras.h | 37 ++++++++++++++
> hw/arm/armv7m.c | 12 +++++
> hw/intc/armv7m_nvic.c | 56 ---------------------
> hw/misc/armv7m_ras.c | 93 +++++++++++++++++++++++++++++++++++
> MAINTAINERS | 2 +
> hw/misc/meson.build | 2 +
> 8 files changed, 148 insertions(+), 57 deletions(-)
> create mode 100644 include/hw/misc/armv7m_ras.h
> create mode 100644 hw/misc/armv7m_ras.c
> diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c
> index 9ce5c30cd5c..8964730d153 100644
> --- a/hw/arm/armv7m.c
> +++ b/hw/arm/armv7m.c
> @@ -231,6 +231,18 @@ static void armv7m_realize(DeviceState *dev, Error **errp)
> memory_region_add_subregion(&s->container, 0xe0000000,
> sysbus_mmio_get_region(sbd, 0));
>
> + /* If the CPU has RAS support, create the RAS register block */
> + if (cpu_isar_feature(aa32_ras, s->cpu)) {
> + object_initialize_child(OBJECT(dev), "armv7m-ras",
> + &s->ras, TYPE_ARMV7M_RAS);
> + sbd = SYS_BUS_DEVICE(&s->ras);
> + if (!sysbus_realize(sbd, errp)) {
> + return;
> + }
> + memory_region_add_subregion_overlap(&s->container, 0xe0005000,
> + sysbus_mmio_get_region(sbd, 0), 1);
Just curious, is the overlap really needed? I see the NVIC default
region is 1 MiB wide. Aren't smaller regions returned first when
multiple regions have same priority? This might be one of my
misunderstandings with QEMU MR/AS APIs. Without looking at the
code, assuming 2 MRs overlapping with the same priority, is there
some assumption which one will be hit first?
> + }
> +
> for (i = 0; i < ARRAY_SIZE(s->bitband); i++) {
> if (s->enable_bitband) {
> Object *obj = OBJECT(&s->bitband[i]);
^ permalink raw reply [flat|nested] 91+ messages in thread
* Re: [PATCH for-6.2 09/25] clock: Provide builtin multiplier/divider
2021-08-12 9:33 ` [PATCH for-6.2 09/25] clock: Provide builtin multiplier/divider Peter Maydell
` (2 preceding siblings ...)
2021-08-15 16:32 ` Philippe Mathieu-Daudé
@ 2021-08-15 21:27 ` Luc Michel
2021-08-17 9:59 ` Damien Hedde
4 siblings, 0 replies; 91+ messages in thread
From: Luc Michel @ 2021-08-15 21:27 UTC (permalink / raw)
To: Peter Maydell
Cc: Damien Hedde, Alistair Francis, qemu-devel, Subbaraya Sundeep,
qemu-arm, Joel Stanley, Alexandre Iooss
Hi Peter,
On 10:33 Thu 12 Aug , Peter Maydell wrote:
> diff --git a/hw/core/clock.c b/hw/core/clock.c
> index fc5a99683f8..c371b9e977a 100644
> --- a/hw/core/clock.c
> +++ b/hw/core/clock.c
> @@ -133,10 +143,21 @@ char *clock_display_freq(Clock *clk)
> return freq_to_str(clock_get_hz(clk));
> }
>
> +void clock_set_mul_div(Clock *clk, uint32_t multiplier, uint32_t divider)
> +{
> + assert(divider != 0);
> +
Maybe add a trace here to ease debugging?
> + clk->multiplier = multiplier;
> + clk->divider = divider;
> +}
> +
Otherwise:
Reviewed-by: Luc Michel <luc@lmichel.fr>
^ permalink raw reply [flat|nested] 91+ messages in thread
* Re: [PATCH for-6.2 01/25] arm: Move M-profile RAS register block into its own device
2021-08-15 17:30 ` Philippe Mathieu-Daudé
@ 2021-08-16 7:28 ` David Hildenbrand
2021-08-16 9:16 ` Peter Maydell
1 sibling, 0 replies; 91+ messages in thread
From: David Hildenbrand @ 2021-08-16 7:28 UTC (permalink / raw)
To: Philippe Mathieu-Daudé,
Peter Maydell, qemu-arm, qemu-devel, Peter Xu
Cc: Damien Hedde, Luc Michel, Alistair Francis, Subbaraya Sundeep,
Joel Stanley, Alexandre Iooss
On 15.08.21 19:30, Philippe Mathieu-Daudé wrote:
> +Peter/David
>
> On 8/12/21 11:33 AM, Peter Maydell wrote:
>> Currently we implement the RAS register block within the NVIC device.
>> It isn't really very tightly coupled with the NVIC proper, so instead
>> move it out into a sysbus device of its own and have the top level
>> ARMv7M container create it and map it into memory at the right
>> address.
>>
>> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
>> ---
>> include/hw/arm/armv7m.h | 2 +
>> include/hw/intc/armv7m_nvic.h | 1 -
>> include/hw/misc/armv7m_ras.h | 37 ++++++++++++++
>> hw/arm/armv7m.c | 12 +++++
>> hw/intc/armv7m_nvic.c | 56 ---------------------
>> hw/misc/armv7m_ras.c | 93 +++++++++++++++++++++++++++++++++++
>> MAINTAINERS | 2 +
>> hw/misc/meson.build | 2 +
>> 8 files changed, 148 insertions(+), 57 deletions(-)
>> create mode 100644 include/hw/misc/armv7m_ras.h
>> create mode 100644 hw/misc/armv7m_ras.c
>
>> diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c
>> index 9ce5c30cd5c..8964730d153 100644
>> --- a/hw/arm/armv7m.c
>> +++ b/hw/arm/armv7m.c
>> @@ -231,6 +231,18 @@ static void armv7m_realize(DeviceState *dev, Error **errp)
>> memory_region_add_subregion(&s->container, 0xe0000000,
>> sysbus_mmio_get_region(sbd, 0));
>>
>> + /* If the CPU has RAS support, create the RAS register block */
>> + if (cpu_isar_feature(aa32_ras, s->cpu)) {
>> + object_initialize_child(OBJECT(dev), "armv7m-ras",
>> + &s->ras, TYPE_ARMV7M_RAS);
>> + sbd = SYS_BUS_DEVICE(&s->ras);
>> + if (!sysbus_realize(sbd, errp)) {
>> + return;
>> + }
>> + memory_region_add_subregion_overlap(&s->container, 0xe0005000,
>> + sysbus_mmio_get_region(sbd, 0), 1);
>
> Just curious, is the overlap really needed? I see the NVIC default
> region is 1 MiB wide. Aren't smaller regions returned first when
> multiple regions have same priority? This might be one of my
> misunderstandings with QEMU MR/AS APIs. Without looking at the
> code, assuming 2 MRs overlapping with the same priority, is there
> some assumption which one will be hit first?
>
memory_region_add_subregion() documents "The subregion may not overlap
with other subregions", however it really just translates to adding with
priority 0.
memory_region_add_subregion_overlap documents "The subregion may overlap
with other subregions. Conflicts are resolved by having a higher
@priority hide a lower @priority. Subregions without priority are taken
as @priority 0 ... highest priority wins"
AFAIU, overlaps with same priority (e.g., 0) have undefined behavior and
we should really be using memory_region_add_subregion_overlap() with
proper priorities.
>> + }
>> +
>> for (i = 0; i < ARRAY_SIZE(s->bitband); i++) {
>> if (s->enable_bitband) {
>> Object *obj = OBJECT(&s->bitband[i]);
>
--
Thanks,
David / dhildenb
^ permalink raw reply [flat|nested] 91+ messages in thread
* Re: [PATCH for-6.2 09/25] clock: Provide builtin multiplier/divider
2021-08-15 16:32 ` Philippe Mathieu-Daudé
@ 2021-08-16 9:05 ` Peter Maydell
2021-08-16 9:32 ` Philippe Mathieu-Daudé
0 siblings, 1 reply; 91+ messages in thread
From: Peter Maydell @ 2021-08-16 9:05 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: Damien Hedde, Luc Michel, Alistair Francis, QEMU Developers,
Subbaraya Sundeep, qemu-arm, Joel Stanley, Alexandre Iooss
On Sun, 15 Aug 2021 at 17:32, Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
>
> On 8/12/21 11:33 AM, Peter Maydell wrote:
> > It is quite common for a clock tree to involve possibly programmable
> > clock multipliers or dividers, where the frequency of a clock is for
> > instance divided by 8 to produce a slower clock to feed to a
> > particular device.
> >
> > Currently we provide no convenient mechanism for modelling this. You
> > can implement it by having an input Clock and an output Clock, and
> > manually setting the period of the output clock in the period-changed
> > callback of the input clock, but that's quite clunky.
> >
> > This patch adds support in the Clock objects themselves for setting a
> > multiplier or divider. The effect of setting this on a clock is that
> > when the clock's period is changed, all the children of the clock are
> > set to period * multiplier / divider, rather than being set to the
> > same period as the parent clock.
>
> This is super nice!
>
> > Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> > ---
> > docs/devel/clocks.rst | 23 +++++++++++++++++++++++
> > include/hw/clock.h | 29 +++++++++++++++++++++++++++++
> > hw/core/clock-vmstate.c | 24 +++++++++++++++++++++++-
> > hw/core/clock.c | 29 +++++++++++++++++++++++++----
> > 4 files changed, 100 insertions(+), 5 deletions(-)
>
> > +void clock_set_mul_div(Clock *clk, uint32_t multiplier, uint32_t divider)
> > +{
> > + assert(divider != 0);
>
> I only wonder if we shouldn't check clock_is_enabled() here.
> Maybe not assert, but at least report a GUEST_ERROR?
Setting the multiplier on a disabled clock doesn't seem like
an error to me. I would expect a common way for the guest to
program a clock-controller would be "first set the divider
and any other parameters; finally, enable the clock".
-- PMM
^ permalink raw reply [flat|nested] 91+ messages in thread
* Re: [PATCH for-6.2 01/25] arm: Move M-profile RAS register block into its own device
2021-08-15 17:30 ` Philippe Mathieu-Daudé
2021-08-16 7:28 ` David Hildenbrand
@ 2021-08-16 9:16 ` Peter Maydell
1 sibling, 0 replies; 91+ messages in thread
From: Peter Maydell @ 2021-08-16 9:16 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: Damien Hedde, Luc Michel, David Hildenbrand, Alistair Francis,
QEMU Developers, Peter Xu, Subbaraya Sundeep, qemu-arm,
Joel Stanley, Alexandre Iooss
On Sun, 15 Aug 2021 at 18:30, Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
>
> +Peter/David
>
> On 8/12/21 11:33 AM, Peter Maydell wrote:
> > Currently we implement the RAS register block within the NVIC device.
> > It isn't really very tightly coupled with the NVIC proper, so instead
> > move it out into a sysbus device of its own and have the top level
> > ARMv7M container create it and map it into memory at the right
> > address.
> >
> > Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> > ---
> > include/hw/arm/armv7m.h | 2 +
> > include/hw/intc/armv7m_nvic.h | 1 -
> > include/hw/misc/armv7m_ras.h | 37 ++++++++++++++
> > hw/arm/armv7m.c | 12 +++++
> > hw/intc/armv7m_nvic.c | 56 ---------------------
> > hw/misc/armv7m_ras.c | 93 +++++++++++++++++++++++++++++++++++
> > MAINTAINERS | 2 +
> > hw/misc/meson.build | 2 +
> > 8 files changed, 148 insertions(+), 57 deletions(-)
> > create mode 100644 include/hw/misc/armv7m_ras.h
> > create mode 100644 hw/misc/armv7m_ras.c
>
> > diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c
> > index 9ce5c30cd5c..8964730d153 100644
> > --- a/hw/arm/armv7m.c
> > +++ b/hw/arm/armv7m.c
> > @@ -231,6 +231,18 @@ static void armv7m_realize(DeviceState *dev, Error **errp)
> > memory_region_add_subregion(&s->container, 0xe0000000,
> > sysbus_mmio_get_region(sbd, 0));
> >
> > + /* If the CPU has RAS support, create the RAS register block */
> > + if (cpu_isar_feature(aa32_ras, s->cpu)) {
> > + object_initialize_child(OBJECT(dev), "armv7m-ras",
> > + &s->ras, TYPE_ARMV7M_RAS);
> > + sbd = SYS_BUS_DEVICE(&s->ras);
> > + if (!sysbus_realize(sbd, errp)) {
> > + return;
> > + }
> > + memory_region_add_subregion_overlap(&s->container, 0xe0005000,
> > + sysbus_mmio_get_region(sbd, 0), 1);
>
> Just curious, is the overlap really needed?
Yes, because this block is currently in the middle of the
PPB-area region provided by the NVIC, and needs to take priority
over it. Once the refactoring is complete, the background-region
will also be created in this armv7m realize function, but the
RAS block still needs to go above it.
> I see the NVIC default
> region is 1 MiB wide. Aren't smaller regions returned first when
> multiple regions have same priority?
As David says, if you don't specify the priority then it's
pot-luck which one you see. Having overlaps and not setting
priorities is a QEMU bug. (We used to have some code to print
a warning about unintentionally overlapping regions, but it was
always disabled with #if 0 and we eventually deleted it in commit
b61359781958. IIRC the reason we never enabled either a warning
or an assertion was because for the PC machine's PCI devices
in particular we thought it might be possible for the guest to
map PCI devices at a silly address and generate overlaps, but
I may well have the details wrong as it was years back.)
-- PMM
^ permalink raw reply [flat|nested] 91+ messages in thread
* Re: [PATCH for-6.2 09/25] clock: Provide builtin multiplier/divider
2021-08-16 9:05 ` Peter Maydell
@ 2021-08-16 9:32 ` Philippe Mathieu-Daudé
2021-08-16 9:36 ` Peter Maydell
0 siblings, 1 reply; 91+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-08-16 9:32 UTC (permalink / raw)
To: Peter Maydell
Cc: Damien Hedde, Luc Michel, Alistair Francis, QEMU Developers,
Subbaraya Sundeep, qemu-arm, Joel Stanley, Alexandre Iooss
On 8/16/21 11:05 AM, Peter Maydell wrote:
> On Sun, 15 Aug 2021 at 17:32, Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
>>
>> On 8/12/21 11:33 AM, Peter Maydell wrote:
>>> It is quite common for a clock tree to involve possibly programmable
>>> clock multipliers or dividers, where the frequency of a clock is for
>>> instance divided by 8 to produce a slower clock to feed to a
>>> particular device.
>>>
>>> Currently we provide no convenient mechanism for modelling this. You
>>> can implement it by having an input Clock and an output Clock, and
>>> manually setting the period of the output clock in the period-changed
>>> callback of the input clock, but that's quite clunky.
>>>
>>> This patch adds support in the Clock objects themselves for setting a
>>> multiplier or divider. The effect of setting this on a clock is that
>>> when the clock's period is changed, all the children of the clock are
>>> set to period * multiplier / divider, rather than being set to the
>>> same period as the parent clock.
>>
>> This is super nice!
>>
>>> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
>>> ---
>>> docs/devel/clocks.rst | 23 +++++++++++++++++++++++
>>> include/hw/clock.h | 29 +++++++++++++++++++++++++++++
>>> hw/core/clock-vmstate.c | 24 +++++++++++++++++++++++-
>>> hw/core/clock.c | 29 +++++++++++++++++++++++++----
>>> 4 files changed, 100 insertions(+), 5 deletions(-)
>>
>>> +void clock_set_mul_div(Clock *clk, uint32_t multiplier, uint32_t divider)
>>> +{
>>> + assert(divider != 0);
>>
>> I only wonder if we shouldn't check clock_is_enabled() here.
>> Maybe not assert, but at least report a GUEST_ERROR?
>
> Setting the multiplier on a disabled clock doesn't seem like
> an error to me. I would expect a common way for the guest to
> program a clock-controller would be "first set the divider
> and any other parameters; finally, enable the clock".
Eh sorry I meant the other way around :/ It is usually either
illegal or undefined behavior on real hw to change a clock scale
while it is active. Personally I'd be interested to catch guests
doing so. I was thinking of:
if (clock_is_enabled(clk)) {
qemu_log_mask(LOG_GUEST_ERROR,
"Changing scale of ENABLED clock '%s'\n'",
CLOCK_PATH(clk));
}
^ permalink raw reply [flat|nested] 91+ messages in thread
* Re: [PATCH for-6.2 09/25] clock: Provide builtin multiplier/divider
2021-08-16 9:32 ` Philippe Mathieu-Daudé
@ 2021-08-16 9:36 ` Peter Maydell
2021-08-16 9:58 ` Philippe Mathieu-Daudé
0 siblings, 1 reply; 91+ messages in thread
From: Peter Maydell @ 2021-08-16 9:36 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: Damien Hedde, Luc Michel, Alistair Francis, QEMU Developers,
Subbaraya Sundeep, qemu-arm, Joel Stanley, Alexandre Iooss
On Mon, 16 Aug 2021 at 10:32, Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
>
> On 8/16/21 11:05 AM, Peter Maydell wrote:
> > On Sun, 15 Aug 2021 at 17:32, Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
> >> I only wonder if we shouldn't check clock_is_enabled() here.
> >> Maybe not assert, but at least report a GUEST_ERROR?
> >
> > Setting the multiplier on a disabled clock doesn't seem like
> > an error to me. I would expect a common way for the guest to
> > program a clock-controller would be "first set the divider
> > and any other parameters; finally, enable the clock".
>
> Eh sorry I meant the other way around :/ It is usually either
> illegal or undefined behavior on real hw to change a clock scale
> while it is active. Personally I'd be interested to catch guests
> doing so. I was thinking of:
>
> if (clock_is_enabled(clk)) {
> qemu_log_mask(LOG_GUEST_ERROR,
> "Changing scale of ENABLED clock '%s'\n'",
> CLOCK_PATH(clk));
> }
I think if particular clock-controller hardware has that
restriction we should be logging guest errors there. (Doing that
also has the advantage that we can make the error clearer by being
specific about what guest hardware register/device is being
mis-programmed.) I don't think we can be certain enough that it's
always wrong to change the divider on a running clock to put the error
in the common clock API code. (Among other things, I suspect a warning
here would be easy to trigger incorrectly when connecting up hard-wired
clock dividers at startup.)
thanks
-- PMM
^ permalink raw reply [flat|nested] 91+ messages in thread
* Re: [PATCH for-6.2 09/25] clock: Provide builtin multiplier/divider
2021-08-16 9:36 ` Peter Maydell
@ 2021-08-16 9:58 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 91+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-08-16 9:58 UTC (permalink / raw)
To: Peter Maydell
Cc: Damien Hedde, Luc Michel, Alistair Francis, QEMU Developers,
Subbaraya Sundeep, qemu-arm, Joel Stanley, Alexandre Iooss
On 8/16/21 11:36 AM, Peter Maydell wrote:
> On Mon, 16 Aug 2021 at 10:32, Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
>>
>> On 8/16/21 11:05 AM, Peter Maydell wrote:
>>> On Sun, 15 Aug 2021 at 17:32, Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
>>>> I only wonder if we shouldn't check clock_is_enabled() here.
>>>> Maybe not assert, but at least report a GUEST_ERROR?
>>>
>>> Setting the multiplier on a disabled clock doesn't seem like
>>> an error to me. I would expect a common way for the guest to
>>> program a clock-controller would be "first set the divider
>>> and any other parameters; finally, enable the clock".
>>
>> Eh sorry I meant the other way around :/ It is usually either
>> illegal or undefined behavior on real hw to change a clock scale
>> while it is active. Personally I'd be interested to catch guests
>> doing so. I was thinking of:
>>
>> if (clock_is_enabled(clk)) {
>> qemu_log_mask(LOG_GUEST_ERROR,
>> "Changing scale of ENABLED clock '%s'\n'",
>> CLOCK_PATH(clk));
>> }
>
> I think if particular clock-controller hardware has that
> restriction we should be logging guest errors there. (Doing that
> also has the advantage that we can make the error clearer by being
> specific about what guest hardware register/device is being
> mis-programmed.)
OK.
> I don't think we can be certain enough that it's
> always wrong to change the divider on a running clock to put the error
> in the common clock API code.
OK.
> (Among other things, I suspect a warning
> here would be easy to trigger incorrectly when connecting up hard-wired
> clock dividers at startup.)
Yes, probably.
Thanks for the clarifications.
Preferably with a trace-event:
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
^ permalink raw reply [flat|nested] 91+ messages in thread
* Re: [PATCH for-6.2 01/25] arm: Move M-profile RAS register block into its own device
2021-08-12 9:33 ` [PATCH for-6.2 01/25] arm: Move M-profile RAS register block into its own device Peter Maydell
` (2 preceding siblings ...)
2021-08-15 17:30 ` Philippe Mathieu-Daudé
@ 2021-08-17 8:25 ` Luc Michel
2021-08-17 10:10 ` Damien Hedde
3 siblings, 1 reply; 91+ messages in thread
From: Luc Michel @ 2021-08-17 8:25 UTC (permalink / raw)
To: Peter Maydell
Cc: Damien Hedde, Alistair Francis, qemu-devel, Subbaraya Sundeep,
qemu-arm, Joel Stanley, Alexandre Iooss
On 10:33 Thu 12 Aug , Peter Maydell wrote:
> Currently we implement the RAS register block within the NVIC device.
> It isn't really very tightly coupled with the NVIC proper, so instead
> move it out into a sysbus device of its own and have the top level
> ARMv7M container create it and map it into memory at the right
> address.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Luc Michel <luc@lmichel.fr>
> ---
> include/hw/arm/armv7m.h | 2 +
> include/hw/intc/armv7m_nvic.h | 1 -
> include/hw/misc/armv7m_ras.h | 37 ++++++++++++++
> hw/arm/armv7m.c | 12 +++++
> hw/intc/armv7m_nvic.c | 56 ---------------------
> hw/misc/armv7m_ras.c | 93 +++++++++++++++++++++++++++++++++++
> MAINTAINERS | 2 +
> hw/misc/meson.build | 2 +
> 8 files changed, 148 insertions(+), 57 deletions(-)
> create mode 100644 include/hw/misc/armv7m_ras.h
> create mode 100644 hw/misc/armv7m_ras.c
>
> diff --git a/include/hw/arm/armv7m.h b/include/hw/arm/armv7m.h
> index bc6733c5184..4cae0d7eeaa 100644
> --- a/include/hw/arm/armv7m.h
> +++ b/include/hw/arm/armv7m.h
> @@ -12,6 +12,7 @@
>
> #include "hw/sysbus.h"
> #include "hw/intc/armv7m_nvic.h"
> +#include "hw/misc/armv7m_ras.h"
> #include "target/arm/idau.h"
> #include "qom/object.h"
>
> @@ -58,6 +59,7 @@ struct ARMv7MState {
> NVICState nvic;
> BitBandState bitband[ARMV7M_NUM_BITBANDS];
> ARMCPU *cpu;
> + ARMv7MRAS ras;
>
> /* MemoryRegion we pass to the CPU, with our devices layered on
> * top of the ones the board provides in board_memory.
> diff --git a/include/hw/intc/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h
> index 39c71e15936..33b6d8810c7 100644
> --- a/include/hw/intc/armv7m_nvic.h
> +++ b/include/hw/intc/armv7m_nvic.h
> @@ -83,7 +83,6 @@ struct NVICState {
> MemoryRegion sysreg_ns_mem;
> MemoryRegion systickmem;
> MemoryRegion systick_ns_mem;
> - MemoryRegion ras_mem;
> MemoryRegion container;
> MemoryRegion defaultmem;
>
> diff --git a/include/hw/misc/armv7m_ras.h b/include/hw/misc/armv7m_ras.h
> new file mode 100644
> index 00000000000..f8773e65b14
> --- /dev/null
> +++ b/include/hw/misc/armv7m_ras.h
> @@ -0,0 +1,37 @@
> +/*
> + * Arm M-profile RAS block
> + *
> + * Copyright (c) 2021 Linaro Limited
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 or
> + * (at your option) any later version.
> + */
> +
> +/*
> + * This is a model of the RAS register block of an M-profile CPU
> + * (the registers starting at 0xE0005000 with ERRFRn).
> + *
> + * QEMU interface:
> + * + sysbus MMIO region 0: the register bank
> + *
> + * The QEMU implementation currently provides "minimal RAS" only.
> + */
> +
> +#ifndef HW_MISC_ARMV7M_RAS_H
> +#define HW_MISC_ARMV7M_RAS_H
> +
> +#include "hw/sysbus.h"
> +
> +#define TYPE_ARMV7M_RAS "armv7m-ras"
> +OBJECT_DECLARE_SIMPLE_TYPE(ARMv7MRAS, ARMV7M_RAS)
> +
> +struct ARMv7MRAS {
> + /*< private >*/
> + SysBusDevice parent_obj;
> +
> + /*< public >*/
> + MemoryRegion iomem;
> +};
> +
> +#endif
> diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c
> index 9ce5c30cd5c..8964730d153 100644
> --- a/hw/arm/armv7m.c
> +++ b/hw/arm/armv7m.c
> @@ -231,6 +231,18 @@ static void armv7m_realize(DeviceState *dev, Error **errp)
> memory_region_add_subregion(&s->container, 0xe0000000,
> sysbus_mmio_get_region(sbd, 0));
>
> + /* If the CPU has RAS support, create the RAS register block */
> + if (cpu_isar_feature(aa32_ras, s->cpu)) {
> + object_initialize_child(OBJECT(dev), "armv7m-ras",
> + &s->ras, TYPE_ARMV7M_RAS);
> + sbd = SYS_BUS_DEVICE(&s->ras);
> + if (!sysbus_realize(sbd, errp)) {
> + return;
> + }
> + memory_region_add_subregion_overlap(&s->container, 0xe0005000,
> + sysbus_mmio_get_region(sbd, 0), 1);
> + }
> +
> for (i = 0; i < ARRAY_SIZE(s->bitband); i++) {
> if (s->enable_bitband) {
> Object *obj = OBJECT(&s->bitband[i]);
> diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
> index 1e7ddcb94cb..a5975592dfa 100644
> --- a/hw/intc/armv7m_nvic.c
> +++ b/hw/intc/armv7m_nvic.c
> @@ -2549,56 +2549,6 @@ static const MemoryRegionOps nvic_systick_ops = {
> .endianness = DEVICE_NATIVE_ENDIAN,
> };
>
> -
> -static MemTxResult ras_read(void *opaque, hwaddr addr,
> - uint64_t *data, unsigned size,
> - MemTxAttrs attrs)
> -{
> - if (attrs.user) {
> - return MEMTX_ERROR;
> - }
> -
> - switch (addr) {
> - case 0xe10: /* ERRIIDR */
> - /* architect field = Arm; product/variant/revision 0 */
> - *data = 0x43b;
> - break;
> - case 0xfc8: /* ERRDEVID */
> - /* Minimal RAS: we implement 0 error record indexes */
> - *data = 0;
> - break;
> - default:
> - qemu_log_mask(LOG_UNIMP, "Read RAS register offset 0x%x\n",
> - (uint32_t)addr);
> - *data = 0;
> - break;
> - }
> - return MEMTX_OK;
> -}
> -
> -static MemTxResult ras_write(void *opaque, hwaddr addr,
> - uint64_t value, unsigned size,
> - MemTxAttrs attrs)
> -{
> - if (attrs.user) {
> - return MEMTX_ERROR;
> - }
> -
> - switch (addr) {
> - default:
> - qemu_log_mask(LOG_UNIMP, "Write to RAS register offset 0x%x\n",
> - (uint32_t)addr);
> - break;
> - }
> - return MEMTX_OK;
> -}
> -
> -static const MemoryRegionOps ras_ops = {
> - .read_with_attrs = ras_read,
> - .write_with_attrs = ras_write,
> - .endianness = DEVICE_NATIVE_ENDIAN,
> -};
> -
> /*
> * Unassigned portions of the PPB space are RAZ/WI for privileged
> * accesses, and fault for non-privileged accesses.
> @@ -2946,12 +2896,6 @@ static void armv7m_nvic_realize(DeviceState *dev, Error **errp)
> &s->systick_ns_mem, 1);
> }
>
> - if (cpu_isar_feature(aa32_ras, s->cpu)) {
> - memory_region_init_io(&s->ras_mem, OBJECT(s),
> - &ras_ops, s, "nvic_ras", 0x1000);
> - memory_region_add_subregion(&s->container, 0x5000, &s->ras_mem);
> - }
> -
> sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->container);
> }
>
> diff --git a/hw/misc/armv7m_ras.c b/hw/misc/armv7m_ras.c
> new file mode 100644
> index 00000000000..a2b4f4b8dc8
> --- /dev/null
> +++ b/hw/misc/armv7m_ras.c
> @@ -0,0 +1,93 @@
> +/*
> + * Arm M-profile RAS block
> + *
> + * Copyright (c) 2021 Linaro Limited
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 or
> + * (at your option) any later version.
> + */
> +
> +#include "qemu/osdep.h"
> +#include "hw/misc/armv7m_ras.h"
> +#include "qemu/log.h"
> +
> +static MemTxResult ras_read(void *opaque, hwaddr addr,
> + uint64_t *data, unsigned size,
> + MemTxAttrs attrs)
> +{
> + if (attrs.user) {
> + return MEMTX_ERROR;
> + }
> +
> + switch (addr) {
> + case 0xe10: /* ERRIIDR */
> + /* architect field = Arm; product/variant/revision 0 */
> + *data = 0x43b;
> + break;
> + case 0xfc8: /* ERRDEVID */
> + /* Minimal RAS: we implement 0 error record indexes */
> + *data = 0;
> + break;
> + default:
> + qemu_log_mask(LOG_UNIMP, "Read RAS register offset 0x%x\n",
> + (uint32_t)addr);
> + *data = 0;
> + break;
> + }
> + return MEMTX_OK;
> +}
> +
> +static MemTxResult ras_write(void *opaque, hwaddr addr,
> + uint64_t value, unsigned size,
> + MemTxAttrs attrs)
> +{
> + if (attrs.user) {
> + return MEMTX_ERROR;
> + }
> +
> + switch (addr) {
> + default:
> + qemu_log_mask(LOG_UNIMP, "Write to RAS register offset 0x%x\n",
> + (uint32_t)addr);
> + break;
> + }
> + return MEMTX_OK;
> +}
> +
> +static const MemoryRegionOps ras_ops = {
> + .read_with_attrs = ras_read,
> + .write_with_attrs = ras_write,
> + .endianness = DEVICE_NATIVE_ENDIAN,
> +};
> +
> +
> +static void armv7m_ras_init(Object *obj)
> +{
> + SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
> + ARMv7MRAS *s = ARMV7M_RAS(obj);
> +
> + memory_region_init_io(&s->iomem, obj, &ras_ops,
> + s, "armv7m-ras", 0x1000);
> + sysbus_init_mmio(sbd, &s->iomem);
> +}
> +
> +static void armv7m_ras_class_init(ObjectClass *klass, void *data)
> +{
> + /* This device has no state: no need for vmstate or reset */
> +}
> +
> +static const TypeInfo armv7m_ras_info = {
> + .name = TYPE_ARMV7M_RAS,
> + .parent = TYPE_SYS_BUS_DEVICE,
> + .instance_size = sizeof(ARMv7MRAS),
> + .instance_init = armv7m_ras_init,
> + .class_init = armv7m_ras_class_init,
> +};
> +
> +static void armv7m_ras_register_types(void)
> +{
> + type_register_static(&armv7m_ras_info);
> +}
> +
> +type_init(armv7m_ras_register_types);
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 37b1a8e4428..3cac393bb48 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -617,6 +617,7 @@ F: hw/intc/gic_internal.h
> F: hw/misc/a9scu.c
> F: hw/misc/arm11scu.c
> F: hw/misc/arm_l2x0.c
> +F: hw/misc/armv7m_ras.c
> F: hw/timer/a9gtimer*
> F: hw/timer/arm*
> F: include/hw/arm/arm*.h
> @@ -626,6 +627,7 @@ F: include/hw/misc/arm11scu.h
> F: include/hw/timer/a9gtimer.h
> F: include/hw/timer/arm_mptimer.h
> F: include/hw/timer/armv7m_systick.h
> +F: include/hw/misc/armv7m_ras.h
> F: tests/qtest/test-arm-mptimer.c
>
> Exynos
> diff --git a/hw/misc/meson.build b/hw/misc/meson.build
> index a53b849a5a0..3f41a3a5b27 100644
> --- a/hw/misc/meson.build
> +++ b/hw/misc/meson.build
> @@ -17,6 +17,8 @@ softmmu_ss.add(when: 'CONFIG_INTEGRATOR_DEBUG', if_true: files('arm_integrator_d
> softmmu_ss.add(when: 'CONFIG_A9SCU', if_true: files('a9scu.c'))
> softmmu_ss.add(when: 'CONFIG_ARM11SCU', if_true: files('arm11scu.c'))
>
> +softmmu_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('armv7m_ras.c'))
> +
> # Mac devices
> softmmu_ss.add(when: 'CONFIG_MOS6522', if_true: files('mos6522.c'))
>
> --
> 2.20.1
>
--
^ permalink raw reply [flat|nested] 91+ messages in thread
* Re: [PATCH for-6.2 02/25] arm: Move systick device creation from NVIC to ARMv7M object
2021-08-12 9:33 ` [PATCH for-6.2 02/25] arm: Move systick device creation from NVIC to ARMv7M object Peter Maydell
2021-08-13 1:23 ` Alistair Francis
@ 2021-08-17 9:24 ` Luc Michel
1 sibling, 0 replies; 91+ messages in thread
From: Luc Michel @ 2021-08-17 9:24 UTC (permalink / raw)
To: Peter Maydell
Cc: Damien Hedde, Alistair Francis, qemu-devel, Subbaraya Sundeep,
qemu-arm, Joel Stanley, Alexandre Iooss
On 10:33 Thu 12 Aug , Peter Maydell wrote:
> There's no particular reason why the NVIC should be owning the
> SysTick device objects; move them into the ARMv7M container object
> instead, as part of consolidating the "create the devices which are
> built into an M-profile CPU and map them into their architected
> locations in the address space" work into one place.
>
> This involves temporarily creating a duplicate copy of the
> nvic_sysreg_ns_ops struct and its read/write functions (renamed as
> v7m_sysreg_ns_*), but we will delete the NVIC's copy of this code in
> a subsequent patch.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Luc Michel <luc@lmichel.fr>
> ---
> include/hw/arm/armv7m.h | 12 ++++
> include/hw/intc/armv7m_nvic.h | 4 --
> hw/arm/armv7m.c | 125 ++++++++++++++++++++++++++++++++++
> hw/intc/armv7m_nvic.c | 73 --------------------
> 4 files changed, 137 insertions(+), 77 deletions(-)
>
> diff --git a/include/hw/arm/armv7m.h b/include/hw/arm/armv7m.h
> index 4cae0d7eeaa..360c35c5fb2 100644
> --- a/include/hw/arm/armv7m.h
> +++ b/include/hw/arm/armv7m.h
> @@ -60,11 +60,23 @@ struct ARMv7MState {
> BitBandState bitband[ARMV7M_NUM_BITBANDS];
> ARMCPU *cpu;
> ARMv7MRAS ras;
> + SysTickState systick[M_REG_NUM_BANKS];
>
> /* MemoryRegion we pass to the CPU, with our devices layered on
> * top of the ones the board provides in board_memory.
> */
> MemoryRegion container;
> + /*
> + * MemoryRegion which passes the transaction to either the S or the
> + * NS systick device depending on the transaction attributes
> + */
> + MemoryRegion systickmem;
> + /*
> + * MemoryRegion which enforces the S/NS handling of the systick
> + * device NS alias region and passes the transaction to the
> + * NS systick device if appropriate.
> + */
> + MemoryRegion systick_ns_mem;
>
> /* Properties */
> char *cpu_type;
> diff --git a/include/hw/intc/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h
> index 33b6d8810c7..6a6a99090c7 100644
> --- a/include/hw/intc/armv7m_nvic.h
> +++ b/include/hw/intc/armv7m_nvic.h
> @@ -81,16 +81,12 @@ struct NVICState {
>
> MemoryRegion sysregmem;
> MemoryRegion sysreg_ns_mem;
> - MemoryRegion systickmem;
> - MemoryRegion systick_ns_mem;
> MemoryRegion container;
> MemoryRegion defaultmem;
>
> uint32_t num_irq;
> qemu_irq excpout;
> qemu_irq sysresetreq;
> -
> - SysTickState systick[M_REG_NUM_BANKS];
> };
>
> #endif
> diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c
> index 8964730d153..364ac069702 100644
> --- a/hw/arm/armv7m.c
> +++ b/hw/arm/armv7m.c
> @@ -124,6 +124,85 @@ static const hwaddr bitband_output_addr[ARMV7M_NUM_BITBANDS] = {
> 0x22000000, 0x42000000
> };
>
> +static MemTxResult v7m_sysreg_ns_write(void *opaque, hwaddr addr,
> + uint64_t value, unsigned size,
> + MemTxAttrs attrs)
> +{
> + MemoryRegion *mr = opaque;
> +
> + if (attrs.secure) {
> + /* S accesses to the alias act like NS accesses to the real region */
> + attrs.secure = 0;
> + return memory_region_dispatch_write(mr, addr, value,
> + size_memop(size) | MO_TE, attrs);
> + } else {
> + /* NS attrs are RAZ/WI for privileged, and BusFault for user */
> + if (attrs.user) {
> + return MEMTX_ERROR;
> + }
> + return MEMTX_OK;
> + }
> +}
> +
> +static MemTxResult v7m_sysreg_ns_read(void *opaque, hwaddr addr,
> + uint64_t *data, unsigned size,
> + MemTxAttrs attrs)
> +{
> + MemoryRegion *mr = opaque;
> +
> + if (attrs.secure) {
> + /* S accesses to the alias act like NS accesses to the real region */
> + attrs.secure = 0;
> + return memory_region_dispatch_read(mr, addr, data,
> + size_memop(size) | MO_TE, attrs);
> + } else {
> + /* NS attrs are RAZ/WI for privileged, and BusFault for user */
> + if (attrs.user) {
> + return MEMTX_ERROR;
> + }
> + *data = 0;
> + return MEMTX_OK;
> + }
> +}
> +
> +static const MemoryRegionOps v7m_sysreg_ns_ops = {
> + .read_with_attrs = v7m_sysreg_ns_read,
> + .write_with_attrs = v7m_sysreg_ns_write,
> + .endianness = DEVICE_NATIVE_ENDIAN,
> +};
> +
> +static MemTxResult v7m_systick_write(void *opaque, hwaddr addr,
> + uint64_t value, unsigned size,
> + MemTxAttrs attrs)
> +{
> + ARMv7MState *s = opaque;
> + MemoryRegion *mr;
> +
> + /* Direct the access to the correct systick */
> + mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->systick[attrs.secure]), 0);
> + return memory_region_dispatch_write(mr, addr, value,
> + size_memop(size) | MO_TE, attrs);
> +}
> +
> +static MemTxResult v7m_systick_read(void *opaque, hwaddr addr,
> + uint64_t *data, unsigned size,
> + MemTxAttrs attrs)
> +{
> + ARMv7MState *s = opaque;
> + MemoryRegion *mr;
> +
> + /* Direct the access to the correct systick */
> + mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->systick[attrs.secure]), 0);
> + return memory_region_dispatch_read(mr, addr, data, size_memop(size) | MO_TE,
> + attrs);
> +}
> +
> +static const MemoryRegionOps v7m_systick_ops = {
> + .read_with_attrs = v7m_systick_read,
> + .write_with_attrs = v7m_systick_write,
> + .endianness = DEVICE_NATIVE_ENDIAN,
> +};
> +
> static void armv7m_instance_init(Object *obj)
> {
> ARMv7MState *s = ARMV7M(obj);
> @@ -137,6 +216,13 @@ static void armv7m_instance_init(Object *obj)
> object_property_add_alias(obj, "num-irq",
> OBJECT(&s->nvic), "num-irq");
>
> + object_initialize_child(obj, "systick-reg-ns", &s->systick[M_REG_NS],
> + TYPE_SYSTICK);
> + /*
> + * We can't initialize the secure systick here, as we don't know
> + * yet if we need it.
> + */
> +
> for (i = 0; i < ARRAY_SIZE(s->bitband); i++) {
> object_initialize_child(obj, "bitband[*]", &s->bitband[i],
> TYPE_BITBAND);
> @@ -231,6 +317,45 @@ static void armv7m_realize(DeviceState *dev, Error **errp)
> memory_region_add_subregion(&s->container, 0xe0000000,
> sysbus_mmio_get_region(sbd, 0));
>
> + /* Create and map the systick devices */
> + if (!sysbus_realize(SYS_BUS_DEVICE(&s->systick[M_REG_NS]), errp)) {
> + return;
> + }
> + sysbus_connect_irq(SYS_BUS_DEVICE(&s->systick[M_REG_NS]), 0,
> + qdev_get_gpio_in_named(DEVICE(&s->nvic),
> + "systick-trigger", M_REG_NS));
> +
> + if (arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY)) {
> + /*
> + * We couldn't init the secure systick device in instance_init
> + * as we didn't know then if the CPU had the security extensions;
> + * so we have to do it here.
> + */
> + object_initialize_child(OBJECT(dev), "systick-reg-s",
> + &s->systick[M_REG_S], TYPE_SYSTICK);
> +
> + if (!sysbus_realize(SYS_BUS_DEVICE(&s->systick[M_REG_S]), errp)) {
> + return;
> + }
> + sysbus_connect_irq(SYS_BUS_DEVICE(&s->systick[M_REG_S]), 0,
> + qdev_get_gpio_in_named(DEVICE(&s->nvic),
> + "systick-trigger", M_REG_S));
> + }
> +
> + memory_region_init_io(&s->systickmem, OBJECT(s),
> + &v7m_systick_ops, s,
> + "v7m_systick", 0xe0);
> +
> + memory_region_add_subregion_overlap(&s->container, 0xe000e010,
> + &s->systickmem, 1);
> + if (arm_feature(&s->cpu->env, ARM_FEATURE_V8)) {
> + memory_region_init_io(&s->systick_ns_mem, OBJECT(s),
> + &v7m_sysreg_ns_ops, &s->systickmem,
> + "v7m_systick_ns", 0xe0);
> + memory_region_add_subregion_overlap(&s->container, 0xe002e010,
> + &s->systick_ns_mem, 1);
> + }
> +
> /* If the CPU has RAS support, create the RAS register block */
> if (cpu_isar_feature(aa32_ras, s->cpu)) {
> object_initialize_child(OBJECT(dev), "armv7m-ras",
> diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
> index a5975592dfa..2b3e79a3da9 100644
> --- a/hw/intc/armv7m_nvic.c
> +++ b/hw/intc/armv7m_nvic.c
> @@ -2517,38 +2517,6 @@ static const MemoryRegionOps nvic_sysreg_ns_ops = {
> .endianness = DEVICE_NATIVE_ENDIAN,
> };
>
> -static MemTxResult nvic_systick_write(void *opaque, hwaddr addr,
> - uint64_t value, unsigned size,
> - MemTxAttrs attrs)
> -{
> - NVICState *s = opaque;
> - MemoryRegion *mr;
> -
> - /* Direct the access to the correct systick */
> - mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->systick[attrs.secure]), 0);
> - return memory_region_dispatch_write(mr, addr, value,
> - size_memop(size) | MO_TE, attrs);
> -}
> -
> -static MemTxResult nvic_systick_read(void *opaque, hwaddr addr,
> - uint64_t *data, unsigned size,
> - MemTxAttrs attrs)
> -{
> - NVICState *s = opaque;
> - MemoryRegion *mr;
> -
> - /* Direct the access to the correct systick */
> - mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->systick[attrs.secure]), 0);
> - return memory_region_dispatch_read(mr, addr, data, size_memop(size) | MO_TE,
> - attrs);
> -}
> -
> -static const MemoryRegionOps nvic_systick_ops = {
> - .read_with_attrs = nvic_systick_read,
> - .write_with_attrs = nvic_systick_write,
> - .endianness = DEVICE_NATIVE_ENDIAN,
> -};
> -
> /*
> * Unassigned portions of the PPB space are RAZ/WI for privileged
> * accesses, and fault for non-privileged accesses.
> @@ -2801,29 +2769,6 @@ static void armv7m_nvic_realize(DeviceState *dev, Error **errp)
>
> s->num_prio_bits = arm_feature(&s->cpu->env, ARM_FEATURE_V7) ? 8 : 2;
>
> - if (!sysbus_realize(SYS_BUS_DEVICE(&s->systick[M_REG_NS]), errp)) {
> - return;
> - }
> - sysbus_connect_irq(SYS_BUS_DEVICE(&s->systick[M_REG_NS]), 0,
> - qdev_get_gpio_in_named(dev, "systick-trigger",
> - M_REG_NS));
> -
> - if (arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY)) {
> - /* We couldn't init the secure systick device in instance_init
> - * as we didn't know then if the CPU had the security extensions;
> - * so we have to do it here.
> - */
> - object_initialize_child(OBJECT(dev), "systick-reg-s",
> - &s->systick[M_REG_S], TYPE_SYSTICK);
> -
> - if (!sysbus_realize(SYS_BUS_DEVICE(&s->systick[M_REG_S]), errp)) {
> - return;
> - }
> - sysbus_connect_irq(SYS_BUS_DEVICE(&s->systick[M_REG_S]), 0,
> - qdev_get_gpio_in_named(dev, "systick-trigger",
> - M_REG_S));
> - }
> -
> /*
> * This device provides a single sysbus memory region which
> * represents the whole of the "System PPB" space. This is the
> @@ -2877,23 +2822,11 @@ static void armv7m_nvic_realize(DeviceState *dev, Error **errp)
> "nvic_sysregs", 0x1000);
> memory_region_add_subregion(&s->container, 0xe000, &s->sysregmem);
>
> - memory_region_init_io(&s->systickmem, OBJECT(s),
> - &nvic_systick_ops, s,
> - "nvic_systick", 0xe0);
> -
> - memory_region_add_subregion_overlap(&s->container, 0xe010,
> - &s->systickmem, 1);
> -
> if (arm_feature(&s->cpu->env, ARM_FEATURE_V8)) {
> memory_region_init_io(&s->sysreg_ns_mem, OBJECT(s),
> &nvic_sysreg_ns_ops, &s->sysregmem,
> "nvic_sysregs_ns", 0x1000);
> memory_region_add_subregion(&s->container, 0x2e000, &s->sysreg_ns_mem);
> - memory_region_init_io(&s->systick_ns_mem, OBJECT(s),
> - &nvic_sysreg_ns_ops, &s->systickmem,
> - "nvic_systick_ns", 0xe0);
> - memory_region_add_subregion_overlap(&s->container, 0x2e010,
> - &s->systick_ns_mem, 1);
> }
>
> sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->container);
> @@ -2905,12 +2838,6 @@ static void armv7m_nvic_instance_init(Object *obj)
> NVICState *nvic = NVIC(obj);
> SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
>
> - object_initialize_child(obj, "systick-reg-ns", &nvic->systick[M_REG_NS],
> - TYPE_SYSTICK);
> - /* We can't initialize the secure systick here, as we don't know
> - * yet if we need it.
> - */
> -
> sysbus_init_irq(sbd, &nvic->excpout);
> qdev_init_gpio_out_named(dev, &nvic->sysresetreq, "SYSRESETREQ", 1);
> qdev_init_gpio_in_named(dev, nvic_systick_trigger, "systick-trigger",
> --
> 2.20.1
>
--
^ permalink raw reply [flat|nested] 91+ messages in thread
* Re: [PATCH for-6.2 03/25] arm: Move system PPB container handling to armv7m
2021-08-12 9:33 ` [PATCH for-6.2 03/25] arm: Move system PPB container handling to armv7m Peter Maydell
2021-08-12 11:56 ` Alexandre IOOSS
@ 2021-08-17 9:25 ` Luc Michel
1 sibling, 0 replies; 91+ messages in thread
From: Luc Michel @ 2021-08-17 9:25 UTC (permalink / raw)
To: Peter Maydell
Cc: Damien Hedde, Alistair Francis, qemu-devel, Subbaraya Sundeep,
qemu-arm, Joel Stanley, Alexandre Iooss
On 10:33 Thu 12 Aug , Peter Maydell wrote:
> @@ -309,13 +347,73 @@ static void armv7m_realize(DeviceState *dev, Error **errp)
> qdev_pass_gpios(DEVICE(&s->nvic), dev, "SYSRESETREQ");
> qdev_pass_gpios(DEVICE(&s->nvic), dev, "NMI");
>
> + /*
> + * We map various devices into the continer MR at their architected
s/continer/container
Reviewed-by: Luc Michel <luc@lmichel.fr>
^ permalink raw reply [flat|nested] 91+ messages in thread
* Re: [PATCH for-6.2 04/25] hw/timer/armv7m_systick: Add usual QEMU interface comment
2021-08-12 9:33 ` [PATCH for-6.2 04/25] hw/timer/armv7m_systick: Add usual QEMU interface comment Peter Maydell
2021-08-13 1:26 ` Alistair Francis
@ 2021-08-17 9:29 ` Luc Michel
1 sibling, 0 replies; 91+ messages in thread
From: Luc Michel @ 2021-08-17 9:29 UTC (permalink / raw)
To: Peter Maydell
Cc: Damien Hedde, Alistair Francis, qemu-devel, Subbaraya Sundeep,
qemu-arm, Joel Stanley, Alexandre Iooss
On 10:33 Thu 12 Aug , Peter Maydell wrote:
> Add the usual-style QEMU interface comment documenting what
> properties, etc, this device exposes.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Luc Michel <luc@lmichel.fr>
> ---
> include/hw/timer/armv7m_systick.h | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/include/hw/timer/armv7m_systick.h b/include/hw/timer/armv7m_systick.h
> index 84496faaf96..685fc5bc0d7 100644
> --- a/include/hw/timer/armv7m_systick.h
> +++ b/include/hw/timer/armv7m_systick.h
> @@ -20,6 +20,13 @@
>
> OBJECT_DECLARE_SIMPLE_TYPE(SysTickState, SYSTICK)
>
> +/*
> + * QEMU interface:
> + * + sysbus MMIO region 0 is the register interface (covering
> + * the registers which are mapped at address 0xE000E010)
> + * + sysbus IRQ 0 is the interrupt line to the NVIC
> + */
> +
> struct SysTickState {
> /*< private >*/
> SysBusDevice parent_obj;
> --
> 2.20.1
>
--
^ permalink raw reply [flat|nested] 91+ messages in thread
* Re: [PATCH for-6.2 05/25] hw/timer/armv7m_systick: Add input clocks
2021-08-12 9:33 ` [PATCH for-6.2 05/25] hw/timer/armv7m_systick: Add input clocks Peter Maydell
2021-08-13 1:27 ` Alistair Francis
@ 2021-08-17 9:32 ` Luc Michel
1 sibling, 0 replies; 91+ messages in thread
From: Luc Michel @ 2021-08-17 9:32 UTC (permalink / raw)
To: Peter Maydell
Cc: Damien Hedde, Alistair Francis, qemu-devel, Subbaraya Sundeep,
qemu-arm, Joel Stanley, Alexandre Iooss
On 10:33 Thu 12 Aug , Peter Maydell wrote:
> The v7M systick timer can be programmed to run from either of
> two clocks:
> * an "external reference clock" (when SYST_CSR.CLKSOURCE == 0)
> * the main CPU clock (when SYST_CSR.CLKSOURCE == 1)
>
> Our implementation currently hardwires the external reference clock
> to be 1MHz, and allows boards to set the main CPU clock frequency via
> the global 'system_clock_scale'. (Most boards set that to a constant
> value; the Stellaris boards allow the guest to reprogram it via the
> board-specific RCC registers).
>
> As the first step in converting this to use the Clock infrastructure,
> add input clocks to the systick device for the reference clock and
> the CPU clock. The device implementation ignores them; once we have
> made all the users of the device correctly wire up the new Clocks we
> will switch the implementation to use them and ignore the old
> system_clock_scale.
>
> This is a migration compat break for all M-profile boards, because of
> the addition of the new clock objects to the vmstate struct.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Luc Michel <luc@lmichel.fr>
> ---
> include/hw/timer/armv7m_systick.h | 7 +++++++
> hw/timer/armv7m_systick.c | 10 ++++++++--
> 2 files changed, 15 insertions(+), 2 deletions(-)
>
> diff --git a/include/hw/timer/armv7m_systick.h b/include/hw/timer/armv7m_systick.h
> index 685fc5bc0d7..38adf8d274e 100644
> --- a/include/hw/timer/armv7m_systick.h
> +++ b/include/hw/timer/armv7m_systick.h
> @@ -15,6 +15,7 @@
> #include "hw/sysbus.h"
> #include "qom/object.h"
> #include "hw/ptimer.h"
> +#include "hw/clock.h"
>
> #define TYPE_SYSTICK "armv7m_systick"
>
> @@ -25,6 +26,10 @@ OBJECT_DECLARE_SIMPLE_TYPE(SysTickState, SYSTICK)
> * + sysbus MMIO region 0 is the register interface (covering
> * the registers which are mapped at address 0xE000E010)
> * + sysbus IRQ 0 is the interrupt line to the NVIC
> + * + Clock input "refclk" is the external reference clock
> + * (used when SYST_CSR.CLKSOURCE == 0)
> + * + Clock input "cpuclk" is the main CPU clock
> + * (used when SYST_CSR.CLKSOURCE == 1)
> */
>
> struct SysTickState {
> @@ -38,6 +43,8 @@ struct SysTickState {
> ptimer_state *ptimer;
> MemoryRegion iomem;
> qemu_irq irq;
> + Clock *refclk;
> + Clock *cpuclk;
> };
>
> /*
> diff --git a/hw/timer/armv7m_systick.c b/hw/timer/armv7m_systick.c
> index 2f192011eb0..e43f74114e8 100644
> --- a/hw/timer/armv7m_systick.c
> +++ b/hw/timer/armv7m_systick.c
> @@ -14,6 +14,7 @@
> #include "migration/vmstate.h"
> #include "hw/irq.h"
> #include "hw/sysbus.h"
> +#include "hw/qdev-clock.h"
> #include "qemu/timer.h"
> #include "qemu/log.h"
> #include "qemu/module.h"
> @@ -201,6 +202,9 @@ static void systick_instance_init(Object *obj)
> memory_region_init_io(&s->iomem, obj, &systick_ops, s, "systick", 0xe0);
> sysbus_init_mmio(sbd, &s->iomem);
> sysbus_init_irq(sbd, &s->irq);
> +
> + s->refclk = qdev_init_clock_in(DEVICE(obj), "refclk", NULL, NULL, 0);
> + s->cpuclk = qdev_init_clock_in(DEVICE(obj), "cpuclk", NULL, NULL, 0);
> }
>
> static void systick_realize(DeviceState *dev, Error **errp)
> @@ -215,9 +219,11 @@ static void systick_realize(DeviceState *dev, Error **errp)
>
> static const VMStateDescription vmstate_systick = {
> .name = "armv7m_systick",
> - .version_id = 2,
> - .minimum_version_id = 2,
> + .version_id = 3,
> + .minimum_version_id = 3,
> .fields = (VMStateField[]) {
> + VMSTATE_CLOCK(refclk, SysTickState),
> + VMSTATE_CLOCK(cpuclk, SysTickState),
> VMSTATE_UINT32(control, SysTickState),
> VMSTATE_INT64(tick, SysTickState),
> VMSTATE_PTIMER(ptimer, SysTickState),
> --
> 2.20.1
>
--
^ permalink raw reply [flat|nested] 91+ messages in thread
* Re: [PATCH for-6.2 06/25] hw/arm/armv7m: Create input clocks
2021-08-12 9:33 ` [PATCH for-6.2 06/25] hw/arm/armv7m: Create " Peter Maydell
2021-08-13 1:28 ` Alistair Francis
@ 2021-08-17 9:34 ` Luc Michel
1 sibling, 0 replies; 91+ messages in thread
From: Luc Michel @ 2021-08-17 9:34 UTC (permalink / raw)
To: Peter Maydell
Cc: Damien Hedde, Alistair Francis, qemu-devel, Subbaraya Sundeep,
qemu-arm, Joel Stanley, Alexandre Iooss
On 10:33 Thu 12 Aug , Peter Maydell wrote:
> Create input clocks on the armv7m container object which pass through
> to the systick timers, so that users of the armv7m object can specify
> the clocks being used.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Luc Michel <luc@lmichel.fr>
> ---
> include/hw/arm/armv7m.h | 6 ++++++
> hw/arm/armv7m.c | 23 +++++++++++++++++++++++
> 2 files changed, 29 insertions(+)
>
> diff --git a/include/hw/arm/armv7m.h b/include/hw/arm/armv7m.h
> index fe8b248a6c6..b7ba0ff409c 100644
> --- a/include/hw/arm/armv7m.h
> +++ b/include/hw/arm/armv7m.h
> @@ -15,6 +15,7 @@
> #include "hw/misc/armv7m_ras.h"
> #include "target/arm/idau.h"
> #include "qom/object.h"
> +#include "hw/clock.h"
>
> #define TYPE_BITBAND "ARM-bitband-memory"
> OBJECT_DECLARE_SIMPLE_TYPE(BitBandState, BITBAND)
> @@ -51,6 +52,8 @@ OBJECT_DECLARE_SIMPLE_TYPE(ARMv7MState, ARMV7M)
> * + Property "vfp": enable VFP (forwarded to CPU object)
> * + Property "dsp": enable DSP (forwarded to CPU object)
> * + Property "enable-bitband": expose bitbanded IO
> + * + Clock input "refclk" is the external reference clock for the systick timers
> + * + Clock input "cpuclk" is the main CPU clock
> */
> struct ARMv7MState {
> /*< private >*/
> @@ -82,6 +85,9 @@ struct ARMv7MState {
> /* MR providing default PPB behaviour */
> MemoryRegion defaultmem;
>
> + Clock *refclk;
> + Clock *cpuclk;
> +
> /* Properties */
> char *cpu_type;
> /* MemoryRegion the board provides to us (with its devices, RAM, etc) */
> diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c
> index 7e7fb7a3ad3..db1bfa98df0 100644
> --- a/hw/arm/armv7m.c
> +++ b/hw/arm/armv7m.c
> @@ -14,12 +14,14 @@
> #include "hw/arm/boot.h"
> #include "hw/loader.h"
> #include "hw/qdev-properties.h"
> +#include "hw/qdev-clock.h"
> #include "elf.h"
> #include "sysemu/reset.h"
> #include "qemu/error-report.h"
> #include "qemu/module.h"
> #include "qemu/log.h"
> #include "target/arm/idau.h"
> +#include "migration/vmstate.h"
>
> /* Bitbanded IO. Each word corresponds to a single bit. */
>
> @@ -265,6 +267,9 @@ static void armv7m_instance_init(Object *obj)
> object_initialize_child(obj, "bitband[*]", &s->bitband[i],
> TYPE_BITBAND);
> }
> +
> + s->refclk = qdev_init_clock_in(DEVICE(obj), "refclk", NULL, NULL, 0);
> + s->cpuclk = qdev_init_clock_in(DEVICE(obj), "cpuclk", NULL, NULL, 0);
> }
>
> static void armv7m_realize(DeviceState *dev, Error **errp)
> @@ -416,6 +421,8 @@ static void armv7m_realize(DeviceState *dev, Error **errp)
> }
>
> /* Create and map the systick devices */
> + qdev_connect_clock_in(DEVICE(&s->systick[M_REG_NS]), "refclk", s->refclk);
> + qdev_connect_clock_in(DEVICE(&s->systick[M_REG_NS]), "cpuclk", s->cpuclk);
> if (!sysbus_realize(SYS_BUS_DEVICE(&s->systick[M_REG_NS]), errp)) {
> return;
> }
> @@ -431,6 +438,10 @@ static void armv7m_realize(DeviceState *dev, Error **errp)
> */
> object_initialize_child(OBJECT(dev), "systick-reg-s",
> &s->systick[M_REG_S], TYPE_SYSTICK);
> + qdev_connect_clock_in(DEVICE(&s->systick[M_REG_S]), "refclk",
> + s->refclk);
> + qdev_connect_clock_in(DEVICE(&s->systick[M_REG_S]), "cpuclk",
> + s->cpuclk);
>
> if (!sysbus_realize(SYS_BUS_DEVICE(&s->systick[M_REG_S]), errp)) {
> return;
> @@ -504,11 +515,23 @@ static Property armv7m_properties[] = {
> DEFINE_PROP_END_OF_LIST(),
> };
>
> +static const VMStateDescription vmstate_armv7m = {
> + .name = "armv7m",
> + .version_id = 1,
> + .minimum_version_id = 1,
> + .fields = (VMStateField[]) {
> + VMSTATE_CLOCK(refclk, SysTickState),
> + VMSTATE_CLOCK(cpuclk, SysTickState),
> + VMSTATE_END_OF_LIST()
> + }
> +};
> +
> static void armv7m_class_init(ObjectClass *klass, void *data)
> {
> DeviceClass *dc = DEVICE_CLASS(klass);
>
> dc->realize = armv7m_realize;
> + dc->vmsd = &vmstate_armv7m;
> device_class_set_props(dc, armv7m_properties);
> }
>
> --
> 2.20.1
>
--
^ permalink raw reply [flat|nested] 91+ messages in thread
* Re: [PATCH for-6.2 07/25] armsse: Wire up systick cpuclk clock
2021-08-12 9:33 ` [PATCH for-6.2 07/25] armsse: Wire up systick cpuclk clock Peter Maydell
2021-08-13 1:29 ` Alistair Francis
@ 2021-08-17 9:36 ` Luc Michel
1 sibling, 0 replies; 91+ messages in thread
From: Luc Michel @ 2021-08-17 9:36 UTC (permalink / raw)
To: Peter Maydell
Cc: Damien Hedde, Alistair Francis, qemu-devel, Subbaraya Sundeep,
qemu-arm, Joel Stanley, Alexandre Iooss
On 10:33 Thu 12 Aug , Peter Maydell wrote:
> Wire up the cpuclk for the systick devices to the SSE object's
> existing mainclk clock.
>
> We do not wire up the refclk because the SSE subsystems do not
> provide a refclk. (This is documented in the IoTKit and SSE-200
> TRMs; the SSE-300 TRM doesn't mention it but we assume it follows the
> same approach.) When we update the systick device later to honour "no
> refclk connected" this will fix a minor emulation inaccuracy for the
> SSE-based boards.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Luc Michel <luc@lmichel.fr>
> ---
> hw/arm/armsse.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c
> index a1456cb0f42..70b52c3d4b9 100644
> --- a/hw/arm/armsse.c
> +++ b/hw/arm/armsse.c
> @@ -995,6 +995,9 @@ static void armsse_realize(DeviceState *dev, Error **errp)
> int j;
> char *gpioname;
>
> + qdev_connect_clock_in(cpudev, "cpuclk", s->mainclk);
> + /* The SSE subsystems do not wire up a systick refclk */
> +
> qdev_prop_set_uint32(cpudev, "num-irq", s->exp_numirq + NUM_SSE_IRQS);
> /*
> * In real hardware the initial Secure VTOR is set from the INITSVTOR*
> --
> 2.20.1
>
--
^ permalink raw reply [flat|nested] 91+ messages in thread
* Re: [PATCH for-6.2 08/25] hw/arm/mps2.c: Connect up armv7m clocks
2021-08-12 9:33 ` [PATCH for-6.2 08/25] hw/arm/mps2.c: Connect up armv7m clocks Peter Maydell
@ 2021-08-17 9:39 ` Luc Michel
0 siblings, 0 replies; 91+ messages in thread
From: Luc Michel @ 2021-08-17 9:39 UTC (permalink / raw)
To: Peter Maydell
Cc: Damien Hedde, Alistair Francis, qemu-devel, Subbaraya Sundeep,
qemu-arm, Joel Stanley, Alexandre Iooss
On 10:33 Thu 12 Aug , Peter Maydell wrote:
> Connect up the armv7m clocks on the mps2-an385/386/500/511.
>
> Connect up the armv7m object's clocks on the MPS boards defined in
> mps2.c. The documentation for these FPGA images doesn't specify what
> systick reference clock is used (if any), so for the moment we
> provide a 1MHz refclock, which will result in no behavioural change
> from the current hardwired 1MHz clock implemented in
> armv7m_systick.c:systick_scale().
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Luc Michel <luc@lmichel.fr>
> ---
> hw/arm/mps2.c | 15 +++++++++++++++
> 1 file changed, 15 insertions(+)
>
> diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c
> index 81413b7133e..3671f49ad7b 100644
> --- a/hw/arm/mps2.c
> +++ b/hw/arm/mps2.c
> @@ -86,6 +86,7 @@ struct MPS2MachineState {
> CMSDKAPBWatchdog watchdog;
> CMSDKAPBTimer timer[2];
> Clock *sysclk;
> + Clock *refclk;
> };
>
> #define TYPE_MPS2_MACHINE "mps2"
> @@ -99,6 +100,15 @@ OBJECT_DECLARE_TYPE(MPS2MachineState, MPS2MachineClass, MPS2_MACHINE)
> /* Main SYSCLK frequency in Hz */
> #define SYSCLK_FRQ 25000000
>
> +/*
> + * The Application Notes don't say anything about how the
> + * systick reference clock is configured. (Quite possibly
> + * they don't have one at all.) This 1MHz clock matches the
> + * pre-existing behaviour that used to be hardcoded in the
> + * armv7m_systick implementation.
> + */
> +#define REFCLK_FRQ (1 * 1000 * 1000)
> +
> /* Initialize the auxiliary RAM region @mr and map it into
> * the memory map at @base.
> */
> @@ -146,6 +156,9 @@ static void mps2_common_init(MachineState *machine)
> mms->sysclk = clock_new(OBJECT(machine), "SYSCLK");
> clock_set_hz(mms->sysclk, SYSCLK_FRQ);
>
> + mms->refclk = clock_new(OBJECT(machine), "REFCLK");
> + clock_set_hz(mms->refclk, REFCLK_FRQ);
> +
> /* The FPGA images have an odd combination of different RAMs,
> * because in hardware they are different implementations and
> * connected to different buses, giving varying performance/size
> @@ -223,6 +236,8 @@ static void mps2_common_init(MachineState *machine)
> default:
> g_assert_not_reached();
> }
> + qdev_connect_clock_in(armv7m, "cpuclk", mms->sysclk);
> + qdev_connect_clock_in(armv7m, "refclk", mms->refclk);
> qdev_prop_set_string(armv7m, "cpu-type", machine->cpu_type);
> qdev_prop_set_bit(armv7m, "enable-bitband", true);
> object_property_set_link(OBJECT(&mms->armv7m), "memory",
> --
> 2.20.1
>
--
^ permalink raw reply [flat|nested] 91+ messages in thread
* Re: [PATCH for-6.2 10/25] hw/arm: Don't allocate separate MemoryRegions in stm32 SoC realize
2021-08-12 9:33 ` [PATCH for-6.2 10/25] hw/arm: Don't allocate separate MemoryRegions in stm32 SoC realize Peter Maydell
2021-08-12 12:13 ` Alexandre IOOSS
2021-08-13 1:34 ` Alistair Francis
@ 2021-08-17 9:41 ` Luc Michel
2 siblings, 0 replies; 91+ messages in thread
From: Luc Michel @ 2021-08-17 9:41 UTC (permalink / raw)
To: Peter Maydell
Cc: Damien Hedde, Alistair Francis, qemu-devel, Subbaraya Sundeep,
qemu-arm, Joel Stanley, Alexandre Iooss
On 10:33 Thu 12 Aug , Peter Maydell wrote:
> In the realize methods of the stm32f100 and stm32f205 SoC objects, we
> call g_new() to create new MemoryRegion objjects for the sram, flash,
> and flash_alias. This is unnecessary (and leaves open the
> possibility of leaking the allocations if we exit from realize with
> an error). Make these MemoryRegions member fields of the device
> state struct instead, as stm32f405 already does.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
(with the typo fixed)
Reviewed-by: Luc Michel <luc@lmichel.fr>
> ---
> include/hw/arm/stm32f100_soc.h | 4 ++++
> include/hw/arm/stm32f205_soc.h | 4 ++++
> hw/arm/stm32f100_soc.c | 17 +++++++----------
> hw/arm/stm32f205_soc.c | 17 +++++++----------
> 4 files changed, 22 insertions(+), 20 deletions(-)
>
> diff --git a/include/hw/arm/stm32f100_soc.h b/include/hw/arm/stm32f100_soc.h
> index 71bffcf4fd5..b7d71c6c634 100644
> --- a/include/hw/arm/stm32f100_soc.h
> +++ b/include/hw/arm/stm32f100_soc.h
> @@ -52,6 +52,10 @@ struct STM32F100State {
>
> STM32F2XXUsartState usart[STM_NUM_USARTS];
> STM32F2XXSPIState spi[STM_NUM_SPIS];
> +
> + MemoryRegion sram;
> + MemoryRegion flash;
> + MemoryRegion flash_alias;
> };
>
> #endif
> diff --git a/include/hw/arm/stm32f205_soc.h b/include/hw/arm/stm32f205_soc.h
> index 985ff63aa9e..75251494917 100644
> --- a/include/hw/arm/stm32f205_soc.h
> +++ b/include/hw/arm/stm32f205_soc.h
> @@ -63,6 +63,10 @@ struct STM32F205State {
> STM32F2XXSPIState spi[STM_NUM_SPIS];
>
> qemu_or_irq *adc_irqs;
> +
> + MemoryRegion sram;
> + MemoryRegion flash;
> + MemoryRegion flash_alias;
> };
>
> #endif
> diff --git a/hw/arm/stm32f100_soc.c b/hw/arm/stm32f100_soc.c
> index 0c4a5c66451..0be92b2c475 100644
> --- a/hw/arm/stm32f100_soc.c
> +++ b/hw/arm/stm32f100_soc.c
> @@ -67,25 +67,22 @@ static void stm32f100_soc_realize(DeviceState *dev_soc, Error **errp)
> int i;
>
> MemoryRegion *system_memory = get_system_memory();
> - MemoryRegion *sram = g_new(MemoryRegion, 1);
> - MemoryRegion *flash = g_new(MemoryRegion, 1);
> - MemoryRegion *flash_alias = g_new(MemoryRegion, 1);
>
> /*
> * Init flash region
> * Flash starts at 0x08000000 and then is aliased to boot memory at 0x0
> */
> - memory_region_init_rom(flash, OBJECT(dev_soc), "STM32F100.flash",
> + memory_region_init_rom(&s->flash, OBJECT(dev_soc), "STM32F100.flash",
> FLASH_SIZE, &error_fatal);
> - memory_region_init_alias(flash_alias, OBJECT(dev_soc),
> - "STM32F100.flash.alias", flash, 0, FLASH_SIZE);
> - memory_region_add_subregion(system_memory, FLASH_BASE_ADDRESS, flash);
> - memory_region_add_subregion(system_memory, 0, flash_alias);
> + memory_region_init_alias(&s->flash_alias, OBJECT(dev_soc),
> + "STM32F100.flash.alias", &s->flash, 0, FLASH_SIZE);
> + memory_region_add_subregion(system_memory, FLASH_BASE_ADDRESS, &s->flash);
> + memory_region_add_subregion(system_memory, 0, &s->flash_alias);
>
> /* Init SRAM region */
> - memory_region_init_ram(sram, NULL, "STM32F100.sram", SRAM_SIZE,
> + memory_region_init_ram(&s->sram, NULL, "STM32F100.sram", SRAM_SIZE,
> &error_fatal);
> - memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, sram);
> + memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, &s->sram);
>
> /* Init ARMv7m */
> armv7m = DEVICE(&s->armv7m);
> diff --git a/hw/arm/stm32f205_soc.c b/hw/arm/stm32f205_soc.c
> index 9cd41bf56da..0bd215aebd7 100644
> --- a/hw/arm/stm32f205_soc.c
> +++ b/hw/arm/stm32f205_soc.c
> @@ -84,21 +84,18 @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
> int i;
>
> MemoryRegion *system_memory = get_system_memory();
> - MemoryRegion *sram = g_new(MemoryRegion, 1);
> - MemoryRegion *flash = g_new(MemoryRegion, 1);
> - MemoryRegion *flash_alias = g_new(MemoryRegion, 1);
>
> - memory_region_init_rom(flash, OBJECT(dev_soc), "STM32F205.flash",
> + memory_region_init_rom(&s->flash, OBJECT(dev_soc), "STM32F205.flash",
> FLASH_SIZE, &error_fatal);
> - memory_region_init_alias(flash_alias, OBJECT(dev_soc),
> - "STM32F205.flash.alias", flash, 0, FLASH_SIZE);
> + memory_region_init_alias(&s->flash_alias, OBJECT(dev_soc),
> + "STM32F205.flash.alias", &s->flash, 0, FLASH_SIZE);
>
> - memory_region_add_subregion(system_memory, FLASH_BASE_ADDRESS, flash);
> - memory_region_add_subregion(system_memory, 0, flash_alias);
> + memory_region_add_subregion(system_memory, FLASH_BASE_ADDRESS, &s->flash);
> + memory_region_add_subregion(system_memory, 0, &s->flash_alias);
>
> - memory_region_init_ram(sram, NULL, "STM32F205.sram", SRAM_SIZE,
> + memory_region_init_ram(&s->sram, NULL, "STM32F205.sram", SRAM_SIZE,
> &error_fatal);
> - memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, sram);
> + memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, &s->sram);
>
> armv7m = DEVICE(&s->armv7m);
> qdev_prop_set_uint32(armv7m, "num-irq", 96);
> --
> 2.20.1
>
--
^ permalink raw reply [flat|nested] 91+ messages in thread
* Re: [PATCH for-6.2 11/25] hw/arm/stm32f100: Wire up sysclk and refclk
2021-08-12 9:33 ` [PATCH for-6.2 11/25] hw/arm/stm32f100: Wire up sysclk and refclk Peter Maydell
2021-08-13 1:36 ` Alistair Francis
2021-08-14 9:01 ` Alexandre IOOSS
@ 2021-08-17 9:45 ` Luc Michel
2 siblings, 0 replies; 91+ messages in thread
From: Luc Michel @ 2021-08-17 9:45 UTC (permalink / raw)
To: Peter Maydell
Cc: Damien Hedde, Alistair Francis, qemu-devel, Subbaraya Sundeep,
qemu-arm, Joel Stanley, Alexandre Iooss
On 10:33 Thu 12 Aug , Peter Maydell wrote:
> Wire up the sysclk and refclk for the stm32f100 SoC. This SoC always
> runs the systick refclk at 1/8 the frequency of the main CPU clock,
> so the board code only needs to provide a single sysclk clock.
>
> Because there is only one board using this SoC, we convert the SoC
> and the board together, rather than splitting it into "add clock to
> SoC; connect clock in board; add error check in SoC code that clock
> is wired up".
>
> When the systick device starts honouring its clock inputs, this will
> fix an emulation inaccuracy in the stm32vldiscovery board where the
> systick reference clock was running at 1MHz rather than 3MHz.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Luc Michel <luc@lmichel.fr>
> ---
> include/hw/arm/stm32f100_soc.h | 4 ++++
> hw/arm/stm32f100_soc.c | 30 ++++++++++++++++++++++++++++++
> hw/arm/stm32vldiscovery.c | 12 +++++++-----
> 3 files changed, 41 insertions(+), 5 deletions(-)
>
> diff --git a/include/hw/arm/stm32f100_soc.h b/include/hw/arm/stm32f100_soc.h
> index b7d71c6c634..40cd415b284 100644
> --- a/include/hw/arm/stm32f100_soc.h
> +++ b/include/hw/arm/stm32f100_soc.h
> @@ -29,6 +29,7 @@
> #include "hw/ssi/stm32f2xx_spi.h"
> #include "hw/arm/armv7m.h"
> #include "qom/object.h"
> +#include "hw/clock.h"
>
> #define TYPE_STM32F100_SOC "stm32f100-soc"
> OBJECT_DECLARE_SIMPLE_TYPE(STM32F100State, STM32F100_SOC)
> @@ -56,6 +57,9 @@ struct STM32F100State {
> MemoryRegion sram;
> MemoryRegion flash;
> MemoryRegion flash_alias;
> +
> + Clock *sysclk;
> + Clock *refclk;
> };
>
> #endif
> diff --git a/hw/arm/stm32f100_soc.c b/hw/arm/stm32f100_soc.c
> index 0be92b2c475..f7b344ba9fb 100644
> --- a/hw/arm/stm32f100_soc.c
> +++ b/hw/arm/stm32f100_soc.c
> @@ -30,6 +30,7 @@
> #include "exec/address-spaces.h"
> #include "hw/arm/stm32f100_soc.h"
> #include "hw/qdev-properties.h"
> +#include "hw/qdev-clock.h"
> #include "hw/misc/unimp.h"
> #include "sysemu/sysemu.h"
>
> @@ -57,6 +58,9 @@ static void stm32f100_soc_initfn(Object *obj)
> for (i = 0; i < STM_NUM_SPIS; i++) {
> object_initialize_child(obj, "spi[*]", &s->spi[i], TYPE_STM32F2XX_SPI);
> }
> +
> + s->sysclk = qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0);
> + s->refclk = qdev_init_clock_in(DEVICE(s), "refclk", NULL, NULL, 0);
> }
>
> static void stm32f100_soc_realize(DeviceState *dev_soc, Error **errp)
> @@ -68,6 +72,30 @@ static void stm32f100_soc_realize(DeviceState *dev_soc, Error **errp)
>
> MemoryRegion *system_memory = get_system_memory();
>
> + /*
> + * We use s->refclk internally and only define it with qdev_init_clock_in()
> + * so it is correctly parented and not leaked on an init/deinit; it is not
> + * intended as an externally exposed clock.
> + */
> + if (clock_has_source(s->refclk)) {
> + error_setg(errp, "refclk clock must not be wired up by the board code");
> + return;
> + }
> +
> + if (!clock_has_source(s->sysclk)) {
> + error_setg(errp, "sysclk clock must be wired up by the board code");
> + return;
> + }
> +
> + /*
> + * TODO: ideally we should model the SoC RCC and its ability to
> + * change the sysclk frequency and define different sysclk sources.
> + */
> +
> + /* The refclk always runs at frequency HCLK / 8 */
> + clock_set_mul_div(s->refclk, 8, 1);
> + clock_set_source(s->refclk, s->sysclk);
> +
> /*
> * Init flash region
> * Flash starts at 0x08000000 and then is aliased to boot memory at 0x0
> @@ -89,6 +117,8 @@ static void stm32f100_soc_realize(DeviceState *dev_soc, Error **errp)
> qdev_prop_set_uint32(armv7m, "num-irq", 61);
> qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type);
> qdev_prop_set_bit(armv7m, "enable-bitband", true);
> + qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk);
> + qdev_connect_clock_in(armv7m, "refclk", s->refclk);
> object_property_set_link(OBJECT(&s->armv7m), "memory",
> OBJECT(get_system_memory()), &error_abort);
> if (!sysbus_realize(SYS_BUS_DEVICE(&s->armv7m), errp)) {
> diff --git a/hw/arm/stm32vldiscovery.c b/hw/arm/stm32vldiscovery.c
> index 7e8191ebf5f..07e401a818d 100644
> --- a/hw/arm/stm32vldiscovery.c
> +++ b/hw/arm/stm32vldiscovery.c
> @@ -27,6 +27,7 @@
> #include "qapi/error.h"
> #include "hw/boards.h"
> #include "hw/qdev-properties.h"
> +#include "hw/qdev-clock.h"
> #include "qemu/error-report.h"
> #include "hw/arm/stm32f100_soc.h"
> #include "hw/arm/boot.h"
> @@ -39,16 +40,17 @@
> static void stm32vldiscovery_init(MachineState *machine)
> {
> DeviceState *dev;
> + Clock *sysclk;
>
> - /*
> - * TODO: ideally we would model the SoC RCC and let it handle
> - * system_clock_scale, including its ability to define different
> - * possible SYSCLK sources.
> - */
> system_clock_scale = NANOSECONDS_PER_SECOND / SYSCLK_FRQ;
>
> + /* This clock doesn't need migration because it is fixed-frequency */
> + sysclk = clock_new(OBJECT(machine), "SYSCLK");
> + clock_set_hz(sysclk, SYSCLK_FRQ);
> +
> dev = qdev_new(TYPE_STM32F100_SOC);
> qdev_prop_set_string(dev, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m3"));
> + qdev_connect_clock_in(dev, "sysclk", sysclk);
> sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
>
> armv7m_load_kernel(ARM_CPU(first_cpu),
> --
> 2.20.1
>
--
^ permalink raw reply [flat|nested] 91+ messages in thread
* Re: [PATCH for-6.2 12/25] hw/arm/stm32f205: Wire up sysclk and refclk
2021-08-12 9:33 ` [PATCH for-6.2 12/25] hw/arm/stm32f205: " Peter Maydell
2021-08-13 1:38 ` Alistair Francis
2021-08-14 9:02 ` Alexandre IOOSS
@ 2021-08-17 9:47 ` Luc Michel
2 siblings, 0 replies; 91+ messages in thread
From: Luc Michel @ 2021-08-17 9:47 UTC (permalink / raw)
To: Peter Maydell
Cc: Damien Hedde, Alistair Francis, qemu-devel, Subbaraya Sundeep,
qemu-arm, Joel Stanley, Alexandre Iooss
On 10:33 Thu 12 Aug , Peter Maydell wrote:
> Wire up the sysclk and refclk for the stm32f205 SoC. This SoC always
> runs the systick refclk at 1/8 the frequency of the main CPU clock,
> so the board code only needs to provide a single sysclk clock.
>
> Because there is only one board using this SoC, we convert the SoC
> and the board together, rather than splitting it into "add clock to
> SoC; connect clock in board; add error check in SoC code that clock
> is wired up".
>
> When the systick device starts honouring its clock inputs, this will
> fix an emulation inaccuracy in the netduino2 board where the systick
> reference clock was running at 1MHz rather than 15MHz.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Luc Michel <luc@lmichel.fr>
> ---
> include/hw/arm/stm32f205_soc.h | 4 ++++
> hw/arm/netduino2.c | 12 +++++++-----
> hw/arm/stm32f205_soc.c | 30 ++++++++++++++++++++++++++++++
> 3 files changed, 41 insertions(+), 5 deletions(-)
>
> diff --git a/include/hw/arm/stm32f205_soc.h b/include/hw/arm/stm32f205_soc.h
> index 75251494917..849d3ed8891 100644
> --- a/include/hw/arm/stm32f205_soc.h
> +++ b/include/hw/arm/stm32f205_soc.h
> @@ -32,6 +32,7 @@
> #include "hw/or-irq.h"
> #include "hw/ssi/stm32f2xx_spi.h"
> #include "hw/arm/armv7m.h"
> +#include "hw/clock.h"
> #include "qom/object.h"
>
> #define TYPE_STM32F205_SOC "stm32f205-soc"
> @@ -67,6 +68,9 @@ struct STM32F205State {
> MemoryRegion sram;
> MemoryRegion flash;
> MemoryRegion flash_alias;
> +
> + Clock *sysclk;
> + Clock *refclk;
> };
>
> #endif
> diff --git a/hw/arm/netduino2.c b/hw/arm/netduino2.c
> index 1733b71507c..b5c0ba23ee5 100644
> --- a/hw/arm/netduino2.c
> +++ b/hw/arm/netduino2.c
> @@ -26,6 +26,7 @@
> #include "qapi/error.h"
> #include "hw/boards.h"
> #include "hw/qdev-properties.h"
> +#include "hw/qdev-clock.h"
> #include "qemu/error-report.h"
> #include "hw/arm/stm32f205_soc.h"
> #include "hw/arm/boot.h"
> @@ -36,16 +37,17 @@
> static void netduino2_init(MachineState *machine)
> {
> DeviceState *dev;
> + Clock *sysclk;
>
> - /*
> - * TODO: ideally we would model the SoC RCC and let it handle
> - * system_clock_scale, including its ability to define different
> - * possible SYSCLK sources.
> - */
> system_clock_scale = NANOSECONDS_PER_SECOND / SYSCLK_FRQ;
>
> + /* This clock doesn't need migration because it is fixed-frequency */
> + sysclk = clock_new(OBJECT(machine), "SYSCLK");
> + clock_set_hz(sysclk, SYSCLK_FRQ);
> +
> dev = qdev_new(TYPE_STM32F205_SOC);
> qdev_prop_set_string(dev, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m3"));
> + qdev_connect_clock_in(dev, "sysclk", sysclk);
> sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
>
> armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename,
> diff --git a/hw/arm/stm32f205_soc.c b/hw/arm/stm32f205_soc.c
> index 0bd215aebd7..c6b75a381d9 100644
> --- a/hw/arm/stm32f205_soc.c
> +++ b/hw/arm/stm32f205_soc.c
> @@ -29,6 +29,7 @@
> #include "exec/address-spaces.h"
> #include "hw/arm/stm32f205_soc.h"
> #include "hw/qdev-properties.h"
> +#include "hw/qdev-clock.h"
> #include "sysemu/sysemu.h"
>
> /* At the moment only Timer 2 to 5 are modelled */
> @@ -74,6 +75,9 @@ static void stm32f205_soc_initfn(Object *obj)
> for (i = 0; i < STM_NUM_SPIS; i++) {
> object_initialize_child(obj, "spi[*]", &s->spi[i], TYPE_STM32F2XX_SPI);
> }
> +
> + s->sysclk = qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0);
> + s->refclk = qdev_init_clock_in(DEVICE(s), "refclk", NULL, NULL, 0);
> }
>
> static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
> @@ -85,6 +89,30 @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
>
> MemoryRegion *system_memory = get_system_memory();
>
> + /*
> + * We use s->refclk internally and only define it with qdev_init_clock_in()
> + * so it is correctly parented and not leaked on an init/deinit; it is not
> + * intended as an externally exposed clock.
> + */
> + if (clock_has_source(s->refclk)) {
> + error_setg(errp, "refclk clock must not be wired up by the board code");
> + return;
> + }
> +
> + if (!clock_has_source(s->sysclk)) {
> + error_setg(errp, "sysclk clock must be wired up by the board code");
> + return;
> + }
> +
> + /*
> + * TODO: ideally we should model the SoC RCC and its ability to
> + * change the sysclk frequency and define different sysclk sources.
> + */
> +
> + /* The refclk always runs at frequency HCLK / 8 */
> + clock_set_mul_div(s->refclk, 8, 1);
> + clock_set_source(s->refclk, s->sysclk);
> +
> memory_region_init_rom(&s->flash, OBJECT(dev_soc), "STM32F205.flash",
> FLASH_SIZE, &error_fatal);
> memory_region_init_alias(&s->flash_alias, OBJECT(dev_soc),
> @@ -101,6 +129,8 @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
> qdev_prop_set_uint32(armv7m, "num-irq", 96);
> qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type);
> qdev_prop_set_bit(armv7m, "enable-bitband", true);
> + qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk);
> + qdev_connect_clock_in(armv7m, "refclk", s->refclk);
> object_property_set_link(OBJECT(&s->armv7m), "memory",
> OBJECT(get_system_memory()), &error_abort);
> if (!sysbus_realize(SYS_BUS_DEVICE(&s->armv7m), errp)) {
> --
> 2.20.1
>
--
^ permalink raw reply [flat|nested] 91+ messages in thread
* Re: [PATCH for-6.2 13/25] hw/arm/stm32f405: Wire up sysclk and refclk
2021-08-12 9:33 ` [PATCH for-6.2 13/25] hw/arm/stm32f405: " Peter Maydell
2021-08-13 1:37 ` Alistair Francis
2021-08-14 9:03 ` Alexandre IOOSS
@ 2021-08-17 9:47 ` Luc Michel
2 siblings, 0 replies; 91+ messages in thread
From: Luc Michel @ 2021-08-17 9:47 UTC (permalink / raw)
To: Peter Maydell
Cc: Damien Hedde, Alistair Francis, qemu-devel, Subbaraya Sundeep,
qemu-arm, Joel Stanley, Alexandre Iooss
On 10:33 Thu 12 Aug , Peter Maydell wrote:
> Wire up the sysclk and refclk for the stm32f405 SoC. This SoC always
> runs the systick refclk at 1/8 the frequency of the main CPU clock,
> so the board code only needs to provide a single sysclk clock.
>
> Because there is only one board using this SoC, we convert the SoC
> and the board together, rather than splitting it into "add clock to
> SoC; connect clock in board; add error check in SoC code that clock
> is wired up".
>
> When the systick device starts honouring its clock inputs, this will
> fix an emulation inaccuracy in the netduinoplus2 board where the
> systick reference clock was running at 1MHz rather than 21MHz.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Luc Michel <luc@lmichel.fr>
> ---
> include/hw/arm/stm32f405_soc.h | 3 +++
> hw/arm/netduinoplus2.c | 12 +++++++-----
> hw/arm/stm32f405_soc.c | 30 ++++++++++++++++++++++++++++++
> 3 files changed, 40 insertions(+), 5 deletions(-)
>
> diff --git a/include/hw/arm/stm32f405_soc.h b/include/hw/arm/stm32f405_soc.h
> index 347105e709b..5bb0c8d5697 100644
> --- a/include/hw/arm/stm32f405_soc.h
> +++ b/include/hw/arm/stm32f405_soc.h
> @@ -68,6 +68,9 @@ struct STM32F405State {
> MemoryRegion sram;
> MemoryRegion flash;
> MemoryRegion flash_alias;
> +
> + Clock *sysclk;
> + Clock *refclk;
> };
>
> #endif
> diff --git a/hw/arm/netduinoplus2.c b/hw/arm/netduinoplus2.c
> index d3ad7a2b675..a5a8999cc8c 100644
> --- a/hw/arm/netduinoplus2.c
> +++ b/hw/arm/netduinoplus2.c
> @@ -26,6 +26,7 @@
> #include "qapi/error.h"
> #include "hw/boards.h"
> #include "hw/qdev-properties.h"
> +#include "hw/qdev-clock.h"
> #include "qemu/error-report.h"
> #include "hw/arm/stm32f405_soc.h"
> #include "hw/arm/boot.h"
> @@ -36,16 +37,17 @@
> static void netduinoplus2_init(MachineState *machine)
> {
> DeviceState *dev;
> + Clock *sysclk;
>
> - /*
> - * TODO: ideally we would model the SoC RCC and let it handle
> - * system_clock_scale, including its ability to define different
> - * possible SYSCLK sources.
> - */
> system_clock_scale = NANOSECONDS_PER_SECOND / SYSCLK_FRQ;
>
> + /* This clock doesn't need migration because it is fixed-frequency */
> + sysclk = clock_new(OBJECT(machine), "SYSCLK");
> + clock_set_hz(sysclk, SYSCLK_FRQ);
> +
> dev = qdev_new(TYPE_STM32F405_SOC);
> qdev_prop_set_string(dev, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m4"));
> + qdev_connect_clock_in(dev, "sysclk", sysclk);
> sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
>
> armv7m_load_kernel(ARM_CPU(first_cpu),
> diff --git a/hw/arm/stm32f405_soc.c b/hw/arm/stm32f405_soc.c
> index cb04c111987..0019b7f4785 100644
> --- a/hw/arm/stm32f405_soc.c
> +++ b/hw/arm/stm32f405_soc.c
> @@ -28,6 +28,7 @@
> #include "exec/address-spaces.h"
> #include "sysemu/sysemu.h"
> #include "hw/arm/stm32f405_soc.h"
> +#include "hw/qdev-clock.h"
> #include "hw/misc/unimp.h"
>
> #define SYSCFG_ADD 0x40013800
> @@ -80,6 +81,9 @@ static void stm32f405_soc_initfn(Object *obj)
> }
>
> object_initialize_child(obj, "exti", &s->exti, TYPE_STM32F4XX_EXTI);
> +
> + s->sysclk = qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0);
> + s->refclk = qdev_init_clock_in(DEVICE(s), "refclk", NULL, NULL, 0);
> }
>
> static void stm32f405_soc_realize(DeviceState *dev_soc, Error **errp)
> @@ -91,6 +95,30 @@ static void stm32f405_soc_realize(DeviceState *dev_soc, Error **errp)
> Error *err = NULL;
> int i;
>
> + /*
> + * We use s->refclk internally and only define it with qdev_init_clock_in()
> + * so it is correctly parented and not leaked on an init/deinit; it is not
> + * intended as an externally exposed clock.
> + */
> + if (clock_has_source(s->refclk)) {
> + error_setg(errp, "refclk clock must not be wired up by the board code");
> + return;
> + }
> +
> + if (!clock_has_source(s->sysclk)) {
> + error_setg(errp, "sysclk clock must be wired up by the board code");
> + return;
> + }
> +
> + /*
> + * TODO: ideally we should model the SoC RCC and its ability to
> + * change the sysclk frequency and define different sysclk sources.
> + */
> +
> + /* The refclk always runs at frequency HCLK / 8 */
> + clock_set_mul_div(s->refclk, 8, 1);
> + clock_set_source(s->refclk, s->sysclk);
> +
> memory_region_init_rom(&s->flash, OBJECT(dev_soc), "STM32F405.flash",
> FLASH_SIZE, &err);
> if (err != NULL) {
> @@ -116,6 +144,8 @@ static void stm32f405_soc_realize(DeviceState *dev_soc, Error **errp)
> qdev_prop_set_uint32(armv7m, "num-irq", 96);
> qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type);
> qdev_prop_set_bit(armv7m, "enable-bitband", true);
> + qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk);
> + qdev_connect_clock_in(armv7m, "refclk", s->refclk);
> object_property_set_link(OBJECT(&s->armv7m), "memory",
> OBJECT(system_memory), &error_abort);
> if (!sysbus_realize(SYS_BUS_DEVICE(&s->armv7m), errp)) {
> --
> 2.20.1
>
--
^ permalink raw reply [flat|nested] 91+ messages in thread
* Re: [PATCH for-6.2 14/25] hw/arm/stm32vldiscovery: Delete trailing blank line
2021-08-12 9:33 ` [PATCH for-6.2 14/25] hw/arm/stm32vldiscovery: Delete trailing blank line Peter Maydell
2021-08-12 12:27 ` Alexandre IOOSS
2021-08-13 1:39 ` Alistair Francis
@ 2021-08-17 9:48 ` Luc Michel
2 siblings, 0 replies; 91+ messages in thread
From: Luc Michel @ 2021-08-17 9:48 UTC (permalink / raw)
To: Peter Maydell
Cc: Damien Hedde, Alistair Francis, qemu-devel, Subbaraya Sundeep,
qemu-arm, Joel Stanley, Alexandre Iooss
On 10:33 Thu 12 Aug , Peter Maydell wrote:
> Delete the trailing blank line at the end of the source file.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Luc Michel <luc@lmichel.fr>
> ---
> hw/arm/stm32vldiscovery.c | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git a/hw/arm/stm32vldiscovery.c b/hw/arm/stm32vldiscovery.c
> index 07e401a818d..9b79004703b 100644
> --- a/hw/arm/stm32vldiscovery.c
> +++ b/hw/arm/stm32vldiscovery.c
> @@ -65,4 +65,3 @@ static void stm32vldiscovery_machine_init(MachineClass *mc)
> }
>
> DEFINE_MACHINE("stm32vldiscovery", stm32vldiscovery_machine_init)
> -
> --
> 2.20.1
>
--
^ permalink raw reply [flat|nested] 91+ messages in thread
* Re: [PATCH for-6.2 09/25] clock: Provide builtin multiplier/divider
2021-08-12 9:33 ` [PATCH for-6.2 09/25] clock: Provide builtin multiplier/divider Peter Maydell
` (3 preceding siblings ...)
2021-08-15 21:27 ` Luc Michel
@ 2021-08-17 9:59 ` Damien Hedde
2021-08-17 10:46 ` Peter Maydell
4 siblings, 1 reply; 91+ messages in thread
From: Damien Hedde @ 2021-08-17 9:59 UTC (permalink / raw)
To: Peter Maydell, qemu-arm, qemu-devel
Cc: Alexandre Iooss, Alistair Francis, Luc Michel, Joel Stanley,
Subbaraya Sundeep
On 8/12/21 11:33 AM, Peter Maydell wrote:
> It is quite common for a clock tree to involve possibly programmable
> clock multipliers or dividers, where the frequency of a clock is for
> instance divided by 8 to produce a slower clock to feed to a
> particular device.
>
> Currently we provide no convenient mechanism for modelling this. You
> can implement it by having an input Clock and an output Clock, and
> manually setting the period of the output clock in the period-changed
> callback of the input clock, but that's quite clunky.
>
> This patch adds support in the Clock objects themselves for setting a
> multiplier or divider. The effect of setting this on a clock is that
> when the clock's period is changed, all the children of the clock are
> set to period * multiplier / divider, rather than being set to the
> same period as the parent clock.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
> docs/devel/clocks.rst | 23 +++++++++++++++++++++++
> include/hw/clock.h | 29 +++++++++++++++++++++++++++++
> hw/core/clock-vmstate.c | 24 +++++++++++++++++++++++-
> hw/core/clock.c | 29 +++++++++++++++++++++++++----
> 4 files changed, 100 insertions(+), 5 deletions(-)
>
> diff --git a/docs/devel/clocks.rst b/docs/devel/clocks.rst
> index 956bd147ea0..430fbd842e5 100644
> --- a/docs/devel/clocks.rst
> +++ b/docs/devel/clocks.rst
> @@ -260,6 +260,29 @@ clocks get the new clock period value: *Clock 2*, *Clock 3* and *Clock 4*.
> It is not possible to disconnect a clock or to change the clock connection
> after it is connected.
>
> +Clock multiplier and divider settings
> +-------------------------------------
> +
> +By default, when clocks are connected together, the child
> +clocks run with the same period as their source (parent) clock.
> +The Clock API supports a built-in period multiplier/divider
> +mechanism so you can configure a clock to make its children
> +run at a different period from its own. If you call the
> +``clock_set_mul_div()`` function you can specify the clock's
> +multiplier and divider values. The children of that clock
> +will all run with a period of ``parent_period * multiplier / divider``.
> +For instance, if the clock has a frequency of 8MHz and you set its
> +multiplier to 2 and its divider to 3, the child clocks will run
> +at 12MHz.
> +
> +You can change the multiplier and divider of a clock at runtime,
> +so you can use this to model clock controller devices which
> +have guest-programmable frequency multipliers or dividers.
> +
> +Note that ``clock_set_mul_div()`` does not automatically call
> +``clock_propagate()``. If you make a runtime change to the
> +multiplier or divider you must call clock_propagate() yourself.a
> +
> Unconnected input clocks
> ------------------------
>
> diff --git a/include/hw/clock.h b/include/hw/clock.h
> index a7187eab95e..11f67fb9701 100644
> --- a/include/hw/clock.h
> +++ b/include/hw/clock.h
> @@ -81,6 +81,10 @@ struct Clock {
> void *callback_opaque;
> unsigned int callback_events;
>
> + /* Ratio of the parent clock to run the child clocks at */
> + uint32_t multiplier;
> + uint32_t divider;
> +
> /* Clocks are organized in a clock tree */
> Clock *source;
> QLIST_HEAD(, Clock) children;
> @@ -350,4 +354,29 @@ static inline bool clock_is_enabled(const Clock *clk)
> */
> char *clock_display_freq(Clock *clk);
>
> +/**
> + * clock_set_mul_div: set multiplier/divider for child clocks
> + * @clk: clock
> + * @multiplier: multiplier value
> + * @divider: divider value
> + *
> + * By default, a Clock's children will all run with the same period
> + * as their parent. This function allows you to adjust the multiplier
> + * and divider used to derive the child clock frequency.
> + * For example, setting a multiplier of 2 and a divider of 3
> + * will run child clocks with a period 2/3 of the parent clock,
> + * so if the parent clock is an 8MHz clock the children will
> + * be 12MHz.
> + *
> + * Setting the multiplier to 0 will stop the child clocks.
> + * Setting the divider to 0 is a programming error (diagnosed with
> + * an assertion failure).
> + * Setting a multiplier value that results in the child period
> + * overflowing is not diagnosed.
> + *
> + * Note that this function does not call clock_propagate(); the
> + * caller should do that if necessary.
> + */
> +void clock_set_mul_div(Clock *clk, uint32_t multiplier, uint32_t divider);
> +
> #endif /* QEMU_HW_CLOCK_H */
> diff --git a/hw/core/clock-vmstate.c b/hw/core/clock-vmstate.c
> index 260b13fc2c8..07bb45d7ed4 100644
> --- a/hw/core/clock-vmstate.c
> +++ b/hw/core/clock-vmstate.c
> @@ -14,6 +14,24 @@
> #include "migration/vmstate.h"
> #include "hw/clock.h"
>
> +static bool muldiv_needed(void *opaque)
> +{
> + Clock *clk = opaque;
> +
> + return clk->multiplier != 1 || clk->divider != 1;
> +}
> +
> +const VMStateDescription vmstate_muldiv = {
> + .name = "clock/muldiv",
> + .version_id = 1,
> + .minimum_version_id = 1,
> + .needed = muldiv_needed,
> + .fields = (VMStateField[]) {
> + VMSTATE_UINT32(multiplier, Clock),
> + VMSTATE_UINT32(divider, Clock),
> + },
> +};
> +
> const VMStateDescription vmstate_clock = {
> .name = "clock",
> .version_id = 0,
> @@ -21,5 +39,9 @@ const VMStateDescription vmstate_clock = {
> .fields = (VMStateField[]) {
> VMSTATE_UINT64(period, Clock),
> VMSTATE_END_OF_LIST()
> - }
> + },
> + .subsections = (const VMStateDescription*[]) {
> + &vmstate_muldiv,
> + NULL
> + },
> };
> diff --git a/hw/core/clock.c b/hw/core/clock.c
> index fc5a99683f8..c371b9e977a 100644
> --- a/hw/core/clock.c
> +++ b/hw/core/clock.c
> @@ -64,6 +64,15 @@ bool clock_set(Clock *clk, uint64_t period)
> return true;
> }
>
> +static uint64_t clock_get_child_period(Clock *clk)
> +{
> + /*
> + * Return the period to be used for child clocks, which is the parent
> + * clock period adjusted for for multiplier and divider effects.
> + */
> + return muldiv64(clk->period, clk->multiplier, clk->divider);
> +}
> +
> static void clock_call_callback(Clock *clk, ClockEvent event)
> {
> /*
> @@ -78,15 +87,16 @@ static void clock_call_callback(Clock *clk, ClockEvent event)
> static void clock_propagate_period(Clock *clk, bool call_callbacks)
> {
> Clock *child;
> + uint64_t child_period = clock_get_child_period(clk);
>
> QLIST_FOREACH(child, &clk->children, sibling) {
> - if (child->period != clk->period) {
> + if (child->period != child_period) {
> if (call_callbacks) {
> clock_call_callback(child, ClockPreUpdate);
> }
> - child->period = clk->period;
> + child->period = child_period;
> trace_clock_update(CLOCK_PATH(child), CLOCK_PATH(clk),
> - CLOCK_PERIOD_TO_HZ(clk->period),
> + CLOCK_PERIOD_TO_HZ(child->period),
> call_callbacks);
> if (call_callbacks) {
> clock_call_callback(child, ClockUpdate);
> @@ -110,7 +120,7 @@ void clock_set_source(Clock *clk, Clock *src)
>
> trace_clock_set_source(CLOCK_PATH(clk), CLOCK_PATH(src));
>
> - clk->period = src->period;
> + clk->period = clock_get_child_period(src);
> QLIST_INSERT_HEAD(&src->children, clk, sibling);
> clk->source = src;
> clock_propagate_period(clk, false);
> @@ -133,10 +143,21 @@ char *clock_display_freq(Clock *clk)
> return freq_to_str(clock_get_hz(clk));
> }
>
> +void clock_set_mul_div(Clock *clk, uint32_t multiplier, uint32_t divider)
> +{
> + assert(divider != 0);
> +
> + clk->multiplier = multiplier;
> + clk->divider = divider;
> +}
> +
> static void clock_initfn(Object *obj)
> {
> Clock *clk = CLOCK(obj);
>
> + clk->multiplier = 1;
> + clk->divider = 1;
> +
> QLIST_INIT(&clk->children);
> }
>
>
Regarding migration, you made the vmstate_muldiv subsection optional. I
suppose it is to keep backward migration working in case of simple
mul=1,div=1 clocks.
Do we need to ensure multiplier and divider fields are set to 1 upon
receiving a state if the vmstate_muldiv subsection is absent ? I
remember there are post_load() tricks to achieve that.
Thanks,
Damien
^ permalink raw reply [flat|nested] 91+ messages in thread
* Re: [PATCH for-6.2 01/25] arm: Move M-profile RAS register block into its own device
2021-08-17 8:25 ` Luc Michel
@ 2021-08-17 10:10 ` Damien Hedde
0 siblings, 0 replies; 91+ messages in thread
From: Damien Hedde @ 2021-08-17 10:10 UTC (permalink / raw)
To: Luc Michel, Peter Maydell
Cc: Alistair Francis, qemu-devel, Subbaraya Sundeep, qemu-arm,
Joel Stanley, Alexandre Iooss
On 8/17/21 10:25 AM, Luc Michel wrote:
> On 10:33 Thu 12 Aug , Peter Maydell wrote:
>> Currently we implement the RAS register block within the NVIC device.
>> It isn't really very tightly coupled with the NVIC proper, so instead
>> move it out into a sysbus device of its own and have the top level
>> ARMv7M container create it and map it into memory at the right
>> address.
>>
>> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
>
> Reviewed-by: Luc Michel <luc@lmichel.fr>
Reviewed-by: Damien Hedde <damien.hedde@greensocs.com>
>
>> ---
>> include/hw/arm/armv7m.h | 2 +
>> include/hw/intc/armv7m_nvic.h | 1 -
>> include/hw/misc/armv7m_ras.h | 37 ++++++++++++++
>> hw/arm/armv7m.c | 12 +++++
>> hw/intc/armv7m_nvic.c | 56 ---------------------
>> hw/misc/armv7m_ras.c | 93 +++++++++++++++++++++++++++++++++++
>> MAINTAINERS | 2 +
>> hw/misc/meson.build | 2 +
>> 8 files changed, 148 insertions(+), 57 deletions(-)
>> create mode 100644 include/hw/misc/armv7m_ras.h
>> create mode 100644 hw/misc/armv7m_ras.c
>>
>> diff --git a/include/hw/arm/armv7m.h b/include/hw/arm/armv7m.h
>> index bc6733c5184..4cae0d7eeaa 100644
>> --- a/include/hw/arm/armv7m.h
>> +++ b/include/hw/arm/armv7m.h
>> @@ -12,6 +12,7 @@
>>
>> #include "hw/sysbus.h"
>> #include "hw/intc/armv7m_nvic.h"
>> +#include "hw/misc/armv7m_ras.h"
>> #include "target/arm/idau.h"
>> #include "qom/object.h"
>>
>> @@ -58,6 +59,7 @@ struct ARMv7MState {
>> NVICState nvic;
>> BitBandState bitband[ARMV7M_NUM_BITBANDS];
>> ARMCPU *cpu;
>> + ARMv7MRAS ras;
>>
>> /* MemoryRegion we pass to the CPU, with our devices layered on
>> * top of the ones the board provides in board_memory.
>> diff --git a/include/hw/intc/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h
>> index 39c71e15936..33b6d8810c7 100644
>> --- a/include/hw/intc/armv7m_nvic.h
>> +++ b/include/hw/intc/armv7m_nvic.h
>> @@ -83,7 +83,6 @@ struct NVICState {
>> MemoryRegion sysreg_ns_mem;
>> MemoryRegion systickmem;
>> MemoryRegion systick_ns_mem;
>> - MemoryRegion ras_mem;
>> MemoryRegion container;
>> MemoryRegion defaultmem;
>>
>> diff --git a/include/hw/misc/armv7m_ras.h b/include/hw/misc/armv7m_ras.h
>> new file mode 100644
>> index 00000000000..f8773e65b14
>> --- /dev/null
>> +++ b/include/hw/misc/armv7m_ras.h
>> @@ -0,0 +1,37 @@
>> +/*
>> + * Arm M-profile RAS block
>> + *
>> + * Copyright (c) 2021 Linaro Limited
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 or
>> + * (at your option) any later version.
>> + */
>> +
>> +/*
>> + * This is a model of the RAS register block of an M-profile CPU
>> + * (the registers starting at 0xE0005000 with ERRFRn).
>> + *
>> + * QEMU interface:
>> + * + sysbus MMIO region 0: the register bank
>> + *
>> + * The QEMU implementation currently provides "minimal RAS" only.
>> + */
>> +
>> +#ifndef HW_MISC_ARMV7M_RAS_H
>> +#define HW_MISC_ARMV7M_RAS_H
>> +
>> +#include "hw/sysbus.h"
>> +
>> +#define TYPE_ARMV7M_RAS "armv7m-ras"
>> +OBJECT_DECLARE_SIMPLE_TYPE(ARMv7MRAS, ARMV7M_RAS)
>> +
>> +struct ARMv7MRAS {
>> + /*< private >*/
>> + SysBusDevice parent_obj;
>> +
>> + /*< public >*/
>> + MemoryRegion iomem;
>> +};
>> +
>> +#endif
>> diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c
>> index 9ce5c30cd5c..8964730d153 100644
>> --- a/hw/arm/armv7m.c
>> +++ b/hw/arm/armv7m.c
>> @@ -231,6 +231,18 @@ static void armv7m_realize(DeviceState *dev, Error **errp)
>> memory_region_add_subregion(&s->container, 0xe0000000,
>> sysbus_mmio_get_region(sbd, 0));
>>
>> + /* If the CPU has RAS support, create the RAS register block */
>> + if (cpu_isar_feature(aa32_ras, s->cpu)) {
>> + object_initialize_child(OBJECT(dev), "armv7m-ras",
>> + &s->ras, TYPE_ARMV7M_RAS);
>> + sbd = SYS_BUS_DEVICE(&s->ras);
>> + if (!sysbus_realize(sbd, errp)) {
>> + return;
>> + }
>> + memory_region_add_subregion_overlap(&s->container, 0xe0005000,
>> + sysbus_mmio_get_region(sbd, 0), 1);
>> + }
>> +
>> for (i = 0; i < ARRAY_SIZE(s->bitband); i++) {
>> if (s->enable_bitband) {
>> Object *obj = OBJECT(&s->bitband[i]);
>> diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
>> index 1e7ddcb94cb..a5975592dfa 100644
>> --- a/hw/intc/armv7m_nvic.c
>> +++ b/hw/intc/armv7m_nvic.c
>> @@ -2549,56 +2549,6 @@ static const MemoryRegionOps nvic_systick_ops = {
>> .endianness = DEVICE_NATIVE_ENDIAN,
>> };
>>
>> -
>> -static MemTxResult ras_read(void *opaque, hwaddr addr,
>> - uint64_t *data, unsigned size,
>> - MemTxAttrs attrs)
>> -{
>> - if (attrs.user) {
>> - return MEMTX_ERROR;
>> - }
>> -
>> - switch (addr) {
>> - case 0xe10: /* ERRIIDR */
>> - /* architect field = Arm; product/variant/revision 0 */
>> - *data = 0x43b;
>> - break;
>> - case 0xfc8: /* ERRDEVID */
>> - /* Minimal RAS: we implement 0 error record indexes */
>> - *data = 0;
>> - break;
>> - default:
>> - qemu_log_mask(LOG_UNIMP, "Read RAS register offset 0x%x\n",
>> - (uint32_t)addr);
>> - *data = 0;
>> - break;
>> - }
>> - return MEMTX_OK;
>> -}
>> -
>> -static MemTxResult ras_write(void *opaque, hwaddr addr,
>> - uint64_t value, unsigned size,
>> - MemTxAttrs attrs)
>> -{
>> - if (attrs.user) {
>> - return MEMTX_ERROR;
>> - }
>> -
>> - switch (addr) {
>> - default:
>> - qemu_log_mask(LOG_UNIMP, "Write to RAS register offset 0x%x\n",
>> - (uint32_t)addr);
>> - break;
>> - }
>> - return MEMTX_OK;
>> -}
>> -
>> -static const MemoryRegionOps ras_ops = {
>> - .read_with_attrs = ras_read,
>> - .write_with_attrs = ras_write,
>> - .endianness = DEVICE_NATIVE_ENDIAN,
>> -};
>> -
>> /*
>> * Unassigned portions of the PPB space are RAZ/WI for privileged
>> * accesses, and fault for non-privileged accesses.
>> @@ -2946,12 +2896,6 @@ static void armv7m_nvic_realize(DeviceState *dev, Error **errp)
>> &s->systick_ns_mem, 1);
>> }
>>
>> - if (cpu_isar_feature(aa32_ras, s->cpu)) {
>> - memory_region_init_io(&s->ras_mem, OBJECT(s),
>> - &ras_ops, s, "nvic_ras", 0x1000);
>> - memory_region_add_subregion(&s->container, 0x5000, &s->ras_mem);
>> - }
>> -
>> sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->container);
>> }
>>
>> diff --git a/hw/misc/armv7m_ras.c b/hw/misc/armv7m_ras.c
>> new file mode 100644
>> index 00000000000..a2b4f4b8dc8
>> --- /dev/null
>> +++ b/hw/misc/armv7m_ras.c
>> @@ -0,0 +1,93 @@
>> +/*
>> + * Arm M-profile RAS block
>> + *
>> + * Copyright (c) 2021 Linaro Limited
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 or
>> + * (at your option) any later version.
>> + */
>> +
>> +#include "qemu/osdep.h"
>> +#include "hw/misc/armv7m_ras.h"
>> +#include "qemu/log.h"
>> +
>> +static MemTxResult ras_read(void *opaque, hwaddr addr,
>> + uint64_t *data, unsigned size,
>> + MemTxAttrs attrs)
>> +{
>> + if (attrs.user) {
>> + return MEMTX_ERROR;
>> + }
>> +
>> + switch (addr) {
>> + case 0xe10: /* ERRIIDR */
>> + /* architect field = Arm; product/variant/revision 0 */
>> + *data = 0x43b;
>> + break;
>> + case 0xfc8: /* ERRDEVID */
>> + /* Minimal RAS: we implement 0 error record indexes */
>> + *data = 0;
>> + break;
>> + default:
>> + qemu_log_mask(LOG_UNIMP, "Read RAS register offset 0x%x\n",
>> + (uint32_t)addr);
>> + *data = 0;
>> + break;
>> + }
>> + return MEMTX_OK;
>> +}
>> +
>> +static MemTxResult ras_write(void *opaque, hwaddr addr,
>> + uint64_t value, unsigned size,
>> + MemTxAttrs attrs)
>> +{
>> + if (attrs.user) {
>> + return MEMTX_ERROR;
>> + }
>> +
>> + switch (addr) {
>> + default:
>> + qemu_log_mask(LOG_UNIMP, "Write to RAS register offset 0x%x\n",
>> + (uint32_t)addr);
>> + break;
>> + }
>> + return MEMTX_OK;
>> +}
>> +
>> +static const MemoryRegionOps ras_ops = {
>> + .read_with_attrs = ras_read,
>> + .write_with_attrs = ras_write,
>> + .endianness = DEVICE_NATIVE_ENDIAN,
>> +};
>> +
>> +
>> +static void armv7m_ras_init(Object *obj)
>> +{
>> + SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
>> + ARMv7MRAS *s = ARMV7M_RAS(obj);
>> +
>> + memory_region_init_io(&s->iomem, obj, &ras_ops,
>> + s, "armv7m-ras", 0x1000);
>> + sysbus_init_mmio(sbd, &s->iomem);
>> +}
>> +
>> +static void armv7m_ras_class_init(ObjectClass *klass, void *data)
>> +{
>> + /* This device has no state: no need for vmstate or reset */
>> +}
>> +
>> +static const TypeInfo armv7m_ras_info = {
>> + .name = TYPE_ARMV7M_RAS,
>> + .parent = TYPE_SYS_BUS_DEVICE,
>> + .instance_size = sizeof(ARMv7MRAS),
>> + .instance_init = armv7m_ras_init,
>> + .class_init = armv7m_ras_class_init,
>> +};
>> +
>> +static void armv7m_ras_register_types(void)
>> +{
>> + type_register_static(&armv7m_ras_info);
>> +}
>> +
>> +type_init(armv7m_ras_register_types);
>> diff --git a/MAINTAINERS b/MAINTAINERS
>> index 37b1a8e4428..3cac393bb48 100644
>> --- a/MAINTAINERS
>> +++ b/MAINTAINERS
>> @@ -617,6 +617,7 @@ F: hw/intc/gic_internal.h
>> F: hw/misc/a9scu.c
>> F: hw/misc/arm11scu.c
>> F: hw/misc/arm_l2x0.c
>> +F: hw/misc/armv7m_ras.c
>> F: hw/timer/a9gtimer*
>> F: hw/timer/arm*
>> F: include/hw/arm/arm*.h
>> @@ -626,6 +627,7 @@ F: include/hw/misc/arm11scu.h
>> F: include/hw/timer/a9gtimer.h
>> F: include/hw/timer/arm_mptimer.h
>> F: include/hw/timer/armv7m_systick.h
>> +F: include/hw/misc/armv7m_ras.h
>> F: tests/qtest/test-arm-mptimer.c
>>
>> Exynos
>> diff --git a/hw/misc/meson.build b/hw/misc/meson.build
>> index a53b849a5a0..3f41a3a5b27 100644
>> --- a/hw/misc/meson.build
>> +++ b/hw/misc/meson.build
>> @@ -17,6 +17,8 @@ softmmu_ss.add(when: 'CONFIG_INTEGRATOR_DEBUG', if_true: files('arm_integrator_d
>> softmmu_ss.add(when: 'CONFIG_A9SCU', if_true: files('a9scu.c'))
>> softmmu_ss.add(when: 'CONFIG_ARM11SCU', if_true: files('arm11scu.c'))
>>
>> +softmmu_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('armv7m_ras.c'))
>> +
>> # Mac devices
>> softmmu_ss.add(when: 'CONFIG_MOS6522', if_true: files('mos6522.c'))
>>
>> --
>> 2.20.1
>>
>
^ permalink raw reply [flat|nested] 91+ messages in thread
* Re: [PATCH for-6.2 09/25] clock: Provide builtin multiplier/divider
2021-08-17 9:59 ` Damien Hedde
@ 2021-08-17 10:46 ` Peter Maydell
2021-08-17 14:58 ` Damien Hedde
0 siblings, 1 reply; 91+ messages in thread
From: Peter Maydell @ 2021-08-17 10:46 UTC (permalink / raw)
To: Damien Hedde
Cc: Luc Michel, Alistair Francis, QEMU Developers, Subbaraya Sundeep,
qemu-arm, Joel Stanley, Alexandre Iooss
On Tue, 17 Aug 2021 at 10:59, Damien Hedde <damien.hedde@greensocs.com> wrote:
>
>
>
> On 8/12/21 11:33 AM, Peter Maydell wrote:
> > +void clock_set_mul_div(Clock *clk, uint32_t multiplier, uint32_t divider)
> > +{
> > + assert(divider != 0);
> > +
> > + clk->multiplier = multiplier;
> > + clk->divider = divider;
> > +}
> > +
> > static void clock_initfn(Object *obj)
> > {
> > Clock *clk = CLOCK(obj);
> >
> > + clk->multiplier = 1;
> > + clk->divider = 1;
> > +
> > QLIST_INIT(&clk->children);
> > }
> >
> >
>
> Regarding migration, you made the vmstate_muldiv subsection optional. I
> suppose it is to keep backward migration working in case of simple
> mul=1,div=1 clocks.
Yes -- we only send the subsection if the mul,div are
something other than 1,1; an inbound migration stream without
the subsection then means "use 1,1".
> Do we need to ensure multiplier and divider fields are set to 1 upon
> receiving a state if the vmstate_muldiv subsection is absent ? I
> remember there are post_load() tricks to achieve that.
I was relying on "we set the default in clock_initfn()" (by analogy
with being able to assume that fields in device state are at their
reset values when an inbound migration happens, so if the migration
doesn't set them then they stay at those reset values). But
thinking about it a bit more I think you're right and we do have to
have a pre_load function to set them to 1. Otherwise we would get
wrong the case where a board/SoC/device sets a clock up on reset
to have a non-1 multiplier, and then later the guest programs it to
be 1, and then we migrate like that. (That is, the mul/div at point
of migration will be the value-on-reset as set by the device etc
code that created the clock, which might be different from what
clock_initfn() set it to.)
So we need to add something like
static int clock_pre_load(void *opaque)
{
Clock *clk = opaque;
/*
* The initial out-of-reset settings of the Clock might have been
* configured by the device to be different from what we set
* in clock_initfn(), so we must here set the default values to
* be used if they are not in the inbound migration state.
*/
clk->multiplier = 1;
clk->divider = 1;
}
thanks
-- PMM
^ permalink raw reply [flat|nested] 91+ messages in thread
* Re: [PATCH for-6.2 09/25] clock: Provide builtin multiplier/divider
2021-08-17 10:46 ` Peter Maydell
@ 2021-08-17 14:58 ` Damien Hedde
0 siblings, 0 replies; 91+ messages in thread
From: Damien Hedde @ 2021-08-17 14:58 UTC (permalink / raw)
To: Peter Maydell
Cc: Luc Michel, Alistair Francis, QEMU Developers, Subbaraya Sundeep,
qemu-arm, Joel Stanley, Alexandre Iooss
On 8/17/21 12:46 PM, Peter Maydell wrote:
> On Tue, 17 Aug 2021 at 10:59, Damien Hedde <damien.hedde@greensocs.com> wrote:
>>
>>
>>
>> On 8/12/21 11:33 AM, Peter Maydell wrote:
>
>>> +void clock_set_mul_div(Clock *clk, uint32_t multiplier, uint32_t divider)
>>> +{
>>> + assert(divider != 0);
>>> +
>>> + clk->multiplier = multiplier;
>>> + clk->divider = divider;
>>> +}
>>> +
>>> static void clock_initfn(Object *obj)
>>> {
>>> Clock *clk = CLOCK(obj);
>>>
>>> + clk->multiplier = 1;
>>> + clk->divider = 1;
>>> +
>>> QLIST_INIT(&clk->children);
>>> }
>>>
>>>
>>
>> Regarding migration, you made the vmstate_muldiv subsection optional. I
>> suppose it is to keep backward migration working in case of simple
>> mul=1,div=1 clocks.
>
> Yes -- we only send the subsection if the mul,div are
> something other than 1,1; an inbound migration stream without
> the subsection then means "use 1,1".
>
>> Do we need to ensure multiplier and divider fields are set to 1 upon
>> receiving a state if the vmstate_muldiv subsection is absent ? I
>> remember there are post_load() tricks to achieve that.
>
> I was relying on "we set the default in clock_initfn()" (by analogy
> with being able to assume that fields in device state are at their
> reset values when an inbound migration happens, so if the migration
> doesn't set them then they stay at those reset values). But
> thinking about it a bit more I think you're right and we do have to
> have a pre_load function to set them to 1. Otherwise we would get
> wrong the case where a board/SoC/device sets a clock up on reset
> to have a non-1 multiplier, and then later the guest programs it to
> be 1, and then we migrate like that. (That is, the mul/div at point
> of migration will be the value-on-reset as set by the device etc
> code that created the clock, which might be different from what
> clock_initfn() set it to.)
Yes, I think we cannot expect the machine init or reset to keep all
clocks in div=1,mul=1 state.
>
> So we need to add something like
>
> static int clock_pre_load(void *opaque)
> {
> Clock *clk = opaque;
> /*
> * The initial out-of-reset settings of the Clock might have been
> * configured by the device to be different from what we set
> * in clock_initfn(), so we must here set the default values to
> * be used if they are not in the inbound migration state.
> */
> clk->multiplier = 1;
> clk->divider = 1;
> }
>
With this callback registered in the main vmsd section,
Reviewed-by: Damien Hedde <damien.hedde@greensocs.com>
Thanks,
--
Damien
^ permalink raw reply [flat|nested] 91+ messages in thread
* Re: [PATCH for-6.2 20/25] hw/arm/msf2-soc: Wire up refclk
2021-08-12 9:33 ` [PATCH for-6.2 20/25] hw/arm/msf2-soc: Wire up refclk Peter Maydell
@ 2021-08-17 15:05 ` Damien Hedde
0 siblings, 0 replies; 91+ messages in thread
From: Damien Hedde @ 2021-08-17 15:05 UTC (permalink / raw)
To: Peter Maydell, qemu-arm, qemu-devel
Cc: Alexandre Iooss, Alistair Francis, Luc Michel, Joel Stanley,
Subbaraya Sundeep
On 8/12/21 11:33 AM, Peter Maydell wrote:
> Wire up the refclk for the msf2 SoC. This SoC runs the refclk at a
> frequency which is programmably either /4, /8, /16 or /32 of the main
> CPU clock. We don't currently model the register which allows the
> guest to set the divisor, so implement the refclk as a fixed /32 of
> the CPU clock (which is the value of the divisor at reset).
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Damien Hedde <damien.hedde@greensocs.com>
^ permalink raw reply [flat|nested] 91+ messages in thread
* Re: [PATCH for-6.2 21/25] hw/timer/armv7m_systick: Use clock inputs instead of system_clock_scale
2021-08-12 9:33 ` [PATCH for-6.2 21/25] hw/timer/armv7m_systick: Use clock inputs instead of system_clock_scale Peter Maydell
@ 2021-08-17 15:55 ` Damien Hedde
2021-08-17 15:59 ` Peter Maydell
0 siblings, 1 reply; 91+ messages in thread
From: Damien Hedde @ 2021-08-17 15:55 UTC (permalink / raw)
To: Peter Maydell, qemu-arm, qemu-devel
Cc: Alexandre Iooss, Alistair Francis, Luc Michel, Joel Stanley,
Subbaraya Sundeep
On 8/12/21 11:33 AM, Peter Maydell wrote:
> Now that all users of the systick devices wire up the clock inputs,
> use those instead of the system_clock_scale and the hardwired 1MHz
> value for the reference clock.
>
> This will fix various board models where we were incorrectly
> providing a 1MHz reference clock instead of some other value or
> instead of providing no reference clock at all.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
> hw/timer/armv7m_systick.c | 110 ++++++++++++++++++++++++++++----------
> 1 file changed, 82 insertions(+), 28 deletions(-)
>
> diff --git a/hw/timer/armv7m_systick.c b/hw/timer/armv7m_systick.c
> index e43f74114e8..39cca206cfd 100644
> --- a/hw/timer/armv7m_systick.c
> +++ b/hw/timer/armv7m_systick.c
> @@ -18,25 +18,29 @@
> #include "qemu/timer.h"
> #include "qemu/log.h"
> #include "qemu/module.h"
> +#include "qapi/error.h"
> #include "trace.h"
>
> -/* qemu timers run at 1GHz. We want something closer to 1MHz. */
> -#define SYSTICK_SCALE 1000ULL
> -
> #define SYSTICK_ENABLE (1 << 0)
> #define SYSTICK_TICKINT (1 << 1)
> #define SYSTICK_CLKSOURCE (1 << 2)
> #define SYSTICK_COUNTFLAG (1 << 16)
>
> +#define SYSCALIB_NOREF (1U << 31)
> +#define SYSCALIB_SKEW (1U << 30)
> +
> int system_clock_scale;
>
> -/* Conversion factor from qemu timer to SysTick frequencies. */
> -static inline int64_t systick_scale(SysTickState *s)
> +static void systick_set_period_from_clock(SysTickState *s)
> {
> + /*
> + * Set the ptimer period from whichever clock is selected.
> + * Must be called from within a ptimer transaction block.
> + */
> if (s->control & SYSTICK_CLKSOURCE) {
> - return system_clock_scale;
> + ptimer_set_period_from_clock(s->ptimer, s->cpuclk, 1);
> } else {
> - return 1000;
> + ptimer_set_period_from_clock(s->ptimer, s->refclk, 1);
> }
> }
>
> @@ -83,7 +87,27 @@ static MemTxResult systick_read(void *opaque, hwaddr addr, uint64_t *data,
> val = ptimer_get_count(s->ptimer);
> break;
> case 0xc: /* SysTick Calibration Value. */
> - val = 10000;
> + /*
> + * In real hardware it is possible to make this register report
> + * a different value from what the reference clock is actually
> + * running at. We don't model that (which usually happens due
> + * to integration errors in the real hardware) and instead always
> + * report the theoretical correct value as described in the
> + * knowledgebase article at
> + * https://developer.arm.com/documentation/ka001325/latest
> + * If necessary, we could implement an extra QOM property on this
> + * device to force the STCALIB value to something different from
> + * the "correct" value.
> + */
> + if (!clock_has_source(s->refclk)) {
> + val = SYSCALIB_NOREF;
> + break;
> + }
> + val = clock_ns_to_ticks(s->refclk, 10 * SCALE_MS) - 1;
According to
https://developer.arm.com/documentation/ddi0403/d/System-Level-Architecture/System-Address-Map/The-system-timer--SysTick/SysTick-Calibration-value-Register--SYST-CALIB
, the field is 24bits wide.
Should we prevent an overflow into the reserved bits and other fields ?
by doing something like this:
val &= SYSCALIB_TENMS;
with the following #define with the other ones, above.
#define SYSCALIB_TENMS ((1U << 24) - 1)
Note, the overflow would happen around ~1.68GHz refclk frequency, it is
probably a config that will never happen. I'm not sure if we should care
or do something if this happens because it is probably an error
somewhere else.
> + if (clock_ticks_to_ns(s->refclk, val + 1) != 10 * SCALE_MS) {
> + /* report that tick count does not yield exactly 10ms */
> + val |= SYSCALIB_SKEW;
> + }
> break;
Otherwise the patch looks great.
Thanks,
Damien
^ permalink raw reply [flat|nested] 91+ messages in thread
* Re: [PATCH for-6.2 21/25] hw/timer/armv7m_systick: Use clock inputs instead of system_clock_scale
2021-08-17 15:55 ` Damien Hedde
@ 2021-08-17 15:59 ` Peter Maydell
2021-08-17 16:14 ` Damien Hedde
0 siblings, 1 reply; 91+ messages in thread
From: Peter Maydell @ 2021-08-17 15:59 UTC (permalink / raw)
To: Damien Hedde
Cc: Luc Michel, Alistair Francis, QEMU Developers, Subbaraya Sundeep,
qemu-arm, Joel Stanley, Alexandre Iooss
On Tue, 17 Aug 2021 at 16:55, Damien Hedde <damien.hedde@greensocs.com> wrote:
>
>
>
> On 8/12/21 11:33 AM, Peter Maydell wrote:
> According to
> https://developer.arm.com/documentation/ddi0403/d/System-Level-Architecture/System-Address-Map/The-system-timer--SysTick/SysTick-Calibration-value-Register--SYST-CALIB
> , the field is 24bits wide.
>
> Should we prevent an overflow into the reserved bits and other fields ?
> by doing something like this:
> val &= SYSCALIB_TENMS;
> with the following #define with the other ones, above.
> #define SYSCALIB_TENMS ((1U << 24) - 1)
>
> Note, the overflow would happen around ~1.68GHz refclk frequency, it is
> probably a config that will never happen. I'm not sure if we should care
> or do something if this happens because it is probably an error
> somewhere else.
I guess we should do something, yes, though pretty much anything
we do will not really provide the guest with sensible data...
I suppose masking out the higher bits is no worse than anything else.
-- PMM
^ permalink raw reply [flat|nested] 91+ messages in thread
* Re: [PATCH for-6.2 23/25] hw/arm/stellaris: Split stellaris-gptm into its own file
2021-08-12 9:33 ` [PATCH for-6.2 23/25] hw/arm/stellaris: Split stellaris-gptm into its own file Peter Maydell
@ 2021-08-17 15:59 ` Damien Hedde
0 siblings, 0 replies; 91+ messages in thread
From: Damien Hedde @ 2021-08-17 15:59 UTC (permalink / raw)
To: Peter Maydell, qemu-arm, qemu-devel
Cc: Alexandre Iooss, Alistair Francis, Luc Michel, Joel Stanley,
Subbaraya Sundeep
On 8/12/21 11:33 AM, Peter Maydell wrote:
> The implementation of the Stellaris general purpose timer module
> device stellaris-gptm is currently in the same source file as the
> board model. Split it out into its own source file in hw/timer.
>
> Apart from the new file comment headers and the Kconfig and
> meson.build changes, this is just code movement.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Damien Hedde <damien.hedde@greensocs.com>
--
Damien
^ permalink raw reply [flat|nested] 91+ messages in thread
* Re: [PATCH for-6.2 21/25] hw/timer/armv7m_systick: Use clock inputs instead of system_clock_scale
2021-08-17 15:59 ` Peter Maydell
@ 2021-08-17 16:14 ` Damien Hedde
0 siblings, 0 replies; 91+ messages in thread
From: Damien Hedde @ 2021-08-17 16:14 UTC (permalink / raw)
To: Peter Maydell
Cc: Luc Michel, Alistair Francis, QEMU Developers, Subbaraya Sundeep,
qemu-arm, Joel Stanley, Alexandre Iooss
On 8/17/21 5:59 PM, Peter Maydell wrote:
> On Tue, 17 Aug 2021 at 16:55, Damien Hedde <damien.hedde@greensocs.com> wrote:
>>
>>
>>
>> On 8/12/21 11:33 AM, Peter Maydell wrote:
>> According to
>> https://developer.arm.com/documentation/ddi0403/d/System-Level-Architecture/System-Address-Map/The-system-timer--SysTick/SysTick-Calibration-value-Register--SYST-CALIB
>> , the field is 24bits wide.
>>
>> Should we prevent an overflow into the reserved bits and other fields ?
>> by doing something like this:
>> val &= SYSCALIB_TENMS;
>> with the following #define with the other ones, above.
>> #define SYSCALIB_TENMS ((1U << 24) - 1)
>>
>> Note, the overflow would happen around ~1.68GHz refclk frequency, it is
>> probably a config that will never happen. I'm not sure if we should care
>> or do something if this happens because it is probably an error
>> somewhere else.
>
> I guess we should do something, yes, though pretty much anything
> we do will not really provide the guest with sensible data...
> I suppose masking out the higher bits is no worse than anything else.
>
> -- PMM
>
Then, with the masking.
Reviewed-by: Damien Hedde <damien.hedde@greensocs.com>
--
Damien
^ permalink raw reply [flat|nested] 91+ messages in thread
* Re: [PATCH for-6.2 24/25] hw/timer/stellaris-gptm: Use Clock input instead of system_clock_scale
2021-08-12 9:33 ` [PATCH for-6.2 24/25] hw/timer/stellaris-gptm: Use Clock input instead of system_clock_scale Peter Maydell
@ 2021-08-18 12:03 ` Damien Hedde
0 siblings, 0 replies; 91+ messages in thread
From: Damien Hedde @ 2021-08-18 12:03 UTC (permalink / raw)
To: Peter Maydell, qemu-arm, qemu-devel
Cc: Alexandre Iooss, Alistair Francis, Luc Michel, Joel Stanley,
Subbaraya Sundeep
On 8/12/21 11:33 AM, Peter Maydell wrote:
> The stellaris-gptm timer currently uses system_clock_scale for one of
> its timer modes where the timer runs at the CPU clock rate. Make it
> use a Clock input instead.
>
> We don't try to make the timer handle changes in the clock frequency
> while the downcounter is running. This is not a change in behaviour
> from the previous system_clock_scale implementation -- we will pick
> up the new frequency only when the downcounter hits zero. Handling
> dynamic clock changes when the counter is running would require state
> that the current gptm implementation doesn't have.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
> As noted in the comment, ideally we would convert the device to use
> ptimer for its downcounter, which supports frequency changes while
> the counter is running and would also allow reading the timer value.
> But I don't want to make and test that change to a minor timer device
> in a board model I wouldn't recommend anybody actually use; this
> series is long enough as it is...
> ---
> include/hw/timer/stellaris-gptm.h | 3 +++
> hw/arm/stellaris.c | 12 +++++++++---
> hw/timer/stellaris-gptm.c | 26 ++++++++++++++++++++++----
> 3 files changed, 34 insertions(+), 7 deletions(-)
>
Reviewed-by: Damien Hedde <damien.hedde@greensocs.com>
^ permalink raw reply [flat|nested] 91+ messages in thread
end of thread, other threads:[~2021-08-18 12:06 UTC | newest]
Thread overview: 91+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-08-12 9:33 [PATCH for-6.2 00/25] arm: Get rid of system_clock_scale global Peter Maydell
2021-08-12 9:33 ` [PATCH for-6.2 01/25] arm: Move M-profile RAS register block into its own device Peter Maydell
2021-08-12 11:08 ` Alexandre IOOSS
2021-08-12 11:09 ` Peter Maydell
2021-08-13 0:59 ` Alistair Francis
2021-08-15 17:30 ` Philippe Mathieu-Daudé
2021-08-16 7:28 ` David Hildenbrand
2021-08-16 9:16 ` Peter Maydell
2021-08-17 8:25 ` Luc Michel
2021-08-17 10:10 ` Damien Hedde
2021-08-12 9:33 ` [PATCH for-6.2 02/25] arm: Move systick device creation from NVIC to ARMv7M object Peter Maydell
2021-08-13 1:23 ` Alistair Francis
2021-08-17 9:24 ` Luc Michel
2021-08-12 9:33 ` [PATCH for-6.2 03/25] arm: Move system PPB container handling to armv7m Peter Maydell
2021-08-12 11:56 ` Alexandre IOOSS
2021-08-17 9:25 ` Luc Michel
2021-08-12 9:33 ` [PATCH for-6.2 04/25] hw/timer/armv7m_systick: Add usual QEMU interface comment Peter Maydell
2021-08-13 1:26 ` Alistair Francis
2021-08-17 9:29 ` Luc Michel
2021-08-12 9:33 ` [PATCH for-6.2 05/25] hw/timer/armv7m_systick: Add input clocks Peter Maydell
2021-08-13 1:27 ` Alistair Francis
2021-08-17 9:32 ` Luc Michel
2021-08-12 9:33 ` [PATCH for-6.2 06/25] hw/arm/armv7m: Create " Peter Maydell
2021-08-13 1:28 ` Alistair Francis
2021-08-17 9:34 ` Luc Michel
2021-08-12 9:33 ` [PATCH for-6.2 07/25] armsse: Wire up systick cpuclk clock Peter Maydell
2021-08-13 1:29 ` Alistair Francis
2021-08-17 9:36 ` Luc Michel
2021-08-12 9:33 ` [PATCH for-6.2 08/25] hw/arm/mps2.c: Connect up armv7m clocks Peter Maydell
2021-08-17 9:39 ` Luc Michel
2021-08-12 9:33 ` [PATCH for-6.2 09/25] clock: Provide builtin multiplier/divider Peter Maydell
2021-08-12 12:08 ` Alexandre IOOSS
2021-08-12 12:22 ` Peter Maydell
2021-08-13 1:33 ` Alistair Francis
2021-08-15 16:32 ` Philippe Mathieu-Daudé
2021-08-16 9:05 ` Peter Maydell
2021-08-16 9:32 ` Philippe Mathieu-Daudé
2021-08-16 9:36 ` Peter Maydell
2021-08-16 9:58 ` Philippe Mathieu-Daudé
2021-08-15 21:27 ` Luc Michel
2021-08-17 9:59 ` Damien Hedde
2021-08-17 10:46 ` Peter Maydell
2021-08-17 14:58 ` Damien Hedde
2021-08-12 9:33 ` [PATCH for-6.2 10/25] hw/arm: Don't allocate separate MemoryRegions in stm32 SoC realize Peter Maydell
2021-08-12 12:13 ` Alexandre IOOSS
2021-08-12 12:27 ` Peter Maydell
2021-08-15 16:37 ` Philippe Mathieu-Daudé
2021-08-13 1:34 ` Alistair Francis
2021-08-17 9:41 ` Luc Michel
2021-08-12 9:33 ` [PATCH for-6.2 11/25] hw/arm/stm32f100: Wire up sysclk and refclk Peter Maydell
2021-08-13 1:36 ` Alistair Francis
2021-08-14 9:01 ` Alexandre IOOSS
2021-08-17 9:45 ` Luc Michel
2021-08-12 9:33 ` [PATCH for-6.2 12/25] hw/arm/stm32f205: " Peter Maydell
2021-08-13 1:38 ` Alistair Francis
2021-08-14 9:02 ` Alexandre IOOSS
2021-08-17 9:47 ` Luc Michel
2021-08-12 9:33 ` [PATCH for-6.2 13/25] hw/arm/stm32f405: " Peter Maydell
2021-08-13 1:37 ` Alistair Francis
2021-08-14 9:03 ` Alexandre IOOSS
2021-08-17 9:47 ` Luc Michel
2021-08-12 9:33 ` [PATCH for-6.2 14/25] hw/arm/stm32vldiscovery: Delete trailing blank line Peter Maydell
2021-08-12 12:27 ` Alexandre IOOSS
2021-08-13 1:39 ` Alistair Francis
2021-08-17 9:48 ` Luc Michel
2021-08-12 9:33 ` [PATCH for-6.2 15/25] hw/arm/nrf51: Wire up sysclk Peter Maydell
2021-08-14 9:06 ` Alexandre IOOSS
2021-08-12 9:33 ` [PATCH for-6.2 16/25] hw/arm/stellaris: split stellaris_sys_init() Peter Maydell
2021-08-14 9:10 ` Alexandre IOOSS
2021-08-12 9:33 ` [PATCH for-6.2 17/25] hw/arm/stellaris: Wire sysclk up to armv7m Peter Maydell
2021-08-14 9:12 ` Alexandre IOOSS
2021-08-12 9:33 ` [PATCH for-6.2 18/25] hw/arm/msf2_soc: Don't allocate separate MemoryRegions Peter Maydell
2021-08-14 9:13 ` Alexandre IOOSS
2021-08-12 9:33 ` [PATCH for-6.2 19/25] hw/arm/msf2: Use Clock input to MSF2_SOC instead of m3clk property Peter Maydell
2021-08-14 9:20 ` Alexandre IOOSS
2021-08-14 10:11 ` Peter Maydell
2021-08-14 10:47 ` Alexandre IOOSS
2021-08-12 9:33 ` [PATCH for-6.2 20/25] hw/arm/msf2-soc: Wire up refclk Peter Maydell
2021-08-17 15:05 ` Damien Hedde
2021-08-12 9:33 ` [PATCH for-6.2 21/25] hw/timer/armv7m_systick: Use clock inputs instead of system_clock_scale Peter Maydell
2021-08-17 15:55 ` Damien Hedde
2021-08-17 15:59 ` Peter Maydell
2021-08-17 16:14 ` Damien Hedde
2021-08-12 9:33 ` [PATCH for-6.2 22/25] hw/arm/stellaris: Fix code style issues in GPTM code Peter Maydell
2021-08-14 9:26 ` Alexandre IOOSS
2021-08-12 9:33 ` [PATCH for-6.2 23/25] hw/arm/stellaris: Split stellaris-gptm into its own file Peter Maydell
2021-08-17 15:59 ` Damien Hedde
2021-08-12 9:33 ` [PATCH for-6.2 24/25] hw/timer/stellaris-gptm: Use Clock input instead of system_clock_scale Peter Maydell
2021-08-18 12:03 ` Damien Hedde
2021-08-12 9:33 ` [PATCH for-6.2 25/25] arm: Remove system_clock_scale global Peter Maydell
2021-08-13 5:08 ` Alistair Francis
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