From mboxrd@z Thu Jan 1 00:00:00 1970 From: Kever Yang Subject: Re: [PATCH v3 12/57] ram: rk3399: Rename sys_reg with sys_reg2 Date: Tue, 16 Jul 2019 21:03:23 +0800 Message-ID: <4006c069-e8ab-69e1-8927-f11241d6e33c@rock-chips.com> References: <20190716115745.12585-1-jagan@amarulasolutions.com> <20190716115745.12585-13-jagan@amarulasolutions.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8"; Format="flowed" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <20190716115745.12585-13-jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org> Content-Language: en-US List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+glpar-linux-rockchip=m.gmane.org-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org To: Jagan Teki , Simon Glass , Philipp Tomsich , YouMin Chen , u-boot-0aAXYlwwYIKGBzrmiIFOJg@public.gmane.org Cc: linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, gajjar04akash-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org, linux-amarula-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org, Manivannan Sadhasivam List-Id: linux-rockchip.vger.kernel.org Ck9uIDIwMTkvNy8xNiDkuIvljYg3OjU3LCBKYWdhbiBUZWtpIHdyb3RlOgo+IFVzZSBkcmFtIGNv bmZpZyB2YXJpYWJsZSBuYW1lIGFzIHN5c19yZWcyIGluc3RlYWQgb2Ygc3lzX3JlZwo+IHNpbmNl IHRoZSBmaW5hbCB2YXJpYWJsZSB2YWx1ZSBpcyB0byB3cml0dGVuIGludG8gYSBwbXVncmYKPiBy ZWdpc3RlciBuYW1lZCBhcyBzeXNfcmVnMi4KPgo+IFRoaXMgcmVmbGVjdCB0aGUgYm90aCB2YXJp YWJsZSBhbmQgYXNzb2NpYXRlZCByZWdpc3Rlcgo+IG5hbWVzIGFyZSBzYW1lIGFuZCBhbHNvIGhl bHAgdG8gYWRkIG5leHQgc3lzX3JlZydzIHRvCj4gYWRkIGl0IGluIGZ1dHVyZS4KPgo+IFNpZ25l ZC1vZmYtYnk6IEphZ2FuIFRla2kgPGphZ2FuQGFtYXJ1bGFzb2x1dGlvbnMuY29tPgo+IFNpZ25l ZC1vZmYtYnk6IFlvdU1pbiBDaGVuIDxjeW1Acm9jay1jaGlwcy5jb20+CgpSZXZpZXdlZC1ieTog S2V2ZXIgWWFuZyA8S2V2ZXIueWFuZ0Byb2NrLWNoaXBzLmNvbT4KClRoYW5rcywKIMKgLSBLZXZl cgo+IC0tLQo+ICAgZHJpdmVycy9yYW0vcm9ja2NoaXAvc2RyYW1fcmszMzk5LmMgfCAyNiArKysr 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References: <20190716115745.12585-1-jagan@amarulasolutions.com> <20190716115745.12585-13-jagan@amarulasolutions.com> Message-ID: <4006c069-e8ab-69e1-8927-f11241d6e33c@rock-chips.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit To: u-boot@lists.denx.de On 2019/7/16 下午7:57, Jagan Teki wrote: > Use dram config variable name as sys_reg2 instead of sys_reg > since the final variable value is to written into a pmugrf > register named as sys_reg2. > > This reflect the both variable and associated register > names are same and also help to add next sys_reg's to > add it in future. > > Signed-off-by: Jagan Teki > Signed-off-by: YouMin Chen Reviewed-by: Kever Yang Thanks,  - Kever > --- > drivers/ram/rockchip/sdram_rk3399.c | 26 +++++++++++++------------- > 1 file changed, 13 insertions(+), 13 deletions(-) > > diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c > index 2d3f0f6902..2ef969c07b 100644 > --- a/drivers/ram/rockchip/sdram_rk3399.c > +++ b/drivers/ram/rockchip/sdram_rk3399.c > @@ -1073,11 +1073,11 @@ static void set_ddrconfig(const struct chan_info *chan, > static void dram_all_config(struct dram_info *dram, > const struct rk3399_sdram_params *params) > { > - u32 sys_reg = 0; > + u32 sys_reg2 = 0; > unsigned int channel, idx; > > - sys_reg |= SYS_REG_ENC_DDRTYPE(params->base.dramtype); > - sys_reg |= SYS_REG_ENC_NUM_CH(params->base.num_channels); > + sys_reg2 |= SYS_REG_ENC_DDRTYPE(params->base.dramtype); > + sys_reg2 |= SYS_REG_ENC_NUM_CH(params->base.num_channels); > > for (channel = 0, idx = 0; > (idx < params->base.num_channels) && (channel < 2); > @@ -1089,15 +1089,15 @@ static void dram_all_config(struct dram_info *dram, > if (params->ch[channel].cap_info.col == 0) > continue; > idx++; > - sys_reg |= SYS_REG_ENC_ROW_3_4(info->cap_info.row_3_4, channel); > - sys_reg |= SYS_REG_ENC_CHINFO(channel); > - sys_reg |= SYS_REG_ENC_RANK(info->cap_info.rank, channel); > - sys_reg |= SYS_REG_ENC_COL(info->cap_info.col, channel); > - sys_reg |= SYS_REG_ENC_BK(info->cap_info.bk, channel); > - sys_reg |= SYS_REG_ENC_CS0_ROW(info->cap_info.cs0_row, channel); > - sys_reg |= SYS_REG_ENC_CS1_ROW(info->cap_info.cs1_row, channel); > - sys_reg |= SYS_REG_ENC_BW(info->cap_info.bw, channel); > - sys_reg |= SYS_REG_ENC_DBW(info->cap_info.dbw, channel); > + sys_reg2 |= SYS_REG_ENC_ROW_3_4(info->cap_info.row_3_4, channel); > + sys_reg2 |= SYS_REG_ENC_CHINFO(channel); > + sys_reg2 |= SYS_REG_ENC_RANK(info->cap_info.rank, channel); > + sys_reg2 |= SYS_REG_ENC_COL(info->cap_info.col, channel); > + sys_reg2 |= SYS_REG_ENC_BK(info->cap_info.bk, channel); > + sys_reg2 |= SYS_REG_ENC_CS0_ROW(info->cap_info.cs0_row, channel); > + sys_reg2 |= SYS_REG_ENC_CS1_ROW(info->cap_info.cs1_row, channel); > + sys_reg2 |= SYS_REG_ENC_BW(info->cap_info.bw, channel); > + sys_reg2 |= SYS_REG_ENC_DBW(info->cap_info.dbw, channel); > > ddr_msch_regs = dram->chan[channel].msch; > noc_timing = ¶ms->ch[channel].noc_timings; > @@ -1118,7 +1118,7 @@ static void dram_all_config(struct dram_info *dram, > 1 << 17); > } > > - writel(sys_reg, &dram->pmugrf->os_reg2); > + writel(sys_reg2, &dram->pmugrf->os_reg2); > rk_clrsetreg(&dram->pmusgrf->soc_con4, 0x1f << 10, > params->base.stride << 10); >