From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756885AbcAYOEn (ORCPT ); Mon, 25 Jan 2016 09:04:43 -0500 Received: from gloria.sntech.de ([95.129.55.99]:46089 "EHLO gloria.sntech.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755405AbcAYOEi (ORCPT ); Mon, 25 Jan 2016 09:04:38 -0500 From: Heiko =?ISO-8859-1?Q?St=FCbner?= To: kishon@ti.com Cc: mturquette@baylibre.com, sboyd@codeaurora.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org, dianders@chromium.org, romain.perier@gmail.com, arnd@arndb.de, hl@rock-chips.com Subject: Re: [PATCH v3 7/8] clk: rockchip: fix usbphy-related clocks Date: Mon, 25 Jan 2016 15:04:31 +0100 Message-ID: <4016576.NEsgSPjyJ9@diego> User-Agent: KMail/4.14.10 (Linux/4.2.0-1-amd64; KDE/4.14.14; x86_64; ; ) In-Reply-To: <1447968149-10979-8-git-send-email-heiko@sntech.de> References: <1447968149-10979-1-git-send-email-heiko@sntech.de> <1447968149-10979-8-git-send-email-heiko@sntech.de> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Kishon, Am Donnerstag, 19. November 2015, 22:22:28 schrieb Heiko Stuebner: > The otgphy clocks really only drive the phy blocks. These in turn > contain plls that then generate the 480m clocks the clock controller > uses to supply some other clocks like uart0, gpu or the video-codec. > > So fix this structure to actually respect that hirarchy and removed > that usb480m fixed-rate clock working as a placeholder till now, as > this wouldn't even work if the supplying phy gets turned off while > its pll-output gets used elsewhere. > > Signed-off-by: Heiko Stuebner > Reviewed-by: Douglas Anderson it looks like this patch didn't make your cutoff time for sending your stuff to Greg. As the core phy series up to patch 5 is in mainline now, I've just applied this patch to my clk-branch for 4.6. Heiko From mboxrd@z Thu Jan 1 00:00:00 1970 From: heiko@sntech.de (Heiko =?ISO-8859-1?Q?St=FCbner?=) Date: Mon, 25 Jan 2016 15:04:31 +0100 Subject: [PATCH v3 7/8] clk: rockchip: fix usbphy-related clocks In-Reply-To: <1447968149-10979-8-git-send-email-heiko@sntech.de> References: <1447968149-10979-1-git-send-email-heiko@sntech.de> <1447968149-10979-8-git-send-email-heiko@sntech.de> Message-ID: <4016576.NEsgSPjyJ9@diego> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Kishon, Am Donnerstag, 19. November 2015, 22:22:28 schrieb Heiko Stuebner: > The otgphy clocks really only drive the phy blocks. These in turn > contain plls that then generate the 480m clocks the clock controller > uses to supply some other clocks like uart0, gpu or the video-codec. > > So fix this structure to actually respect that hirarchy and removed > that usb480m fixed-rate clock working as a placeholder till now, as > this wouldn't even work if the supplying phy gets turned off while > its pll-output gets used elsewhere. > > Signed-off-by: Heiko Stuebner > Reviewed-by: Douglas Anderson it looks like this patch didn't make your cutoff time for sending your stuff to Greg. As the core phy series up to patch 5 is in mainline now, I've just applied this patch to my clk-branch for 4.6. Heiko