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[82.81.161.50]) by smtp.gmail.com with ESMTPSA id o21-20020a05622a009500b0031d4044c464sm7807985qtw.46.2022.07.12.06.37.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Jul 2022 06:37:09 -0700 (PDT) Message-ID: <4017447bfd4636f4075d29d8f3c57c4c32fd67d2.camel@redhat.com> Subject: Re: [PATCH 2/3] KVM: x86: Set error code to segment selector on LLDT/LTR non-canonical #GP From: Maxim Levitsky To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, syzbot+760a73552f47a8cd0fd9@syzkaller.appspotmail.com, Tetsuo Handa , Hou Wenlong Date: Tue, 12 Jul 2022 16:37:06 +0300 In-Reply-To: <20220711232750.1092012-3-seanjc@google.com> References: <20220711232750.1092012-1-seanjc@google.com> <20220711232750.1092012-3-seanjc@google.com> Content-Type: text/plain; charset="UTF-8" User-Agent: Evolution 3.40.4 (3.40.4-5.fc34) MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, 2022-07-11 at 23:27 +0000, Sean Christopherson wrote: > When injecting a #GP on LLDT/LTR due to a non-canonical LDT/TSS base, set > the error code to the selector.  Intel SDM's says nothing about the #GP, > but AMD's APM explicitly states that both LLDT and LTR set the error code > to the selector, not zero. > > Note, a non-canonical memory operand on LLDT/LTR does generate a #GP(0), > but the KVM code in question is specific to the base from the descriptor. > > Fixes: e37a75a13cda ("KVM: x86: Emulator ignores LDTR/TR extended base on LLDT/LTR") > Cc: stable@vger.kernel.org > Signed-off-by: Sean Christopherson > --- >  arch/x86/kvm/emulate.c | 4 ++-- >  1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/arch/x86/kvm/emulate.c b/arch/x86/kvm/emulate.c > index 09e4b67b881f..bd9e9c5627d0 100644 > --- a/arch/x86/kvm/emulate.c > +++ b/arch/x86/kvm/emulate.c > @@ -1736,8 +1736,8 @@ static int __load_segment_descriptor(struct x86_emulate_ctxt *ctxt, >                 if (ret != X86EMUL_CONTINUE) >                         return ret; >                 if (emul_is_noncanonical_address(get_desc_base(&seg_desc) | > -                               ((u64)base3 << 32), ctxt)) > -                       return emulate_gp(ctxt, 0); > +                                                ((u64)base3 << 32), ctxt)) > +                       return emulate_gp(ctxt, err_code); >         } >   >         if (seg == VCPU_SREG_TR) { I guess this is the quote from AMD's manual (might we worth to add to the source?) "The 64-bit system-segment base address must be in canonical form. Otherwise, a general-protection exception occurs with a selector error-code, #GP(selector), when the system segment is loaded. System-segment limit values are checked by the processor in both 64-bit and compatibility modes, under the control of the granularity (G) bit." Reviewed-by: Maxim Levitsky Best regards, Maxim Levitsky