* [PATCH v20 0/8] Add Mediatek Soc DRM (vdosys0) support for mt8195
@ 2022-04-19 9:41 ` jason-jh.lin
0 siblings, 0 replies; 110+ messages in thread
From: jason-jh.lin @ 2022-04-19 9:41 UTC (permalink / raw)
To: Matthias Brugger, Chun-Kuang Hu, AngeloGioacchino Del Regno
Cc: devicetree, jason-jhlin, Jason-JH Lin, Singo Chang, linux-kernel,
dri-devel, Project_Global_Chrome_Upstream_Group, Nancy Lin,
linux-mediatek, linux-arm-kernel
From: jason-jhlin <jason-jh.lin@mediatek.corp-partner.google.com>
Change in v20:
- split binding patch to another series 'MediaTek MT8195 display binding':
https://patchwork.ozlabs.org/project/devicetree-bindings/list/?series=295669
- fix io_start type from u32 to resource_size_t
- fix some commit message for DITHER enum
Change in v19:
- fix checking condition for the return vaule of platform resource
- drm/mediatek fix build waning for [-Wunused-const-variable]
Change in v18:
- change get driver data by io_start and wrap mmsys driver data into
mmsys match data structure to support identifying multi mmsys driver
data with the same compatible name
- change DDP_COMPONENT_DITHER to DDP_CONPONENT_DITHER0
Change in v17:
- change compatible name from 2 vdosys to 1 mmsys
- add get driver data by clk name function to get corresponding
driver data for mt8195 vdosys0
- add all routing table setting for mt8195 vdosys0
- remove useless mutex define
Change in v16:
- rebase on linu-next tag: 'next-20220303'
- rebase on series: 'Fix MediaTek display dt-bindings issues'
Change in v15:
- remove mt8195-mmsys.h comment for mux settings
- define the mask macro to replace using value as mask
to fix zero mask problem
- add EOF setting comment for MUTEX sof register
Change in v14:
- rebase on mediatek-drm-next-5.17
- rebase on "Add mmsys and mutex support for MDP" series
- rebase on "media: mediatek: support mdp3 on mt8183 platform" series
Change in v13:
- remove dts patch
- rebase on kernel-5.16-rc1
- rebase on mediatek-drm-next
Change in v12:
- add clock-names property to merge yaml
- using BIT(nr) macro to define the settings of mmsys routing table
- fix clk_get and clk_prepare_enable error handling issue
Change in v11:
- rebase on kernel-5.15-rc1
- change mbox label to gce0 for dts node of vdosys0
- change ovl compatibale to mt8192 to set smi_id_en=true in driver data
- move common module from display folder to common folder,
such as AAL, COCLOR, CCORR and MUTEX
Change in v10:
- rebase on "drm/mediatek: add support for mediatek SOC MT8192" series
- rebase on "soc: mediatek: mmsys: add mt8192 mmsys support" series
- fix some typo and "mediatek" start with capital in every dt-bindings
- move mutex yaml from dfisplay folder to soc folder
- separate merge additional propoerties to an individual dt-bindings patch
Change in v9:
- separate power and gce properties of mmsys into another dt-binding patch
- rebase on "Separate aal module" series
- keep mtk_ddp_clk_enable/disable in the same place
- change mtk_dsc_start config register to mtk_drm_ddp_write_mask
- remove the 0 setting of merge fifo config function
- add CCORR driver data for mt8195
Change in v8:
- add DP_INTF0 mux into mmsys routing table
- add DP_INTF0 mutex mod and enum into add/remove comp function
- remove bypass DSC enum in mtk_ddp_comp_init
Change in v7:
- add dt=binding of mmsys and disp path into this series
- separate th modidfication of alphabetic order, remove unused define and
rename the define of register offset to individual patch
- add comment for MERGE ultra and preultra setting
Change in v6:
- adjust alphabetic order for mediatek-drm
- move the patch that add mt8195 support for mediatek-drm as
the lastest patch
- add MERGE define for const varriable
Change in v5:
- add power-domain property into vdosys0 and vdosys1 dts node.
- add MT8195 prifix and remove unused VDO1 define in mt8195-mmsys.h
Change in v4:
- extract dt-binding patches to another patch series
- squash DSC module into mtk_drm_ddp_comp.c
- add coment and simplify MERGE config function
Change in v3:
- change mmsys and display dt-bindings document from txt to yaml
- add MERGE additional description in display dt-bindings document
- fix mboxes-cells number of vdosys0 node in dts
- drop mutex eof convert define
- remove pm_runtime apis in DSC and MERGE
- change DSC and MERGE enum to alphabetic order
Change in v2:
- add DSC yaml file
- add mt8195 drm driver porting parts in to one patch
- remove useless define, variable, structure member and function
- simplify DSC and MERGE file and switch threre order
jason-jh.lin (8):
soc: mediatek: add mtk-mmsys support for mt8195 vdosys0
soc: mediatek: add mtk-mutex support for mt8195 vdosys0
drm/mediatek: add DSC support for mediatek-drm
drm/mediatek: add MERGE support for mediatek-drm
drm/mediatek: add mediatek-drm of vdosys0 support for mt8195
soc: mediatek: add DDP_DOMPONENT_DITHER0 enum for mt8195 vdosys0
drm/mediatek: add suffix 0 to DDP_COMPONENT_DITHER for mt8195 vdosys0
soc: mediatek: remove DDP_DOMPONENT_DITHER from enum
drivers/gpu/drm/mediatek/Makefile | 1 +
drivers/gpu/drm/mediatek/mtk_disp_drv.h | 8 +
drivers/gpu/drm/mediatek/mtk_disp_merge.c | 246 +++++++++++++
drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 6 +
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 65 +++-
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 2 +
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 151 +++++++-
drivers/gpu/drm/mediatek/mtk_drm_drv.h | 7 +
drivers/soc/mediatek/mt8167-mmsys.h | 2 +-
drivers/soc/mediatek/mt8183-mmsys.h | 2 +-
drivers/soc/mediatek/mt8186-mmsys.h | 4 +-
drivers/soc/mediatek/mt8192-mmsys.h | 4 +-
drivers/soc/mediatek/mt8195-mmsys.h | 370 ++++++++++++++++++++
drivers/soc/mediatek/mt8365-mmsys.h | 4 +-
drivers/soc/mediatek/mtk-mmsys.c | 152 +++++++-
drivers/soc/mediatek/mtk-mmsys.h | 6 +
drivers/soc/mediatek/mtk-mutex.c | 95 ++++-
include/linux/soc/mediatek/mtk-mmsys.h | 13 +-
18 files changed, 1098 insertions(+), 40 deletions(-)
create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_merge.c
create mode 100644 drivers/soc/mediatek/mt8195-mmsys.h
--
2.18.0
^ permalink raw reply [flat|nested] 110+ messages in thread
* [PATCH v20 0/8] Add Mediatek Soc DRM (vdosys0) support for mt8195
@ 2022-04-19 9:41 ` jason-jh.lin
0 siblings, 0 replies; 110+ messages in thread
From: jason-jh.lin @ 2022-04-19 9:41 UTC (permalink / raw)
To: Matthias Brugger, Chun-Kuang Hu, AngeloGioacchino Del Regno
Cc: CK Hu, Jason-JH Lin, Nancy Lin, Singo Chang, devicetree,
linux-kernel, dri-devel, linux-mediatek, linux-arm-kernel,
Project_Global_Chrome_Upstream_Group, jason-jhlin
From: jason-jhlin <jason-jh.lin@mediatek.corp-partner.google.com>
Change in v20:
- split binding patch to another series 'MediaTek MT8195 display binding':
https://patchwork.ozlabs.org/project/devicetree-bindings/list/?series=295669
- fix io_start type from u32 to resource_size_t
- fix some commit message for DITHER enum
Change in v19:
- fix checking condition for the return vaule of platform resource
- drm/mediatek fix build waning for [-Wunused-const-variable]
Change in v18:
- change get driver data by io_start and wrap mmsys driver data into
mmsys match data structure to support identifying multi mmsys driver
data with the same compatible name
- change DDP_COMPONENT_DITHER to DDP_CONPONENT_DITHER0
Change in v17:
- change compatible name from 2 vdosys to 1 mmsys
- add get driver data by clk name function to get corresponding
driver data for mt8195 vdosys0
- add all routing table setting for mt8195 vdosys0
- remove useless mutex define
Change in v16:
- rebase on linu-next tag: 'next-20220303'
- rebase on series: 'Fix MediaTek display dt-bindings issues'
Change in v15:
- remove mt8195-mmsys.h comment for mux settings
- define the mask macro to replace using value as mask
to fix zero mask problem
- add EOF setting comment for MUTEX sof register
Change in v14:
- rebase on mediatek-drm-next-5.17
- rebase on "Add mmsys and mutex support for MDP" series
- rebase on "media: mediatek: support mdp3 on mt8183 platform" series
Change in v13:
- remove dts patch
- rebase on kernel-5.16-rc1
- rebase on mediatek-drm-next
Change in v12:
- add clock-names property to merge yaml
- using BIT(nr) macro to define the settings of mmsys routing table
- fix clk_get and clk_prepare_enable error handling issue
Change in v11:
- rebase on kernel-5.15-rc1
- change mbox label to gce0 for dts node of vdosys0
- change ovl compatibale to mt8192 to set smi_id_en=true in driver data
- move common module from display folder to common folder,
such as AAL, COCLOR, CCORR and MUTEX
Change in v10:
- rebase on "drm/mediatek: add support for mediatek SOC MT8192" series
- rebase on "soc: mediatek: mmsys: add mt8192 mmsys support" series
- fix some typo and "mediatek" start with capital in every dt-bindings
- move mutex yaml from dfisplay folder to soc folder
- separate merge additional propoerties to an individual dt-bindings patch
Change in v9:
- separate power and gce properties of mmsys into another dt-binding patch
- rebase on "Separate aal module" series
- keep mtk_ddp_clk_enable/disable in the same place
- change mtk_dsc_start config register to mtk_drm_ddp_write_mask
- remove the 0 setting of merge fifo config function
- add CCORR driver data for mt8195
Change in v8:
- add DP_INTF0 mux into mmsys routing table
- add DP_INTF0 mutex mod and enum into add/remove comp function
- remove bypass DSC enum in mtk_ddp_comp_init
Change in v7:
- add dt=binding of mmsys and disp path into this series
- separate th modidfication of alphabetic order, remove unused define and
rename the define of register offset to individual patch
- add comment for MERGE ultra and preultra setting
Change in v6:
- adjust alphabetic order for mediatek-drm
- move the patch that add mt8195 support for mediatek-drm as
the lastest patch
- add MERGE define for const varriable
Change in v5:
- add power-domain property into vdosys0 and vdosys1 dts node.
- add MT8195 prifix and remove unused VDO1 define in mt8195-mmsys.h
Change in v4:
- extract dt-binding patches to another patch series
- squash DSC module into mtk_drm_ddp_comp.c
- add coment and simplify MERGE config function
Change in v3:
- change mmsys and display dt-bindings document from txt to yaml
- add MERGE additional description in display dt-bindings document
- fix mboxes-cells number of vdosys0 node in dts
- drop mutex eof convert define
- remove pm_runtime apis in DSC and MERGE
- change DSC and MERGE enum to alphabetic order
Change in v2:
- add DSC yaml file
- add mt8195 drm driver porting parts in to one patch
- remove useless define, variable, structure member and function
- simplify DSC and MERGE file and switch threre order
jason-jh.lin (8):
soc: mediatek: add mtk-mmsys support for mt8195 vdosys0
soc: mediatek: add mtk-mutex support for mt8195 vdosys0
drm/mediatek: add DSC support for mediatek-drm
drm/mediatek: add MERGE support for mediatek-drm
drm/mediatek: add mediatek-drm of vdosys0 support for mt8195
soc: mediatek: add DDP_DOMPONENT_DITHER0 enum for mt8195 vdosys0
drm/mediatek: add suffix 0 to DDP_COMPONENT_DITHER for mt8195 vdosys0
soc: mediatek: remove DDP_DOMPONENT_DITHER from enum
drivers/gpu/drm/mediatek/Makefile | 1 +
drivers/gpu/drm/mediatek/mtk_disp_drv.h | 8 +
drivers/gpu/drm/mediatek/mtk_disp_merge.c | 246 +++++++++++++
drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 6 +
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 65 +++-
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 2 +
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 151 +++++++-
drivers/gpu/drm/mediatek/mtk_drm_drv.h | 7 +
drivers/soc/mediatek/mt8167-mmsys.h | 2 +-
drivers/soc/mediatek/mt8183-mmsys.h | 2 +-
drivers/soc/mediatek/mt8186-mmsys.h | 4 +-
drivers/soc/mediatek/mt8192-mmsys.h | 4 +-
drivers/soc/mediatek/mt8195-mmsys.h | 370 ++++++++++++++++++++
drivers/soc/mediatek/mt8365-mmsys.h | 4 +-
drivers/soc/mediatek/mtk-mmsys.c | 152 +++++++-
drivers/soc/mediatek/mtk-mmsys.h | 6 +
drivers/soc/mediatek/mtk-mutex.c | 95 ++++-
include/linux/soc/mediatek/mtk-mmsys.h | 13 +-
18 files changed, 1098 insertions(+), 40 deletions(-)
create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_merge.c
create mode 100644 drivers/soc/mediatek/mt8195-mmsys.h
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 110+ messages in thread
* [PATCH v20 0/8] Add Mediatek Soc DRM (vdosys0) support for mt8195
@ 2022-04-19 9:41 ` jason-jh.lin
0 siblings, 0 replies; 110+ messages in thread
From: jason-jh.lin @ 2022-04-19 9:41 UTC (permalink / raw)
To: Matthias Brugger, Chun-Kuang Hu, AngeloGioacchino Del Regno
Cc: CK Hu, Jason-JH Lin, Nancy Lin, Singo Chang, devicetree,
linux-kernel, dri-devel, linux-mediatek, linux-arm-kernel,
Project_Global_Chrome_Upstream_Group, jason-jhlin
From: jason-jhlin <jason-jh.lin@mediatek.corp-partner.google.com>
Change in v20:
- split binding patch to another series 'MediaTek MT8195 display binding':
https://patchwork.ozlabs.org/project/devicetree-bindings/list/?series=295669
- fix io_start type from u32 to resource_size_t
- fix some commit message for DITHER enum
Change in v19:
- fix checking condition for the return vaule of platform resource
- drm/mediatek fix build waning for [-Wunused-const-variable]
Change in v18:
- change get driver data by io_start and wrap mmsys driver data into
mmsys match data structure to support identifying multi mmsys driver
data with the same compatible name
- change DDP_COMPONENT_DITHER to DDP_CONPONENT_DITHER0
Change in v17:
- change compatible name from 2 vdosys to 1 mmsys
- add get driver data by clk name function to get corresponding
driver data for mt8195 vdosys0
- add all routing table setting for mt8195 vdosys0
- remove useless mutex define
Change in v16:
- rebase on linu-next tag: 'next-20220303'
- rebase on series: 'Fix MediaTek display dt-bindings issues'
Change in v15:
- remove mt8195-mmsys.h comment for mux settings
- define the mask macro to replace using value as mask
to fix zero mask problem
- add EOF setting comment for MUTEX sof register
Change in v14:
- rebase on mediatek-drm-next-5.17
- rebase on "Add mmsys and mutex support for MDP" series
- rebase on "media: mediatek: support mdp3 on mt8183 platform" series
Change in v13:
- remove dts patch
- rebase on kernel-5.16-rc1
- rebase on mediatek-drm-next
Change in v12:
- add clock-names property to merge yaml
- using BIT(nr) macro to define the settings of mmsys routing table
- fix clk_get and clk_prepare_enable error handling issue
Change in v11:
- rebase on kernel-5.15-rc1
- change mbox label to gce0 for dts node of vdosys0
- change ovl compatibale to mt8192 to set smi_id_en=true in driver data
- move common module from display folder to common folder,
such as AAL, COCLOR, CCORR and MUTEX
Change in v10:
- rebase on "drm/mediatek: add support for mediatek SOC MT8192" series
- rebase on "soc: mediatek: mmsys: add mt8192 mmsys support" series
- fix some typo and "mediatek" start with capital in every dt-bindings
- move mutex yaml from dfisplay folder to soc folder
- separate merge additional propoerties to an individual dt-bindings patch
Change in v9:
- separate power and gce properties of mmsys into another dt-binding patch
- rebase on "Separate aal module" series
- keep mtk_ddp_clk_enable/disable in the same place
- change mtk_dsc_start config register to mtk_drm_ddp_write_mask
- remove the 0 setting of merge fifo config function
- add CCORR driver data for mt8195
Change in v8:
- add DP_INTF0 mux into mmsys routing table
- add DP_INTF0 mutex mod and enum into add/remove comp function
- remove bypass DSC enum in mtk_ddp_comp_init
Change in v7:
- add dt=binding of mmsys and disp path into this series
- separate th modidfication of alphabetic order, remove unused define and
rename the define of register offset to individual patch
- add comment for MERGE ultra and preultra setting
Change in v6:
- adjust alphabetic order for mediatek-drm
- move the patch that add mt8195 support for mediatek-drm as
the lastest patch
- add MERGE define for const varriable
Change in v5:
- add power-domain property into vdosys0 and vdosys1 dts node.
- add MT8195 prifix and remove unused VDO1 define in mt8195-mmsys.h
Change in v4:
- extract dt-binding patches to another patch series
- squash DSC module into mtk_drm_ddp_comp.c
- add coment and simplify MERGE config function
Change in v3:
- change mmsys and display dt-bindings document from txt to yaml
- add MERGE additional description in display dt-bindings document
- fix mboxes-cells number of vdosys0 node in dts
- drop mutex eof convert define
- remove pm_runtime apis in DSC and MERGE
- change DSC and MERGE enum to alphabetic order
Change in v2:
- add DSC yaml file
- add mt8195 drm driver porting parts in to one patch
- remove useless define, variable, structure member and function
- simplify DSC and MERGE file and switch threre order
jason-jh.lin (8):
soc: mediatek: add mtk-mmsys support for mt8195 vdosys0
soc: mediatek: add mtk-mutex support for mt8195 vdosys0
drm/mediatek: add DSC support for mediatek-drm
drm/mediatek: add MERGE support for mediatek-drm
drm/mediatek: add mediatek-drm of vdosys0 support for mt8195
soc: mediatek: add DDP_DOMPONENT_DITHER0 enum for mt8195 vdosys0
drm/mediatek: add suffix 0 to DDP_COMPONENT_DITHER for mt8195 vdosys0
soc: mediatek: remove DDP_DOMPONENT_DITHER from enum
drivers/gpu/drm/mediatek/Makefile | 1 +
drivers/gpu/drm/mediatek/mtk_disp_drv.h | 8 +
drivers/gpu/drm/mediatek/mtk_disp_merge.c | 246 +++++++++++++
drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 6 +
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 65 +++-
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 2 +
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 151 +++++++-
drivers/gpu/drm/mediatek/mtk_drm_drv.h | 7 +
drivers/soc/mediatek/mt8167-mmsys.h | 2 +-
drivers/soc/mediatek/mt8183-mmsys.h | 2 +-
drivers/soc/mediatek/mt8186-mmsys.h | 4 +-
drivers/soc/mediatek/mt8192-mmsys.h | 4 +-
drivers/soc/mediatek/mt8195-mmsys.h | 370 ++++++++++++++++++++
drivers/soc/mediatek/mt8365-mmsys.h | 4 +-
drivers/soc/mediatek/mtk-mmsys.c | 152 +++++++-
drivers/soc/mediatek/mtk-mmsys.h | 6 +
drivers/soc/mediatek/mtk-mutex.c | 95 ++++-
include/linux/soc/mediatek/mtk-mmsys.h | 13 +-
18 files changed, 1098 insertions(+), 40 deletions(-)
create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_merge.c
create mode 100644 drivers/soc/mediatek/mt8195-mmsys.h
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 110+ messages in thread
* [PATCH v20 1/8] soc: mediatek: add mtk-mmsys support for mt8195 vdosys0
2022-04-19 9:41 ` jason-jh.lin
(?)
@ 2022-04-19 9:41 ` jason-jh.lin
-1 siblings, 0 replies; 110+ messages in thread
From: jason-jh.lin @ 2022-04-19 9:41 UTC (permalink / raw)
To: Matthias Brugger, Chun-Kuang Hu, AngeloGioacchino Del Regno
Cc: devicetree, Jason-JH Lin, Singo Chang, linux-kernel, dri-devel,
Project_Global_Chrome_Upstream_Group, Nancy Lin, linux-mediatek,
linux-arm-kernel
1. Add mt8195 mmsys compatible for 2 vdosys.
2. Add io_start into each driver data of mt8195 vdosys.
3. Add get match data function to identify mmsys by io_start.
4. Add mt8195 routing table settings of vdosys0.
Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
Based on series [1]
[1] MediaTek MT8195 display binding
- https://patchwork.ozlabs.org/project/devicetree-bindings/list/?series=295669
---
drivers/soc/mediatek/mt8195-mmsys.h | 370 +++++++++++++++++++++++++
drivers/soc/mediatek/mtk-mmsys.c | 152 +++++++++-
drivers/soc/mediatek/mtk-mmsys.h | 6 +
include/linux/soc/mediatek/mtk-mmsys.h | 11 +
4 files changed, 528 insertions(+), 11 deletions(-)
create mode 100644 drivers/soc/mediatek/mt8195-mmsys.h
diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h
new file mode 100644
index 000000000000..13ab0ab64396
--- /dev/null
+++ b/drivers/soc/mediatek/mt8195-mmsys.h
@@ -0,0 +1,370 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __SOC_MEDIATEK_MT8195_MMSYS_H
+#define __SOC_MEDIATEK_MT8195_MMSYS_H
+
+#define MT8195_VDO0_OVL_MOUT_EN 0xf14
+#define MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0 BIT(0)
+#define MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0 BIT(1)
+#define MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1 BIT(2)
+#define MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1 BIT(4)
+#define MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1 BIT(5)
+#define MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0 BIT(6)
+
+#define MT8195_VDO0_SEL_IN 0xf34
+#define MT8195_SEL_IN_VPP_MERGE_FROM_MASK GENMASK(1, 0)
+#define MT8195_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT (0 << 0)
+#define MT8195_SEL_IN_VPP_MERGE_FROM_DISP_DITHER1 (1 << 0)
+#define MT8195_SEL_IN_VPP_MERGE_FROM_VDO1_VIRTUAL0 (2 << 0)
+#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK GENMASK(4, 4)
+#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0 (0 << 4)
+#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_VPP_MERGE (1 << 4)
+#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_MASK GENMASK(5, 5)
+#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_DISP_DITHER1 (0 << 5)
+#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_VPP_MERGE (1 << 5)
+#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK GENMASK(8, 8)
+#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE (0 << 8)
+#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT (1 << 8)
+#define MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK GENMASK(9, 9)
+#define MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT (0 << 9)
+#define MT8195_SEL_IN_DP_INTF0_FROM_MASK GENMASK(13, 12)
+#define MT8195_SEL_IN_DP_INTF0_FROM_DSC_WRAP1_OUT (0 << 0)
+#define MT8195_SEL_IN_DP_INTF0_FROM_VPP_MERGE (1 << 12)
+#define MT8195_SEL_IN_DP_INTF0_FROM_VDO1_VIRTUAL0 (2 << 12)
+#define MT8195_SEL_IN_DSI0_FROM_MASK GENMASK(16, 16)
+#define MT8195_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT (0 << 16)
+#define MT8195_SEL_IN_DSI0_FROM_DISP_DITHER0 (1 << 16)
+#define MT8195_SEL_IN_DSI1_FROM_MASK GENMASK(17, 17)
+#define MT8195_SEL_IN_DSI1_FROM_DSC_WRAP1_OUT (0 << 17)
+#define MT8195_SEL_IN_DSI1_FROM_VPP_MERGE (1 << 17)
+#define MT8195_SEL_IN_DISP_WDMA1_FROM_MASK GENMASK(20, 20)
+#define MT8195_SEL_IN_DISP_WDMA1_FROM_DISP_OVL1 (0 << 20)
+#define MT8195_SEL_IN_DISP_WDMA1_FROM_VPP_MERGE (1 << 20)
+#define MT8195_SEL_IN_DSC_WRAP1_FROM_MASK GENMASK(21, 21)
+#define MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN (0 << 21)
+#define MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1 (1 << 21)
+#define MT8195_SEL_IN_DISP_WDMA0_FROM_MASK GENMASK(22, 22)
+#define MT8195_SEL_IN_DISP_WDMA0_FROM_DISP_OVL0 (0 << 22)
+
+#define MT8195_VDO0_SEL_OUT 0xf38
+#define MT8195_SOUT_DISP_DITHER0_TO_MASK BIT(0)
+#define MT8195_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN (0 << 0)
+#define MT8195_SOUT_DISP_DITHER0_TO_DSI0 (1 << 0)
+#define MT8195_SOUT_DISP_DITHER1_TO_MASK GENMASK(2, 1)
+#define MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_IN (0 << 1)
+#define MT8195_SOUT_DISP_DITHER1_TO_VPP_MERGE (1 << 1)
+#define MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT (2 << 1)
+#define MT8195_SOUT_VDO1_VIRTUAL0_TO_MASK GENMASK(4, 4)
+#define MT8195_SOUT_VDO1_VIRTUAL0_TO_VPP_MERGE (0 << 4)
+#define MT8195_SOUT_VDO1_VIRTUAL0_TO_DP_INTF0 (1 << 4)
+#define MT8195_SOUT_VPP_MERGE_TO_MASK GENMASK(10, 8)
+#define MT8195_SOUT_VPP_MERGE_TO_DSI1 (0 << 8)
+#define MT8195_SOUT_VPP_MERGE_TO_DP_INTF0 (1 << 8)
+#define MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0 (2 << 8)
+#define MT8195_SOUT_VPP_MERGE_TO_DISP_WDMA1 (3 << 8)
+#define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP0_IN (4 << 8)
+#define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN_MASK GENMASK(11, 11)
+#define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN (0 << 11)
+#define MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK GENMASK(13, 12)
+#define MT8195_SOUT_DSC_WRAP0_OUT_TO_DSI0 (0 << 12)
+#define MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0 (1 << 12)
+#define MT8195_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE (2 << 12)
+#define MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK GENMASK(17, 16)
+#define MT8195_SOUT_DSC_WRAP1_OUT_TO_DSI1 (0 << 16)
+#define MT8195_SOUT_DSC_WRAP1_OUT_TO_DP_INTF0 (1 << 16)
+#define MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0 (2 << 16)
+#define MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE (3 << 16)
+
+static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
+ {
+ DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
+ MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0,
+ MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0
+ }, {
+ DDP_COMPONENT_OVL0, DDP_COMPONENT_WDMA0,
+ MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0,
+ MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0
+ }, {
+ DDP_COMPONENT_OVL0, DDP_COMPONENT_OVL1,
+ MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1,
+ MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1
+ }, {
+ DDP_COMPONENT_OVL1, DDP_COMPONENT_RDMA1,
+ MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1,
+ MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1
+ }, {
+ DDP_COMPONENT_OVL1, DDP_COMPONENT_WDMA1,
+ MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1,
+ MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1
+ }, {
+ DDP_COMPONENT_OVL1, DDP_COMPONENT_OVL0,
+ MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0,
+ MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0
+ }, {
+ DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK,
+ MT8195_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT
+ }, {
+ DDP_COMPONENT_DITHER1, DDP_COMPONENT_MERGE0,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK,
+ MT8195_SEL_IN_VPP_MERGE_FROM_DISP_DITHER1
+ }, {
+ DDP_COMPONENT_MERGE5, DDP_COMPONENT_MERGE0,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK,
+ MT8195_SEL_IN_VPP_MERGE_FROM_VDO1_VIRTUAL0
+ }, {
+ DDP_COMPONENT_DITHER, DDP_COMPONENT_DSC0,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK,
+ MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0
+ }, {
+ DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC0,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK,
+ MT8195_SEL_IN_DSC_WRAP0_IN_FROM_VPP_MERGE
+ }, {
+ DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSC1,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_IN_FROM_MASK,
+ MT8195_SEL_IN_DSC_WRAP1_IN_FROM_DISP_DITHER1
+ }, {
+ DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC1,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_IN_FROM_MASK,
+ MT8195_SEL_IN_DSC_WRAP1_IN_FROM_VPP_MERGE
+ }, {
+ DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF1,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
+ MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE
+ }, {
+ DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI0,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
+ MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE
+ }, {
+ DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI1,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
+ MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE
+ }, {
+ DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF1,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
+ MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT
+ }, {
+ DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI0,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
+ MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT
+ }, {
+ DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI1,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
+ MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT
+ }, {
+ DDP_COMPONENT_DSC0, DDP_COMPONENT_DP_INTF1,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK,
+ MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT
+ }, {
+ DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI0,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK,
+ MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT
+ }, {
+ DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI1,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK,
+ MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT
+ }, {
+ DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF0,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_MASK,
+ MT8195_SEL_IN_DP_INTF0_FROM_DSC_WRAP1_OUT
+ }, {
+ DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF0,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_MASK,
+ MT8195_SEL_IN_DP_INTF0_FROM_VPP_MERGE
+ }, {
+ DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF0,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_MASK,
+ MT8195_SEL_IN_DP_INTF0_FROM_VDO1_VIRTUAL0
+ }, {
+ DDP_COMPONENT_DSC0, DDP_COMPONENT_DSI0,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI0_FROM_MASK,
+ MT8195_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT
+ }, {
+ DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI0_FROM_MASK,
+ MT8195_SEL_IN_DSI0_FROM_DISP_DITHER0
+ }, {
+ DDP_COMPONENT_DSC1, DDP_COMPONENT_DSI1,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI1_FROM_MASK,
+ MT8195_SEL_IN_DSI1_FROM_DSC_WRAP1_OUT
+ }, {
+ DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSI1,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI1_FROM_MASK,
+ MT8195_SEL_IN_DSI1_FROM_VPP_MERGE
+ }, {
+ DDP_COMPONENT_OVL1, DDP_COMPONENT_WDMA1,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA1_FROM_MASK,
+ MT8195_SEL_IN_DISP_WDMA1_FROM_DISP_OVL1
+ }, {
+ DDP_COMPONENT_MERGE0, DDP_COMPONENT_WDMA1,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA1_FROM_MASK,
+ MT8195_SEL_IN_DISP_WDMA1_FROM_VPP_MERGE
+ }, {
+ DDP_COMPONENT_DSC1, DDP_COMPONENT_DSI1,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
+ MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
+ }, {
+ DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF0,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
+ MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
+ }, {
+ DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF1,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
+ MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
+ }, {
+ DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI0,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
+ MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
+ }, {
+ DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI1,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
+ MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
+ }, {
+ DDP_COMPONENT_DSC1, DDP_COMPONENT_MERGE0,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
+ MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
+ }, {
+ DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSI1,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
+ MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1
+ }, {
+ DDP_COMPONENT_DITHER1, DDP_COMPONENT_DP_INTF0,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
+ MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1
+ }, {
+ DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI0,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
+ MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1
+ }, {
+ DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI1,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
+ MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1
+ }, {
+ DDP_COMPONENT_OVL0, DDP_COMPONENT_WDMA0,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA0_FROM_MASK,
+ MT8195_SEL_IN_DISP_WDMA0_FROM_DISP_OVL0
+ }, {
+ DDP_COMPONENT_DITHER, DDP_COMPONENT_DSC0,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER0_TO_MASK,
+ MT8195_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN
+ }, {
+ DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER0_TO_MASK,
+ MT8195_SOUT_DISP_DITHER0_TO_DSI0
+ }, {
+ DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSC1,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
+ MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_IN
+ }, {
+ DDP_COMPONENT_DITHER1, DDP_COMPONENT_MERGE0,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
+ MT8195_SOUT_DISP_DITHER1_TO_VPP_MERGE
+ }, {
+ DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSI1,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
+ MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT
+ }, {
+ DDP_COMPONENT_DITHER1, DDP_COMPONENT_DP_INTF0,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
+ MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT
+ }, {
+ DDP_COMPONENT_DITHER1, DDP_COMPONENT_DP_INTF1,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
+ MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT
+ }, {
+ DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI0,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
+ MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT
+ }, {
+ DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI1,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
+ MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT
+ }, {
+ DDP_COMPONENT_MERGE5, DDP_COMPONENT_MERGE0,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_VDO1_VIRTUAL0_TO_MASK,
+ MT8195_SOUT_VDO1_VIRTUAL0_TO_VPP_MERGE
+ }, {
+ DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF0,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_VDO1_VIRTUAL0_TO_MASK,
+ MT8195_SOUT_VDO1_VIRTUAL0_TO_DP_INTF0
+ }, {
+ DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSI1,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
+ MT8195_SOUT_VPP_MERGE_TO_DSI1
+ }, {
+ DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF0,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
+ MT8195_SOUT_VPP_MERGE_TO_DP_INTF0
+ }, {
+ DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF1,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
+ MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0
+ }, {
+ DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI0,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
+ MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0
+ }, {
+ DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI1,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
+ MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0
+ }, {
+ DDP_COMPONENT_MERGE0, DDP_COMPONENT_WDMA1,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
+ MT8195_SOUT_VPP_MERGE_TO_DISP_WDMA1
+ }, {
+ DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC0,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
+ MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP0_IN
+ }, {
+ DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC1,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN_MASK,
+ MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN
+ }, {
+ DDP_COMPONENT_DSC0, DDP_COMPONENT_DSI0,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
+ MT8195_SOUT_DSC_WRAP0_OUT_TO_DSI0
+ }, {
+ DDP_COMPONENT_DSC0, DDP_COMPONENT_DP_INTF1,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
+ MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0
+ }, {
+ DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI0,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
+ MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0
+ }, {
+ DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI1,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
+ MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0
+ }, {
+ DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
+ MT8195_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE
+ }, {
+ DDP_COMPONENT_DSC1, DDP_COMPONENT_DSI1,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
+ MT8195_SOUT_DSC_WRAP1_OUT_TO_DSI1
+ }, {
+ DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF0,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
+ MT8195_SOUT_DSC_WRAP1_OUT_TO_DP_INTF0
+ }, {
+ DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF1,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
+ MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0
+ }, {
+ DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI0,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
+ MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0
+ }, {
+ DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI1,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
+ MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0
+ }, {
+ DDP_COMPONENT_DSC1, DDP_COMPONENT_MERGE0,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
+ MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE
+ }
+};
+
+#endif /* __SOC_MEDIATEK_MT8195_MMSYS_H */
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index 4fc4c2c9ea20..548efed8dc1c 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -17,6 +17,7 @@
#include "mt8183-mmsys.h"
#include "mt8186-mmsys.h"
#include "mt8192-mmsys.h"
+#include "mt8195-mmsys.h"
#include "mt8365-mmsys.h"
static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
@@ -25,26 +26,61 @@ static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
.num_routes = ARRAY_SIZE(mmsys_default_routing_table),
};
+static const struct mtk_mmsys_match_data mt2701_mmsys_match_data = {
+ .num_drv_data = 1,
+ .drv_data = {
+ &mt2701_mmsys_driver_data,
+ },
+};
+
static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = {
.clk_driver = "clk-mt2712-mm",
.routes = mmsys_default_routing_table,
.num_routes = ARRAY_SIZE(mmsys_default_routing_table),
};
+static const struct mtk_mmsys_match_data mt2712_mmsys_match_data = {
+ .num_drv_data = 1,
+ .drv_data = {
+ &mt2712_mmsys_driver_data,
+ },
+};
+
static const struct mtk_mmsys_driver_data mt6779_mmsys_driver_data = {
.clk_driver = "clk-mt6779-mm",
};
+static const struct mtk_mmsys_match_data mt6779_mmsys_match_data = {
+ .num_drv_data = 1,
+ .drv_data = {
+ &mt6779_mmsys_driver_data,
+ },
+};
+
static const struct mtk_mmsys_driver_data mt6797_mmsys_driver_data = {
.clk_driver = "clk-mt6797-mm",
};
+static const struct mtk_mmsys_match_data mt6797_mmsys_match_data = {
+ .num_drv_data = 1,
+ .drv_data = {
+ &mt6797_mmsys_driver_data,
+ },
+};
+
static const struct mtk_mmsys_driver_data mt8167_mmsys_driver_data = {
.clk_driver = "clk-mt8167-mm",
.routes = mt8167_mmsys_routing_table,
.num_routes = ARRAY_SIZE(mt8167_mmsys_routing_table),
};
+static const struct mtk_mmsys_match_data mt8167_mmsys_match_data = {
+ .num_drv_data = 1,
+ .drv_data = {
+ &mt8167_mmsys_driver_data,
+ },
+};
+
static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
.clk_driver = "clk-mt8173-mm",
.routes = mmsys_default_routing_table,
@@ -52,6 +88,13 @@ static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
.sw0_rst_offset = MT8183_MMSYS_SW0_RST_B,
};
+static const struct mtk_mmsys_match_data mt8173_mmsys_match_data = {
+ .num_drv_data = 1,
+ .drv_data = {
+ &mt8173_mmsys_driver_data,
+ },
+};
+
static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
.clk_driver = "clk-mt8183-mm",
.routes = mmsys_mt8183_routing_table,
@@ -59,6 +102,13 @@ static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
.sw0_rst_offset = MT8183_MMSYS_SW0_RST_B,
};
+static const struct mtk_mmsys_match_data mt8183_mmsys_match_data = {
+ .num_drv_data = 1,
+ .drv_data = {
+ &mt8183_mmsys_driver_data,
+ },
+};
+
static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = {
.clk_driver = "clk-mt8186-mm",
.routes = mmsys_mt8186_routing_table,
@@ -66,25 +116,79 @@ static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = {
.sw0_rst_offset = MT8186_MMSYS_SW0_RST_B,
};
+static const struct mtk_mmsys_match_data mt8186_mmsys_match_data = {
+ .num_drv_data = 1,
+ .drv_data = {
+ &mt8186_mmsys_driver_data,
+ },
+};
+
static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
.clk_driver = "clk-mt8192-mm",
.routes = mmsys_mt8192_routing_table,
.num_routes = ARRAY_SIZE(mmsys_mt8192_routing_table),
};
+static const struct mtk_mmsys_match_data mt8192_mmsys_match_data = {
+ .num_drv_data = 1,
+ .drv_data = {
+ &mt8192_mmsys_driver_data,
+ },
+};
+
+static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = {
+ .io_start = 0x1c01a000,
+ .clk_driver = "clk-mt8195-vdo0",
+ .routes = mmsys_mt8195_routing_table,
+ .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
+};
+
+static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
+ .io_start = 0x1c100000,
+ .clk_driver = "clk-mt8195-vdo1",
+};
+
+static const struct mtk_mmsys_match_data mt8195_mmsys_match_data = {
+ .num_drv_data = 2,
+ .drv_data = {
+ &mt8195_vdosys0_driver_data,
+ &mt8195_vdosys1_driver_data,
+ },
+};
+
static const struct mtk_mmsys_driver_data mt8365_mmsys_driver_data = {
.clk_driver = "clk-mt8365-mm",
.routes = mt8365_mmsys_routing_table,
.num_routes = ARRAY_SIZE(mt8365_mmsys_routing_table),
};
+static const struct mtk_mmsys_match_data mt8365_mmsys_match_data = {
+ .num_drv_data = 1,
+ .drv_data = {
+ &mt8365_mmsys_driver_data,
+ },
+};
+
struct mtk_mmsys {
void __iomem *regs;
const struct mtk_mmsys_driver_data *data;
spinlock_t lock; /* protects mmsys_sw_rst_b reg */
struct reset_controller_dev rcdev;
+ phys_addr_t io_start;
};
+static int mtk_mmsys_find_match_drvdata(struct mtk_mmsys *mmsys,
+ const struct mtk_mmsys_match_data *match)
+{
+ int i;
+
+ for (i = 0; i < match->num_drv_data; i++)
+ if (mmsys->io_start == match->drv_data[i]->io_start)
+ return i;
+
+ return -EINVAL;
+}
+
void mtk_mmsys_ddp_connect(struct device *dev,
enum mtk_ddp_comp_id cur,
enum mtk_ddp_comp_id next)
@@ -179,7 +283,9 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
struct device *dev = &pdev->dev;
struct platform_device *clks;
struct platform_device *drm;
+ const struct mtk_mmsys_match_data *match_data;
struct mtk_mmsys *mmsys;
+ struct resource *res;
int ret;
mmsys = devm_kzalloc(dev, sizeof(*mmsys), GFP_KERNEL);
@@ -205,7 +311,27 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
return ret;
}
- mmsys->data = of_device_get_match_data(&pdev->dev);
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!res) {
+ dev_err(dev, "Couldn't get mmsys resource\n");
+ return -EINVAL;
+ }
+ mmsys->io_start = res->start;
+
+ match_data = of_device_get_match_data(dev);
+ if (match_data->num_drv_data > 1) {
+ /* This SoC has multiple mmsys channels */
+ ret = mtk_mmsys_find_match_drvdata(mmsys, match_data);
+ if (ret < 0) {
+ dev_err(dev, "Couldn't get match driver data\n");
+ return ret;
+ }
+ mmsys->data = match_data->drv_data[ret];
+ } else {
+ dev_dbg(dev, "Using single mmsys channel\n");
+ mmsys->data = match_data->drv_data[0];
+ }
+
platform_set_drvdata(pdev, mmsys);
clks = platform_device_register_data(&pdev->dev, mmsys->data->clk_driver,
@@ -226,43 +352,47 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
static const struct of_device_id of_match_mtk_mmsys[] = {
{
.compatible = "mediatek,mt2701-mmsys",
- .data = &mt2701_mmsys_driver_data,
+ .data = &mt2701_mmsys_match_data,
},
{
.compatible = "mediatek,mt2712-mmsys",
- .data = &mt2712_mmsys_driver_data,
+ .data = &mt2712_mmsys_match_data,
},
{
.compatible = "mediatek,mt6779-mmsys",
- .data = &mt6779_mmsys_driver_data,
+ .data = &mt6779_mmsys_match_data,
},
{
.compatible = "mediatek,mt6797-mmsys",
- .data = &mt6797_mmsys_driver_data,
+ .data = &mt6797_mmsys_match_data,
},
{
.compatible = "mediatek,mt8167-mmsys",
- .data = &mt8167_mmsys_driver_data,
+ .data = &mt8167_mmsys_match_data,
},
{
.compatible = "mediatek,mt8173-mmsys",
- .data = &mt8173_mmsys_driver_data,
+ .data = &mt8173_mmsys_match_data,
},
{
.compatible = "mediatek,mt8183-mmsys",
- .data = &mt8183_mmsys_driver_data,
+ .data = &mt8183_mmsys_match_data,
},
{
.compatible = "mediatek,mt8186-mmsys",
- .data = &mt8186_mmsys_driver_data,
+ .data = &mt8186_mmsys_match_data,
},
{
.compatible = "mediatek,mt8192-mmsys",
- .data = &mt8192_mmsys_driver_data,
+ .data = &mt8192_mmsys_match_data,
+ },
+ {
+ .compatible = "mediatek,mt8195-mmsys",
+ .data = &mt8195_mmsys_match_data,
},
{
.compatible = "mediatek,mt8365-mmsys",
- .data = &mt8365_mmsys_driver_data,
+ .data = &mt8365_mmsys_match_data,
},
{ }
};
diff --git a/drivers/soc/mediatek/mtk-mmsys.h b/drivers/soc/mediatek/mtk-mmsys.h
index 77f37f8c715b..f01ba206481d 100644
--- a/drivers/soc/mediatek/mtk-mmsys.h
+++ b/drivers/soc/mediatek/mtk-mmsys.h
@@ -87,12 +87,18 @@ struct mtk_mmsys_routes {
};
struct mtk_mmsys_driver_data {
+ const resource_size_t io_start;
const char *clk_driver;
const struct mtk_mmsys_routes *routes;
const unsigned int num_routes;
const u16 sw0_rst_offset;
};
+struct mtk_mmsys_match_data {
+ unsigned short num_drv_data;
+ const struct mtk_mmsys_driver_data *drv_data[];
+};
+
/*
* Routes in mt8173, mt2701, mt2712 are different. That means
* in the same register address, it controls different input/output
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
index 4bba275e235a..cff5c9adbf46 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -17,13 +17,24 @@ enum mtk_ddp_comp_id {
DDP_COMPONENT_COLOR0,
DDP_COMPONENT_COLOR1,
DDP_COMPONENT_DITHER,
+ DDP_COMPONENT_DITHER1,
+ DDP_COMPONENT_DP_INTF0,
+ DDP_COMPONENT_DP_INTF1,
DDP_COMPONENT_DPI0,
DDP_COMPONENT_DPI1,
+ DDP_COMPONENT_DSC0,
+ DDP_COMPONENT_DSC1,
DDP_COMPONENT_DSI0,
DDP_COMPONENT_DSI1,
DDP_COMPONENT_DSI2,
DDP_COMPONENT_DSI3,
DDP_COMPONENT_GAMMA,
+ DDP_COMPONENT_MERGE0,
+ DDP_COMPONENT_MERGE1,
+ DDP_COMPONENT_MERGE2,
+ DDP_COMPONENT_MERGE3,
+ DDP_COMPONENT_MERGE4,
+ DDP_COMPONENT_MERGE5,
DDP_COMPONENT_OD0,
DDP_COMPONENT_OD1,
DDP_COMPONENT_OVL0,
--
2.18.0
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [PATCH v20 1/8] soc: mediatek: add mtk-mmsys support for mt8195 vdosys0
@ 2022-04-19 9:41 ` jason-jh.lin
0 siblings, 0 replies; 110+ messages in thread
From: jason-jh.lin @ 2022-04-19 9:41 UTC (permalink / raw)
To: Matthias Brugger, Chun-Kuang Hu, AngeloGioacchino Del Regno
Cc: CK Hu, Jason-JH Lin, Nancy Lin, Singo Chang, devicetree,
linux-kernel, dri-devel, linux-mediatek, linux-arm-kernel,
Project_Global_Chrome_Upstream_Group
1. Add mt8195 mmsys compatible for 2 vdosys.
2. Add io_start into each driver data of mt8195 vdosys.
3. Add get match data function to identify mmsys by io_start.
4. Add mt8195 routing table settings of vdosys0.
Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
Based on series [1]
[1] MediaTek MT8195 display binding
- https://patchwork.ozlabs.org/project/devicetree-bindings/list/?series=295669
---
drivers/soc/mediatek/mt8195-mmsys.h | 370 +++++++++++++++++++++++++
drivers/soc/mediatek/mtk-mmsys.c | 152 +++++++++-
drivers/soc/mediatek/mtk-mmsys.h | 6 +
include/linux/soc/mediatek/mtk-mmsys.h | 11 +
4 files changed, 528 insertions(+), 11 deletions(-)
create mode 100644 drivers/soc/mediatek/mt8195-mmsys.h
diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h
new file mode 100644
index 000000000000..13ab0ab64396
--- /dev/null
+++ b/drivers/soc/mediatek/mt8195-mmsys.h
@@ -0,0 +1,370 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __SOC_MEDIATEK_MT8195_MMSYS_H
+#define __SOC_MEDIATEK_MT8195_MMSYS_H
+
+#define MT8195_VDO0_OVL_MOUT_EN 0xf14
+#define MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0 BIT(0)
+#define MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0 BIT(1)
+#define MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1 BIT(2)
+#define MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1 BIT(4)
+#define MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1 BIT(5)
+#define MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0 BIT(6)
+
+#define MT8195_VDO0_SEL_IN 0xf34
+#define MT8195_SEL_IN_VPP_MERGE_FROM_MASK GENMASK(1, 0)
+#define MT8195_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT (0 << 0)
+#define MT8195_SEL_IN_VPP_MERGE_FROM_DISP_DITHER1 (1 << 0)
+#define MT8195_SEL_IN_VPP_MERGE_FROM_VDO1_VIRTUAL0 (2 << 0)
+#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK GENMASK(4, 4)
+#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0 (0 << 4)
+#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_VPP_MERGE (1 << 4)
+#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_MASK GENMASK(5, 5)
+#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_DISP_DITHER1 (0 << 5)
+#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_VPP_MERGE (1 << 5)
+#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK GENMASK(8, 8)
+#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE (0 << 8)
+#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT (1 << 8)
+#define MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK GENMASK(9, 9)
+#define MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT (0 << 9)
+#define MT8195_SEL_IN_DP_INTF0_FROM_MASK GENMASK(13, 12)
+#define MT8195_SEL_IN_DP_INTF0_FROM_DSC_WRAP1_OUT (0 << 0)
+#define MT8195_SEL_IN_DP_INTF0_FROM_VPP_MERGE (1 << 12)
+#define MT8195_SEL_IN_DP_INTF0_FROM_VDO1_VIRTUAL0 (2 << 12)
+#define MT8195_SEL_IN_DSI0_FROM_MASK GENMASK(16, 16)
+#define MT8195_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT (0 << 16)
+#define MT8195_SEL_IN_DSI0_FROM_DISP_DITHER0 (1 << 16)
+#define MT8195_SEL_IN_DSI1_FROM_MASK GENMASK(17, 17)
+#define MT8195_SEL_IN_DSI1_FROM_DSC_WRAP1_OUT (0 << 17)
+#define MT8195_SEL_IN_DSI1_FROM_VPP_MERGE (1 << 17)
+#define MT8195_SEL_IN_DISP_WDMA1_FROM_MASK GENMASK(20, 20)
+#define MT8195_SEL_IN_DISP_WDMA1_FROM_DISP_OVL1 (0 << 20)
+#define MT8195_SEL_IN_DISP_WDMA1_FROM_VPP_MERGE (1 << 20)
+#define MT8195_SEL_IN_DSC_WRAP1_FROM_MASK GENMASK(21, 21)
+#define MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN (0 << 21)
+#define MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1 (1 << 21)
+#define MT8195_SEL_IN_DISP_WDMA0_FROM_MASK GENMASK(22, 22)
+#define MT8195_SEL_IN_DISP_WDMA0_FROM_DISP_OVL0 (0 << 22)
+
+#define MT8195_VDO0_SEL_OUT 0xf38
+#define MT8195_SOUT_DISP_DITHER0_TO_MASK BIT(0)
+#define MT8195_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN (0 << 0)
+#define MT8195_SOUT_DISP_DITHER0_TO_DSI0 (1 << 0)
+#define MT8195_SOUT_DISP_DITHER1_TO_MASK GENMASK(2, 1)
+#define MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_IN (0 << 1)
+#define MT8195_SOUT_DISP_DITHER1_TO_VPP_MERGE (1 << 1)
+#define MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT (2 << 1)
+#define MT8195_SOUT_VDO1_VIRTUAL0_TO_MASK GENMASK(4, 4)
+#define MT8195_SOUT_VDO1_VIRTUAL0_TO_VPP_MERGE (0 << 4)
+#define MT8195_SOUT_VDO1_VIRTUAL0_TO_DP_INTF0 (1 << 4)
+#define MT8195_SOUT_VPP_MERGE_TO_MASK GENMASK(10, 8)
+#define MT8195_SOUT_VPP_MERGE_TO_DSI1 (0 << 8)
+#define MT8195_SOUT_VPP_MERGE_TO_DP_INTF0 (1 << 8)
+#define MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0 (2 << 8)
+#define MT8195_SOUT_VPP_MERGE_TO_DISP_WDMA1 (3 << 8)
+#define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP0_IN (4 << 8)
+#define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN_MASK GENMASK(11, 11)
+#define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN (0 << 11)
+#define MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK GENMASK(13, 12)
+#define MT8195_SOUT_DSC_WRAP0_OUT_TO_DSI0 (0 << 12)
+#define MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0 (1 << 12)
+#define MT8195_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE (2 << 12)
+#define MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK GENMASK(17, 16)
+#define MT8195_SOUT_DSC_WRAP1_OUT_TO_DSI1 (0 << 16)
+#define MT8195_SOUT_DSC_WRAP1_OUT_TO_DP_INTF0 (1 << 16)
+#define MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0 (2 << 16)
+#define MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE (3 << 16)
+
+static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
+ {
+ DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
+ MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0,
+ MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0
+ }, {
+ DDP_COMPONENT_OVL0, DDP_COMPONENT_WDMA0,
+ MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0,
+ MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0
+ }, {
+ DDP_COMPONENT_OVL0, DDP_COMPONENT_OVL1,
+ MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1,
+ MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1
+ }, {
+ DDP_COMPONENT_OVL1, DDP_COMPONENT_RDMA1,
+ MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1,
+ MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1
+ }, {
+ DDP_COMPONENT_OVL1, DDP_COMPONENT_WDMA1,
+ MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1,
+ MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1
+ }, {
+ DDP_COMPONENT_OVL1, DDP_COMPONENT_OVL0,
+ MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0,
+ MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0
+ }, {
+ DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK,
+ MT8195_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT
+ }, {
+ DDP_COMPONENT_DITHER1, DDP_COMPONENT_MERGE0,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK,
+ MT8195_SEL_IN_VPP_MERGE_FROM_DISP_DITHER1
+ }, {
+ DDP_COMPONENT_MERGE5, DDP_COMPONENT_MERGE0,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK,
+ MT8195_SEL_IN_VPP_MERGE_FROM_VDO1_VIRTUAL0
+ }, {
+ DDP_COMPONENT_DITHER, DDP_COMPONENT_DSC0,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK,
+ MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0
+ }, {
+ DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC0,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK,
+ MT8195_SEL_IN_DSC_WRAP0_IN_FROM_VPP_MERGE
+ }, {
+ DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSC1,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_IN_FROM_MASK,
+ MT8195_SEL_IN_DSC_WRAP1_IN_FROM_DISP_DITHER1
+ }, {
+ DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC1,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_IN_FROM_MASK,
+ MT8195_SEL_IN_DSC_WRAP1_IN_FROM_VPP_MERGE
+ }, {
+ DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF1,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
+ MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE
+ }, {
+ DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI0,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
+ MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE
+ }, {
+ DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI1,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
+ MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE
+ }, {
+ DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF1,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
+ MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT
+ }, {
+ DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI0,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
+ MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT
+ }, {
+ DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI1,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
+ MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT
+ }, {
+ DDP_COMPONENT_DSC0, DDP_COMPONENT_DP_INTF1,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK,
+ MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT
+ }, {
+ DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI0,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK,
+ MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT
+ }, {
+ DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI1,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK,
+ MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT
+ }, {
+ DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF0,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_MASK,
+ MT8195_SEL_IN_DP_INTF0_FROM_DSC_WRAP1_OUT
+ }, {
+ DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF0,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_MASK,
+ MT8195_SEL_IN_DP_INTF0_FROM_VPP_MERGE
+ }, {
+ DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF0,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_MASK,
+ MT8195_SEL_IN_DP_INTF0_FROM_VDO1_VIRTUAL0
+ }, {
+ DDP_COMPONENT_DSC0, DDP_COMPONENT_DSI0,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI0_FROM_MASK,
+ MT8195_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT
+ }, {
+ DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI0_FROM_MASK,
+ MT8195_SEL_IN_DSI0_FROM_DISP_DITHER0
+ }, {
+ DDP_COMPONENT_DSC1, DDP_COMPONENT_DSI1,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI1_FROM_MASK,
+ MT8195_SEL_IN_DSI1_FROM_DSC_WRAP1_OUT
+ }, {
+ DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSI1,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI1_FROM_MASK,
+ MT8195_SEL_IN_DSI1_FROM_VPP_MERGE
+ }, {
+ DDP_COMPONENT_OVL1, DDP_COMPONENT_WDMA1,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA1_FROM_MASK,
+ MT8195_SEL_IN_DISP_WDMA1_FROM_DISP_OVL1
+ }, {
+ DDP_COMPONENT_MERGE0, DDP_COMPONENT_WDMA1,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA1_FROM_MASK,
+ MT8195_SEL_IN_DISP_WDMA1_FROM_VPP_MERGE
+ }, {
+ DDP_COMPONENT_DSC1, DDP_COMPONENT_DSI1,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
+ MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
+ }, {
+ DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF0,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
+ MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
+ }, {
+ DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF1,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
+ MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
+ }, {
+ DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI0,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
+ MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
+ }, {
+ DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI1,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
+ MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
+ }, {
+ DDP_COMPONENT_DSC1, DDP_COMPONENT_MERGE0,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
+ MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
+ }, {
+ DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSI1,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
+ MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1
+ }, {
+ DDP_COMPONENT_DITHER1, DDP_COMPONENT_DP_INTF0,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
+ MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1
+ }, {
+ DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI0,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
+ MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1
+ }, {
+ DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI1,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
+ MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1
+ }, {
+ DDP_COMPONENT_OVL0, DDP_COMPONENT_WDMA0,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA0_FROM_MASK,
+ MT8195_SEL_IN_DISP_WDMA0_FROM_DISP_OVL0
+ }, {
+ DDP_COMPONENT_DITHER, DDP_COMPONENT_DSC0,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER0_TO_MASK,
+ MT8195_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN
+ }, {
+ DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER0_TO_MASK,
+ MT8195_SOUT_DISP_DITHER0_TO_DSI0
+ }, {
+ DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSC1,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
+ MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_IN
+ }, {
+ DDP_COMPONENT_DITHER1, DDP_COMPONENT_MERGE0,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
+ MT8195_SOUT_DISP_DITHER1_TO_VPP_MERGE
+ }, {
+ DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSI1,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
+ MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT
+ }, {
+ DDP_COMPONENT_DITHER1, DDP_COMPONENT_DP_INTF0,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
+ MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT
+ }, {
+ DDP_COMPONENT_DITHER1, DDP_COMPONENT_DP_INTF1,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
+ MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT
+ }, {
+ DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI0,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
+ MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT
+ }, {
+ DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI1,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
+ MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT
+ }, {
+ DDP_COMPONENT_MERGE5, DDP_COMPONENT_MERGE0,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_VDO1_VIRTUAL0_TO_MASK,
+ MT8195_SOUT_VDO1_VIRTUAL0_TO_VPP_MERGE
+ }, {
+ DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF0,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_VDO1_VIRTUAL0_TO_MASK,
+ MT8195_SOUT_VDO1_VIRTUAL0_TO_DP_INTF0
+ }, {
+ DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSI1,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
+ MT8195_SOUT_VPP_MERGE_TO_DSI1
+ }, {
+ DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF0,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
+ MT8195_SOUT_VPP_MERGE_TO_DP_INTF0
+ }, {
+ DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF1,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
+ MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0
+ }, {
+ DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI0,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
+ MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0
+ }, {
+ DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI1,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
+ MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0
+ }, {
+ DDP_COMPONENT_MERGE0, DDP_COMPONENT_WDMA1,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
+ MT8195_SOUT_VPP_MERGE_TO_DISP_WDMA1
+ }, {
+ DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC0,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
+ MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP0_IN
+ }, {
+ DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC1,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN_MASK,
+ MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN
+ }, {
+ DDP_COMPONENT_DSC0, DDP_COMPONENT_DSI0,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
+ MT8195_SOUT_DSC_WRAP0_OUT_TO_DSI0
+ }, {
+ DDP_COMPONENT_DSC0, DDP_COMPONENT_DP_INTF1,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
+ MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0
+ }, {
+ DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI0,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
+ MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0
+ }, {
+ DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI1,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
+ MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0
+ }, {
+ DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
+ MT8195_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE
+ }, {
+ DDP_COMPONENT_DSC1, DDP_COMPONENT_DSI1,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
+ MT8195_SOUT_DSC_WRAP1_OUT_TO_DSI1
+ }, {
+ DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF0,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
+ MT8195_SOUT_DSC_WRAP1_OUT_TO_DP_INTF0
+ }, {
+ DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF1,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
+ MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0
+ }, {
+ DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI0,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
+ MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0
+ }, {
+ DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI1,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
+ MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0
+ }, {
+ DDP_COMPONENT_DSC1, DDP_COMPONENT_MERGE0,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
+ MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE
+ }
+};
+
+#endif /* __SOC_MEDIATEK_MT8195_MMSYS_H */
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index 4fc4c2c9ea20..548efed8dc1c 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -17,6 +17,7 @@
#include "mt8183-mmsys.h"
#include "mt8186-mmsys.h"
#include "mt8192-mmsys.h"
+#include "mt8195-mmsys.h"
#include "mt8365-mmsys.h"
static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
@@ -25,26 +26,61 @@ static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
.num_routes = ARRAY_SIZE(mmsys_default_routing_table),
};
+static const struct mtk_mmsys_match_data mt2701_mmsys_match_data = {
+ .num_drv_data = 1,
+ .drv_data = {
+ &mt2701_mmsys_driver_data,
+ },
+};
+
static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = {
.clk_driver = "clk-mt2712-mm",
.routes = mmsys_default_routing_table,
.num_routes = ARRAY_SIZE(mmsys_default_routing_table),
};
+static const struct mtk_mmsys_match_data mt2712_mmsys_match_data = {
+ .num_drv_data = 1,
+ .drv_data = {
+ &mt2712_mmsys_driver_data,
+ },
+};
+
static const struct mtk_mmsys_driver_data mt6779_mmsys_driver_data = {
.clk_driver = "clk-mt6779-mm",
};
+static const struct mtk_mmsys_match_data mt6779_mmsys_match_data = {
+ .num_drv_data = 1,
+ .drv_data = {
+ &mt6779_mmsys_driver_data,
+ },
+};
+
static const struct mtk_mmsys_driver_data mt6797_mmsys_driver_data = {
.clk_driver = "clk-mt6797-mm",
};
+static const struct mtk_mmsys_match_data mt6797_mmsys_match_data = {
+ .num_drv_data = 1,
+ .drv_data = {
+ &mt6797_mmsys_driver_data,
+ },
+};
+
static const struct mtk_mmsys_driver_data mt8167_mmsys_driver_data = {
.clk_driver = "clk-mt8167-mm",
.routes = mt8167_mmsys_routing_table,
.num_routes = ARRAY_SIZE(mt8167_mmsys_routing_table),
};
+static const struct mtk_mmsys_match_data mt8167_mmsys_match_data = {
+ .num_drv_data = 1,
+ .drv_data = {
+ &mt8167_mmsys_driver_data,
+ },
+};
+
static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
.clk_driver = "clk-mt8173-mm",
.routes = mmsys_default_routing_table,
@@ -52,6 +88,13 @@ static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
.sw0_rst_offset = MT8183_MMSYS_SW0_RST_B,
};
+static const struct mtk_mmsys_match_data mt8173_mmsys_match_data = {
+ .num_drv_data = 1,
+ .drv_data = {
+ &mt8173_mmsys_driver_data,
+ },
+};
+
static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
.clk_driver = "clk-mt8183-mm",
.routes = mmsys_mt8183_routing_table,
@@ -59,6 +102,13 @@ static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
.sw0_rst_offset = MT8183_MMSYS_SW0_RST_B,
};
+static const struct mtk_mmsys_match_data mt8183_mmsys_match_data = {
+ .num_drv_data = 1,
+ .drv_data = {
+ &mt8183_mmsys_driver_data,
+ },
+};
+
static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = {
.clk_driver = "clk-mt8186-mm",
.routes = mmsys_mt8186_routing_table,
@@ -66,25 +116,79 @@ static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = {
.sw0_rst_offset = MT8186_MMSYS_SW0_RST_B,
};
+static const struct mtk_mmsys_match_data mt8186_mmsys_match_data = {
+ .num_drv_data = 1,
+ .drv_data = {
+ &mt8186_mmsys_driver_data,
+ },
+};
+
static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
.clk_driver = "clk-mt8192-mm",
.routes = mmsys_mt8192_routing_table,
.num_routes = ARRAY_SIZE(mmsys_mt8192_routing_table),
};
+static const struct mtk_mmsys_match_data mt8192_mmsys_match_data = {
+ .num_drv_data = 1,
+ .drv_data = {
+ &mt8192_mmsys_driver_data,
+ },
+};
+
+static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = {
+ .io_start = 0x1c01a000,
+ .clk_driver = "clk-mt8195-vdo0",
+ .routes = mmsys_mt8195_routing_table,
+ .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
+};
+
+static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
+ .io_start = 0x1c100000,
+ .clk_driver = "clk-mt8195-vdo1",
+};
+
+static const struct mtk_mmsys_match_data mt8195_mmsys_match_data = {
+ .num_drv_data = 2,
+ .drv_data = {
+ &mt8195_vdosys0_driver_data,
+ &mt8195_vdosys1_driver_data,
+ },
+};
+
static const struct mtk_mmsys_driver_data mt8365_mmsys_driver_data = {
.clk_driver = "clk-mt8365-mm",
.routes = mt8365_mmsys_routing_table,
.num_routes = ARRAY_SIZE(mt8365_mmsys_routing_table),
};
+static const struct mtk_mmsys_match_data mt8365_mmsys_match_data = {
+ .num_drv_data = 1,
+ .drv_data = {
+ &mt8365_mmsys_driver_data,
+ },
+};
+
struct mtk_mmsys {
void __iomem *regs;
const struct mtk_mmsys_driver_data *data;
spinlock_t lock; /* protects mmsys_sw_rst_b reg */
struct reset_controller_dev rcdev;
+ phys_addr_t io_start;
};
+static int mtk_mmsys_find_match_drvdata(struct mtk_mmsys *mmsys,
+ const struct mtk_mmsys_match_data *match)
+{
+ int i;
+
+ for (i = 0; i < match->num_drv_data; i++)
+ if (mmsys->io_start == match->drv_data[i]->io_start)
+ return i;
+
+ return -EINVAL;
+}
+
void mtk_mmsys_ddp_connect(struct device *dev,
enum mtk_ddp_comp_id cur,
enum mtk_ddp_comp_id next)
@@ -179,7 +283,9 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
struct device *dev = &pdev->dev;
struct platform_device *clks;
struct platform_device *drm;
+ const struct mtk_mmsys_match_data *match_data;
struct mtk_mmsys *mmsys;
+ struct resource *res;
int ret;
mmsys = devm_kzalloc(dev, sizeof(*mmsys), GFP_KERNEL);
@@ -205,7 +311,27 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
return ret;
}
- mmsys->data = of_device_get_match_data(&pdev->dev);
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!res) {
+ dev_err(dev, "Couldn't get mmsys resource\n");
+ return -EINVAL;
+ }
+ mmsys->io_start = res->start;
+
+ match_data = of_device_get_match_data(dev);
+ if (match_data->num_drv_data > 1) {
+ /* This SoC has multiple mmsys channels */
+ ret = mtk_mmsys_find_match_drvdata(mmsys, match_data);
+ if (ret < 0) {
+ dev_err(dev, "Couldn't get match driver data\n");
+ return ret;
+ }
+ mmsys->data = match_data->drv_data[ret];
+ } else {
+ dev_dbg(dev, "Using single mmsys channel\n");
+ mmsys->data = match_data->drv_data[0];
+ }
+
platform_set_drvdata(pdev, mmsys);
clks = platform_device_register_data(&pdev->dev, mmsys->data->clk_driver,
@@ -226,43 +352,47 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
static const struct of_device_id of_match_mtk_mmsys[] = {
{
.compatible = "mediatek,mt2701-mmsys",
- .data = &mt2701_mmsys_driver_data,
+ .data = &mt2701_mmsys_match_data,
},
{
.compatible = "mediatek,mt2712-mmsys",
- .data = &mt2712_mmsys_driver_data,
+ .data = &mt2712_mmsys_match_data,
},
{
.compatible = "mediatek,mt6779-mmsys",
- .data = &mt6779_mmsys_driver_data,
+ .data = &mt6779_mmsys_match_data,
},
{
.compatible = "mediatek,mt6797-mmsys",
- .data = &mt6797_mmsys_driver_data,
+ .data = &mt6797_mmsys_match_data,
},
{
.compatible = "mediatek,mt8167-mmsys",
- .data = &mt8167_mmsys_driver_data,
+ .data = &mt8167_mmsys_match_data,
},
{
.compatible = "mediatek,mt8173-mmsys",
- .data = &mt8173_mmsys_driver_data,
+ .data = &mt8173_mmsys_match_data,
},
{
.compatible = "mediatek,mt8183-mmsys",
- .data = &mt8183_mmsys_driver_data,
+ .data = &mt8183_mmsys_match_data,
},
{
.compatible = "mediatek,mt8186-mmsys",
- .data = &mt8186_mmsys_driver_data,
+ .data = &mt8186_mmsys_match_data,
},
{
.compatible = "mediatek,mt8192-mmsys",
- .data = &mt8192_mmsys_driver_data,
+ .data = &mt8192_mmsys_match_data,
+ },
+ {
+ .compatible = "mediatek,mt8195-mmsys",
+ .data = &mt8195_mmsys_match_data,
},
{
.compatible = "mediatek,mt8365-mmsys",
- .data = &mt8365_mmsys_driver_data,
+ .data = &mt8365_mmsys_match_data,
},
{ }
};
diff --git a/drivers/soc/mediatek/mtk-mmsys.h b/drivers/soc/mediatek/mtk-mmsys.h
index 77f37f8c715b..f01ba206481d 100644
--- a/drivers/soc/mediatek/mtk-mmsys.h
+++ b/drivers/soc/mediatek/mtk-mmsys.h
@@ -87,12 +87,18 @@ struct mtk_mmsys_routes {
};
struct mtk_mmsys_driver_data {
+ const resource_size_t io_start;
const char *clk_driver;
const struct mtk_mmsys_routes *routes;
const unsigned int num_routes;
const u16 sw0_rst_offset;
};
+struct mtk_mmsys_match_data {
+ unsigned short num_drv_data;
+ const struct mtk_mmsys_driver_data *drv_data[];
+};
+
/*
* Routes in mt8173, mt2701, mt2712 are different. That means
* in the same register address, it controls different input/output
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
index 4bba275e235a..cff5c9adbf46 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -17,13 +17,24 @@ enum mtk_ddp_comp_id {
DDP_COMPONENT_COLOR0,
DDP_COMPONENT_COLOR1,
DDP_COMPONENT_DITHER,
+ DDP_COMPONENT_DITHER1,
+ DDP_COMPONENT_DP_INTF0,
+ DDP_COMPONENT_DP_INTF1,
DDP_COMPONENT_DPI0,
DDP_COMPONENT_DPI1,
+ DDP_COMPONENT_DSC0,
+ DDP_COMPONENT_DSC1,
DDP_COMPONENT_DSI0,
DDP_COMPONENT_DSI1,
DDP_COMPONENT_DSI2,
DDP_COMPONENT_DSI3,
DDP_COMPONENT_GAMMA,
+ DDP_COMPONENT_MERGE0,
+ DDP_COMPONENT_MERGE1,
+ DDP_COMPONENT_MERGE2,
+ DDP_COMPONENT_MERGE3,
+ DDP_COMPONENT_MERGE4,
+ DDP_COMPONENT_MERGE5,
DDP_COMPONENT_OD0,
DDP_COMPONENT_OD1,
DDP_COMPONENT_OVL0,
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [PATCH v20 1/8] soc: mediatek: add mtk-mmsys support for mt8195 vdosys0
@ 2022-04-19 9:41 ` jason-jh.lin
0 siblings, 0 replies; 110+ messages in thread
From: jason-jh.lin @ 2022-04-19 9:41 UTC (permalink / raw)
To: Matthias Brugger, Chun-Kuang Hu, AngeloGioacchino Del Regno
Cc: CK Hu, Jason-JH Lin, Nancy Lin, Singo Chang, devicetree,
linux-kernel, dri-devel, linux-mediatek, linux-arm-kernel,
Project_Global_Chrome_Upstream_Group
1. Add mt8195 mmsys compatible for 2 vdosys.
2. Add io_start into each driver data of mt8195 vdosys.
3. Add get match data function to identify mmsys by io_start.
4. Add mt8195 routing table settings of vdosys0.
Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
Based on series [1]
[1] MediaTek MT8195 display binding
- https://patchwork.ozlabs.org/project/devicetree-bindings/list/?series=295669
---
drivers/soc/mediatek/mt8195-mmsys.h | 370 +++++++++++++++++++++++++
drivers/soc/mediatek/mtk-mmsys.c | 152 +++++++++-
drivers/soc/mediatek/mtk-mmsys.h | 6 +
include/linux/soc/mediatek/mtk-mmsys.h | 11 +
4 files changed, 528 insertions(+), 11 deletions(-)
create mode 100644 drivers/soc/mediatek/mt8195-mmsys.h
diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h
new file mode 100644
index 000000000000..13ab0ab64396
--- /dev/null
+++ b/drivers/soc/mediatek/mt8195-mmsys.h
@@ -0,0 +1,370 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __SOC_MEDIATEK_MT8195_MMSYS_H
+#define __SOC_MEDIATEK_MT8195_MMSYS_H
+
+#define MT8195_VDO0_OVL_MOUT_EN 0xf14
+#define MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0 BIT(0)
+#define MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0 BIT(1)
+#define MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1 BIT(2)
+#define MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1 BIT(4)
+#define MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1 BIT(5)
+#define MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0 BIT(6)
+
+#define MT8195_VDO0_SEL_IN 0xf34
+#define MT8195_SEL_IN_VPP_MERGE_FROM_MASK GENMASK(1, 0)
+#define MT8195_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT (0 << 0)
+#define MT8195_SEL_IN_VPP_MERGE_FROM_DISP_DITHER1 (1 << 0)
+#define MT8195_SEL_IN_VPP_MERGE_FROM_VDO1_VIRTUAL0 (2 << 0)
+#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK GENMASK(4, 4)
+#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0 (0 << 4)
+#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_VPP_MERGE (1 << 4)
+#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_MASK GENMASK(5, 5)
+#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_DISP_DITHER1 (0 << 5)
+#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_VPP_MERGE (1 << 5)
+#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK GENMASK(8, 8)
+#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE (0 << 8)
+#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT (1 << 8)
+#define MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK GENMASK(9, 9)
+#define MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT (0 << 9)
+#define MT8195_SEL_IN_DP_INTF0_FROM_MASK GENMASK(13, 12)
+#define MT8195_SEL_IN_DP_INTF0_FROM_DSC_WRAP1_OUT (0 << 0)
+#define MT8195_SEL_IN_DP_INTF0_FROM_VPP_MERGE (1 << 12)
+#define MT8195_SEL_IN_DP_INTF0_FROM_VDO1_VIRTUAL0 (2 << 12)
+#define MT8195_SEL_IN_DSI0_FROM_MASK GENMASK(16, 16)
+#define MT8195_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT (0 << 16)
+#define MT8195_SEL_IN_DSI0_FROM_DISP_DITHER0 (1 << 16)
+#define MT8195_SEL_IN_DSI1_FROM_MASK GENMASK(17, 17)
+#define MT8195_SEL_IN_DSI1_FROM_DSC_WRAP1_OUT (0 << 17)
+#define MT8195_SEL_IN_DSI1_FROM_VPP_MERGE (1 << 17)
+#define MT8195_SEL_IN_DISP_WDMA1_FROM_MASK GENMASK(20, 20)
+#define MT8195_SEL_IN_DISP_WDMA1_FROM_DISP_OVL1 (0 << 20)
+#define MT8195_SEL_IN_DISP_WDMA1_FROM_VPP_MERGE (1 << 20)
+#define MT8195_SEL_IN_DSC_WRAP1_FROM_MASK GENMASK(21, 21)
+#define MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN (0 << 21)
+#define MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1 (1 << 21)
+#define MT8195_SEL_IN_DISP_WDMA0_FROM_MASK GENMASK(22, 22)
+#define MT8195_SEL_IN_DISP_WDMA0_FROM_DISP_OVL0 (0 << 22)
+
+#define MT8195_VDO0_SEL_OUT 0xf38
+#define MT8195_SOUT_DISP_DITHER0_TO_MASK BIT(0)
+#define MT8195_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN (0 << 0)
+#define MT8195_SOUT_DISP_DITHER0_TO_DSI0 (1 << 0)
+#define MT8195_SOUT_DISP_DITHER1_TO_MASK GENMASK(2, 1)
+#define MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_IN (0 << 1)
+#define MT8195_SOUT_DISP_DITHER1_TO_VPP_MERGE (1 << 1)
+#define MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT (2 << 1)
+#define MT8195_SOUT_VDO1_VIRTUAL0_TO_MASK GENMASK(4, 4)
+#define MT8195_SOUT_VDO1_VIRTUAL0_TO_VPP_MERGE (0 << 4)
+#define MT8195_SOUT_VDO1_VIRTUAL0_TO_DP_INTF0 (1 << 4)
+#define MT8195_SOUT_VPP_MERGE_TO_MASK GENMASK(10, 8)
+#define MT8195_SOUT_VPP_MERGE_TO_DSI1 (0 << 8)
+#define MT8195_SOUT_VPP_MERGE_TO_DP_INTF0 (1 << 8)
+#define MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0 (2 << 8)
+#define MT8195_SOUT_VPP_MERGE_TO_DISP_WDMA1 (3 << 8)
+#define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP0_IN (4 << 8)
+#define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN_MASK GENMASK(11, 11)
+#define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN (0 << 11)
+#define MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK GENMASK(13, 12)
+#define MT8195_SOUT_DSC_WRAP0_OUT_TO_DSI0 (0 << 12)
+#define MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0 (1 << 12)
+#define MT8195_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE (2 << 12)
+#define MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK GENMASK(17, 16)
+#define MT8195_SOUT_DSC_WRAP1_OUT_TO_DSI1 (0 << 16)
+#define MT8195_SOUT_DSC_WRAP1_OUT_TO_DP_INTF0 (1 << 16)
+#define MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0 (2 << 16)
+#define MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE (3 << 16)
+
+static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
+ {
+ DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
+ MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0,
+ MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0
+ }, {
+ DDP_COMPONENT_OVL0, DDP_COMPONENT_WDMA0,
+ MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0,
+ MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0
+ }, {
+ DDP_COMPONENT_OVL0, DDP_COMPONENT_OVL1,
+ MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1,
+ MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1
+ }, {
+ DDP_COMPONENT_OVL1, DDP_COMPONENT_RDMA1,
+ MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1,
+ MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1
+ }, {
+ DDP_COMPONENT_OVL1, DDP_COMPONENT_WDMA1,
+ MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1,
+ MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1
+ }, {
+ DDP_COMPONENT_OVL1, DDP_COMPONENT_OVL0,
+ MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0,
+ MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0
+ }, {
+ DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK,
+ MT8195_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT
+ }, {
+ DDP_COMPONENT_DITHER1, DDP_COMPONENT_MERGE0,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK,
+ MT8195_SEL_IN_VPP_MERGE_FROM_DISP_DITHER1
+ }, {
+ DDP_COMPONENT_MERGE5, DDP_COMPONENT_MERGE0,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK,
+ MT8195_SEL_IN_VPP_MERGE_FROM_VDO1_VIRTUAL0
+ }, {
+ DDP_COMPONENT_DITHER, DDP_COMPONENT_DSC0,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK,
+ MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0
+ }, {
+ DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC0,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK,
+ MT8195_SEL_IN_DSC_WRAP0_IN_FROM_VPP_MERGE
+ }, {
+ DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSC1,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_IN_FROM_MASK,
+ MT8195_SEL_IN_DSC_WRAP1_IN_FROM_DISP_DITHER1
+ }, {
+ DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC1,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_IN_FROM_MASK,
+ MT8195_SEL_IN_DSC_WRAP1_IN_FROM_VPP_MERGE
+ }, {
+ DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF1,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
+ MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE
+ }, {
+ DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI0,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
+ MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE
+ }, {
+ DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI1,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
+ MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE
+ }, {
+ DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF1,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
+ MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT
+ }, {
+ DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI0,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
+ MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT
+ }, {
+ DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI1,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
+ MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT
+ }, {
+ DDP_COMPONENT_DSC0, DDP_COMPONENT_DP_INTF1,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK,
+ MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT
+ }, {
+ DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI0,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK,
+ MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT
+ }, {
+ DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI1,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK,
+ MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT
+ }, {
+ DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF0,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_MASK,
+ MT8195_SEL_IN_DP_INTF0_FROM_DSC_WRAP1_OUT
+ }, {
+ DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF0,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_MASK,
+ MT8195_SEL_IN_DP_INTF0_FROM_VPP_MERGE
+ }, {
+ DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF0,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_MASK,
+ MT8195_SEL_IN_DP_INTF0_FROM_VDO1_VIRTUAL0
+ }, {
+ DDP_COMPONENT_DSC0, DDP_COMPONENT_DSI0,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI0_FROM_MASK,
+ MT8195_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT
+ }, {
+ DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI0_FROM_MASK,
+ MT8195_SEL_IN_DSI0_FROM_DISP_DITHER0
+ }, {
+ DDP_COMPONENT_DSC1, DDP_COMPONENT_DSI1,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI1_FROM_MASK,
+ MT8195_SEL_IN_DSI1_FROM_DSC_WRAP1_OUT
+ }, {
+ DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSI1,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI1_FROM_MASK,
+ MT8195_SEL_IN_DSI1_FROM_VPP_MERGE
+ }, {
+ DDP_COMPONENT_OVL1, DDP_COMPONENT_WDMA1,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA1_FROM_MASK,
+ MT8195_SEL_IN_DISP_WDMA1_FROM_DISP_OVL1
+ }, {
+ DDP_COMPONENT_MERGE0, DDP_COMPONENT_WDMA1,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA1_FROM_MASK,
+ MT8195_SEL_IN_DISP_WDMA1_FROM_VPP_MERGE
+ }, {
+ DDP_COMPONENT_DSC1, DDP_COMPONENT_DSI1,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
+ MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
+ }, {
+ DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF0,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
+ MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
+ }, {
+ DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF1,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
+ MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
+ }, {
+ DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI0,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
+ MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
+ }, {
+ DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI1,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
+ MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
+ }, {
+ DDP_COMPONENT_DSC1, DDP_COMPONENT_MERGE0,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
+ MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
+ }, {
+ DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSI1,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
+ MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1
+ }, {
+ DDP_COMPONENT_DITHER1, DDP_COMPONENT_DP_INTF0,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
+ MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1
+ }, {
+ DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI0,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
+ MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1
+ }, {
+ DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI1,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
+ MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1
+ }, {
+ DDP_COMPONENT_OVL0, DDP_COMPONENT_WDMA0,
+ MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA0_FROM_MASK,
+ MT8195_SEL_IN_DISP_WDMA0_FROM_DISP_OVL0
+ }, {
+ DDP_COMPONENT_DITHER, DDP_COMPONENT_DSC0,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER0_TO_MASK,
+ MT8195_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN
+ }, {
+ DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER0_TO_MASK,
+ MT8195_SOUT_DISP_DITHER0_TO_DSI0
+ }, {
+ DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSC1,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
+ MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_IN
+ }, {
+ DDP_COMPONENT_DITHER1, DDP_COMPONENT_MERGE0,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
+ MT8195_SOUT_DISP_DITHER1_TO_VPP_MERGE
+ }, {
+ DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSI1,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
+ MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT
+ }, {
+ DDP_COMPONENT_DITHER1, DDP_COMPONENT_DP_INTF0,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
+ MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT
+ }, {
+ DDP_COMPONENT_DITHER1, DDP_COMPONENT_DP_INTF1,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
+ MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT
+ }, {
+ DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI0,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
+ MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT
+ }, {
+ DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI1,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
+ MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT
+ }, {
+ DDP_COMPONENT_MERGE5, DDP_COMPONENT_MERGE0,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_VDO1_VIRTUAL0_TO_MASK,
+ MT8195_SOUT_VDO1_VIRTUAL0_TO_VPP_MERGE
+ }, {
+ DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF0,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_VDO1_VIRTUAL0_TO_MASK,
+ MT8195_SOUT_VDO1_VIRTUAL0_TO_DP_INTF0
+ }, {
+ DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSI1,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
+ MT8195_SOUT_VPP_MERGE_TO_DSI1
+ }, {
+ DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF0,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
+ MT8195_SOUT_VPP_MERGE_TO_DP_INTF0
+ }, {
+ DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF1,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
+ MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0
+ }, {
+ DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI0,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
+ MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0
+ }, {
+ DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI1,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
+ MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0
+ }, {
+ DDP_COMPONENT_MERGE0, DDP_COMPONENT_WDMA1,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
+ MT8195_SOUT_VPP_MERGE_TO_DISP_WDMA1
+ }, {
+ DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC0,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
+ MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP0_IN
+ }, {
+ DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC1,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN_MASK,
+ MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN
+ }, {
+ DDP_COMPONENT_DSC0, DDP_COMPONENT_DSI0,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
+ MT8195_SOUT_DSC_WRAP0_OUT_TO_DSI0
+ }, {
+ DDP_COMPONENT_DSC0, DDP_COMPONENT_DP_INTF1,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
+ MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0
+ }, {
+ DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI0,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
+ MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0
+ }, {
+ DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI1,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
+ MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0
+ }, {
+ DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
+ MT8195_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE
+ }, {
+ DDP_COMPONENT_DSC1, DDP_COMPONENT_DSI1,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
+ MT8195_SOUT_DSC_WRAP1_OUT_TO_DSI1
+ }, {
+ DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF0,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
+ MT8195_SOUT_DSC_WRAP1_OUT_TO_DP_INTF0
+ }, {
+ DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF1,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
+ MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0
+ }, {
+ DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI0,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
+ MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0
+ }, {
+ DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI1,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
+ MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0
+ }, {
+ DDP_COMPONENT_DSC1, DDP_COMPONENT_MERGE0,
+ MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
+ MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE
+ }
+};
+
+#endif /* __SOC_MEDIATEK_MT8195_MMSYS_H */
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index 4fc4c2c9ea20..548efed8dc1c 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -17,6 +17,7 @@
#include "mt8183-mmsys.h"
#include "mt8186-mmsys.h"
#include "mt8192-mmsys.h"
+#include "mt8195-mmsys.h"
#include "mt8365-mmsys.h"
static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
@@ -25,26 +26,61 @@ static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
.num_routes = ARRAY_SIZE(mmsys_default_routing_table),
};
+static const struct mtk_mmsys_match_data mt2701_mmsys_match_data = {
+ .num_drv_data = 1,
+ .drv_data = {
+ &mt2701_mmsys_driver_data,
+ },
+};
+
static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = {
.clk_driver = "clk-mt2712-mm",
.routes = mmsys_default_routing_table,
.num_routes = ARRAY_SIZE(mmsys_default_routing_table),
};
+static const struct mtk_mmsys_match_data mt2712_mmsys_match_data = {
+ .num_drv_data = 1,
+ .drv_data = {
+ &mt2712_mmsys_driver_data,
+ },
+};
+
static const struct mtk_mmsys_driver_data mt6779_mmsys_driver_data = {
.clk_driver = "clk-mt6779-mm",
};
+static const struct mtk_mmsys_match_data mt6779_mmsys_match_data = {
+ .num_drv_data = 1,
+ .drv_data = {
+ &mt6779_mmsys_driver_data,
+ },
+};
+
static const struct mtk_mmsys_driver_data mt6797_mmsys_driver_data = {
.clk_driver = "clk-mt6797-mm",
};
+static const struct mtk_mmsys_match_data mt6797_mmsys_match_data = {
+ .num_drv_data = 1,
+ .drv_data = {
+ &mt6797_mmsys_driver_data,
+ },
+};
+
static const struct mtk_mmsys_driver_data mt8167_mmsys_driver_data = {
.clk_driver = "clk-mt8167-mm",
.routes = mt8167_mmsys_routing_table,
.num_routes = ARRAY_SIZE(mt8167_mmsys_routing_table),
};
+static const struct mtk_mmsys_match_data mt8167_mmsys_match_data = {
+ .num_drv_data = 1,
+ .drv_data = {
+ &mt8167_mmsys_driver_data,
+ },
+};
+
static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
.clk_driver = "clk-mt8173-mm",
.routes = mmsys_default_routing_table,
@@ -52,6 +88,13 @@ static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
.sw0_rst_offset = MT8183_MMSYS_SW0_RST_B,
};
+static const struct mtk_mmsys_match_data mt8173_mmsys_match_data = {
+ .num_drv_data = 1,
+ .drv_data = {
+ &mt8173_mmsys_driver_data,
+ },
+};
+
static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
.clk_driver = "clk-mt8183-mm",
.routes = mmsys_mt8183_routing_table,
@@ -59,6 +102,13 @@ static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
.sw0_rst_offset = MT8183_MMSYS_SW0_RST_B,
};
+static const struct mtk_mmsys_match_data mt8183_mmsys_match_data = {
+ .num_drv_data = 1,
+ .drv_data = {
+ &mt8183_mmsys_driver_data,
+ },
+};
+
static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = {
.clk_driver = "clk-mt8186-mm",
.routes = mmsys_mt8186_routing_table,
@@ -66,25 +116,79 @@ static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = {
.sw0_rst_offset = MT8186_MMSYS_SW0_RST_B,
};
+static const struct mtk_mmsys_match_data mt8186_mmsys_match_data = {
+ .num_drv_data = 1,
+ .drv_data = {
+ &mt8186_mmsys_driver_data,
+ },
+};
+
static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
.clk_driver = "clk-mt8192-mm",
.routes = mmsys_mt8192_routing_table,
.num_routes = ARRAY_SIZE(mmsys_mt8192_routing_table),
};
+static const struct mtk_mmsys_match_data mt8192_mmsys_match_data = {
+ .num_drv_data = 1,
+ .drv_data = {
+ &mt8192_mmsys_driver_data,
+ },
+};
+
+static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = {
+ .io_start = 0x1c01a000,
+ .clk_driver = "clk-mt8195-vdo0",
+ .routes = mmsys_mt8195_routing_table,
+ .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
+};
+
+static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
+ .io_start = 0x1c100000,
+ .clk_driver = "clk-mt8195-vdo1",
+};
+
+static const struct mtk_mmsys_match_data mt8195_mmsys_match_data = {
+ .num_drv_data = 2,
+ .drv_data = {
+ &mt8195_vdosys0_driver_data,
+ &mt8195_vdosys1_driver_data,
+ },
+};
+
static const struct mtk_mmsys_driver_data mt8365_mmsys_driver_data = {
.clk_driver = "clk-mt8365-mm",
.routes = mt8365_mmsys_routing_table,
.num_routes = ARRAY_SIZE(mt8365_mmsys_routing_table),
};
+static const struct mtk_mmsys_match_data mt8365_mmsys_match_data = {
+ .num_drv_data = 1,
+ .drv_data = {
+ &mt8365_mmsys_driver_data,
+ },
+};
+
struct mtk_mmsys {
void __iomem *regs;
const struct mtk_mmsys_driver_data *data;
spinlock_t lock; /* protects mmsys_sw_rst_b reg */
struct reset_controller_dev rcdev;
+ phys_addr_t io_start;
};
+static int mtk_mmsys_find_match_drvdata(struct mtk_mmsys *mmsys,
+ const struct mtk_mmsys_match_data *match)
+{
+ int i;
+
+ for (i = 0; i < match->num_drv_data; i++)
+ if (mmsys->io_start == match->drv_data[i]->io_start)
+ return i;
+
+ return -EINVAL;
+}
+
void mtk_mmsys_ddp_connect(struct device *dev,
enum mtk_ddp_comp_id cur,
enum mtk_ddp_comp_id next)
@@ -179,7 +283,9 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
struct device *dev = &pdev->dev;
struct platform_device *clks;
struct platform_device *drm;
+ const struct mtk_mmsys_match_data *match_data;
struct mtk_mmsys *mmsys;
+ struct resource *res;
int ret;
mmsys = devm_kzalloc(dev, sizeof(*mmsys), GFP_KERNEL);
@@ -205,7 +311,27 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
return ret;
}
- mmsys->data = of_device_get_match_data(&pdev->dev);
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!res) {
+ dev_err(dev, "Couldn't get mmsys resource\n");
+ return -EINVAL;
+ }
+ mmsys->io_start = res->start;
+
+ match_data = of_device_get_match_data(dev);
+ if (match_data->num_drv_data > 1) {
+ /* This SoC has multiple mmsys channels */
+ ret = mtk_mmsys_find_match_drvdata(mmsys, match_data);
+ if (ret < 0) {
+ dev_err(dev, "Couldn't get match driver data\n");
+ return ret;
+ }
+ mmsys->data = match_data->drv_data[ret];
+ } else {
+ dev_dbg(dev, "Using single mmsys channel\n");
+ mmsys->data = match_data->drv_data[0];
+ }
+
platform_set_drvdata(pdev, mmsys);
clks = platform_device_register_data(&pdev->dev, mmsys->data->clk_driver,
@@ -226,43 +352,47 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
static const struct of_device_id of_match_mtk_mmsys[] = {
{
.compatible = "mediatek,mt2701-mmsys",
- .data = &mt2701_mmsys_driver_data,
+ .data = &mt2701_mmsys_match_data,
},
{
.compatible = "mediatek,mt2712-mmsys",
- .data = &mt2712_mmsys_driver_data,
+ .data = &mt2712_mmsys_match_data,
},
{
.compatible = "mediatek,mt6779-mmsys",
- .data = &mt6779_mmsys_driver_data,
+ .data = &mt6779_mmsys_match_data,
},
{
.compatible = "mediatek,mt6797-mmsys",
- .data = &mt6797_mmsys_driver_data,
+ .data = &mt6797_mmsys_match_data,
},
{
.compatible = "mediatek,mt8167-mmsys",
- .data = &mt8167_mmsys_driver_data,
+ .data = &mt8167_mmsys_match_data,
},
{
.compatible = "mediatek,mt8173-mmsys",
- .data = &mt8173_mmsys_driver_data,
+ .data = &mt8173_mmsys_match_data,
},
{
.compatible = "mediatek,mt8183-mmsys",
- .data = &mt8183_mmsys_driver_data,
+ .data = &mt8183_mmsys_match_data,
},
{
.compatible = "mediatek,mt8186-mmsys",
- .data = &mt8186_mmsys_driver_data,
+ .data = &mt8186_mmsys_match_data,
},
{
.compatible = "mediatek,mt8192-mmsys",
- .data = &mt8192_mmsys_driver_data,
+ .data = &mt8192_mmsys_match_data,
+ },
+ {
+ .compatible = "mediatek,mt8195-mmsys",
+ .data = &mt8195_mmsys_match_data,
},
{
.compatible = "mediatek,mt8365-mmsys",
- .data = &mt8365_mmsys_driver_data,
+ .data = &mt8365_mmsys_match_data,
},
{ }
};
diff --git a/drivers/soc/mediatek/mtk-mmsys.h b/drivers/soc/mediatek/mtk-mmsys.h
index 77f37f8c715b..f01ba206481d 100644
--- a/drivers/soc/mediatek/mtk-mmsys.h
+++ b/drivers/soc/mediatek/mtk-mmsys.h
@@ -87,12 +87,18 @@ struct mtk_mmsys_routes {
};
struct mtk_mmsys_driver_data {
+ const resource_size_t io_start;
const char *clk_driver;
const struct mtk_mmsys_routes *routes;
const unsigned int num_routes;
const u16 sw0_rst_offset;
};
+struct mtk_mmsys_match_data {
+ unsigned short num_drv_data;
+ const struct mtk_mmsys_driver_data *drv_data[];
+};
+
/*
* Routes in mt8173, mt2701, mt2712 are different. That means
* in the same register address, it controls different input/output
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
index 4bba275e235a..cff5c9adbf46 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -17,13 +17,24 @@ enum mtk_ddp_comp_id {
DDP_COMPONENT_COLOR0,
DDP_COMPONENT_COLOR1,
DDP_COMPONENT_DITHER,
+ DDP_COMPONENT_DITHER1,
+ DDP_COMPONENT_DP_INTF0,
+ DDP_COMPONENT_DP_INTF1,
DDP_COMPONENT_DPI0,
DDP_COMPONENT_DPI1,
+ DDP_COMPONENT_DSC0,
+ DDP_COMPONENT_DSC1,
DDP_COMPONENT_DSI0,
DDP_COMPONENT_DSI1,
DDP_COMPONENT_DSI2,
DDP_COMPONENT_DSI3,
DDP_COMPONENT_GAMMA,
+ DDP_COMPONENT_MERGE0,
+ DDP_COMPONENT_MERGE1,
+ DDP_COMPONENT_MERGE2,
+ DDP_COMPONENT_MERGE3,
+ DDP_COMPONENT_MERGE4,
+ DDP_COMPONENT_MERGE5,
DDP_COMPONENT_OD0,
DDP_COMPONENT_OD1,
DDP_COMPONENT_OVL0,
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [PATCH v20 2/8] soc: mediatek: add mtk-mutex support for mt8195 vdosys0
2022-04-19 9:41 ` jason-jh.lin
(?)
@ 2022-04-19 9:41 ` jason-jh.lin
-1 siblings, 0 replies; 110+ messages in thread
From: jason-jh.lin @ 2022-04-19 9:41 UTC (permalink / raw)
To: Matthias Brugger, Chun-Kuang Hu, AngeloGioacchino Del Regno
Cc: devicetree, Jason-JH Lin, Singo Chang, linux-kernel, dri-devel,
Project_Global_Chrome_Upstream_Group, Nancy Lin, linux-mediatek,
linux-arm-kernel
Add mtk-mutex support for mt8195 vdosys0.
Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
Acked-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Tested-by: Fei Shao <fshao@chromium.org>
---
drivers/soc/mediatek/mtk-mutex.c | 87 ++++++++++++++++++++++++++++++--
1 file changed, 84 insertions(+), 3 deletions(-)
diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c
index aaf8fc1abb43..729ee88035ed 100644
--- a/drivers/soc/mediatek/mtk-mutex.c
+++ b/drivers/soc/mediatek/mtk-mutex.c
@@ -17,6 +17,9 @@
#define MT8183_MUTEX0_MOD0 0x30
#define MT8183_MUTEX0_SOF0 0x2c
+#define MT8195_DISP_MUTEX0_MOD0 0x30
+#define MT8195_DISP_MUTEX0_SOF 0x2c
+
#define DISP_REG_MUTEX_EN(n) (0x20 + 0x20 * (n))
#define DISP_REG_MUTEX(n) (0x24 + 0x20 * (n))
#define DISP_REG_MUTEX_RST(n) (0x28 + 0x20 * (n))
@@ -96,6 +99,20 @@
#define MT8173_MUTEX_MOD_DISP_PWM1 24
#define MT8173_MUTEX_MOD_DISP_OD 25
+#define MT8195_MUTEX_MOD_DISP_OVL0 0
+#define MT8195_MUTEX_MOD_DISP_WDMA0 1
+#define MT8195_MUTEX_MOD_DISP_RDMA0 2
+#define MT8195_MUTEX_MOD_DISP_COLOR0 3
+#define MT8195_MUTEX_MOD_DISP_CCORR0 4
+#define MT8195_MUTEX_MOD_DISP_AAL0 5
+#define MT8195_MUTEX_MOD_DISP_GAMMA0 6
+#define MT8195_MUTEX_MOD_DISP_DITHER0 7
+#define MT8195_MUTEX_MOD_DISP_DSI0 8
+#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0 9
+#define MT8195_MUTEX_MOD_DISP_VPP_MERGE 20
+#define MT8195_MUTEX_MOD_DISP_DP_INTF0 21
+#define MT8195_MUTEX_MOD_DISP_PWM0 27
+
#define MT2712_MUTEX_MOD_DISP_PWM2 10
#define MT2712_MUTEX_MOD_DISP_OVL0 11
#define MT2712_MUTEX_MOD_DISP_OVL1 12
@@ -132,9 +149,21 @@
#define MT8167_MUTEX_SOF_DPI1 3
#define MT8183_MUTEX_SOF_DSI0 1
#define MT8183_MUTEX_SOF_DPI0 2
+#define MT8195_MUTEX_SOF_DSI0 1
+#define MT8195_MUTEX_SOF_DSI1 2
+#define MT8195_MUTEX_SOF_DP_INTF0 3
+#define MT8195_MUTEX_SOF_DP_INTF1 4
+#define MT8195_MUTEX_SOF_DPI0 6 /* for HDMI_TX */
+#define MT8195_MUTEX_SOF_DPI1 5 /* for digital video out */
#define MT8183_MUTEX_EOF_DSI0 (MT8183_MUTEX_SOF_DSI0 << 6)
#define MT8183_MUTEX_EOF_DPI0 (MT8183_MUTEX_SOF_DPI0 << 6)
+#define MT8195_MUTEX_EOF_DSI0 (MT8195_MUTEX_SOF_DSI0 << 7)
+#define MT8195_MUTEX_EOF_DSI1 (MT8195_MUTEX_SOF_DSI1 << 7)
+#define MT8195_MUTEX_EOF_DP_INTF0 (MT8195_MUTEX_SOF_DP_INTF0 << 7)
+#define MT8195_MUTEX_EOF_DP_INTF1 (MT8195_MUTEX_SOF_DP_INTF1 << 7)
+#define MT8195_MUTEX_EOF_DPI0 (MT8195_MUTEX_SOF_DPI0 << 7)
+#define MT8195_MUTEX_EOF_DPI1 (MT8195_MUTEX_SOF_DPI1 << 7)
struct mtk_mutex {
int id;
@@ -149,6 +178,9 @@ enum mtk_mutex_sof_id {
MUTEX_SOF_DPI1,
MUTEX_SOF_DSI2,
MUTEX_SOF_DSI3,
+ MUTEX_SOF_DP_INTF0,
+ MUTEX_SOF_DP_INTF1,
+ DDP_MUTEX_SOF_MAX,
};
struct mtk_mutex_data {
@@ -270,7 +302,23 @@ static const unsigned int mt8192_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_RDMA4] = MT8192_MUTEX_MOD_DISP_RDMA4,
};
-static const unsigned int mt2712_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
+static const unsigned int mt8195_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+ [DDP_COMPONENT_OVL0] = MT8195_MUTEX_MOD_DISP_OVL0,
+ [DDP_COMPONENT_WDMA0] = MT8195_MUTEX_MOD_DISP_WDMA0,
+ [DDP_COMPONENT_RDMA0] = MT8195_MUTEX_MOD_DISP_RDMA0,
+ [DDP_COMPONENT_COLOR0] = MT8195_MUTEX_MOD_DISP_COLOR0,
+ [DDP_COMPONENT_CCORR] = MT8195_MUTEX_MOD_DISP_CCORR0,
+ [DDP_COMPONENT_AAL0] = MT8195_MUTEX_MOD_DISP_AAL0,
+ [DDP_COMPONENT_GAMMA] = MT8195_MUTEX_MOD_DISP_GAMMA0,
+ [DDP_COMPONENT_DITHER] = MT8195_MUTEX_MOD_DISP_DITHER0,
+ [DDP_COMPONENT_MERGE0] = MT8195_MUTEX_MOD_DISP_VPP_MERGE,
+ [DDP_COMPONENT_DSC0] = MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0,
+ [DDP_COMPONENT_DSI0] = MT8195_MUTEX_MOD_DISP_DSI0,
+ [DDP_COMPONENT_PWM0] = MT8195_MUTEX_MOD_DISP_PWM0,
+ [DDP_COMPONENT_DP_INTF0] = MT8195_MUTEX_MOD_DISP_DP_INTF0,
+};
+
+static const unsigned int mt2712_mutex_sof[DDP_MUTEX_SOF_MAX] = {
[MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
[MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0,
[MUTEX_SOF_DSI1] = MUTEX_SOF_DSI1,
@@ -280,7 +328,7 @@ static const unsigned int mt2712_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
[MUTEX_SOF_DSI3] = MUTEX_SOF_DSI3,
};
-static const unsigned int mt8167_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
+static const unsigned int mt8167_mutex_sof[DDP_MUTEX_SOF_MAX] = {
[MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
[MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0,
[MUTEX_SOF_DPI0] = MT8167_MUTEX_SOF_DPI0,
@@ -288,7 +336,7 @@ static const unsigned int mt8167_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
};
/* Add EOF setting so overlay hardware can receive frame done irq */
-static const unsigned int mt8183_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
+static const unsigned int mt8183_mutex_sof[DDP_MUTEX_SOF_MAX] = {
[MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
[MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0 | MT8183_MUTEX_EOF_DSI0,
[MUTEX_SOF_DPI0] = MT8183_MUTEX_SOF_DPI0 | MT8183_MUTEX_EOF_DPI0,
@@ -300,6 +348,26 @@ static const unsigned int mt8186_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
[MUTEX_SOF_DPI0] = MT8186_MUTEX_SOF_DPI0 | MT8186_MUTEX_EOF_DPI0,
};
+/*
+ * To support refresh mode(video mode), DISP_REG_MUTEX_SOF should
+ * select the EOF source and configure the EOF plus timing from the
+ * module that provides the timing signal.
+ * So that MUTEX can not only send a STREAM_DONE event to GCE
+ * but also detect the error at end of frame(EAEOF) when EOF signal
+ * arrives.
+ */
+static const unsigned int mt8195_mutex_sof[DDP_MUTEX_SOF_MAX] = {
+ [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
+ [MUTEX_SOF_DSI0] = MT8195_MUTEX_SOF_DSI0 | MT8195_MUTEX_EOF_DSI0,
+ [MUTEX_SOF_DSI1] = MT8195_MUTEX_SOF_DSI1 | MT8195_MUTEX_EOF_DSI1,
+ [MUTEX_SOF_DPI0] = MT8195_MUTEX_SOF_DPI0 | MT8195_MUTEX_EOF_DPI0,
+ [MUTEX_SOF_DPI1] = MT8195_MUTEX_SOF_DPI1 | MT8195_MUTEX_EOF_DPI1,
+ [MUTEX_SOF_DP_INTF0] =
+ MT8195_MUTEX_SOF_DP_INTF0 | MT8195_MUTEX_EOF_DP_INTF0,
+ [MUTEX_SOF_DP_INTF1] =
+ MT8195_MUTEX_SOF_DP_INTF1 | MT8195_MUTEX_EOF_DP_INTF1,
+};
+
static const struct mtk_mutex_data mt2701_mutex_driver_data = {
.mutex_mod = mt2701_mutex_mod,
.mutex_sof = mt2712_mutex_sof,
@@ -351,6 +419,13 @@ static const struct mtk_mutex_data mt8192_mutex_driver_data = {
.mutex_sof_reg = MT8183_MUTEX0_SOF0,
};
+static const struct mtk_mutex_data mt8195_mutex_driver_data = {
+ .mutex_mod = mt8195_mutex_mod,
+ .mutex_sof = mt8195_mutex_sof,
+ .mutex_mod_reg = MT8195_DISP_MUTEX0_MOD0,
+ .mutex_sof_reg = MT8195_DISP_MUTEX0_SOF,
+};
+
struct mtk_mutex *mtk_mutex_get(struct device *dev)
{
struct mtk_mutex_ctx *mtx = dev_get_drvdata(dev);
@@ -423,6 +498,9 @@ void mtk_mutex_add_comp(struct mtk_mutex *mutex,
case DDP_COMPONENT_DPI1:
sof_id = MUTEX_SOF_DPI1;
break;
+ case DDP_COMPONENT_DP_INTF0:
+ sof_id = MUTEX_SOF_DP_INTF0;
+ break;
default:
if (mtx->data->mutex_mod[id] < 32) {
offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg,
@@ -462,6 +540,7 @@ void mtk_mutex_remove_comp(struct mtk_mutex *mutex,
case DDP_COMPONENT_DSI3:
case DDP_COMPONENT_DPI0:
case DDP_COMPONENT_DPI1:
+ case DDP_COMPONENT_DP_INTF0:
writel_relaxed(MUTEX_SOF_SINGLE_MODE,
mtx->regs +
DISP_REG_MUTEX_SOF(mtx->data->mutex_sof_reg,
@@ -587,6 +666,8 @@ static const struct of_device_id mutex_driver_dt_match[] = {
.data = &mt8186_mutex_driver_data},
{ .compatible = "mediatek,mt8192-disp-mutex",
.data = &mt8192_mutex_driver_data},
+ { .compatible = "mediatek,mt8195-disp-mutex",
+ .data = &mt8195_mutex_driver_data},
{},
};
MODULE_DEVICE_TABLE(of, mutex_driver_dt_match);
--
2.18.0
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [PATCH v20 2/8] soc: mediatek: add mtk-mutex support for mt8195 vdosys0
@ 2022-04-19 9:41 ` jason-jh.lin
0 siblings, 0 replies; 110+ messages in thread
From: jason-jh.lin @ 2022-04-19 9:41 UTC (permalink / raw)
To: Matthias Brugger, Chun-Kuang Hu, AngeloGioacchino Del Regno
Cc: CK Hu, Jason-JH Lin, Nancy Lin, Singo Chang, devicetree,
linux-kernel, dri-devel, linux-mediatek, linux-arm-kernel,
Project_Global_Chrome_Upstream_Group
Add mtk-mutex support for mt8195 vdosys0.
Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
Acked-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Tested-by: Fei Shao <fshao@chromium.org>
---
drivers/soc/mediatek/mtk-mutex.c | 87 ++++++++++++++++++++++++++++++--
1 file changed, 84 insertions(+), 3 deletions(-)
diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c
index aaf8fc1abb43..729ee88035ed 100644
--- a/drivers/soc/mediatek/mtk-mutex.c
+++ b/drivers/soc/mediatek/mtk-mutex.c
@@ -17,6 +17,9 @@
#define MT8183_MUTEX0_MOD0 0x30
#define MT8183_MUTEX0_SOF0 0x2c
+#define MT8195_DISP_MUTEX0_MOD0 0x30
+#define MT8195_DISP_MUTEX0_SOF 0x2c
+
#define DISP_REG_MUTEX_EN(n) (0x20 + 0x20 * (n))
#define DISP_REG_MUTEX(n) (0x24 + 0x20 * (n))
#define DISP_REG_MUTEX_RST(n) (0x28 + 0x20 * (n))
@@ -96,6 +99,20 @@
#define MT8173_MUTEX_MOD_DISP_PWM1 24
#define MT8173_MUTEX_MOD_DISP_OD 25
+#define MT8195_MUTEX_MOD_DISP_OVL0 0
+#define MT8195_MUTEX_MOD_DISP_WDMA0 1
+#define MT8195_MUTEX_MOD_DISP_RDMA0 2
+#define MT8195_MUTEX_MOD_DISP_COLOR0 3
+#define MT8195_MUTEX_MOD_DISP_CCORR0 4
+#define MT8195_MUTEX_MOD_DISP_AAL0 5
+#define MT8195_MUTEX_MOD_DISP_GAMMA0 6
+#define MT8195_MUTEX_MOD_DISP_DITHER0 7
+#define MT8195_MUTEX_MOD_DISP_DSI0 8
+#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0 9
+#define MT8195_MUTEX_MOD_DISP_VPP_MERGE 20
+#define MT8195_MUTEX_MOD_DISP_DP_INTF0 21
+#define MT8195_MUTEX_MOD_DISP_PWM0 27
+
#define MT2712_MUTEX_MOD_DISP_PWM2 10
#define MT2712_MUTEX_MOD_DISP_OVL0 11
#define MT2712_MUTEX_MOD_DISP_OVL1 12
@@ -132,9 +149,21 @@
#define MT8167_MUTEX_SOF_DPI1 3
#define MT8183_MUTEX_SOF_DSI0 1
#define MT8183_MUTEX_SOF_DPI0 2
+#define MT8195_MUTEX_SOF_DSI0 1
+#define MT8195_MUTEX_SOF_DSI1 2
+#define MT8195_MUTEX_SOF_DP_INTF0 3
+#define MT8195_MUTEX_SOF_DP_INTF1 4
+#define MT8195_MUTEX_SOF_DPI0 6 /* for HDMI_TX */
+#define MT8195_MUTEX_SOF_DPI1 5 /* for digital video out */
#define MT8183_MUTEX_EOF_DSI0 (MT8183_MUTEX_SOF_DSI0 << 6)
#define MT8183_MUTEX_EOF_DPI0 (MT8183_MUTEX_SOF_DPI0 << 6)
+#define MT8195_MUTEX_EOF_DSI0 (MT8195_MUTEX_SOF_DSI0 << 7)
+#define MT8195_MUTEX_EOF_DSI1 (MT8195_MUTEX_SOF_DSI1 << 7)
+#define MT8195_MUTEX_EOF_DP_INTF0 (MT8195_MUTEX_SOF_DP_INTF0 << 7)
+#define MT8195_MUTEX_EOF_DP_INTF1 (MT8195_MUTEX_SOF_DP_INTF1 << 7)
+#define MT8195_MUTEX_EOF_DPI0 (MT8195_MUTEX_SOF_DPI0 << 7)
+#define MT8195_MUTEX_EOF_DPI1 (MT8195_MUTEX_SOF_DPI1 << 7)
struct mtk_mutex {
int id;
@@ -149,6 +178,9 @@ enum mtk_mutex_sof_id {
MUTEX_SOF_DPI1,
MUTEX_SOF_DSI2,
MUTEX_SOF_DSI3,
+ MUTEX_SOF_DP_INTF0,
+ MUTEX_SOF_DP_INTF1,
+ DDP_MUTEX_SOF_MAX,
};
struct mtk_mutex_data {
@@ -270,7 +302,23 @@ static const unsigned int mt8192_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_RDMA4] = MT8192_MUTEX_MOD_DISP_RDMA4,
};
-static const unsigned int mt2712_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
+static const unsigned int mt8195_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+ [DDP_COMPONENT_OVL0] = MT8195_MUTEX_MOD_DISP_OVL0,
+ [DDP_COMPONENT_WDMA0] = MT8195_MUTEX_MOD_DISP_WDMA0,
+ [DDP_COMPONENT_RDMA0] = MT8195_MUTEX_MOD_DISP_RDMA0,
+ [DDP_COMPONENT_COLOR0] = MT8195_MUTEX_MOD_DISP_COLOR0,
+ [DDP_COMPONENT_CCORR] = MT8195_MUTEX_MOD_DISP_CCORR0,
+ [DDP_COMPONENT_AAL0] = MT8195_MUTEX_MOD_DISP_AAL0,
+ [DDP_COMPONENT_GAMMA] = MT8195_MUTEX_MOD_DISP_GAMMA0,
+ [DDP_COMPONENT_DITHER] = MT8195_MUTEX_MOD_DISP_DITHER0,
+ [DDP_COMPONENT_MERGE0] = MT8195_MUTEX_MOD_DISP_VPP_MERGE,
+ [DDP_COMPONENT_DSC0] = MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0,
+ [DDP_COMPONENT_DSI0] = MT8195_MUTEX_MOD_DISP_DSI0,
+ [DDP_COMPONENT_PWM0] = MT8195_MUTEX_MOD_DISP_PWM0,
+ [DDP_COMPONENT_DP_INTF0] = MT8195_MUTEX_MOD_DISP_DP_INTF0,
+};
+
+static const unsigned int mt2712_mutex_sof[DDP_MUTEX_SOF_MAX] = {
[MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
[MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0,
[MUTEX_SOF_DSI1] = MUTEX_SOF_DSI1,
@@ -280,7 +328,7 @@ static const unsigned int mt2712_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
[MUTEX_SOF_DSI3] = MUTEX_SOF_DSI3,
};
-static const unsigned int mt8167_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
+static const unsigned int mt8167_mutex_sof[DDP_MUTEX_SOF_MAX] = {
[MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
[MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0,
[MUTEX_SOF_DPI0] = MT8167_MUTEX_SOF_DPI0,
@@ -288,7 +336,7 @@ static const unsigned int mt8167_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
};
/* Add EOF setting so overlay hardware can receive frame done irq */
-static const unsigned int mt8183_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
+static const unsigned int mt8183_mutex_sof[DDP_MUTEX_SOF_MAX] = {
[MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
[MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0 | MT8183_MUTEX_EOF_DSI0,
[MUTEX_SOF_DPI0] = MT8183_MUTEX_SOF_DPI0 | MT8183_MUTEX_EOF_DPI0,
@@ -300,6 +348,26 @@ static const unsigned int mt8186_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
[MUTEX_SOF_DPI0] = MT8186_MUTEX_SOF_DPI0 | MT8186_MUTEX_EOF_DPI0,
};
+/*
+ * To support refresh mode(video mode), DISP_REG_MUTEX_SOF should
+ * select the EOF source and configure the EOF plus timing from the
+ * module that provides the timing signal.
+ * So that MUTEX can not only send a STREAM_DONE event to GCE
+ * but also detect the error at end of frame(EAEOF) when EOF signal
+ * arrives.
+ */
+static const unsigned int mt8195_mutex_sof[DDP_MUTEX_SOF_MAX] = {
+ [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
+ [MUTEX_SOF_DSI0] = MT8195_MUTEX_SOF_DSI0 | MT8195_MUTEX_EOF_DSI0,
+ [MUTEX_SOF_DSI1] = MT8195_MUTEX_SOF_DSI1 | MT8195_MUTEX_EOF_DSI1,
+ [MUTEX_SOF_DPI0] = MT8195_MUTEX_SOF_DPI0 | MT8195_MUTEX_EOF_DPI0,
+ [MUTEX_SOF_DPI1] = MT8195_MUTEX_SOF_DPI1 | MT8195_MUTEX_EOF_DPI1,
+ [MUTEX_SOF_DP_INTF0] =
+ MT8195_MUTEX_SOF_DP_INTF0 | MT8195_MUTEX_EOF_DP_INTF0,
+ [MUTEX_SOF_DP_INTF1] =
+ MT8195_MUTEX_SOF_DP_INTF1 | MT8195_MUTEX_EOF_DP_INTF1,
+};
+
static const struct mtk_mutex_data mt2701_mutex_driver_data = {
.mutex_mod = mt2701_mutex_mod,
.mutex_sof = mt2712_mutex_sof,
@@ -351,6 +419,13 @@ static const struct mtk_mutex_data mt8192_mutex_driver_data = {
.mutex_sof_reg = MT8183_MUTEX0_SOF0,
};
+static const struct mtk_mutex_data mt8195_mutex_driver_data = {
+ .mutex_mod = mt8195_mutex_mod,
+ .mutex_sof = mt8195_mutex_sof,
+ .mutex_mod_reg = MT8195_DISP_MUTEX0_MOD0,
+ .mutex_sof_reg = MT8195_DISP_MUTEX0_SOF,
+};
+
struct mtk_mutex *mtk_mutex_get(struct device *dev)
{
struct mtk_mutex_ctx *mtx = dev_get_drvdata(dev);
@@ -423,6 +498,9 @@ void mtk_mutex_add_comp(struct mtk_mutex *mutex,
case DDP_COMPONENT_DPI1:
sof_id = MUTEX_SOF_DPI1;
break;
+ case DDP_COMPONENT_DP_INTF0:
+ sof_id = MUTEX_SOF_DP_INTF0;
+ break;
default:
if (mtx->data->mutex_mod[id] < 32) {
offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg,
@@ -462,6 +540,7 @@ void mtk_mutex_remove_comp(struct mtk_mutex *mutex,
case DDP_COMPONENT_DSI3:
case DDP_COMPONENT_DPI0:
case DDP_COMPONENT_DPI1:
+ case DDP_COMPONENT_DP_INTF0:
writel_relaxed(MUTEX_SOF_SINGLE_MODE,
mtx->regs +
DISP_REG_MUTEX_SOF(mtx->data->mutex_sof_reg,
@@ -587,6 +666,8 @@ static const struct of_device_id mutex_driver_dt_match[] = {
.data = &mt8186_mutex_driver_data},
{ .compatible = "mediatek,mt8192-disp-mutex",
.data = &mt8192_mutex_driver_data},
+ { .compatible = "mediatek,mt8195-disp-mutex",
+ .data = &mt8195_mutex_driver_data},
{},
};
MODULE_DEVICE_TABLE(of, mutex_driver_dt_match);
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [PATCH v20 2/8] soc: mediatek: add mtk-mutex support for mt8195 vdosys0
@ 2022-04-19 9:41 ` jason-jh.lin
0 siblings, 0 replies; 110+ messages in thread
From: jason-jh.lin @ 2022-04-19 9:41 UTC (permalink / raw)
To: Matthias Brugger, Chun-Kuang Hu, AngeloGioacchino Del Regno
Cc: CK Hu, Jason-JH Lin, Nancy Lin, Singo Chang, devicetree,
linux-kernel, dri-devel, linux-mediatek, linux-arm-kernel,
Project_Global_Chrome_Upstream_Group
Add mtk-mutex support for mt8195 vdosys0.
Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
Acked-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Tested-by: Fei Shao <fshao@chromium.org>
---
drivers/soc/mediatek/mtk-mutex.c | 87 ++++++++++++++++++++++++++++++--
1 file changed, 84 insertions(+), 3 deletions(-)
diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c
index aaf8fc1abb43..729ee88035ed 100644
--- a/drivers/soc/mediatek/mtk-mutex.c
+++ b/drivers/soc/mediatek/mtk-mutex.c
@@ -17,6 +17,9 @@
#define MT8183_MUTEX0_MOD0 0x30
#define MT8183_MUTEX0_SOF0 0x2c
+#define MT8195_DISP_MUTEX0_MOD0 0x30
+#define MT8195_DISP_MUTEX0_SOF 0x2c
+
#define DISP_REG_MUTEX_EN(n) (0x20 + 0x20 * (n))
#define DISP_REG_MUTEX(n) (0x24 + 0x20 * (n))
#define DISP_REG_MUTEX_RST(n) (0x28 + 0x20 * (n))
@@ -96,6 +99,20 @@
#define MT8173_MUTEX_MOD_DISP_PWM1 24
#define MT8173_MUTEX_MOD_DISP_OD 25
+#define MT8195_MUTEX_MOD_DISP_OVL0 0
+#define MT8195_MUTEX_MOD_DISP_WDMA0 1
+#define MT8195_MUTEX_MOD_DISP_RDMA0 2
+#define MT8195_MUTEX_MOD_DISP_COLOR0 3
+#define MT8195_MUTEX_MOD_DISP_CCORR0 4
+#define MT8195_MUTEX_MOD_DISP_AAL0 5
+#define MT8195_MUTEX_MOD_DISP_GAMMA0 6
+#define MT8195_MUTEX_MOD_DISP_DITHER0 7
+#define MT8195_MUTEX_MOD_DISP_DSI0 8
+#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0 9
+#define MT8195_MUTEX_MOD_DISP_VPP_MERGE 20
+#define MT8195_MUTEX_MOD_DISP_DP_INTF0 21
+#define MT8195_MUTEX_MOD_DISP_PWM0 27
+
#define MT2712_MUTEX_MOD_DISP_PWM2 10
#define MT2712_MUTEX_MOD_DISP_OVL0 11
#define MT2712_MUTEX_MOD_DISP_OVL1 12
@@ -132,9 +149,21 @@
#define MT8167_MUTEX_SOF_DPI1 3
#define MT8183_MUTEX_SOF_DSI0 1
#define MT8183_MUTEX_SOF_DPI0 2
+#define MT8195_MUTEX_SOF_DSI0 1
+#define MT8195_MUTEX_SOF_DSI1 2
+#define MT8195_MUTEX_SOF_DP_INTF0 3
+#define MT8195_MUTEX_SOF_DP_INTF1 4
+#define MT8195_MUTEX_SOF_DPI0 6 /* for HDMI_TX */
+#define MT8195_MUTEX_SOF_DPI1 5 /* for digital video out */
#define MT8183_MUTEX_EOF_DSI0 (MT8183_MUTEX_SOF_DSI0 << 6)
#define MT8183_MUTEX_EOF_DPI0 (MT8183_MUTEX_SOF_DPI0 << 6)
+#define MT8195_MUTEX_EOF_DSI0 (MT8195_MUTEX_SOF_DSI0 << 7)
+#define MT8195_MUTEX_EOF_DSI1 (MT8195_MUTEX_SOF_DSI1 << 7)
+#define MT8195_MUTEX_EOF_DP_INTF0 (MT8195_MUTEX_SOF_DP_INTF0 << 7)
+#define MT8195_MUTEX_EOF_DP_INTF1 (MT8195_MUTEX_SOF_DP_INTF1 << 7)
+#define MT8195_MUTEX_EOF_DPI0 (MT8195_MUTEX_SOF_DPI0 << 7)
+#define MT8195_MUTEX_EOF_DPI1 (MT8195_MUTEX_SOF_DPI1 << 7)
struct mtk_mutex {
int id;
@@ -149,6 +178,9 @@ enum mtk_mutex_sof_id {
MUTEX_SOF_DPI1,
MUTEX_SOF_DSI2,
MUTEX_SOF_DSI3,
+ MUTEX_SOF_DP_INTF0,
+ MUTEX_SOF_DP_INTF1,
+ DDP_MUTEX_SOF_MAX,
};
struct mtk_mutex_data {
@@ -270,7 +302,23 @@ static const unsigned int mt8192_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_RDMA4] = MT8192_MUTEX_MOD_DISP_RDMA4,
};
-static const unsigned int mt2712_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
+static const unsigned int mt8195_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+ [DDP_COMPONENT_OVL0] = MT8195_MUTEX_MOD_DISP_OVL0,
+ [DDP_COMPONENT_WDMA0] = MT8195_MUTEX_MOD_DISP_WDMA0,
+ [DDP_COMPONENT_RDMA0] = MT8195_MUTEX_MOD_DISP_RDMA0,
+ [DDP_COMPONENT_COLOR0] = MT8195_MUTEX_MOD_DISP_COLOR0,
+ [DDP_COMPONENT_CCORR] = MT8195_MUTEX_MOD_DISP_CCORR0,
+ [DDP_COMPONENT_AAL0] = MT8195_MUTEX_MOD_DISP_AAL0,
+ [DDP_COMPONENT_GAMMA] = MT8195_MUTEX_MOD_DISP_GAMMA0,
+ [DDP_COMPONENT_DITHER] = MT8195_MUTEX_MOD_DISP_DITHER0,
+ [DDP_COMPONENT_MERGE0] = MT8195_MUTEX_MOD_DISP_VPP_MERGE,
+ [DDP_COMPONENT_DSC0] = MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0,
+ [DDP_COMPONENT_DSI0] = MT8195_MUTEX_MOD_DISP_DSI0,
+ [DDP_COMPONENT_PWM0] = MT8195_MUTEX_MOD_DISP_PWM0,
+ [DDP_COMPONENT_DP_INTF0] = MT8195_MUTEX_MOD_DISP_DP_INTF0,
+};
+
+static const unsigned int mt2712_mutex_sof[DDP_MUTEX_SOF_MAX] = {
[MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
[MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0,
[MUTEX_SOF_DSI1] = MUTEX_SOF_DSI1,
@@ -280,7 +328,7 @@ static const unsigned int mt2712_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
[MUTEX_SOF_DSI3] = MUTEX_SOF_DSI3,
};
-static const unsigned int mt8167_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
+static const unsigned int mt8167_mutex_sof[DDP_MUTEX_SOF_MAX] = {
[MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
[MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0,
[MUTEX_SOF_DPI0] = MT8167_MUTEX_SOF_DPI0,
@@ -288,7 +336,7 @@ static const unsigned int mt8167_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
};
/* Add EOF setting so overlay hardware can receive frame done irq */
-static const unsigned int mt8183_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
+static const unsigned int mt8183_mutex_sof[DDP_MUTEX_SOF_MAX] = {
[MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
[MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0 | MT8183_MUTEX_EOF_DSI0,
[MUTEX_SOF_DPI0] = MT8183_MUTEX_SOF_DPI0 | MT8183_MUTEX_EOF_DPI0,
@@ -300,6 +348,26 @@ static const unsigned int mt8186_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
[MUTEX_SOF_DPI0] = MT8186_MUTEX_SOF_DPI0 | MT8186_MUTEX_EOF_DPI0,
};
+/*
+ * To support refresh mode(video mode), DISP_REG_MUTEX_SOF should
+ * select the EOF source and configure the EOF plus timing from the
+ * module that provides the timing signal.
+ * So that MUTEX can not only send a STREAM_DONE event to GCE
+ * but also detect the error at end of frame(EAEOF) when EOF signal
+ * arrives.
+ */
+static const unsigned int mt8195_mutex_sof[DDP_MUTEX_SOF_MAX] = {
+ [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
+ [MUTEX_SOF_DSI0] = MT8195_MUTEX_SOF_DSI0 | MT8195_MUTEX_EOF_DSI0,
+ [MUTEX_SOF_DSI1] = MT8195_MUTEX_SOF_DSI1 | MT8195_MUTEX_EOF_DSI1,
+ [MUTEX_SOF_DPI0] = MT8195_MUTEX_SOF_DPI0 | MT8195_MUTEX_EOF_DPI0,
+ [MUTEX_SOF_DPI1] = MT8195_MUTEX_SOF_DPI1 | MT8195_MUTEX_EOF_DPI1,
+ [MUTEX_SOF_DP_INTF0] =
+ MT8195_MUTEX_SOF_DP_INTF0 | MT8195_MUTEX_EOF_DP_INTF0,
+ [MUTEX_SOF_DP_INTF1] =
+ MT8195_MUTEX_SOF_DP_INTF1 | MT8195_MUTEX_EOF_DP_INTF1,
+};
+
static const struct mtk_mutex_data mt2701_mutex_driver_data = {
.mutex_mod = mt2701_mutex_mod,
.mutex_sof = mt2712_mutex_sof,
@@ -351,6 +419,13 @@ static const struct mtk_mutex_data mt8192_mutex_driver_data = {
.mutex_sof_reg = MT8183_MUTEX0_SOF0,
};
+static const struct mtk_mutex_data mt8195_mutex_driver_data = {
+ .mutex_mod = mt8195_mutex_mod,
+ .mutex_sof = mt8195_mutex_sof,
+ .mutex_mod_reg = MT8195_DISP_MUTEX0_MOD0,
+ .mutex_sof_reg = MT8195_DISP_MUTEX0_SOF,
+};
+
struct mtk_mutex *mtk_mutex_get(struct device *dev)
{
struct mtk_mutex_ctx *mtx = dev_get_drvdata(dev);
@@ -423,6 +498,9 @@ void mtk_mutex_add_comp(struct mtk_mutex *mutex,
case DDP_COMPONENT_DPI1:
sof_id = MUTEX_SOF_DPI1;
break;
+ case DDP_COMPONENT_DP_INTF0:
+ sof_id = MUTEX_SOF_DP_INTF0;
+ break;
default:
if (mtx->data->mutex_mod[id] < 32) {
offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg,
@@ -462,6 +540,7 @@ void mtk_mutex_remove_comp(struct mtk_mutex *mutex,
case DDP_COMPONENT_DSI3:
case DDP_COMPONENT_DPI0:
case DDP_COMPONENT_DPI1:
+ case DDP_COMPONENT_DP_INTF0:
writel_relaxed(MUTEX_SOF_SINGLE_MODE,
mtx->regs +
DISP_REG_MUTEX_SOF(mtx->data->mutex_sof_reg,
@@ -587,6 +666,8 @@ static const struct of_device_id mutex_driver_dt_match[] = {
.data = &mt8186_mutex_driver_data},
{ .compatible = "mediatek,mt8192-disp-mutex",
.data = &mt8192_mutex_driver_data},
+ { .compatible = "mediatek,mt8195-disp-mutex",
+ .data = &mt8195_mutex_driver_data},
{},
};
MODULE_DEVICE_TABLE(of, mutex_driver_dt_match);
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [PATCH v20 3/8] drm/mediatek: add DSC support for mediatek-drm
2022-04-19 9:41 ` jason-jh.lin
(?)
@ 2022-04-19 9:41 ` jason-jh.lin
-1 siblings, 0 replies; 110+ messages in thread
From: jason-jh.lin @ 2022-04-19 9:41 UTC (permalink / raw)
To: Matthias Brugger, Chun-Kuang Hu, AngeloGioacchino Del Regno
Cc: devicetree, Jason-JH Lin, Singo Chang, linux-kernel, dri-devel,
Project_Global_Chrome_Upstream_Group, Nancy Lin, linux-mediatek,
linux-arm-kernel
DSC is designed for real-time systems with real-time compression,
transmission, decompression and display.
The DSC standard is a specification of the algorithms used for
compressing and decompressing image display streams, including
the specification of the syntax and semantics of the compressed
video bit stream.
Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
Acked-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 47 +++++++++++++++++++++
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 +
2 files changed, 48 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index 2e99aee13dfe..68a00b336897 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -40,6 +40,12 @@
#define DITHER_LSB_ERR_SHIFT_G(x) (((x) & 0x7) << 12)
#define DITHER_ADD_LSHIFT_G(x) (((x) & 0x7) << 4)
+#define DISP_REG_DSC_CON 0x0000
+#define DSC_EN BIT(0)
+#define DSC_DUAL_INOUT BIT(2)
+#define DSC_BYPASS BIT(4)
+#define DSC_UFOE_SEL BIT(16)
+
#define DISP_REG_OD_EN 0x0000
#define DISP_REG_OD_CFG 0x0020
#define OD_RELAYMODE BIT(0)
@@ -181,6 +187,36 @@ static void mtk_dither_set(struct device *dev, unsigned int bpc,
DISP_DITHERING, cmdq_pkt);
}
+static void mtk_dsc_config(struct device *dev, unsigned int w,
+ unsigned int h, unsigned int vrefresh,
+ unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
+{
+ struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
+
+ /* dsc bypass mode */
+ mtk_ddp_write_mask(cmdq_pkt, DSC_BYPASS, &priv->cmdq_reg, priv->regs,
+ DISP_REG_DSC_CON, DSC_BYPASS);
+ mtk_ddp_write_mask(cmdq_pkt, DSC_UFOE_SEL, &priv->cmdq_reg, priv->regs,
+ DISP_REG_DSC_CON, DSC_UFOE_SEL);
+ mtk_ddp_write_mask(cmdq_pkt, DSC_DUAL_INOUT, &priv->cmdq_reg, priv->regs,
+ DISP_REG_DSC_CON, DSC_DUAL_INOUT);
+}
+
+static void mtk_dsc_start(struct device *dev)
+{
+ struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
+
+ /* write with mask to reserve the value set in mtk_dsc_config */
+ mtk_ddp_write_mask(NULL, DSC_EN, &priv->cmdq_reg, priv->regs, DISP_REG_DSC_CON, DSC_EN);
+}
+
+static void mtk_dsc_stop(struct device *dev)
+{
+ struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
+
+ writel_relaxed(0x0, priv->regs + DISP_REG_DSC_CON);
+}
+
static void mtk_od_config(struct device *dev, unsigned int w,
unsigned int h, unsigned int vrefresh,
unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
@@ -270,6 +306,14 @@ static const struct mtk_ddp_comp_funcs ddp_dpi = {
.stop = mtk_dpi_stop,
};
+static const struct mtk_ddp_comp_funcs ddp_dsc = {
+ .clk_enable = mtk_ddp_clk_enable,
+ .clk_disable = mtk_ddp_clk_disable,
+ .config = mtk_dsc_config,
+ .start = mtk_dsc_start,
+ .stop = mtk_dsc_stop,
+};
+
static const struct mtk_ddp_comp_funcs ddp_dsi = {
.start = mtk_dsi_ddp_start,
.stop = mtk_dsi_ddp_stop,
@@ -339,6 +383,7 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
[MTK_DISP_CCORR] = "ccorr",
[MTK_DISP_COLOR] = "color",
[MTK_DISP_DITHER] = "dither",
+ [MTK_DISP_DSC] = "dsc",
[MTK_DISP_GAMMA] = "gamma",
[MTK_DISP_MUTEX] = "mutex",
[MTK_DISP_OD] = "od",
@@ -369,6 +414,8 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_DITHER] = { MTK_DISP_DITHER, 0, &ddp_dither },
[DDP_COMPONENT_DPI0] = { MTK_DPI, 0, &ddp_dpi },
[DDP_COMPONENT_DPI1] = { MTK_DPI, 1, &ddp_dpi },
+ [DDP_COMPONENT_DSC0] = { MTK_DISP_DSC, 0, &ddp_dsc },
+ [DDP_COMPONENT_DSC1] = { MTK_DISP_DSC, 1, &ddp_dsc },
[DDP_COMPONENT_DSI0] = { MTK_DSI, 0, &ddp_dsi },
[DDP_COMPONENT_DSI1] = { MTK_DSI, 1, &ddp_dsi },
[DDP_COMPONENT_DSI2] = { MTK_DSI, 2, &ddp_dsi },
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
index ad267bb8fc9b..763725fe72b3 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
@@ -23,6 +23,7 @@ enum mtk_ddp_comp_type {
MTK_DISP_CCORR,
MTK_DISP_COLOR,
MTK_DISP_DITHER,
+ MTK_DISP_DSC,
MTK_DISP_GAMMA,
MTK_DISP_MUTEX,
MTK_DISP_OD,
--
2.18.0
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [PATCH v20 3/8] drm/mediatek: add DSC support for mediatek-drm
@ 2022-04-19 9:41 ` jason-jh.lin
0 siblings, 0 replies; 110+ messages in thread
From: jason-jh.lin @ 2022-04-19 9:41 UTC (permalink / raw)
To: Matthias Brugger, Chun-Kuang Hu, AngeloGioacchino Del Regno
Cc: CK Hu, Jason-JH Lin, Nancy Lin, Singo Chang, devicetree,
linux-kernel, dri-devel, linux-mediatek, linux-arm-kernel,
Project_Global_Chrome_Upstream_Group
DSC is designed for real-time systems with real-time compression,
transmission, decompression and display.
The DSC standard is a specification of the algorithms used for
compressing and decompressing image display streams, including
the specification of the syntax and semantics of the compressed
video bit stream.
Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
Acked-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 47 +++++++++++++++++++++
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 +
2 files changed, 48 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index 2e99aee13dfe..68a00b336897 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -40,6 +40,12 @@
#define DITHER_LSB_ERR_SHIFT_G(x) (((x) & 0x7) << 12)
#define DITHER_ADD_LSHIFT_G(x) (((x) & 0x7) << 4)
+#define DISP_REG_DSC_CON 0x0000
+#define DSC_EN BIT(0)
+#define DSC_DUAL_INOUT BIT(2)
+#define DSC_BYPASS BIT(4)
+#define DSC_UFOE_SEL BIT(16)
+
#define DISP_REG_OD_EN 0x0000
#define DISP_REG_OD_CFG 0x0020
#define OD_RELAYMODE BIT(0)
@@ -181,6 +187,36 @@ static void mtk_dither_set(struct device *dev, unsigned int bpc,
DISP_DITHERING, cmdq_pkt);
}
+static void mtk_dsc_config(struct device *dev, unsigned int w,
+ unsigned int h, unsigned int vrefresh,
+ unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
+{
+ struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
+
+ /* dsc bypass mode */
+ mtk_ddp_write_mask(cmdq_pkt, DSC_BYPASS, &priv->cmdq_reg, priv->regs,
+ DISP_REG_DSC_CON, DSC_BYPASS);
+ mtk_ddp_write_mask(cmdq_pkt, DSC_UFOE_SEL, &priv->cmdq_reg, priv->regs,
+ DISP_REG_DSC_CON, DSC_UFOE_SEL);
+ mtk_ddp_write_mask(cmdq_pkt, DSC_DUAL_INOUT, &priv->cmdq_reg, priv->regs,
+ DISP_REG_DSC_CON, DSC_DUAL_INOUT);
+}
+
+static void mtk_dsc_start(struct device *dev)
+{
+ struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
+
+ /* write with mask to reserve the value set in mtk_dsc_config */
+ mtk_ddp_write_mask(NULL, DSC_EN, &priv->cmdq_reg, priv->regs, DISP_REG_DSC_CON, DSC_EN);
+}
+
+static void mtk_dsc_stop(struct device *dev)
+{
+ struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
+
+ writel_relaxed(0x0, priv->regs + DISP_REG_DSC_CON);
+}
+
static void mtk_od_config(struct device *dev, unsigned int w,
unsigned int h, unsigned int vrefresh,
unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
@@ -270,6 +306,14 @@ static const struct mtk_ddp_comp_funcs ddp_dpi = {
.stop = mtk_dpi_stop,
};
+static const struct mtk_ddp_comp_funcs ddp_dsc = {
+ .clk_enable = mtk_ddp_clk_enable,
+ .clk_disable = mtk_ddp_clk_disable,
+ .config = mtk_dsc_config,
+ .start = mtk_dsc_start,
+ .stop = mtk_dsc_stop,
+};
+
static const struct mtk_ddp_comp_funcs ddp_dsi = {
.start = mtk_dsi_ddp_start,
.stop = mtk_dsi_ddp_stop,
@@ -339,6 +383,7 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
[MTK_DISP_CCORR] = "ccorr",
[MTK_DISP_COLOR] = "color",
[MTK_DISP_DITHER] = "dither",
+ [MTK_DISP_DSC] = "dsc",
[MTK_DISP_GAMMA] = "gamma",
[MTK_DISP_MUTEX] = "mutex",
[MTK_DISP_OD] = "od",
@@ -369,6 +414,8 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_DITHER] = { MTK_DISP_DITHER, 0, &ddp_dither },
[DDP_COMPONENT_DPI0] = { MTK_DPI, 0, &ddp_dpi },
[DDP_COMPONENT_DPI1] = { MTK_DPI, 1, &ddp_dpi },
+ [DDP_COMPONENT_DSC0] = { MTK_DISP_DSC, 0, &ddp_dsc },
+ [DDP_COMPONENT_DSC1] = { MTK_DISP_DSC, 1, &ddp_dsc },
[DDP_COMPONENT_DSI0] = { MTK_DSI, 0, &ddp_dsi },
[DDP_COMPONENT_DSI1] = { MTK_DSI, 1, &ddp_dsi },
[DDP_COMPONENT_DSI2] = { MTK_DSI, 2, &ddp_dsi },
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
index ad267bb8fc9b..763725fe72b3 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
@@ -23,6 +23,7 @@ enum mtk_ddp_comp_type {
MTK_DISP_CCORR,
MTK_DISP_COLOR,
MTK_DISP_DITHER,
+ MTK_DISP_DSC,
MTK_DISP_GAMMA,
MTK_DISP_MUTEX,
MTK_DISP_OD,
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [PATCH v20 3/8] drm/mediatek: add DSC support for mediatek-drm
@ 2022-04-19 9:41 ` jason-jh.lin
0 siblings, 0 replies; 110+ messages in thread
From: jason-jh.lin @ 2022-04-19 9:41 UTC (permalink / raw)
To: Matthias Brugger, Chun-Kuang Hu, AngeloGioacchino Del Regno
Cc: CK Hu, Jason-JH Lin, Nancy Lin, Singo Chang, devicetree,
linux-kernel, dri-devel, linux-mediatek, linux-arm-kernel,
Project_Global_Chrome_Upstream_Group
DSC is designed for real-time systems with real-time compression,
transmission, decompression and display.
The DSC standard is a specification of the algorithms used for
compressing and decompressing image display streams, including
the specification of the syntax and semantics of the compressed
video bit stream.
Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
Acked-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 47 +++++++++++++++++++++
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 +
2 files changed, 48 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index 2e99aee13dfe..68a00b336897 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -40,6 +40,12 @@
#define DITHER_LSB_ERR_SHIFT_G(x) (((x) & 0x7) << 12)
#define DITHER_ADD_LSHIFT_G(x) (((x) & 0x7) << 4)
+#define DISP_REG_DSC_CON 0x0000
+#define DSC_EN BIT(0)
+#define DSC_DUAL_INOUT BIT(2)
+#define DSC_BYPASS BIT(4)
+#define DSC_UFOE_SEL BIT(16)
+
#define DISP_REG_OD_EN 0x0000
#define DISP_REG_OD_CFG 0x0020
#define OD_RELAYMODE BIT(0)
@@ -181,6 +187,36 @@ static void mtk_dither_set(struct device *dev, unsigned int bpc,
DISP_DITHERING, cmdq_pkt);
}
+static void mtk_dsc_config(struct device *dev, unsigned int w,
+ unsigned int h, unsigned int vrefresh,
+ unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
+{
+ struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
+
+ /* dsc bypass mode */
+ mtk_ddp_write_mask(cmdq_pkt, DSC_BYPASS, &priv->cmdq_reg, priv->regs,
+ DISP_REG_DSC_CON, DSC_BYPASS);
+ mtk_ddp_write_mask(cmdq_pkt, DSC_UFOE_SEL, &priv->cmdq_reg, priv->regs,
+ DISP_REG_DSC_CON, DSC_UFOE_SEL);
+ mtk_ddp_write_mask(cmdq_pkt, DSC_DUAL_INOUT, &priv->cmdq_reg, priv->regs,
+ DISP_REG_DSC_CON, DSC_DUAL_INOUT);
+}
+
+static void mtk_dsc_start(struct device *dev)
+{
+ struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
+
+ /* write with mask to reserve the value set in mtk_dsc_config */
+ mtk_ddp_write_mask(NULL, DSC_EN, &priv->cmdq_reg, priv->regs, DISP_REG_DSC_CON, DSC_EN);
+}
+
+static void mtk_dsc_stop(struct device *dev)
+{
+ struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
+
+ writel_relaxed(0x0, priv->regs + DISP_REG_DSC_CON);
+}
+
static void mtk_od_config(struct device *dev, unsigned int w,
unsigned int h, unsigned int vrefresh,
unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
@@ -270,6 +306,14 @@ static const struct mtk_ddp_comp_funcs ddp_dpi = {
.stop = mtk_dpi_stop,
};
+static const struct mtk_ddp_comp_funcs ddp_dsc = {
+ .clk_enable = mtk_ddp_clk_enable,
+ .clk_disable = mtk_ddp_clk_disable,
+ .config = mtk_dsc_config,
+ .start = mtk_dsc_start,
+ .stop = mtk_dsc_stop,
+};
+
static const struct mtk_ddp_comp_funcs ddp_dsi = {
.start = mtk_dsi_ddp_start,
.stop = mtk_dsi_ddp_stop,
@@ -339,6 +383,7 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
[MTK_DISP_CCORR] = "ccorr",
[MTK_DISP_COLOR] = "color",
[MTK_DISP_DITHER] = "dither",
+ [MTK_DISP_DSC] = "dsc",
[MTK_DISP_GAMMA] = "gamma",
[MTK_DISP_MUTEX] = "mutex",
[MTK_DISP_OD] = "od",
@@ -369,6 +414,8 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_DITHER] = { MTK_DISP_DITHER, 0, &ddp_dither },
[DDP_COMPONENT_DPI0] = { MTK_DPI, 0, &ddp_dpi },
[DDP_COMPONENT_DPI1] = { MTK_DPI, 1, &ddp_dpi },
+ [DDP_COMPONENT_DSC0] = { MTK_DISP_DSC, 0, &ddp_dsc },
+ [DDP_COMPONENT_DSC1] = { MTK_DISP_DSC, 1, &ddp_dsc },
[DDP_COMPONENT_DSI0] = { MTK_DSI, 0, &ddp_dsi },
[DDP_COMPONENT_DSI1] = { MTK_DSI, 1, &ddp_dsi },
[DDP_COMPONENT_DSI2] = { MTK_DSI, 2, &ddp_dsi },
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
index ad267bb8fc9b..763725fe72b3 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
@@ -23,6 +23,7 @@ enum mtk_ddp_comp_type {
MTK_DISP_CCORR,
MTK_DISP_COLOR,
MTK_DISP_DITHER,
+ MTK_DISP_DSC,
MTK_DISP_GAMMA,
MTK_DISP_MUTEX,
MTK_DISP_OD,
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [PATCH v20 4/8] drm/mediatek: add MERGE support for mediatek-drm
2022-04-19 9:41 ` jason-jh.lin
(?)
@ 2022-04-19 9:41 ` jason-jh.lin
-1 siblings, 0 replies; 110+ messages in thread
From: jason-jh.lin @ 2022-04-19 9:41 UTC (permalink / raw)
To: Matthias Brugger, Chun-Kuang Hu, AngeloGioacchino Del Regno
Cc: devicetree, Jason-JH Lin, Singo Chang, linux-kernel, dri-devel,
Project_Global_Chrome_Upstream_Group, Nancy Lin, linux-mediatek,
linux-arm-kernel
Add MERGE engine file:
MERGE module is used to merge two slice-per-line inputs
into one side-by-side output.
Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
Acked-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
---
drivers/gpu/drm/mediatek/Makefile | 1 +
drivers/gpu/drm/mediatek/mtk_disp_drv.h | 8 +
drivers/gpu/drm/mediatek/mtk_disp_merge.c | 246 ++++++++++++++++++++
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 16 ++
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 +
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 4 +-
drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 +
7 files changed, 276 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_merge.c
diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile
index 29098d7c8307..a38e88e82d12 100644
--- a/drivers/gpu/drm/mediatek/Makefile
+++ b/drivers/gpu/drm/mediatek/Makefile
@@ -4,6 +4,7 @@ mediatek-drm-y := mtk_disp_aal.o \
mtk_disp_ccorr.o \
mtk_disp_color.o \
mtk_disp_gamma.o \
+ mtk_disp_merge.o \
mtk_disp_ovl.o \
mtk_disp_rdma.o \
mtk_drm_crtc.o \
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
index 86c3068894b1..a33b13fe2b6e 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
@@ -55,6 +55,14 @@ void mtk_gamma_set_common(void __iomem *regs, struct drm_crtc_state *state);
void mtk_gamma_start(struct device *dev);
void mtk_gamma_stop(struct device *dev);
+int mtk_merge_clk_enable(struct device *dev);
+void mtk_merge_clk_disable(struct device *dev);
+void mtk_merge_config(struct device *dev, unsigned int width,
+ unsigned int height, unsigned int vrefresh,
+ unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
+void mtk_merge_start(struct device *dev);
+void mtk_merge_stop(struct device *dev);
+
void mtk_ovl_bgclr_in_on(struct device *dev);
void mtk_ovl_bgclr_in_off(struct device *dev);
void mtk_ovl_bypass_shadow(struct device *dev);
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_merge.c b/drivers/gpu/drm/mediatek/mtk_disp_merge.c
new file mode 100644
index 000000000000..45face638153
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_disp_merge.c
@@ -0,0 +1,246 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ */
+
+#include <linux/clk.h>
+#include <linux/component.h>
+#include <linux/of_device.h>
+#include <linux/of_irq.h>
+#include <linux/platform_device.h>
+#include <linux/soc/mediatek/mtk-cmdq.h>
+
+#include "mtk_drm_ddp_comp.h"
+#include "mtk_drm_drv.h"
+#include "mtk_disp_drv.h"
+
+#define DISP_REG_MERGE_CTRL 0x000
+#define MERGE_EN 1
+#define DISP_REG_MERGE_CFG_0 0x010
+#define DISP_REG_MERGE_CFG_4 0x020
+#define DISP_REG_MERGE_CFG_10 0x038
+/* no swap */
+#define SWAP_MODE 0
+#define FLD_SWAP_MODE GENMASK(4, 0)
+#define DISP_REG_MERGE_CFG_12 0x040
+#define CFG_10_10_1PI_2PO_BUF_MODE 6
+#define CFG_10_10_2PI_2PO_BUF_MODE 8
+#define FLD_CFG_MERGE_MODE GENMASK(4, 0)
+#define DISP_REG_MERGE_CFG_24 0x070
+#define DISP_REG_MERGE_CFG_25 0x074
+#define DISP_REG_MERGE_CFG_36 0x0a0
+#define ULTRA_EN BIT(0)
+#define PREULTRA_EN BIT(4)
+#define DISP_REG_MERGE_CFG_37 0x0a4
+/* 0: Off, 1: SRAM0, 2: SRAM1, 3: SRAM0 + SRAM1 */
+#define BUFFER_MODE 3
+#define FLD_BUFFER_MODE GENMASK(1, 0)
+/*
+ * For the ultra and preultra settings, 6us ~ 9us is experience value
+ * and the maximum frequency of mmsys clock is 594MHz.
+ */
+#define DISP_REG_MERGE_CFG_40 0x0b0
+/* 6 us, 594M pixel/sec */
+#define ULTRA_TH_LOW (6 * 594)
+/* 8 us, 594M pixel/sec */
+#define ULTRA_TH_HIGH (8 * 594)
+#define FLD_ULTRA_TH_LOW GENMASK(15, 0)
+#define FLD_ULTRA_TH_HIGH GENMASK(31, 16)
+#define DISP_REG_MERGE_CFG_41 0x0b4
+/* 8 us, 594M pixel/sec */
+#define PREULTRA_TH_LOW (8 * 594)
+/* 9 us, 594M pixel/sec */
+#define PREULTRA_TH_HIGH (9 * 594)
+#define FLD_PREULTRA_TH_LOW GENMASK(15, 0)
+#define FLD_PREULTRA_TH_HIGH GENMASK(31, 16)
+
+struct mtk_disp_merge {
+ void __iomem *regs;
+ struct clk *clk;
+ struct clk *async_clk;
+ struct cmdq_client_reg cmdq_reg;
+ bool fifo_en;
+};
+
+void mtk_merge_start(struct device *dev)
+{
+ struct mtk_disp_merge *priv = dev_get_drvdata(dev);
+
+ writel(MERGE_EN, priv->regs + DISP_REG_MERGE_CTRL);
+}
+
+void mtk_merge_stop(struct device *dev)
+{
+ struct mtk_disp_merge *priv = dev_get_drvdata(dev);
+
+ writel(0x0, priv->regs + DISP_REG_MERGE_CTRL);
+}
+
+static void mtk_merge_fifo_setting(struct mtk_disp_merge *priv,
+ struct cmdq_pkt *cmdq_pkt)
+{
+ mtk_ddp_write(cmdq_pkt, ULTRA_EN | PREULTRA_EN,
+ &priv->cmdq_reg, priv->regs, DISP_REG_MERGE_CFG_36);
+
+ mtk_ddp_write_mask(cmdq_pkt, BUFFER_MODE,
+ &priv->cmdq_reg, priv->regs, DISP_REG_MERGE_CFG_37,
+ FLD_BUFFER_MODE);
+
+ mtk_ddp_write_mask(cmdq_pkt, ULTRA_TH_LOW | ULTRA_TH_HIGH << 16,
+ &priv->cmdq_reg, priv->regs, DISP_REG_MERGE_CFG_40,
+ FLD_ULTRA_TH_LOW | FLD_ULTRA_TH_HIGH);
+
+ mtk_ddp_write_mask(cmdq_pkt, PREULTRA_TH_LOW | PREULTRA_TH_HIGH << 16,
+ &priv->cmdq_reg, priv->regs, DISP_REG_MERGE_CFG_41,
+ FLD_PREULTRA_TH_LOW | FLD_PREULTRA_TH_HIGH);
+}
+
+void mtk_merge_config(struct device *dev, unsigned int w,
+ unsigned int h, unsigned int vrefresh,
+ unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
+{
+ struct mtk_disp_merge *priv = dev_get_drvdata(dev);
+ unsigned int mode = CFG_10_10_1PI_2PO_BUF_MODE;
+
+ if (!h || !w) {
+ dev_err(dev, "%s: input width(%d) or height(%d) is invalid\n", __func__, w, h);
+ return;
+ }
+
+ if (priv->fifo_en) {
+ mtk_merge_fifo_setting(priv, cmdq_pkt);
+ mode = CFG_10_10_2PI_2PO_BUF_MODE;
+ }
+
+ mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs,
+ DISP_REG_MERGE_CFG_0);
+ mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs,
+ DISP_REG_MERGE_CFG_4);
+ mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs,
+ DISP_REG_MERGE_CFG_24);
+ mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs,
+ DISP_REG_MERGE_CFG_25);
+ mtk_ddp_write_mask(cmdq_pkt, SWAP_MODE, &priv->cmdq_reg, priv->regs,
+ DISP_REG_MERGE_CFG_10, FLD_SWAP_MODE);
+ mtk_ddp_write_mask(cmdq_pkt, mode, &priv->cmdq_reg, priv->regs,
+ DISP_REG_MERGE_CFG_12, FLD_CFG_MERGE_MODE);
+}
+
+int mtk_merge_clk_enable(struct device *dev)
+{
+ int ret = 0;
+ struct mtk_disp_merge *priv = dev_get_drvdata(dev);
+
+ ret = clk_prepare_enable(priv->clk);
+ if (ret) {
+ dev_err(dev, "merge clk prepare enable failed\n");
+ return ret;
+ }
+
+ ret = clk_prepare_enable(priv->async_clk);
+ if (ret) {
+ /* should clean up the state of priv->clk */
+ clk_disable_unprepare(priv->clk);
+
+ dev_err(dev, "async clk prepare enable failed\n");
+ return ret;
+ }
+
+ return ret;
+}
+
+void mtk_merge_clk_disable(struct device *dev)
+{
+ struct mtk_disp_merge *priv = dev_get_drvdata(dev);
+
+ clk_disable_unprepare(priv->async_clk);
+ clk_disable_unprepare(priv->clk);
+}
+
+static int mtk_disp_merge_bind(struct device *dev, struct device *master,
+ void *data)
+{
+ return 0;
+}
+
+static void mtk_disp_merge_unbind(struct device *dev, struct device *master,
+ void *data)
+{
+}
+
+static const struct component_ops mtk_disp_merge_component_ops = {
+ .bind = mtk_disp_merge_bind,
+ .unbind = mtk_disp_merge_unbind,
+};
+
+static int mtk_disp_merge_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct resource *res;
+ struct mtk_disp_merge *priv;
+ int ret;
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ priv->regs = devm_ioremap_resource(dev, res);
+ if (IS_ERR(priv->regs)) {
+ dev_err(dev, "failed to ioremap merge\n");
+ return PTR_ERR(priv->regs);
+ }
+
+ priv->clk = devm_clk_get(dev, NULL);
+ if (IS_ERR(priv->clk)) {
+ dev_err(dev, "failed to get merge clk\n");
+ return PTR_ERR(priv->clk);
+ }
+
+ priv->async_clk = devm_clk_get_optional(dev, "merge_async");
+ if (IS_ERR(priv->async_clk)) {
+ dev_err(dev, "failed to get merge async clock\n");
+ return PTR_ERR(priv->async_clk);
+ }
+
+#if IS_REACHABLE(CONFIG_MTK_CMDQ)
+ ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0);
+ if (ret)
+ dev_dbg(dev, "get mediatek,gce-client-reg fail!\n");
+#endif
+
+ priv->fifo_en = of_property_read_bool(dev->of_node,
+ "mediatek,merge-fifo-en");
+
+ platform_set_drvdata(pdev, priv);
+
+ ret = component_add(dev, &mtk_disp_merge_component_ops);
+ if (ret != 0)
+ dev_err(dev, "Failed to add component: %d\n", ret);
+
+ return ret;
+}
+
+static int mtk_disp_merge_remove(struct platform_device *pdev)
+{
+ component_del(&pdev->dev, &mtk_disp_merge_component_ops);
+
+ return 0;
+}
+
+static const struct of_device_id mtk_disp_merge_driver_dt_match[] = {
+ { .compatible = "mediatek,mt8195-disp-merge", },
+ {},
+};
+
+MODULE_DEVICE_TABLE(of, mtk_disp_merge_driver_dt_match);
+
+struct platform_driver mtk_disp_merge_driver = {
+ .probe = mtk_disp_merge_probe,
+ .remove = mtk_disp_merge_remove,
+ .driver = {
+ .name = "mediatek-disp-merge",
+ .owner = THIS_MODULE,
+ .of_match_table = mtk_disp_merge_driver_dt_match,
+ },
+};
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index 68a00b336897..f683e768d61b 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -328,6 +328,14 @@ static const struct mtk_ddp_comp_funcs ddp_gamma = {
.stop = mtk_gamma_stop,
};
+static const struct mtk_ddp_comp_funcs ddp_merge = {
+ .clk_enable = mtk_merge_clk_enable,
+ .clk_disable = mtk_merge_clk_disable,
+ .start = mtk_merge_start,
+ .stop = mtk_merge_stop,
+ .config = mtk_merge_config,
+};
+
static const struct mtk_ddp_comp_funcs ddp_od = {
.clk_enable = mtk_ddp_clk_enable,
.clk_disable = mtk_ddp_clk_disable,
@@ -385,6 +393,7 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
[MTK_DISP_DITHER] = "dither",
[MTK_DISP_DSC] = "dsc",
[MTK_DISP_GAMMA] = "gamma",
+ [MTK_DISP_MERGE] = "merge",
[MTK_DISP_MUTEX] = "mutex",
[MTK_DISP_OD] = "od",
[MTK_DISP_OVL] = "ovl",
@@ -421,6 +430,12 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_DSI2] = { MTK_DSI, 2, &ddp_dsi },
[DDP_COMPONENT_DSI3] = { MTK_DSI, 3, &ddp_dsi },
[DDP_COMPONENT_GAMMA] = { MTK_DISP_GAMMA, 0, &ddp_gamma },
+ [DDP_COMPONENT_MERGE0] = { MTK_DISP_MERGE, 0, &ddp_merge },
+ [DDP_COMPONENT_MERGE1] = { MTK_DISP_MERGE, 1, &ddp_merge },
+ [DDP_COMPONENT_MERGE2] = { MTK_DISP_MERGE, 2, &ddp_merge },
+ [DDP_COMPONENT_MERGE3] = { MTK_DISP_MERGE, 3, &ddp_merge },
+ [DDP_COMPONENT_MERGE4] = { MTK_DISP_MERGE, 4, &ddp_merge },
+ [DDP_COMPONENT_MERGE5] = { MTK_DISP_MERGE, 5, &ddp_merge },
[DDP_COMPONENT_OD0] = { MTK_DISP_OD, 0, &ddp_od },
[DDP_COMPONENT_OD1] = { MTK_DISP_OD, 1, &ddp_od },
[DDP_COMPONENT_OVL0] = { MTK_DISP_OVL, 0, &ddp_ovl },
@@ -523,6 +538,7 @@ int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp,
type == MTK_DISP_CCORR ||
type == MTK_DISP_COLOR ||
type == MTK_DISP_GAMMA ||
+ type == MTK_DISP_MERGE ||
type == MTK_DISP_OVL ||
type == MTK_DISP_OVL_2L ||
type == MTK_DISP_PWM ||
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
index 763725fe72b3..09ac9496547d 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
@@ -25,6 +25,7 @@ enum mtk_ddp_comp_type {
MTK_DISP_DITHER,
MTK_DISP_DSC,
MTK_DISP_GAMMA,
+ MTK_DISP_MERGE,
MTK_DISP_MUTEX,
MTK_DISP_OD,
MTK_DISP_OVL,
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index 247c6ff277ef..f54b650a2ea1 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -597,7 +597,7 @@ static int mtk_drm_probe(struct platform_device *pdev)
private->comp_node[comp_id] = of_node_get(node);
/*
- * Currently only the AAL, CCORR, COLOR, GAMMA, OVL, RDMA, DSI, and DPI
+ * Currently only the AAL, CCORR, COLOR, GAMMA, MERGE, OVL, RDMA, DSI, and DPI
* blocks have separate component platform drivers and initialize their own
* DDP component structure. The others are initialized here.
*/
@@ -605,6 +605,7 @@ static int mtk_drm_probe(struct platform_device *pdev)
comp_type == MTK_DISP_CCORR ||
comp_type == MTK_DISP_COLOR ||
comp_type == MTK_DISP_GAMMA ||
+ comp_type == MTK_DISP_MERGE ||
comp_type == MTK_DISP_OVL ||
comp_type == MTK_DISP_OVL_2L ||
comp_type == MTK_DISP_RDMA ||
@@ -703,6 +704,7 @@ static struct platform_driver * const mtk_drm_drivers[] = {
&mtk_disp_ccorr_driver,
&mtk_disp_color_driver,
&mtk_disp_gamma_driver,
+ &mtk_disp_merge_driver,
&mtk_disp_ovl_driver,
&mtk_disp_rdma_driver,
&mtk_dpi_driver,
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
index 3e7d1e6fbe01..a58cebd01d35 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
@@ -50,6 +50,7 @@ extern struct platform_driver mtk_disp_aal_driver;
extern struct platform_driver mtk_disp_ccorr_driver;
extern struct platform_driver mtk_disp_color_driver;
extern struct platform_driver mtk_disp_gamma_driver;
+extern struct platform_driver mtk_disp_merge_driver;
extern struct platform_driver mtk_disp_ovl_driver;
extern struct platform_driver mtk_disp_rdma_driver;
extern struct platform_driver mtk_dpi_driver;
--
2.18.0
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [PATCH v20 4/8] drm/mediatek: add MERGE support for mediatek-drm
@ 2022-04-19 9:41 ` jason-jh.lin
0 siblings, 0 replies; 110+ messages in thread
From: jason-jh.lin @ 2022-04-19 9:41 UTC (permalink / raw)
To: Matthias Brugger, Chun-Kuang Hu, AngeloGioacchino Del Regno
Cc: CK Hu, Jason-JH Lin, Nancy Lin, Singo Chang, devicetree,
linux-kernel, dri-devel, linux-mediatek, linux-arm-kernel,
Project_Global_Chrome_Upstream_Group
Add MERGE engine file:
MERGE module is used to merge two slice-per-line inputs
into one side-by-side output.
Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
Acked-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
---
drivers/gpu/drm/mediatek/Makefile | 1 +
drivers/gpu/drm/mediatek/mtk_disp_drv.h | 8 +
drivers/gpu/drm/mediatek/mtk_disp_merge.c | 246 ++++++++++++++++++++
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 16 ++
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 +
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 4 +-
drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 +
7 files changed, 276 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_merge.c
diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile
index 29098d7c8307..a38e88e82d12 100644
--- a/drivers/gpu/drm/mediatek/Makefile
+++ b/drivers/gpu/drm/mediatek/Makefile
@@ -4,6 +4,7 @@ mediatek-drm-y := mtk_disp_aal.o \
mtk_disp_ccorr.o \
mtk_disp_color.o \
mtk_disp_gamma.o \
+ mtk_disp_merge.o \
mtk_disp_ovl.o \
mtk_disp_rdma.o \
mtk_drm_crtc.o \
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
index 86c3068894b1..a33b13fe2b6e 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
@@ -55,6 +55,14 @@ void mtk_gamma_set_common(void __iomem *regs, struct drm_crtc_state *state);
void mtk_gamma_start(struct device *dev);
void mtk_gamma_stop(struct device *dev);
+int mtk_merge_clk_enable(struct device *dev);
+void mtk_merge_clk_disable(struct device *dev);
+void mtk_merge_config(struct device *dev, unsigned int width,
+ unsigned int height, unsigned int vrefresh,
+ unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
+void mtk_merge_start(struct device *dev);
+void mtk_merge_stop(struct device *dev);
+
void mtk_ovl_bgclr_in_on(struct device *dev);
void mtk_ovl_bgclr_in_off(struct device *dev);
void mtk_ovl_bypass_shadow(struct device *dev);
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_merge.c b/drivers/gpu/drm/mediatek/mtk_disp_merge.c
new file mode 100644
index 000000000000..45face638153
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_disp_merge.c
@@ -0,0 +1,246 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ */
+
+#include <linux/clk.h>
+#include <linux/component.h>
+#include <linux/of_device.h>
+#include <linux/of_irq.h>
+#include <linux/platform_device.h>
+#include <linux/soc/mediatek/mtk-cmdq.h>
+
+#include "mtk_drm_ddp_comp.h"
+#include "mtk_drm_drv.h"
+#include "mtk_disp_drv.h"
+
+#define DISP_REG_MERGE_CTRL 0x000
+#define MERGE_EN 1
+#define DISP_REG_MERGE_CFG_0 0x010
+#define DISP_REG_MERGE_CFG_4 0x020
+#define DISP_REG_MERGE_CFG_10 0x038
+/* no swap */
+#define SWAP_MODE 0
+#define FLD_SWAP_MODE GENMASK(4, 0)
+#define DISP_REG_MERGE_CFG_12 0x040
+#define CFG_10_10_1PI_2PO_BUF_MODE 6
+#define CFG_10_10_2PI_2PO_BUF_MODE 8
+#define FLD_CFG_MERGE_MODE GENMASK(4, 0)
+#define DISP_REG_MERGE_CFG_24 0x070
+#define DISP_REG_MERGE_CFG_25 0x074
+#define DISP_REG_MERGE_CFG_36 0x0a0
+#define ULTRA_EN BIT(0)
+#define PREULTRA_EN BIT(4)
+#define DISP_REG_MERGE_CFG_37 0x0a4
+/* 0: Off, 1: SRAM0, 2: SRAM1, 3: SRAM0 + SRAM1 */
+#define BUFFER_MODE 3
+#define FLD_BUFFER_MODE GENMASK(1, 0)
+/*
+ * For the ultra and preultra settings, 6us ~ 9us is experience value
+ * and the maximum frequency of mmsys clock is 594MHz.
+ */
+#define DISP_REG_MERGE_CFG_40 0x0b0
+/* 6 us, 594M pixel/sec */
+#define ULTRA_TH_LOW (6 * 594)
+/* 8 us, 594M pixel/sec */
+#define ULTRA_TH_HIGH (8 * 594)
+#define FLD_ULTRA_TH_LOW GENMASK(15, 0)
+#define FLD_ULTRA_TH_HIGH GENMASK(31, 16)
+#define DISP_REG_MERGE_CFG_41 0x0b4
+/* 8 us, 594M pixel/sec */
+#define PREULTRA_TH_LOW (8 * 594)
+/* 9 us, 594M pixel/sec */
+#define PREULTRA_TH_HIGH (9 * 594)
+#define FLD_PREULTRA_TH_LOW GENMASK(15, 0)
+#define FLD_PREULTRA_TH_HIGH GENMASK(31, 16)
+
+struct mtk_disp_merge {
+ void __iomem *regs;
+ struct clk *clk;
+ struct clk *async_clk;
+ struct cmdq_client_reg cmdq_reg;
+ bool fifo_en;
+};
+
+void mtk_merge_start(struct device *dev)
+{
+ struct mtk_disp_merge *priv = dev_get_drvdata(dev);
+
+ writel(MERGE_EN, priv->regs + DISP_REG_MERGE_CTRL);
+}
+
+void mtk_merge_stop(struct device *dev)
+{
+ struct mtk_disp_merge *priv = dev_get_drvdata(dev);
+
+ writel(0x0, priv->regs + DISP_REG_MERGE_CTRL);
+}
+
+static void mtk_merge_fifo_setting(struct mtk_disp_merge *priv,
+ struct cmdq_pkt *cmdq_pkt)
+{
+ mtk_ddp_write(cmdq_pkt, ULTRA_EN | PREULTRA_EN,
+ &priv->cmdq_reg, priv->regs, DISP_REG_MERGE_CFG_36);
+
+ mtk_ddp_write_mask(cmdq_pkt, BUFFER_MODE,
+ &priv->cmdq_reg, priv->regs, DISP_REG_MERGE_CFG_37,
+ FLD_BUFFER_MODE);
+
+ mtk_ddp_write_mask(cmdq_pkt, ULTRA_TH_LOW | ULTRA_TH_HIGH << 16,
+ &priv->cmdq_reg, priv->regs, DISP_REG_MERGE_CFG_40,
+ FLD_ULTRA_TH_LOW | FLD_ULTRA_TH_HIGH);
+
+ mtk_ddp_write_mask(cmdq_pkt, PREULTRA_TH_LOW | PREULTRA_TH_HIGH << 16,
+ &priv->cmdq_reg, priv->regs, DISP_REG_MERGE_CFG_41,
+ FLD_PREULTRA_TH_LOW | FLD_PREULTRA_TH_HIGH);
+}
+
+void mtk_merge_config(struct device *dev, unsigned int w,
+ unsigned int h, unsigned int vrefresh,
+ unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
+{
+ struct mtk_disp_merge *priv = dev_get_drvdata(dev);
+ unsigned int mode = CFG_10_10_1PI_2PO_BUF_MODE;
+
+ if (!h || !w) {
+ dev_err(dev, "%s: input width(%d) or height(%d) is invalid\n", __func__, w, h);
+ return;
+ }
+
+ if (priv->fifo_en) {
+ mtk_merge_fifo_setting(priv, cmdq_pkt);
+ mode = CFG_10_10_2PI_2PO_BUF_MODE;
+ }
+
+ mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs,
+ DISP_REG_MERGE_CFG_0);
+ mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs,
+ DISP_REG_MERGE_CFG_4);
+ mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs,
+ DISP_REG_MERGE_CFG_24);
+ mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs,
+ DISP_REG_MERGE_CFG_25);
+ mtk_ddp_write_mask(cmdq_pkt, SWAP_MODE, &priv->cmdq_reg, priv->regs,
+ DISP_REG_MERGE_CFG_10, FLD_SWAP_MODE);
+ mtk_ddp_write_mask(cmdq_pkt, mode, &priv->cmdq_reg, priv->regs,
+ DISP_REG_MERGE_CFG_12, FLD_CFG_MERGE_MODE);
+}
+
+int mtk_merge_clk_enable(struct device *dev)
+{
+ int ret = 0;
+ struct mtk_disp_merge *priv = dev_get_drvdata(dev);
+
+ ret = clk_prepare_enable(priv->clk);
+ if (ret) {
+ dev_err(dev, "merge clk prepare enable failed\n");
+ return ret;
+ }
+
+ ret = clk_prepare_enable(priv->async_clk);
+ if (ret) {
+ /* should clean up the state of priv->clk */
+ clk_disable_unprepare(priv->clk);
+
+ dev_err(dev, "async clk prepare enable failed\n");
+ return ret;
+ }
+
+ return ret;
+}
+
+void mtk_merge_clk_disable(struct device *dev)
+{
+ struct mtk_disp_merge *priv = dev_get_drvdata(dev);
+
+ clk_disable_unprepare(priv->async_clk);
+ clk_disable_unprepare(priv->clk);
+}
+
+static int mtk_disp_merge_bind(struct device *dev, struct device *master,
+ void *data)
+{
+ return 0;
+}
+
+static void mtk_disp_merge_unbind(struct device *dev, struct device *master,
+ void *data)
+{
+}
+
+static const struct component_ops mtk_disp_merge_component_ops = {
+ .bind = mtk_disp_merge_bind,
+ .unbind = mtk_disp_merge_unbind,
+};
+
+static int mtk_disp_merge_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct resource *res;
+ struct mtk_disp_merge *priv;
+ int ret;
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ priv->regs = devm_ioremap_resource(dev, res);
+ if (IS_ERR(priv->regs)) {
+ dev_err(dev, "failed to ioremap merge\n");
+ return PTR_ERR(priv->regs);
+ }
+
+ priv->clk = devm_clk_get(dev, NULL);
+ if (IS_ERR(priv->clk)) {
+ dev_err(dev, "failed to get merge clk\n");
+ return PTR_ERR(priv->clk);
+ }
+
+ priv->async_clk = devm_clk_get_optional(dev, "merge_async");
+ if (IS_ERR(priv->async_clk)) {
+ dev_err(dev, "failed to get merge async clock\n");
+ return PTR_ERR(priv->async_clk);
+ }
+
+#if IS_REACHABLE(CONFIG_MTK_CMDQ)
+ ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0);
+ if (ret)
+ dev_dbg(dev, "get mediatek,gce-client-reg fail!\n");
+#endif
+
+ priv->fifo_en = of_property_read_bool(dev->of_node,
+ "mediatek,merge-fifo-en");
+
+ platform_set_drvdata(pdev, priv);
+
+ ret = component_add(dev, &mtk_disp_merge_component_ops);
+ if (ret != 0)
+ dev_err(dev, "Failed to add component: %d\n", ret);
+
+ return ret;
+}
+
+static int mtk_disp_merge_remove(struct platform_device *pdev)
+{
+ component_del(&pdev->dev, &mtk_disp_merge_component_ops);
+
+ return 0;
+}
+
+static const struct of_device_id mtk_disp_merge_driver_dt_match[] = {
+ { .compatible = "mediatek,mt8195-disp-merge", },
+ {},
+};
+
+MODULE_DEVICE_TABLE(of, mtk_disp_merge_driver_dt_match);
+
+struct platform_driver mtk_disp_merge_driver = {
+ .probe = mtk_disp_merge_probe,
+ .remove = mtk_disp_merge_remove,
+ .driver = {
+ .name = "mediatek-disp-merge",
+ .owner = THIS_MODULE,
+ .of_match_table = mtk_disp_merge_driver_dt_match,
+ },
+};
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index 68a00b336897..f683e768d61b 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -328,6 +328,14 @@ static const struct mtk_ddp_comp_funcs ddp_gamma = {
.stop = mtk_gamma_stop,
};
+static const struct mtk_ddp_comp_funcs ddp_merge = {
+ .clk_enable = mtk_merge_clk_enable,
+ .clk_disable = mtk_merge_clk_disable,
+ .start = mtk_merge_start,
+ .stop = mtk_merge_stop,
+ .config = mtk_merge_config,
+};
+
static const struct mtk_ddp_comp_funcs ddp_od = {
.clk_enable = mtk_ddp_clk_enable,
.clk_disable = mtk_ddp_clk_disable,
@@ -385,6 +393,7 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
[MTK_DISP_DITHER] = "dither",
[MTK_DISP_DSC] = "dsc",
[MTK_DISP_GAMMA] = "gamma",
+ [MTK_DISP_MERGE] = "merge",
[MTK_DISP_MUTEX] = "mutex",
[MTK_DISP_OD] = "od",
[MTK_DISP_OVL] = "ovl",
@@ -421,6 +430,12 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_DSI2] = { MTK_DSI, 2, &ddp_dsi },
[DDP_COMPONENT_DSI3] = { MTK_DSI, 3, &ddp_dsi },
[DDP_COMPONENT_GAMMA] = { MTK_DISP_GAMMA, 0, &ddp_gamma },
+ [DDP_COMPONENT_MERGE0] = { MTK_DISP_MERGE, 0, &ddp_merge },
+ [DDP_COMPONENT_MERGE1] = { MTK_DISP_MERGE, 1, &ddp_merge },
+ [DDP_COMPONENT_MERGE2] = { MTK_DISP_MERGE, 2, &ddp_merge },
+ [DDP_COMPONENT_MERGE3] = { MTK_DISP_MERGE, 3, &ddp_merge },
+ [DDP_COMPONENT_MERGE4] = { MTK_DISP_MERGE, 4, &ddp_merge },
+ [DDP_COMPONENT_MERGE5] = { MTK_DISP_MERGE, 5, &ddp_merge },
[DDP_COMPONENT_OD0] = { MTK_DISP_OD, 0, &ddp_od },
[DDP_COMPONENT_OD1] = { MTK_DISP_OD, 1, &ddp_od },
[DDP_COMPONENT_OVL0] = { MTK_DISP_OVL, 0, &ddp_ovl },
@@ -523,6 +538,7 @@ int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp,
type == MTK_DISP_CCORR ||
type == MTK_DISP_COLOR ||
type == MTK_DISP_GAMMA ||
+ type == MTK_DISP_MERGE ||
type == MTK_DISP_OVL ||
type == MTK_DISP_OVL_2L ||
type == MTK_DISP_PWM ||
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
index 763725fe72b3..09ac9496547d 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
@@ -25,6 +25,7 @@ enum mtk_ddp_comp_type {
MTK_DISP_DITHER,
MTK_DISP_DSC,
MTK_DISP_GAMMA,
+ MTK_DISP_MERGE,
MTK_DISP_MUTEX,
MTK_DISP_OD,
MTK_DISP_OVL,
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index 247c6ff277ef..f54b650a2ea1 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -597,7 +597,7 @@ static int mtk_drm_probe(struct platform_device *pdev)
private->comp_node[comp_id] = of_node_get(node);
/*
- * Currently only the AAL, CCORR, COLOR, GAMMA, OVL, RDMA, DSI, and DPI
+ * Currently only the AAL, CCORR, COLOR, GAMMA, MERGE, OVL, RDMA, DSI, and DPI
* blocks have separate component platform drivers and initialize their own
* DDP component structure. The others are initialized here.
*/
@@ -605,6 +605,7 @@ static int mtk_drm_probe(struct platform_device *pdev)
comp_type == MTK_DISP_CCORR ||
comp_type == MTK_DISP_COLOR ||
comp_type == MTK_DISP_GAMMA ||
+ comp_type == MTK_DISP_MERGE ||
comp_type == MTK_DISP_OVL ||
comp_type == MTK_DISP_OVL_2L ||
comp_type == MTK_DISP_RDMA ||
@@ -703,6 +704,7 @@ static struct platform_driver * const mtk_drm_drivers[] = {
&mtk_disp_ccorr_driver,
&mtk_disp_color_driver,
&mtk_disp_gamma_driver,
+ &mtk_disp_merge_driver,
&mtk_disp_ovl_driver,
&mtk_disp_rdma_driver,
&mtk_dpi_driver,
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
index 3e7d1e6fbe01..a58cebd01d35 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
@@ -50,6 +50,7 @@ extern struct platform_driver mtk_disp_aal_driver;
extern struct platform_driver mtk_disp_ccorr_driver;
extern struct platform_driver mtk_disp_color_driver;
extern struct platform_driver mtk_disp_gamma_driver;
+extern struct platform_driver mtk_disp_merge_driver;
extern struct platform_driver mtk_disp_ovl_driver;
extern struct platform_driver mtk_disp_rdma_driver;
extern struct platform_driver mtk_dpi_driver;
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [PATCH v20 4/8] drm/mediatek: add MERGE support for mediatek-drm
@ 2022-04-19 9:41 ` jason-jh.lin
0 siblings, 0 replies; 110+ messages in thread
From: jason-jh.lin @ 2022-04-19 9:41 UTC (permalink / raw)
To: Matthias Brugger, Chun-Kuang Hu, AngeloGioacchino Del Regno
Cc: CK Hu, Jason-JH Lin, Nancy Lin, Singo Chang, devicetree,
linux-kernel, dri-devel, linux-mediatek, linux-arm-kernel,
Project_Global_Chrome_Upstream_Group
Add MERGE engine file:
MERGE module is used to merge two slice-per-line inputs
into one side-by-side output.
Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
Acked-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
---
drivers/gpu/drm/mediatek/Makefile | 1 +
drivers/gpu/drm/mediatek/mtk_disp_drv.h | 8 +
drivers/gpu/drm/mediatek/mtk_disp_merge.c | 246 ++++++++++++++++++++
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 16 ++
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 +
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 4 +-
drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 +
7 files changed, 276 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_merge.c
diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile
index 29098d7c8307..a38e88e82d12 100644
--- a/drivers/gpu/drm/mediatek/Makefile
+++ b/drivers/gpu/drm/mediatek/Makefile
@@ -4,6 +4,7 @@ mediatek-drm-y := mtk_disp_aal.o \
mtk_disp_ccorr.o \
mtk_disp_color.o \
mtk_disp_gamma.o \
+ mtk_disp_merge.o \
mtk_disp_ovl.o \
mtk_disp_rdma.o \
mtk_drm_crtc.o \
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
index 86c3068894b1..a33b13fe2b6e 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
@@ -55,6 +55,14 @@ void mtk_gamma_set_common(void __iomem *regs, struct drm_crtc_state *state);
void mtk_gamma_start(struct device *dev);
void mtk_gamma_stop(struct device *dev);
+int mtk_merge_clk_enable(struct device *dev);
+void mtk_merge_clk_disable(struct device *dev);
+void mtk_merge_config(struct device *dev, unsigned int width,
+ unsigned int height, unsigned int vrefresh,
+ unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
+void mtk_merge_start(struct device *dev);
+void mtk_merge_stop(struct device *dev);
+
void mtk_ovl_bgclr_in_on(struct device *dev);
void mtk_ovl_bgclr_in_off(struct device *dev);
void mtk_ovl_bypass_shadow(struct device *dev);
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_merge.c b/drivers/gpu/drm/mediatek/mtk_disp_merge.c
new file mode 100644
index 000000000000..45face638153
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_disp_merge.c
@@ -0,0 +1,246 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ */
+
+#include <linux/clk.h>
+#include <linux/component.h>
+#include <linux/of_device.h>
+#include <linux/of_irq.h>
+#include <linux/platform_device.h>
+#include <linux/soc/mediatek/mtk-cmdq.h>
+
+#include "mtk_drm_ddp_comp.h"
+#include "mtk_drm_drv.h"
+#include "mtk_disp_drv.h"
+
+#define DISP_REG_MERGE_CTRL 0x000
+#define MERGE_EN 1
+#define DISP_REG_MERGE_CFG_0 0x010
+#define DISP_REG_MERGE_CFG_4 0x020
+#define DISP_REG_MERGE_CFG_10 0x038
+/* no swap */
+#define SWAP_MODE 0
+#define FLD_SWAP_MODE GENMASK(4, 0)
+#define DISP_REG_MERGE_CFG_12 0x040
+#define CFG_10_10_1PI_2PO_BUF_MODE 6
+#define CFG_10_10_2PI_2PO_BUF_MODE 8
+#define FLD_CFG_MERGE_MODE GENMASK(4, 0)
+#define DISP_REG_MERGE_CFG_24 0x070
+#define DISP_REG_MERGE_CFG_25 0x074
+#define DISP_REG_MERGE_CFG_36 0x0a0
+#define ULTRA_EN BIT(0)
+#define PREULTRA_EN BIT(4)
+#define DISP_REG_MERGE_CFG_37 0x0a4
+/* 0: Off, 1: SRAM0, 2: SRAM1, 3: SRAM0 + SRAM1 */
+#define BUFFER_MODE 3
+#define FLD_BUFFER_MODE GENMASK(1, 0)
+/*
+ * For the ultra and preultra settings, 6us ~ 9us is experience value
+ * and the maximum frequency of mmsys clock is 594MHz.
+ */
+#define DISP_REG_MERGE_CFG_40 0x0b0
+/* 6 us, 594M pixel/sec */
+#define ULTRA_TH_LOW (6 * 594)
+/* 8 us, 594M pixel/sec */
+#define ULTRA_TH_HIGH (8 * 594)
+#define FLD_ULTRA_TH_LOW GENMASK(15, 0)
+#define FLD_ULTRA_TH_HIGH GENMASK(31, 16)
+#define DISP_REG_MERGE_CFG_41 0x0b4
+/* 8 us, 594M pixel/sec */
+#define PREULTRA_TH_LOW (8 * 594)
+/* 9 us, 594M pixel/sec */
+#define PREULTRA_TH_HIGH (9 * 594)
+#define FLD_PREULTRA_TH_LOW GENMASK(15, 0)
+#define FLD_PREULTRA_TH_HIGH GENMASK(31, 16)
+
+struct mtk_disp_merge {
+ void __iomem *regs;
+ struct clk *clk;
+ struct clk *async_clk;
+ struct cmdq_client_reg cmdq_reg;
+ bool fifo_en;
+};
+
+void mtk_merge_start(struct device *dev)
+{
+ struct mtk_disp_merge *priv = dev_get_drvdata(dev);
+
+ writel(MERGE_EN, priv->regs + DISP_REG_MERGE_CTRL);
+}
+
+void mtk_merge_stop(struct device *dev)
+{
+ struct mtk_disp_merge *priv = dev_get_drvdata(dev);
+
+ writel(0x0, priv->regs + DISP_REG_MERGE_CTRL);
+}
+
+static void mtk_merge_fifo_setting(struct mtk_disp_merge *priv,
+ struct cmdq_pkt *cmdq_pkt)
+{
+ mtk_ddp_write(cmdq_pkt, ULTRA_EN | PREULTRA_EN,
+ &priv->cmdq_reg, priv->regs, DISP_REG_MERGE_CFG_36);
+
+ mtk_ddp_write_mask(cmdq_pkt, BUFFER_MODE,
+ &priv->cmdq_reg, priv->regs, DISP_REG_MERGE_CFG_37,
+ FLD_BUFFER_MODE);
+
+ mtk_ddp_write_mask(cmdq_pkt, ULTRA_TH_LOW | ULTRA_TH_HIGH << 16,
+ &priv->cmdq_reg, priv->regs, DISP_REG_MERGE_CFG_40,
+ FLD_ULTRA_TH_LOW | FLD_ULTRA_TH_HIGH);
+
+ mtk_ddp_write_mask(cmdq_pkt, PREULTRA_TH_LOW | PREULTRA_TH_HIGH << 16,
+ &priv->cmdq_reg, priv->regs, DISP_REG_MERGE_CFG_41,
+ FLD_PREULTRA_TH_LOW | FLD_PREULTRA_TH_HIGH);
+}
+
+void mtk_merge_config(struct device *dev, unsigned int w,
+ unsigned int h, unsigned int vrefresh,
+ unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
+{
+ struct mtk_disp_merge *priv = dev_get_drvdata(dev);
+ unsigned int mode = CFG_10_10_1PI_2PO_BUF_MODE;
+
+ if (!h || !w) {
+ dev_err(dev, "%s: input width(%d) or height(%d) is invalid\n", __func__, w, h);
+ return;
+ }
+
+ if (priv->fifo_en) {
+ mtk_merge_fifo_setting(priv, cmdq_pkt);
+ mode = CFG_10_10_2PI_2PO_BUF_MODE;
+ }
+
+ mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs,
+ DISP_REG_MERGE_CFG_0);
+ mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs,
+ DISP_REG_MERGE_CFG_4);
+ mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs,
+ DISP_REG_MERGE_CFG_24);
+ mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs,
+ DISP_REG_MERGE_CFG_25);
+ mtk_ddp_write_mask(cmdq_pkt, SWAP_MODE, &priv->cmdq_reg, priv->regs,
+ DISP_REG_MERGE_CFG_10, FLD_SWAP_MODE);
+ mtk_ddp_write_mask(cmdq_pkt, mode, &priv->cmdq_reg, priv->regs,
+ DISP_REG_MERGE_CFG_12, FLD_CFG_MERGE_MODE);
+}
+
+int mtk_merge_clk_enable(struct device *dev)
+{
+ int ret = 0;
+ struct mtk_disp_merge *priv = dev_get_drvdata(dev);
+
+ ret = clk_prepare_enable(priv->clk);
+ if (ret) {
+ dev_err(dev, "merge clk prepare enable failed\n");
+ return ret;
+ }
+
+ ret = clk_prepare_enable(priv->async_clk);
+ if (ret) {
+ /* should clean up the state of priv->clk */
+ clk_disable_unprepare(priv->clk);
+
+ dev_err(dev, "async clk prepare enable failed\n");
+ return ret;
+ }
+
+ return ret;
+}
+
+void mtk_merge_clk_disable(struct device *dev)
+{
+ struct mtk_disp_merge *priv = dev_get_drvdata(dev);
+
+ clk_disable_unprepare(priv->async_clk);
+ clk_disable_unprepare(priv->clk);
+}
+
+static int mtk_disp_merge_bind(struct device *dev, struct device *master,
+ void *data)
+{
+ return 0;
+}
+
+static void mtk_disp_merge_unbind(struct device *dev, struct device *master,
+ void *data)
+{
+}
+
+static const struct component_ops mtk_disp_merge_component_ops = {
+ .bind = mtk_disp_merge_bind,
+ .unbind = mtk_disp_merge_unbind,
+};
+
+static int mtk_disp_merge_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct resource *res;
+ struct mtk_disp_merge *priv;
+ int ret;
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ priv->regs = devm_ioremap_resource(dev, res);
+ if (IS_ERR(priv->regs)) {
+ dev_err(dev, "failed to ioremap merge\n");
+ return PTR_ERR(priv->regs);
+ }
+
+ priv->clk = devm_clk_get(dev, NULL);
+ if (IS_ERR(priv->clk)) {
+ dev_err(dev, "failed to get merge clk\n");
+ return PTR_ERR(priv->clk);
+ }
+
+ priv->async_clk = devm_clk_get_optional(dev, "merge_async");
+ if (IS_ERR(priv->async_clk)) {
+ dev_err(dev, "failed to get merge async clock\n");
+ return PTR_ERR(priv->async_clk);
+ }
+
+#if IS_REACHABLE(CONFIG_MTK_CMDQ)
+ ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0);
+ if (ret)
+ dev_dbg(dev, "get mediatek,gce-client-reg fail!\n");
+#endif
+
+ priv->fifo_en = of_property_read_bool(dev->of_node,
+ "mediatek,merge-fifo-en");
+
+ platform_set_drvdata(pdev, priv);
+
+ ret = component_add(dev, &mtk_disp_merge_component_ops);
+ if (ret != 0)
+ dev_err(dev, "Failed to add component: %d\n", ret);
+
+ return ret;
+}
+
+static int mtk_disp_merge_remove(struct platform_device *pdev)
+{
+ component_del(&pdev->dev, &mtk_disp_merge_component_ops);
+
+ return 0;
+}
+
+static const struct of_device_id mtk_disp_merge_driver_dt_match[] = {
+ { .compatible = "mediatek,mt8195-disp-merge", },
+ {},
+};
+
+MODULE_DEVICE_TABLE(of, mtk_disp_merge_driver_dt_match);
+
+struct platform_driver mtk_disp_merge_driver = {
+ .probe = mtk_disp_merge_probe,
+ .remove = mtk_disp_merge_remove,
+ .driver = {
+ .name = "mediatek-disp-merge",
+ .owner = THIS_MODULE,
+ .of_match_table = mtk_disp_merge_driver_dt_match,
+ },
+};
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index 68a00b336897..f683e768d61b 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -328,6 +328,14 @@ static const struct mtk_ddp_comp_funcs ddp_gamma = {
.stop = mtk_gamma_stop,
};
+static const struct mtk_ddp_comp_funcs ddp_merge = {
+ .clk_enable = mtk_merge_clk_enable,
+ .clk_disable = mtk_merge_clk_disable,
+ .start = mtk_merge_start,
+ .stop = mtk_merge_stop,
+ .config = mtk_merge_config,
+};
+
static const struct mtk_ddp_comp_funcs ddp_od = {
.clk_enable = mtk_ddp_clk_enable,
.clk_disable = mtk_ddp_clk_disable,
@@ -385,6 +393,7 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
[MTK_DISP_DITHER] = "dither",
[MTK_DISP_DSC] = "dsc",
[MTK_DISP_GAMMA] = "gamma",
+ [MTK_DISP_MERGE] = "merge",
[MTK_DISP_MUTEX] = "mutex",
[MTK_DISP_OD] = "od",
[MTK_DISP_OVL] = "ovl",
@@ -421,6 +430,12 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_DSI2] = { MTK_DSI, 2, &ddp_dsi },
[DDP_COMPONENT_DSI3] = { MTK_DSI, 3, &ddp_dsi },
[DDP_COMPONENT_GAMMA] = { MTK_DISP_GAMMA, 0, &ddp_gamma },
+ [DDP_COMPONENT_MERGE0] = { MTK_DISP_MERGE, 0, &ddp_merge },
+ [DDP_COMPONENT_MERGE1] = { MTK_DISP_MERGE, 1, &ddp_merge },
+ [DDP_COMPONENT_MERGE2] = { MTK_DISP_MERGE, 2, &ddp_merge },
+ [DDP_COMPONENT_MERGE3] = { MTK_DISP_MERGE, 3, &ddp_merge },
+ [DDP_COMPONENT_MERGE4] = { MTK_DISP_MERGE, 4, &ddp_merge },
+ [DDP_COMPONENT_MERGE5] = { MTK_DISP_MERGE, 5, &ddp_merge },
[DDP_COMPONENT_OD0] = { MTK_DISP_OD, 0, &ddp_od },
[DDP_COMPONENT_OD1] = { MTK_DISP_OD, 1, &ddp_od },
[DDP_COMPONENT_OVL0] = { MTK_DISP_OVL, 0, &ddp_ovl },
@@ -523,6 +538,7 @@ int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp,
type == MTK_DISP_CCORR ||
type == MTK_DISP_COLOR ||
type == MTK_DISP_GAMMA ||
+ type == MTK_DISP_MERGE ||
type == MTK_DISP_OVL ||
type == MTK_DISP_OVL_2L ||
type == MTK_DISP_PWM ||
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
index 763725fe72b3..09ac9496547d 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
@@ -25,6 +25,7 @@ enum mtk_ddp_comp_type {
MTK_DISP_DITHER,
MTK_DISP_DSC,
MTK_DISP_GAMMA,
+ MTK_DISP_MERGE,
MTK_DISP_MUTEX,
MTK_DISP_OD,
MTK_DISP_OVL,
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index 247c6ff277ef..f54b650a2ea1 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -597,7 +597,7 @@ static int mtk_drm_probe(struct platform_device *pdev)
private->comp_node[comp_id] = of_node_get(node);
/*
- * Currently only the AAL, CCORR, COLOR, GAMMA, OVL, RDMA, DSI, and DPI
+ * Currently only the AAL, CCORR, COLOR, GAMMA, MERGE, OVL, RDMA, DSI, and DPI
* blocks have separate component platform drivers and initialize their own
* DDP component structure. The others are initialized here.
*/
@@ -605,6 +605,7 @@ static int mtk_drm_probe(struct platform_device *pdev)
comp_type == MTK_DISP_CCORR ||
comp_type == MTK_DISP_COLOR ||
comp_type == MTK_DISP_GAMMA ||
+ comp_type == MTK_DISP_MERGE ||
comp_type == MTK_DISP_OVL ||
comp_type == MTK_DISP_OVL_2L ||
comp_type == MTK_DISP_RDMA ||
@@ -703,6 +704,7 @@ static struct platform_driver * const mtk_drm_drivers[] = {
&mtk_disp_ccorr_driver,
&mtk_disp_color_driver,
&mtk_disp_gamma_driver,
+ &mtk_disp_merge_driver,
&mtk_disp_ovl_driver,
&mtk_disp_rdma_driver,
&mtk_dpi_driver,
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
index 3e7d1e6fbe01..a58cebd01d35 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
@@ -50,6 +50,7 @@ extern struct platform_driver mtk_disp_aal_driver;
extern struct platform_driver mtk_disp_ccorr_driver;
extern struct platform_driver mtk_disp_color_driver;
extern struct platform_driver mtk_disp_gamma_driver;
+extern struct platform_driver mtk_disp_merge_driver;
extern struct platform_driver mtk_disp_ovl_driver;
extern struct platform_driver mtk_disp_rdma_driver;
extern struct platform_driver mtk_dpi_driver;
--
2.18.0
_______________________________________________
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linux-arm-kernel@lists.infradead.org
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^ permalink raw reply related [flat|nested] 110+ messages in thread
* [PATCH v20 5/8] drm/mediatek: add mediatek-drm of vdosys0 support for mt8195
2022-04-19 9:41 ` jason-jh.lin
(?)
@ 2022-04-19 9:41 ` jason-jh.lin
-1 siblings, 0 replies; 110+ messages in thread
From: jason-jh.lin @ 2022-04-19 9:41 UTC (permalink / raw)
To: Matthias Brugger, Chun-Kuang Hu, AngeloGioacchino Del Regno
Cc: devicetree, Jason-JH Lin, Singo Chang, linux-kernel, dri-devel,
Project_Global_Chrome_Upstream_Group, Nancy Lin, linux-mediatek,
linux-arm-kernel
1. Add driver data of mt8195 vdosys0 to mediatek-drm and the sub driver.
2. Add get driver data function to identify which vdosys by io_start.
Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 6 +
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 141 +++++++++++++++++++++--
drivers/gpu/drm/mediatek/mtk_drm_drv.h | 6 +
3 files changed, 145 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
index 662e91d9d45f..8ce60371536e 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
@@ -364,6 +364,10 @@ static const struct mtk_disp_rdma_data mt8192_rdma_driver_data = {
.fifo_size = 5 * SZ_1K,
};
+static const struct mtk_disp_rdma_data mt8195_rdma_driver_data = {
+ .fifo_size = 1920,
+};
+
static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = {
{ .compatible = "mediatek,mt2701-disp-rdma",
.data = &mt2701_rdma_driver_data},
@@ -373,6 +377,8 @@ static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = {
.data = &mt8183_rdma_driver_data},
{ .compatible = "mediatek,mt8192-disp-rdma",
.data = &mt8192_rdma_driver_data},
+ { .compatible = "mediatek,mt8195-disp-rdma",
+ .data = &mt8195_rdma_driver_data},
{},
};
MODULE_DEVICE_TABLE(of, mtk_disp_rdma_driver_dt_match);
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index f54b650a2ea1..a3d01940d4c6 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -4,6 +4,8 @@
* Author: YT SHEN <yt.shen@mediatek.com>
*/
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
#include <linux/component.h>
#include <linux/iommu.h>
#include <linux/module.h>
@@ -177,6 +179,19 @@ static const enum mtk_ddp_comp_id mt8192_mtk_ddp_ext[] = {
DDP_COMPONENT_DPI0,
};
+static const enum mtk_ddp_comp_id mt8195_mtk_ddp_main[] = {
+ DDP_COMPONENT_OVL0,
+ DDP_COMPONENT_RDMA0,
+ DDP_COMPONENT_COLOR0,
+ DDP_COMPONENT_CCORR,
+ DDP_COMPONENT_AAL0,
+ DDP_COMPONENT_GAMMA,
+ DDP_COMPONENT_DITHER,
+ DDP_COMPONENT_DSC0,
+ DDP_COMPONENT_MERGE0,
+ DDP_COMPONENT_DP_INTF0,
+};
+
static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
.main_path = mt2701_mtk_ddp_main,
.main_len = ARRAY_SIZE(mt2701_mtk_ddp_main),
@@ -185,6 +200,13 @@ static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
.shadow_register = true,
};
+static const struct mtk_mmsys_match_data mt2701_mmsys_match_data = {
+ .num_drv_data = 1,
+ .drv_data = {
+ &mt2701_mmsys_driver_data,
+ },
+};
+
static const struct mtk_mmsys_driver_data mt7623_mmsys_driver_data = {
.main_path = mt7623_mtk_ddp_main,
.main_len = ARRAY_SIZE(mt7623_mtk_ddp_main),
@@ -193,6 +215,13 @@ static const struct mtk_mmsys_driver_data mt7623_mmsys_driver_data = {
.shadow_register = true,
};
+static const struct mtk_mmsys_match_data mt7623_mmsys_match_data = {
+ .num_drv_data = 1,
+ .drv_data = {
+ &mt7623_mmsys_driver_data,
+ },
+};
+
static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = {
.main_path = mt2712_mtk_ddp_main,
.main_len = ARRAY_SIZE(mt2712_mtk_ddp_main),
@@ -202,11 +231,25 @@ static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = {
.third_len = ARRAY_SIZE(mt2712_mtk_ddp_third),
};
+static const struct mtk_mmsys_match_data mt2712_mmsys_match_data = {
+ .num_drv_data = 1,
+ .drv_data = {
+ &mt2712_mmsys_driver_data,
+ },
+};
+
static const struct mtk_mmsys_driver_data mt8167_mmsys_driver_data = {
.main_path = mt8167_mtk_ddp_main,
.main_len = ARRAY_SIZE(mt8167_mtk_ddp_main),
};
+static const struct mtk_mmsys_match_data mt8167_mmsys_match_data = {
+ .num_drv_data = 1,
+ .drv_data = {
+ &mt8167_mmsys_driver_data,
+ },
+};
+
static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
.main_path = mt8173_mtk_ddp_main,
.main_len = ARRAY_SIZE(mt8173_mtk_ddp_main),
@@ -214,6 +257,13 @@ static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
.ext_len = ARRAY_SIZE(mt8173_mtk_ddp_ext),
};
+static const struct mtk_mmsys_match_data mt8173_mmsys_match_data = {
+ .num_drv_data = 1,
+ .drv_data = {
+ &mt8173_mmsys_driver_data,
+ },
+};
+
static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
.main_path = mt8183_mtk_ddp_main,
.main_len = ARRAY_SIZE(mt8183_mtk_ddp_main),
@@ -221,6 +271,13 @@ static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
.ext_len = ARRAY_SIZE(mt8183_mtk_ddp_ext),
};
+static const struct mtk_mmsys_match_data mt8183_mmsys_match_data = {
+ .num_drv_data = 1,
+ .drv_data = {
+ &mt8183_mmsys_driver_data,
+ },
+};
+
static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
.main_path = mt8192_mtk_ddp_main,
.main_len = ARRAY_SIZE(mt8192_mtk_ddp_main),
@@ -228,6 +285,31 @@ static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
.ext_len = ARRAY_SIZE(mt8192_mtk_ddp_ext),
};
+static const struct mtk_mmsys_match_data mt8192_mmsys_match_data = {
+ .num_drv_data = 1,
+ .drv_data = {
+ &mt8192_mmsys_driver_data,
+ },
+};
+
+static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = {
+ .io_start = 0x1c01a000,
+ .main_path = mt8195_mtk_ddp_main,
+ .main_len = ARRAY_SIZE(mt8195_mtk_ddp_main),
+};
+
+static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
+ .io_start = 0x1c100000,
+};
+
+static const struct mtk_mmsys_match_data mt8195_mmsys_match_data = {
+ .num_drv_data = 1,
+ .drv_data = {
+ &mt8195_vdosys0_driver_data,
+ &mt8195_vdosys1_driver_data,
+ },
+};
+
static int mtk_drm_kms_init(struct drm_device *drm)
{
struct mtk_drm_private *private = drm->dev_private;
@@ -445,12 +527,16 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
.data = (void *)MTK_DISP_DITHER },
{ .compatible = "mediatek,mt8183-disp-dither",
.data = (void *)MTK_DISP_DITHER },
+ { .compatible = "mediatek,mt8195-disp-dsc",
+ .data = (void *)MTK_DISP_DSC },
{ .compatible = "mediatek,mt8167-disp-gamma",
.data = (void *)MTK_DISP_GAMMA, },
{ .compatible = "mediatek,mt8173-disp-gamma",
.data = (void *)MTK_DISP_GAMMA, },
{ .compatible = "mediatek,mt8183-disp-gamma",
.data = (void *)MTK_DISP_GAMMA, },
+ { .compatible = "mediatek,mt8195-disp-merge",
+ .data = (void *)MTK_DISP_MERGE },
{ .compatible = "mediatek,mt2701-disp-mutex",
.data = (void *)MTK_DISP_MUTEX },
{ .compatible = "mediatek,mt2712-disp-mutex",
@@ -463,6 +549,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
.data = (void *)MTK_DISP_MUTEX },
{ .compatible = "mediatek,mt8192-disp-mutex",
.data = (void *)MTK_DISP_MUTEX },
+ { .compatible = "mediatek,mt8195-disp-mutex",
+ .data = (void *)MTK_DISP_MUTEX },
{ .compatible = "mediatek,mt8173-disp-od",
.data = (void *)MTK_DISP_OD },
{ .compatible = "mediatek,mt2701-disp-ovl",
@@ -497,6 +585,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
.data = (void *)MTK_DISP_RDMA },
{ .compatible = "mediatek,mt8192-disp-rdma",
.data = (void *)MTK_DISP_RDMA },
+ { .compatible = "mediatek,mt8195-disp-rdma",
+ .data = (void *)MTK_DISP_RDMA },
{ .compatible = "mediatek,mt8173-disp-ufoe",
.data = (void *)MTK_DISP_UFOE },
{ .compatible = "mediatek,mt8173-disp-wdma",
@@ -520,28 +610,51 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
static const struct of_device_id mtk_drm_of_ids[] = {
{ .compatible = "mediatek,mt2701-mmsys",
- .data = &mt2701_mmsys_driver_data},
+ .data = &mt2701_mmsys_match_data},
{ .compatible = "mediatek,mt7623-mmsys",
- .data = &mt7623_mmsys_driver_data},
+ .data = &mt7623_mmsys_match_data},
{ .compatible = "mediatek,mt2712-mmsys",
- .data = &mt2712_mmsys_driver_data},
+ .data = &mt2712_mmsys_match_data},
{ .compatible = "mediatek,mt8167-mmsys",
- .data = &mt8167_mmsys_driver_data},
+ .data = &mt8167_mmsys_match_data},
{ .compatible = "mediatek,mt8173-mmsys",
- .data = &mt8173_mmsys_driver_data},
+ .data = &mt8173_mmsys_match_data},
{ .compatible = "mediatek,mt8183-mmsys",
- .data = &mt8183_mmsys_driver_data},
+ .data = &mt8183_mmsys_match_data},
{ .compatible = "mediatek,mt8192-mmsys",
- .data = &mt8192_mmsys_driver_data},
+ .data = &mt8192_mmsys_match_data},
+ { .compatible = "mediatek,mt8195-mmsys",
+ .data = &mt8195_mmsys_match_data},
{ }
};
MODULE_DEVICE_TABLE(of, mtk_drm_of_ids);
+static int mtk_drm_find_match_data(struct device *dev,
+ const struct mtk_mmsys_match_data *match_data)
+{
+ int i;
+ struct platform_device *pdev = of_find_device_by_node(dev->parent->of_node);
+ struct resource *res;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!res) {
+ dev_err(dev, "failed to get parent resource\n");
+ return -EINVAL;
+ }
+
+ for (i = 0; i < match_data->num_drv_data; i++)
+ if (match_data->drv_data[i]->io_start == res->start)
+ return i;
+
+ return -EINVAL;
+}
+
static int mtk_drm_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct device_node *phandle = dev->parent->of_node;
const struct of_device_id *of_id;
+ const struct mtk_mmsys_match_data *match_data;
struct mtk_drm_private *private;
struct device_node *node;
struct component_match *match = NULL;
@@ -562,7 +675,19 @@ static int mtk_drm_probe(struct platform_device *pdev)
if (!of_id)
return -ENODEV;
- private->data = of_id->data;
+ match_data = of_id->data;
+ if (match_data->num_drv_data > 1) {
+ /* This SoC has multiple mmsys channels */
+ ret = mtk_drm_find_match_data(dev, match_data);
+ if (ret < 0) {
+ dev_err(dev, "Couldn't get match driver data\n");
+ return ret;
+ }
+ private->data = match_data->drv_data[ret];
+ } else {
+ dev_dbg(dev, "Using single mmsys channel\n");
+ private->data = match_data->drv_data[0];
+ }
/* Iterate over sibling DISP function blocks */
for_each_child_of_node(phandle->parent, node) {
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
index a58cebd01d35..9fc922b1684f 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
@@ -21,6 +21,7 @@ struct drm_property;
struct regmap;
struct mtk_mmsys_driver_data {
+ const resource_size_t io_start;
const enum mtk_ddp_comp_id *main_path;
unsigned int main_len;
const enum mtk_ddp_comp_id *ext_path;
@@ -31,6 +32,11 @@ struct mtk_mmsys_driver_data {
bool shadow_register;
};
+struct mtk_mmsys_match_data {
+ unsigned short num_drv_data;
+ const struct mtk_mmsys_driver_data *drv_data[];
+};
+
struct mtk_drm_private {
struct drm_device *drm;
struct device *dma_dev;
--
2.18.0
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [PATCH v20 5/8] drm/mediatek: add mediatek-drm of vdosys0 support for mt8195
@ 2022-04-19 9:41 ` jason-jh.lin
0 siblings, 0 replies; 110+ messages in thread
From: jason-jh.lin @ 2022-04-19 9:41 UTC (permalink / raw)
To: Matthias Brugger, Chun-Kuang Hu, AngeloGioacchino Del Regno
Cc: CK Hu, Jason-JH Lin, Nancy Lin, Singo Chang, devicetree,
linux-kernel, dri-devel, linux-mediatek, linux-arm-kernel,
Project_Global_Chrome_Upstream_Group
1. Add driver data of mt8195 vdosys0 to mediatek-drm and the sub driver.
2. Add get driver data function to identify which vdosys by io_start.
Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 6 +
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 141 +++++++++++++++++++++--
drivers/gpu/drm/mediatek/mtk_drm_drv.h | 6 +
3 files changed, 145 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
index 662e91d9d45f..8ce60371536e 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
@@ -364,6 +364,10 @@ static const struct mtk_disp_rdma_data mt8192_rdma_driver_data = {
.fifo_size = 5 * SZ_1K,
};
+static const struct mtk_disp_rdma_data mt8195_rdma_driver_data = {
+ .fifo_size = 1920,
+};
+
static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = {
{ .compatible = "mediatek,mt2701-disp-rdma",
.data = &mt2701_rdma_driver_data},
@@ -373,6 +377,8 @@ static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = {
.data = &mt8183_rdma_driver_data},
{ .compatible = "mediatek,mt8192-disp-rdma",
.data = &mt8192_rdma_driver_data},
+ { .compatible = "mediatek,mt8195-disp-rdma",
+ .data = &mt8195_rdma_driver_data},
{},
};
MODULE_DEVICE_TABLE(of, mtk_disp_rdma_driver_dt_match);
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index f54b650a2ea1..a3d01940d4c6 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -4,6 +4,8 @@
* Author: YT SHEN <yt.shen@mediatek.com>
*/
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
#include <linux/component.h>
#include <linux/iommu.h>
#include <linux/module.h>
@@ -177,6 +179,19 @@ static const enum mtk_ddp_comp_id mt8192_mtk_ddp_ext[] = {
DDP_COMPONENT_DPI0,
};
+static const enum mtk_ddp_comp_id mt8195_mtk_ddp_main[] = {
+ DDP_COMPONENT_OVL0,
+ DDP_COMPONENT_RDMA0,
+ DDP_COMPONENT_COLOR0,
+ DDP_COMPONENT_CCORR,
+ DDP_COMPONENT_AAL0,
+ DDP_COMPONENT_GAMMA,
+ DDP_COMPONENT_DITHER,
+ DDP_COMPONENT_DSC0,
+ DDP_COMPONENT_MERGE0,
+ DDP_COMPONENT_DP_INTF0,
+};
+
static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
.main_path = mt2701_mtk_ddp_main,
.main_len = ARRAY_SIZE(mt2701_mtk_ddp_main),
@@ -185,6 +200,13 @@ static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
.shadow_register = true,
};
+static const struct mtk_mmsys_match_data mt2701_mmsys_match_data = {
+ .num_drv_data = 1,
+ .drv_data = {
+ &mt2701_mmsys_driver_data,
+ },
+};
+
static const struct mtk_mmsys_driver_data mt7623_mmsys_driver_data = {
.main_path = mt7623_mtk_ddp_main,
.main_len = ARRAY_SIZE(mt7623_mtk_ddp_main),
@@ -193,6 +215,13 @@ static const struct mtk_mmsys_driver_data mt7623_mmsys_driver_data = {
.shadow_register = true,
};
+static const struct mtk_mmsys_match_data mt7623_mmsys_match_data = {
+ .num_drv_data = 1,
+ .drv_data = {
+ &mt7623_mmsys_driver_data,
+ },
+};
+
static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = {
.main_path = mt2712_mtk_ddp_main,
.main_len = ARRAY_SIZE(mt2712_mtk_ddp_main),
@@ -202,11 +231,25 @@ static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = {
.third_len = ARRAY_SIZE(mt2712_mtk_ddp_third),
};
+static const struct mtk_mmsys_match_data mt2712_mmsys_match_data = {
+ .num_drv_data = 1,
+ .drv_data = {
+ &mt2712_mmsys_driver_data,
+ },
+};
+
static const struct mtk_mmsys_driver_data mt8167_mmsys_driver_data = {
.main_path = mt8167_mtk_ddp_main,
.main_len = ARRAY_SIZE(mt8167_mtk_ddp_main),
};
+static const struct mtk_mmsys_match_data mt8167_mmsys_match_data = {
+ .num_drv_data = 1,
+ .drv_data = {
+ &mt8167_mmsys_driver_data,
+ },
+};
+
static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
.main_path = mt8173_mtk_ddp_main,
.main_len = ARRAY_SIZE(mt8173_mtk_ddp_main),
@@ -214,6 +257,13 @@ static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
.ext_len = ARRAY_SIZE(mt8173_mtk_ddp_ext),
};
+static const struct mtk_mmsys_match_data mt8173_mmsys_match_data = {
+ .num_drv_data = 1,
+ .drv_data = {
+ &mt8173_mmsys_driver_data,
+ },
+};
+
static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
.main_path = mt8183_mtk_ddp_main,
.main_len = ARRAY_SIZE(mt8183_mtk_ddp_main),
@@ -221,6 +271,13 @@ static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
.ext_len = ARRAY_SIZE(mt8183_mtk_ddp_ext),
};
+static const struct mtk_mmsys_match_data mt8183_mmsys_match_data = {
+ .num_drv_data = 1,
+ .drv_data = {
+ &mt8183_mmsys_driver_data,
+ },
+};
+
static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
.main_path = mt8192_mtk_ddp_main,
.main_len = ARRAY_SIZE(mt8192_mtk_ddp_main),
@@ -228,6 +285,31 @@ static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
.ext_len = ARRAY_SIZE(mt8192_mtk_ddp_ext),
};
+static const struct mtk_mmsys_match_data mt8192_mmsys_match_data = {
+ .num_drv_data = 1,
+ .drv_data = {
+ &mt8192_mmsys_driver_data,
+ },
+};
+
+static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = {
+ .io_start = 0x1c01a000,
+ .main_path = mt8195_mtk_ddp_main,
+ .main_len = ARRAY_SIZE(mt8195_mtk_ddp_main),
+};
+
+static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
+ .io_start = 0x1c100000,
+};
+
+static const struct mtk_mmsys_match_data mt8195_mmsys_match_data = {
+ .num_drv_data = 1,
+ .drv_data = {
+ &mt8195_vdosys0_driver_data,
+ &mt8195_vdosys1_driver_data,
+ },
+};
+
static int mtk_drm_kms_init(struct drm_device *drm)
{
struct mtk_drm_private *private = drm->dev_private;
@@ -445,12 +527,16 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
.data = (void *)MTK_DISP_DITHER },
{ .compatible = "mediatek,mt8183-disp-dither",
.data = (void *)MTK_DISP_DITHER },
+ { .compatible = "mediatek,mt8195-disp-dsc",
+ .data = (void *)MTK_DISP_DSC },
{ .compatible = "mediatek,mt8167-disp-gamma",
.data = (void *)MTK_DISP_GAMMA, },
{ .compatible = "mediatek,mt8173-disp-gamma",
.data = (void *)MTK_DISP_GAMMA, },
{ .compatible = "mediatek,mt8183-disp-gamma",
.data = (void *)MTK_DISP_GAMMA, },
+ { .compatible = "mediatek,mt8195-disp-merge",
+ .data = (void *)MTK_DISP_MERGE },
{ .compatible = "mediatek,mt2701-disp-mutex",
.data = (void *)MTK_DISP_MUTEX },
{ .compatible = "mediatek,mt2712-disp-mutex",
@@ -463,6 +549,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
.data = (void *)MTK_DISP_MUTEX },
{ .compatible = "mediatek,mt8192-disp-mutex",
.data = (void *)MTK_DISP_MUTEX },
+ { .compatible = "mediatek,mt8195-disp-mutex",
+ .data = (void *)MTK_DISP_MUTEX },
{ .compatible = "mediatek,mt8173-disp-od",
.data = (void *)MTK_DISP_OD },
{ .compatible = "mediatek,mt2701-disp-ovl",
@@ -497,6 +585,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
.data = (void *)MTK_DISP_RDMA },
{ .compatible = "mediatek,mt8192-disp-rdma",
.data = (void *)MTK_DISP_RDMA },
+ { .compatible = "mediatek,mt8195-disp-rdma",
+ .data = (void *)MTK_DISP_RDMA },
{ .compatible = "mediatek,mt8173-disp-ufoe",
.data = (void *)MTK_DISP_UFOE },
{ .compatible = "mediatek,mt8173-disp-wdma",
@@ -520,28 +610,51 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
static const struct of_device_id mtk_drm_of_ids[] = {
{ .compatible = "mediatek,mt2701-mmsys",
- .data = &mt2701_mmsys_driver_data},
+ .data = &mt2701_mmsys_match_data},
{ .compatible = "mediatek,mt7623-mmsys",
- .data = &mt7623_mmsys_driver_data},
+ .data = &mt7623_mmsys_match_data},
{ .compatible = "mediatek,mt2712-mmsys",
- .data = &mt2712_mmsys_driver_data},
+ .data = &mt2712_mmsys_match_data},
{ .compatible = "mediatek,mt8167-mmsys",
- .data = &mt8167_mmsys_driver_data},
+ .data = &mt8167_mmsys_match_data},
{ .compatible = "mediatek,mt8173-mmsys",
- .data = &mt8173_mmsys_driver_data},
+ .data = &mt8173_mmsys_match_data},
{ .compatible = "mediatek,mt8183-mmsys",
- .data = &mt8183_mmsys_driver_data},
+ .data = &mt8183_mmsys_match_data},
{ .compatible = "mediatek,mt8192-mmsys",
- .data = &mt8192_mmsys_driver_data},
+ .data = &mt8192_mmsys_match_data},
+ { .compatible = "mediatek,mt8195-mmsys",
+ .data = &mt8195_mmsys_match_data},
{ }
};
MODULE_DEVICE_TABLE(of, mtk_drm_of_ids);
+static int mtk_drm_find_match_data(struct device *dev,
+ const struct mtk_mmsys_match_data *match_data)
+{
+ int i;
+ struct platform_device *pdev = of_find_device_by_node(dev->parent->of_node);
+ struct resource *res;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!res) {
+ dev_err(dev, "failed to get parent resource\n");
+ return -EINVAL;
+ }
+
+ for (i = 0; i < match_data->num_drv_data; i++)
+ if (match_data->drv_data[i]->io_start == res->start)
+ return i;
+
+ return -EINVAL;
+}
+
static int mtk_drm_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct device_node *phandle = dev->parent->of_node;
const struct of_device_id *of_id;
+ const struct mtk_mmsys_match_data *match_data;
struct mtk_drm_private *private;
struct device_node *node;
struct component_match *match = NULL;
@@ -562,7 +675,19 @@ static int mtk_drm_probe(struct platform_device *pdev)
if (!of_id)
return -ENODEV;
- private->data = of_id->data;
+ match_data = of_id->data;
+ if (match_data->num_drv_data > 1) {
+ /* This SoC has multiple mmsys channels */
+ ret = mtk_drm_find_match_data(dev, match_data);
+ if (ret < 0) {
+ dev_err(dev, "Couldn't get match driver data\n");
+ return ret;
+ }
+ private->data = match_data->drv_data[ret];
+ } else {
+ dev_dbg(dev, "Using single mmsys channel\n");
+ private->data = match_data->drv_data[0];
+ }
/* Iterate over sibling DISP function blocks */
for_each_child_of_node(phandle->parent, node) {
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
index a58cebd01d35..9fc922b1684f 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
@@ -21,6 +21,7 @@ struct drm_property;
struct regmap;
struct mtk_mmsys_driver_data {
+ const resource_size_t io_start;
const enum mtk_ddp_comp_id *main_path;
unsigned int main_len;
const enum mtk_ddp_comp_id *ext_path;
@@ -31,6 +32,11 @@ struct mtk_mmsys_driver_data {
bool shadow_register;
};
+struct mtk_mmsys_match_data {
+ unsigned short num_drv_data;
+ const struct mtk_mmsys_driver_data *drv_data[];
+};
+
struct mtk_drm_private {
struct drm_device *drm;
struct device *dma_dev;
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [PATCH v20 5/8] drm/mediatek: add mediatek-drm of vdosys0 support for mt8195
@ 2022-04-19 9:41 ` jason-jh.lin
0 siblings, 0 replies; 110+ messages in thread
From: jason-jh.lin @ 2022-04-19 9:41 UTC (permalink / raw)
To: Matthias Brugger, Chun-Kuang Hu, AngeloGioacchino Del Regno
Cc: CK Hu, Jason-JH Lin, Nancy Lin, Singo Chang, devicetree,
linux-kernel, dri-devel, linux-mediatek, linux-arm-kernel,
Project_Global_Chrome_Upstream_Group
1. Add driver data of mt8195 vdosys0 to mediatek-drm and the sub driver.
2. Add get driver data function to identify which vdosys by io_start.
Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 6 +
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 141 +++++++++++++++++++++--
drivers/gpu/drm/mediatek/mtk_drm_drv.h | 6 +
3 files changed, 145 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
index 662e91d9d45f..8ce60371536e 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
@@ -364,6 +364,10 @@ static const struct mtk_disp_rdma_data mt8192_rdma_driver_data = {
.fifo_size = 5 * SZ_1K,
};
+static const struct mtk_disp_rdma_data mt8195_rdma_driver_data = {
+ .fifo_size = 1920,
+};
+
static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = {
{ .compatible = "mediatek,mt2701-disp-rdma",
.data = &mt2701_rdma_driver_data},
@@ -373,6 +377,8 @@ static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = {
.data = &mt8183_rdma_driver_data},
{ .compatible = "mediatek,mt8192-disp-rdma",
.data = &mt8192_rdma_driver_data},
+ { .compatible = "mediatek,mt8195-disp-rdma",
+ .data = &mt8195_rdma_driver_data},
{},
};
MODULE_DEVICE_TABLE(of, mtk_disp_rdma_driver_dt_match);
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index f54b650a2ea1..a3d01940d4c6 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -4,6 +4,8 @@
* Author: YT SHEN <yt.shen@mediatek.com>
*/
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
#include <linux/component.h>
#include <linux/iommu.h>
#include <linux/module.h>
@@ -177,6 +179,19 @@ static const enum mtk_ddp_comp_id mt8192_mtk_ddp_ext[] = {
DDP_COMPONENT_DPI0,
};
+static const enum mtk_ddp_comp_id mt8195_mtk_ddp_main[] = {
+ DDP_COMPONENT_OVL0,
+ DDP_COMPONENT_RDMA0,
+ DDP_COMPONENT_COLOR0,
+ DDP_COMPONENT_CCORR,
+ DDP_COMPONENT_AAL0,
+ DDP_COMPONENT_GAMMA,
+ DDP_COMPONENT_DITHER,
+ DDP_COMPONENT_DSC0,
+ DDP_COMPONENT_MERGE0,
+ DDP_COMPONENT_DP_INTF0,
+};
+
static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
.main_path = mt2701_mtk_ddp_main,
.main_len = ARRAY_SIZE(mt2701_mtk_ddp_main),
@@ -185,6 +200,13 @@ static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
.shadow_register = true,
};
+static const struct mtk_mmsys_match_data mt2701_mmsys_match_data = {
+ .num_drv_data = 1,
+ .drv_data = {
+ &mt2701_mmsys_driver_data,
+ },
+};
+
static const struct mtk_mmsys_driver_data mt7623_mmsys_driver_data = {
.main_path = mt7623_mtk_ddp_main,
.main_len = ARRAY_SIZE(mt7623_mtk_ddp_main),
@@ -193,6 +215,13 @@ static const struct mtk_mmsys_driver_data mt7623_mmsys_driver_data = {
.shadow_register = true,
};
+static const struct mtk_mmsys_match_data mt7623_mmsys_match_data = {
+ .num_drv_data = 1,
+ .drv_data = {
+ &mt7623_mmsys_driver_data,
+ },
+};
+
static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = {
.main_path = mt2712_mtk_ddp_main,
.main_len = ARRAY_SIZE(mt2712_mtk_ddp_main),
@@ -202,11 +231,25 @@ static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = {
.third_len = ARRAY_SIZE(mt2712_mtk_ddp_third),
};
+static const struct mtk_mmsys_match_data mt2712_mmsys_match_data = {
+ .num_drv_data = 1,
+ .drv_data = {
+ &mt2712_mmsys_driver_data,
+ },
+};
+
static const struct mtk_mmsys_driver_data mt8167_mmsys_driver_data = {
.main_path = mt8167_mtk_ddp_main,
.main_len = ARRAY_SIZE(mt8167_mtk_ddp_main),
};
+static const struct mtk_mmsys_match_data mt8167_mmsys_match_data = {
+ .num_drv_data = 1,
+ .drv_data = {
+ &mt8167_mmsys_driver_data,
+ },
+};
+
static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
.main_path = mt8173_mtk_ddp_main,
.main_len = ARRAY_SIZE(mt8173_mtk_ddp_main),
@@ -214,6 +257,13 @@ static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
.ext_len = ARRAY_SIZE(mt8173_mtk_ddp_ext),
};
+static const struct mtk_mmsys_match_data mt8173_mmsys_match_data = {
+ .num_drv_data = 1,
+ .drv_data = {
+ &mt8173_mmsys_driver_data,
+ },
+};
+
static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
.main_path = mt8183_mtk_ddp_main,
.main_len = ARRAY_SIZE(mt8183_mtk_ddp_main),
@@ -221,6 +271,13 @@ static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
.ext_len = ARRAY_SIZE(mt8183_mtk_ddp_ext),
};
+static const struct mtk_mmsys_match_data mt8183_mmsys_match_data = {
+ .num_drv_data = 1,
+ .drv_data = {
+ &mt8183_mmsys_driver_data,
+ },
+};
+
static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
.main_path = mt8192_mtk_ddp_main,
.main_len = ARRAY_SIZE(mt8192_mtk_ddp_main),
@@ -228,6 +285,31 @@ static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
.ext_len = ARRAY_SIZE(mt8192_mtk_ddp_ext),
};
+static const struct mtk_mmsys_match_data mt8192_mmsys_match_data = {
+ .num_drv_data = 1,
+ .drv_data = {
+ &mt8192_mmsys_driver_data,
+ },
+};
+
+static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = {
+ .io_start = 0x1c01a000,
+ .main_path = mt8195_mtk_ddp_main,
+ .main_len = ARRAY_SIZE(mt8195_mtk_ddp_main),
+};
+
+static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
+ .io_start = 0x1c100000,
+};
+
+static const struct mtk_mmsys_match_data mt8195_mmsys_match_data = {
+ .num_drv_data = 1,
+ .drv_data = {
+ &mt8195_vdosys0_driver_data,
+ &mt8195_vdosys1_driver_data,
+ },
+};
+
static int mtk_drm_kms_init(struct drm_device *drm)
{
struct mtk_drm_private *private = drm->dev_private;
@@ -445,12 +527,16 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
.data = (void *)MTK_DISP_DITHER },
{ .compatible = "mediatek,mt8183-disp-dither",
.data = (void *)MTK_DISP_DITHER },
+ { .compatible = "mediatek,mt8195-disp-dsc",
+ .data = (void *)MTK_DISP_DSC },
{ .compatible = "mediatek,mt8167-disp-gamma",
.data = (void *)MTK_DISP_GAMMA, },
{ .compatible = "mediatek,mt8173-disp-gamma",
.data = (void *)MTK_DISP_GAMMA, },
{ .compatible = "mediatek,mt8183-disp-gamma",
.data = (void *)MTK_DISP_GAMMA, },
+ { .compatible = "mediatek,mt8195-disp-merge",
+ .data = (void *)MTK_DISP_MERGE },
{ .compatible = "mediatek,mt2701-disp-mutex",
.data = (void *)MTK_DISP_MUTEX },
{ .compatible = "mediatek,mt2712-disp-mutex",
@@ -463,6 +549,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
.data = (void *)MTK_DISP_MUTEX },
{ .compatible = "mediatek,mt8192-disp-mutex",
.data = (void *)MTK_DISP_MUTEX },
+ { .compatible = "mediatek,mt8195-disp-mutex",
+ .data = (void *)MTK_DISP_MUTEX },
{ .compatible = "mediatek,mt8173-disp-od",
.data = (void *)MTK_DISP_OD },
{ .compatible = "mediatek,mt2701-disp-ovl",
@@ -497,6 +585,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
.data = (void *)MTK_DISP_RDMA },
{ .compatible = "mediatek,mt8192-disp-rdma",
.data = (void *)MTK_DISP_RDMA },
+ { .compatible = "mediatek,mt8195-disp-rdma",
+ .data = (void *)MTK_DISP_RDMA },
{ .compatible = "mediatek,mt8173-disp-ufoe",
.data = (void *)MTK_DISP_UFOE },
{ .compatible = "mediatek,mt8173-disp-wdma",
@@ -520,28 +610,51 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
static const struct of_device_id mtk_drm_of_ids[] = {
{ .compatible = "mediatek,mt2701-mmsys",
- .data = &mt2701_mmsys_driver_data},
+ .data = &mt2701_mmsys_match_data},
{ .compatible = "mediatek,mt7623-mmsys",
- .data = &mt7623_mmsys_driver_data},
+ .data = &mt7623_mmsys_match_data},
{ .compatible = "mediatek,mt2712-mmsys",
- .data = &mt2712_mmsys_driver_data},
+ .data = &mt2712_mmsys_match_data},
{ .compatible = "mediatek,mt8167-mmsys",
- .data = &mt8167_mmsys_driver_data},
+ .data = &mt8167_mmsys_match_data},
{ .compatible = "mediatek,mt8173-mmsys",
- .data = &mt8173_mmsys_driver_data},
+ .data = &mt8173_mmsys_match_data},
{ .compatible = "mediatek,mt8183-mmsys",
- .data = &mt8183_mmsys_driver_data},
+ .data = &mt8183_mmsys_match_data},
{ .compatible = "mediatek,mt8192-mmsys",
- .data = &mt8192_mmsys_driver_data},
+ .data = &mt8192_mmsys_match_data},
+ { .compatible = "mediatek,mt8195-mmsys",
+ .data = &mt8195_mmsys_match_data},
{ }
};
MODULE_DEVICE_TABLE(of, mtk_drm_of_ids);
+static int mtk_drm_find_match_data(struct device *dev,
+ const struct mtk_mmsys_match_data *match_data)
+{
+ int i;
+ struct platform_device *pdev = of_find_device_by_node(dev->parent->of_node);
+ struct resource *res;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!res) {
+ dev_err(dev, "failed to get parent resource\n");
+ return -EINVAL;
+ }
+
+ for (i = 0; i < match_data->num_drv_data; i++)
+ if (match_data->drv_data[i]->io_start == res->start)
+ return i;
+
+ return -EINVAL;
+}
+
static int mtk_drm_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct device_node *phandle = dev->parent->of_node;
const struct of_device_id *of_id;
+ const struct mtk_mmsys_match_data *match_data;
struct mtk_drm_private *private;
struct device_node *node;
struct component_match *match = NULL;
@@ -562,7 +675,19 @@ static int mtk_drm_probe(struct platform_device *pdev)
if (!of_id)
return -ENODEV;
- private->data = of_id->data;
+ match_data = of_id->data;
+ if (match_data->num_drv_data > 1) {
+ /* This SoC has multiple mmsys channels */
+ ret = mtk_drm_find_match_data(dev, match_data);
+ if (ret < 0) {
+ dev_err(dev, "Couldn't get match driver data\n");
+ return ret;
+ }
+ private->data = match_data->drv_data[ret];
+ } else {
+ dev_dbg(dev, "Using single mmsys channel\n");
+ private->data = match_data->drv_data[0];
+ }
/* Iterate over sibling DISP function blocks */
for_each_child_of_node(phandle->parent, node) {
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
index a58cebd01d35..9fc922b1684f 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
@@ -21,6 +21,7 @@ struct drm_property;
struct regmap;
struct mtk_mmsys_driver_data {
+ const resource_size_t io_start;
const enum mtk_ddp_comp_id *main_path;
unsigned int main_len;
const enum mtk_ddp_comp_id *ext_path;
@@ -31,6 +32,11 @@ struct mtk_mmsys_driver_data {
bool shadow_register;
};
+struct mtk_mmsys_match_data {
+ unsigned short num_drv_data;
+ const struct mtk_mmsys_driver_data *drv_data[];
+};
+
struct mtk_drm_private {
struct drm_device *drm;
struct device *dma_dev;
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [PATCH v20 6/8] soc: mediatek: add DDP_DOMPONENT_DITHER0 enum for mt8195 vdosys0
2022-04-19 9:41 ` jason-jh.lin
(?)
@ 2022-04-19 9:41 ` jason-jh.lin
-1 siblings, 0 replies; 110+ messages in thread
From: jason-jh.lin @ 2022-04-19 9:41 UTC (permalink / raw)
To: Matthias Brugger, Chun-Kuang Hu, AngeloGioacchino Del Regno
Cc: devicetree, Jason-JH Lin, Singo Chang, linux-kernel, dri-devel,
Project_Global_Chrome_Upstream_Group, Nancy Lin, linux-mediatek,
linux-arm-kernel
The mmsys routing table of mt8195 vdosys0 has 2 DITHER components,
so mmsys need to add DDP_COMPONENT_DITHER1 and change all usages of
DITHER enum form DDP_COMPONENT_DITHER to DDP_COMPONENT_DITHER0.
But its header need to keep DDP_COMPONENT_DITHER enum
until drm/mediatek also changed it.
Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
drivers/soc/mediatek/mt8167-mmsys.h | 2 +-
drivers/soc/mediatek/mt8183-mmsys.h | 2 +-
drivers/soc/mediatek/mt8186-mmsys.h | 4 ++--
drivers/soc/mediatek/mt8192-mmsys.h | 4 ++--
drivers/soc/mediatek/mt8195-mmsys.h | 8 ++++----
drivers/soc/mediatek/mt8365-mmsys.h | 4 ++--
drivers/soc/mediatek/mtk-mutex.c | 10 +++++-----
include/linux/soc/mediatek/mtk-mmsys.h | 1 +
8 files changed, 18 insertions(+), 17 deletions(-)
diff --git a/drivers/soc/mediatek/mt8167-mmsys.h b/drivers/soc/mediatek/mt8167-mmsys.h
index 2772ef5e3934..f7a35b3656bb 100644
--- a/drivers/soc/mediatek/mt8167-mmsys.h
+++ b/drivers/soc/mediatek/mt8167-mmsys.h
@@ -18,7 +18,7 @@ static const struct mtk_mmsys_routes mt8167_mmsys_routing_table[] = {
DDP_COMPONENT_OVL0, DDP_COMPONENT_COLOR0,
MT8167_DISP_REG_CONFIG_DISP_OVL0_MOUT_EN, OVL0_MOUT_EN_COLOR0,
}, {
- DDP_COMPONENT_DITHER, DDP_COMPONENT_RDMA0,
+ DDP_COMPONENT_DITHER0, DDP_COMPONENT_RDMA0,
MT8167_DISP_REG_CONFIG_DISP_DITHER_MOUT_EN, MT8167_DITHER_MOUT_EN_RDMA0
}, {
DDP_COMPONENT_OVL0, DDP_COMPONENT_COLOR0,
diff --git a/drivers/soc/mediatek/mt8183-mmsys.h b/drivers/soc/mediatek/mt8183-mmsys.h
index 0c021f4b76d2..ff6be1703469 100644
--- a/drivers/soc/mediatek/mt8183-mmsys.h
+++ b/drivers/soc/mediatek/mt8183-mmsys.h
@@ -41,7 +41,7 @@ static const struct mtk_mmsys_routes mmsys_mt8183_routing_table[] = {
MT8183_DISP_OVL1_2L_MOUT_EN, MT8183_OVL1_2L_MOUT_EN_RDMA1,
MT8183_OVL1_2L_MOUT_EN_RDMA1
}, {
- DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
+ DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
MT8183_DISP_DITHER0_MOUT_EN, MT8183_DITHER0_MOUT_IN_DSI0,
MT8183_DITHER0_MOUT_IN_DSI0
}, {
diff --git a/drivers/soc/mediatek/mt8186-mmsys.h b/drivers/soc/mediatek/mt8186-mmsys.h
index c72ccf86ea28..eb1ad9c37a9c 100644
--- a/drivers/soc/mediatek/mt8186-mmsys.h
+++ b/drivers/soc/mediatek/mt8186-mmsys.h
@@ -76,12 +76,12 @@ static const struct mtk_mmsys_routes mmsys_mt8186_routing_table[] = {
MT8186_RDMA0_SOUT_TO_COLOR0
},
{
- DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
+ DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
MT8186_DISP_DITHER0_MOUT_EN, MT8186_DITHER0_MOUT_EN_MASK,
MT8186_DITHER0_MOUT_TO_DSI0,
},
{
- DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
+ DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
MT8186_DISP_DSI0_SEL_IN, MT8186_DSI0_SEL_IN_MASK,
MT8186_DSI0_FROM_DITHER0
},
diff --git a/drivers/soc/mediatek/mt8192-mmsys.h b/drivers/soc/mediatek/mt8192-mmsys.h
index 6aae0b12b6ff..a016d80b4bc1 100644
--- a/drivers/soc/mediatek/mt8192-mmsys.h
+++ b/drivers/soc/mediatek/mt8192-mmsys.h
@@ -40,7 +40,7 @@ static const struct mtk_mmsys_routes mmsys_mt8192_routing_table[] = {
MT8192_DISP_OVL2_2L_MOUT_EN, MT8192_OVL2_2L_MOUT_EN_RDMA4,
MT8192_OVL2_2L_MOUT_EN_RDMA4
}, {
- DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
+ DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
MT8192_DISP_DITHER0_MOUT_EN, MT8192_DITHER0_MOUT_IN_DSI0,
MT8192_DITHER0_MOUT_IN_DSI0
}, {
@@ -52,7 +52,7 @@ static const struct mtk_mmsys_routes mmsys_mt8192_routing_table[] = {
MT8192_DISP_AAL0_SEL_IN, MT8192_AAL0_SEL_IN_CCORR0,
MT8192_AAL0_SEL_IN_CCORR0
}, {
- DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
+ DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
MT8192_DISP_DSI0_SEL_IN, MT8192_DSI0_SEL_IN_DITHER0,
MT8192_DSI0_SEL_IN_DITHER0
}, {
diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h
index 13ab0ab64396..abfe94a30248 100644
--- a/drivers/soc/mediatek/mt8195-mmsys.h
+++ b/drivers/soc/mediatek/mt8195-mmsys.h
@@ -113,7 +113,7 @@ static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK,
MT8195_SEL_IN_VPP_MERGE_FROM_VDO1_VIRTUAL0
}, {
- DDP_COMPONENT_DITHER, DDP_COMPONENT_DSC0,
+ DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSC0,
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK,
MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0
}, {
@@ -181,7 +181,7 @@ static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI0_FROM_MASK,
MT8195_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT
}, {
- DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
+ DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI0_FROM_MASK,
MT8195_SEL_IN_DSI0_FROM_DISP_DITHER0
}, {
@@ -245,11 +245,11 @@ static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA0_FROM_MASK,
MT8195_SEL_IN_DISP_WDMA0_FROM_DISP_OVL0
}, {
- DDP_COMPONENT_DITHER, DDP_COMPONENT_DSC0,
+ DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSC0,
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER0_TO_MASK,
MT8195_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN
}, {
- DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
+ DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER0_TO_MASK,
MT8195_SOUT_DISP_DITHER0_TO_DSI0
}, {
diff --git a/drivers/soc/mediatek/mt8365-mmsys.h b/drivers/soc/mediatek/mt8365-mmsys.h
index 690e3fe2dee0..24129a6c25f8 100644
--- a/drivers/soc/mediatek/mt8365-mmsys.h
+++ b/drivers/soc/mediatek/mt8365-mmsys.h
@@ -41,12 +41,12 @@ static const struct mtk_mmsys_routes mt8365_mmsys_routing_table[] = {
MT8365_DISP_COLOR_SEL_IN_COLOR0,MT8365_DISP_COLOR_SEL_IN_COLOR0
},
{
- DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
+ DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
MT8365_DISP_REG_CONFIG_DISP_DITHER0_MOUT_EN,
MT8365_DITHER_MOUT_EN_DSI0, MT8365_DITHER_MOUT_EN_DSI0
},
{
- DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
+ DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
MT8365_DISP_REG_CONFIG_DISP_DSI0_SEL_IN,
MT8365_DSI0_SEL_IN_DITHER, MT8365_DSI0_SEL_IN_DITHER
},
diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c
index 729ee88035ed..9184684baf1d 100644
--- a/drivers/soc/mediatek/mtk-mutex.c
+++ b/drivers/soc/mediatek/mtk-mutex.c
@@ -232,7 +232,7 @@ static const unsigned int mt8167_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_AAL0] = MT8167_MUTEX_MOD_DISP_AAL,
[DDP_COMPONENT_CCORR] = MT8167_MUTEX_MOD_DISP_CCORR,
[DDP_COMPONENT_COLOR0] = MT8167_MUTEX_MOD_DISP_COLOR,
- [DDP_COMPONENT_DITHER] = MT8167_MUTEX_MOD_DISP_DITHER,
+ [DDP_COMPONENT_DITHER0] = MT8167_MUTEX_MOD_DISP_DITHER,
[DDP_COMPONENT_GAMMA] = MT8167_MUTEX_MOD_DISP_GAMMA,
[DDP_COMPONENT_OVL0] = MT8167_MUTEX_MOD_DISP_OVL0,
[DDP_COMPONENT_OVL1] = MT8167_MUTEX_MOD_DISP_OVL1,
@@ -265,7 +265,7 @@ static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_AAL0] = MT8183_MUTEX_MOD_DISP_AAL0,
[DDP_COMPONENT_CCORR] = MT8183_MUTEX_MOD_DISP_CCORR0,
[DDP_COMPONENT_COLOR0] = MT8183_MUTEX_MOD_DISP_COLOR0,
- [DDP_COMPONENT_DITHER] = MT8183_MUTEX_MOD_DISP_DITHER0,
+ [DDP_COMPONENT_DITHER0] = MT8183_MUTEX_MOD_DISP_DITHER0,
[DDP_COMPONENT_GAMMA] = MT8183_MUTEX_MOD_DISP_GAMMA0,
[DDP_COMPONENT_OVL0] = MT8183_MUTEX_MOD_DISP_OVL0,
[DDP_COMPONENT_OVL_2L0] = MT8183_MUTEX_MOD_DISP_OVL0_2L,
@@ -279,7 +279,7 @@ static const unsigned int mt8186_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_AAL0] = MT8186_MUTEX_MOD_DISP_AAL0,
[DDP_COMPONENT_CCORR] = MT8186_MUTEX_MOD_DISP_CCORR0,
[DDP_COMPONENT_COLOR0] = MT8186_MUTEX_MOD_DISP_COLOR0,
- [DDP_COMPONENT_DITHER] = MT8186_MUTEX_MOD_DISP_DITHER0,
+ [DDP_COMPONENT_DITHER0] = MT8186_MUTEX_MOD_DISP_DITHER0,
[DDP_COMPONENT_GAMMA] = MT8186_MUTEX_MOD_DISP_GAMMA0,
[DDP_COMPONENT_OVL0] = MT8186_MUTEX_MOD_DISP_OVL0,
[DDP_COMPONENT_OVL_2L0] = MT8186_MUTEX_MOD_DISP_OVL0_2L,
@@ -292,7 +292,7 @@ static const unsigned int mt8192_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_AAL0] = MT8192_MUTEX_MOD_DISP_AAL0,
[DDP_COMPONENT_CCORR] = MT8192_MUTEX_MOD_DISP_CCORR0,
[DDP_COMPONENT_COLOR0] = MT8192_MUTEX_MOD_DISP_COLOR0,
- [DDP_COMPONENT_DITHER] = MT8192_MUTEX_MOD_DISP_DITHER0,
+ [DDP_COMPONENT_DITHER0] = MT8192_MUTEX_MOD_DISP_DITHER0,
[DDP_COMPONENT_GAMMA] = MT8192_MUTEX_MOD_DISP_GAMMA0,
[DDP_COMPONENT_POSTMASK0] = MT8192_MUTEX_MOD_DISP_POSTMASK0,
[DDP_COMPONENT_OVL0] = MT8192_MUTEX_MOD_DISP_OVL0,
@@ -310,7 +310,7 @@ static const unsigned int mt8195_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_CCORR] = MT8195_MUTEX_MOD_DISP_CCORR0,
[DDP_COMPONENT_AAL0] = MT8195_MUTEX_MOD_DISP_AAL0,
[DDP_COMPONENT_GAMMA] = MT8195_MUTEX_MOD_DISP_GAMMA0,
- [DDP_COMPONENT_DITHER] = MT8195_MUTEX_MOD_DISP_DITHER0,
+ [DDP_COMPONENT_DITHER0] = MT8195_MUTEX_MOD_DISP_DITHER0,
[DDP_COMPONENT_MERGE0] = MT8195_MUTEX_MOD_DISP_VPP_MERGE,
[DDP_COMPONENT_DSC0] = MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0,
[DDP_COMPONENT_DSI0] = MT8195_MUTEX_MOD_DISP_DSI0,
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
index cff5c9adbf46..59117d970daf 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -17,6 +17,7 @@ enum mtk_ddp_comp_id {
DDP_COMPONENT_COLOR0,
DDP_COMPONENT_COLOR1,
DDP_COMPONENT_DITHER,
+ DDP_COMPONENT_DITHER0 = DDP_COMPONENT_DITHER,
DDP_COMPONENT_DITHER1,
DDP_COMPONENT_DP_INTF0,
DDP_COMPONENT_DP_INTF1,
--
2.18.0
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [PATCH v20 6/8] soc: mediatek: add DDP_DOMPONENT_DITHER0 enum for mt8195 vdosys0
@ 2022-04-19 9:41 ` jason-jh.lin
0 siblings, 0 replies; 110+ messages in thread
From: jason-jh.lin @ 2022-04-19 9:41 UTC (permalink / raw)
To: Matthias Brugger, Chun-Kuang Hu, AngeloGioacchino Del Regno
Cc: CK Hu, Jason-JH Lin, Nancy Lin, Singo Chang, devicetree,
linux-kernel, dri-devel, linux-mediatek, linux-arm-kernel,
Project_Global_Chrome_Upstream_Group
The mmsys routing table of mt8195 vdosys0 has 2 DITHER components,
so mmsys need to add DDP_COMPONENT_DITHER1 and change all usages of
DITHER enum form DDP_COMPONENT_DITHER to DDP_COMPONENT_DITHER0.
But its header need to keep DDP_COMPONENT_DITHER enum
until drm/mediatek also changed it.
Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
drivers/soc/mediatek/mt8167-mmsys.h | 2 +-
drivers/soc/mediatek/mt8183-mmsys.h | 2 +-
drivers/soc/mediatek/mt8186-mmsys.h | 4 ++--
drivers/soc/mediatek/mt8192-mmsys.h | 4 ++--
drivers/soc/mediatek/mt8195-mmsys.h | 8 ++++----
drivers/soc/mediatek/mt8365-mmsys.h | 4 ++--
drivers/soc/mediatek/mtk-mutex.c | 10 +++++-----
include/linux/soc/mediatek/mtk-mmsys.h | 1 +
8 files changed, 18 insertions(+), 17 deletions(-)
diff --git a/drivers/soc/mediatek/mt8167-mmsys.h b/drivers/soc/mediatek/mt8167-mmsys.h
index 2772ef5e3934..f7a35b3656bb 100644
--- a/drivers/soc/mediatek/mt8167-mmsys.h
+++ b/drivers/soc/mediatek/mt8167-mmsys.h
@@ -18,7 +18,7 @@ static const struct mtk_mmsys_routes mt8167_mmsys_routing_table[] = {
DDP_COMPONENT_OVL0, DDP_COMPONENT_COLOR0,
MT8167_DISP_REG_CONFIG_DISP_OVL0_MOUT_EN, OVL0_MOUT_EN_COLOR0,
}, {
- DDP_COMPONENT_DITHER, DDP_COMPONENT_RDMA0,
+ DDP_COMPONENT_DITHER0, DDP_COMPONENT_RDMA0,
MT8167_DISP_REG_CONFIG_DISP_DITHER_MOUT_EN, MT8167_DITHER_MOUT_EN_RDMA0
}, {
DDP_COMPONENT_OVL0, DDP_COMPONENT_COLOR0,
diff --git a/drivers/soc/mediatek/mt8183-mmsys.h b/drivers/soc/mediatek/mt8183-mmsys.h
index 0c021f4b76d2..ff6be1703469 100644
--- a/drivers/soc/mediatek/mt8183-mmsys.h
+++ b/drivers/soc/mediatek/mt8183-mmsys.h
@@ -41,7 +41,7 @@ static const struct mtk_mmsys_routes mmsys_mt8183_routing_table[] = {
MT8183_DISP_OVL1_2L_MOUT_EN, MT8183_OVL1_2L_MOUT_EN_RDMA1,
MT8183_OVL1_2L_MOUT_EN_RDMA1
}, {
- DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
+ DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
MT8183_DISP_DITHER0_MOUT_EN, MT8183_DITHER0_MOUT_IN_DSI0,
MT8183_DITHER0_MOUT_IN_DSI0
}, {
diff --git a/drivers/soc/mediatek/mt8186-mmsys.h b/drivers/soc/mediatek/mt8186-mmsys.h
index c72ccf86ea28..eb1ad9c37a9c 100644
--- a/drivers/soc/mediatek/mt8186-mmsys.h
+++ b/drivers/soc/mediatek/mt8186-mmsys.h
@@ -76,12 +76,12 @@ static const struct mtk_mmsys_routes mmsys_mt8186_routing_table[] = {
MT8186_RDMA0_SOUT_TO_COLOR0
},
{
- DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
+ DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
MT8186_DISP_DITHER0_MOUT_EN, MT8186_DITHER0_MOUT_EN_MASK,
MT8186_DITHER0_MOUT_TO_DSI0,
},
{
- DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
+ DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
MT8186_DISP_DSI0_SEL_IN, MT8186_DSI0_SEL_IN_MASK,
MT8186_DSI0_FROM_DITHER0
},
diff --git a/drivers/soc/mediatek/mt8192-mmsys.h b/drivers/soc/mediatek/mt8192-mmsys.h
index 6aae0b12b6ff..a016d80b4bc1 100644
--- a/drivers/soc/mediatek/mt8192-mmsys.h
+++ b/drivers/soc/mediatek/mt8192-mmsys.h
@@ -40,7 +40,7 @@ static const struct mtk_mmsys_routes mmsys_mt8192_routing_table[] = {
MT8192_DISP_OVL2_2L_MOUT_EN, MT8192_OVL2_2L_MOUT_EN_RDMA4,
MT8192_OVL2_2L_MOUT_EN_RDMA4
}, {
- DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
+ DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
MT8192_DISP_DITHER0_MOUT_EN, MT8192_DITHER0_MOUT_IN_DSI0,
MT8192_DITHER0_MOUT_IN_DSI0
}, {
@@ -52,7 +52,7 @@ static const struct mtk_mmsys_routes mmsys_mt8192_routing_table[] = {
MT8192_DISP_AAL0_SEL_IN, MT8192_AAL0_SEL_IN_CCORR0,
MT8192_AAL0_SEL_IN_CCORR0
}, {
- DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
+ DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
MT8192_DISP_DSI0_SEL_IN, MT8192_DSI0_SEL_IN_DITHER0,
MT8192_DSI0_SEL_IN_DITHER0
}, {
diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h
index 13ab0ab64396..abfe94a30248 100644
--- a/drivers/soc/mediatek/mt8195-mmsys.h
+++ b/drivers/soc/mediatek/mt8195-mmsys.h
@@ -113,7 +113,7 @@ static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK,
MT8195_SEL_IN_VPP_MERGE_FROM_VDO1_VIRTUAL0
}, {
- DDP_COMPONENT_DITHER, DDP_COMPONENT_DSC0,
+ DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSC0,
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK,
MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0
}, {
@@ -181,7 +181,7 @@ static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI0_FROM_MASK,
MT8195_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT
}, {
- DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
+ DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI0_FROM_MASK,
MT8195_SEL_IN_DSI0_FROM_DISP_DITHER0
}, {
@@ -245,11 +245,11 @@ static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA0_FROM_MASK,
MT8195_SEL_IN_DISP_WDMA0_FROM_DISP_OVL0
}, {
- DDP_COMPONENT_DITHER, DDP_COMPONENT_DSC0,
+ DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSC0,
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER0_TO_MASK,
MT8195_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN
}, {
- DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
+ DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER0_TO_MASK,
MT8195_SOUT_DISP_DITHER0_TO_DSI0
}, {
diff --git a/drivers/soc/mediatek/mt8365-mmsys.h b/drivers/soc/mediatek/mt8365-mmsys.h
index 690e3fe2dee0..24129a6c25f8 100644
--- a/drivers/soc/mediatek/mt8365-mmsys.h
+++ b/drivers/soc/mediatek/mt8365-mmsys.h
@@ -41,12 +41,12 @@ static const struct mtk_mmsys_routes mt8365_mmsys_routing_table[] = {
MT8365_DISP_COLOR_SEL_IN_COLOR0,MT8365_DISP_COLOR_SEL_IN_COLOR0
},
{
- DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
+ DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
MT8365_DISP_REG_CONFIG_DISP_DITHER0_MOUT_EN,
MT8365_DITHER_MOUT_EN_DSI0, MT8365_DITHER_MOUT_EN_DSI0
},
{
- DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
+ DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
MT8365_DISP_REG_CONFIG_DISP_DSI0_SEL_IN,
MT8365_DSI0_SEL_IN_DITHER, MT8365_DSI0_SEL_IN_DITHER
},
diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c
index 729ee88035ed..9184684baf1d 100644
--- a/drivers/soc/mediatek/mtk-mutex.c
+++ b/drivers/soc/mediatek/mtk-mutex.c
@@ -232,7 +232,7 @@ static const unsigned int mt8167_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_AAL0] = MT8167_MUTEX_MOD_DISP_AAL,
[DDP_COMPONENT_CCORR] = MT8167_MUTEX_MOD_DISP_CCORR,
[DDP_COMPONENT_COLOR0] = MT8167_MUTEX_MOD_DISP_COLOR,
- [DDP_COMPONENT_DITHER] = MT8167_MUTEX_MOD_DISP_DITHER,
+ [DDP_COMPONENT_DITHER0] = MT8167_MUTEX_MOD_DISP_DITHER,
[DDP_COMPONENT_GAMMA] = MT8167_MUTEX_MOD_DISP_GAMMA,
[DDP_COMPONENT_OVL0] = MT8167_MUTEX_MOD_DISP_OVL0,
[DDP_COMPONENT_OVL1] = MT8167_MUTEX_MOD_DISP_OVL1,
@@ -265,7 +265,7 @@ static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_AAL0] = MT8183_MUTEX_MOD_DISP_AAL0,
[DDP_COMPONENT_CCORR] = MT8183_MUTEX_MOD_DISP_CCORR0,
[DDP_COMPONENT_COLOR0] = MT8183_MUTEX_MOD_DISP_COLOR0,
- [DDP_COMPONENT_DITHER] = MT8183_MUTEX_MOD_DISP_DITHER0,
+ [DDP_COMPONENT_DITHER0] = MT8183_MUTEX_MOD_DISP_DITHER0,
[DDP_COMPONENT_GAMMA] = MT8183_MUTEX_MOD_DISP_GAMMA0,
[DDP_COMPONENT_OVL0] = MT8183_MUTEX_MOD_DISP_OVL0,
[DDP_COMPONENT_OVL_2L0] = MT8183_MUTEX_MOD_DISP_OVL0_2L,
@@ -279,7 +279,7 @@ static const unsigned int mt8186_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_AAL0] = MT8186_MUTEX_MOD_DISP_AAL0,
[DDP_COMPONENT_CCORR] = MT8186_MUTEX_MOD_DISP_CCORR0,
[DDP_COMPONENT_COLOR0] = MT8186_MUTEX_MOD_DISP_COLOR0,
- [DDP_COMPONENT_DITHER] = MT8186_MUTEX_MOD_DISP_DITHER0,
+ [DDP_COMPONENT_DITHER0] = MT8186_MUTEX_MOD_DISP_DITHER0,
[DDP_COMPONENT_GAMMA] = MT8186_MUTEX_MOD_DISP_GAMMA0,
[DDP_COMPONENT_OVL0] = MT8186_MUTEX_MOD_DISP_OVL0,
[DDP_COMPONENT_OVL_2L0] = MT8186_MUTEX_MOD_DISP_OVL0_2L,
@@ -292,7 +292,7 @@ static const unsigned int mt8192_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_AAL0] = MT8192_MUTEX_MOD_DISP_AAL0,
[DDP_COMPONENT_CCORR] = MT8192_MUTEX_MOD_DISP_CCORR0,
[DDP_COMPONENT_COLOR0] = MT8192_MUTEX_MOD_DISP_COLOR0,
- [DDP_COMPONENT_DITHER] = MT8192_MUTEX_MOD_DISP_DITHER0,
+ [DDP_COMPONENT_DITHER0] = MT8192_MUTEX_MOD_DISP_DITHER0,
[DDP_COMPONENT_GAMMA] = MT8192_MUTEX_MOD_DISP_GAMMA0,
[DDP_COMPONENT_POSTMASK0] = MT8192_MUTEX_MOD_DISP_POSTMASK0,
[DDP_COMPONENT_OVL0] = MT8192_MUTEX_MOD_DISP_OVL0,
@@ -310,7 +310,7 @@ static const unsigned int mt8195_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_CCORR] = MT8195_MUTEX_MOD_DISP_CCORR0,
[DDP_COMPONENT_AAL0] = MT8195_MUTEX_MOD_DISP_AAL0,
[DDP_COMPONENT_GAMMA] = MT8195_MUTEX_MOD_DISP_GAMMA0,
- [DDP_COMPONENT_DITHER] = MT8195_MUTEX_MOD_DISP_DITHER0,
+ [DDP_COMPONENT_DITHER0] = MT8195_MUTEX_MOD_DISP_DITHER0,
[DDP_COMPONENT_MERGE0] = MT8195_MUTEX_MOD_DISP_VPP_MERGE,
[DDP_COMPONENT_DSC0] = MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0,
[DDP_COMPONENT_DSI0] = MT8195_MUTEX_MOD_DISP_DSI0,
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
index cff5c9adbf46..59117d970daf 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -17,6 +17,7 @@ enum mtk_ddp_comp_id {
DDP_COMPONENT_COLOR0,
DDP_COMPONENT_COLOR1,
DDP_COMPONENT_DITHER,
+ DDP_COMPONENT_DITHER0 = DDP_COMPONENT_DITHER,
DDP_COMPONENT_DITHER1,
DDP_COMPONENT_DP_INTF0,
DDP_COMPONENT_DP_INTF1,
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [PATCH v20 6/8] soc: mediatek: add DDP_DOMPONENT_DITHER0 enum for mt8195 vdosys0
@ 2022-04-19 9:41 ` jason-jh.lin
0 siblings, 0 replies; 110+ messages in thread
From: jason-jh.lin @ 2022-04-19 9:41 UTC (permalink / raw)
To: Matthias Brugger, Chun-Kuang Hu, AngeloGioacchino Del Regno
Cc: CK Hu, Jason-JH Lin, Nancy Lin, Singo Chang, devicetree,
linux-kernel, dri-devel, linux-mediatek, linux-arm-kernel,
Project_Global_Chrome_Upstream_Group
The mmsys routing table of mt8195 vdosys0 has 2 DITHER components,
so mmsys need to add DDP_COMPONENT_DITHER1 and change all usages of
DITHER enum form DDP_COMPONENT_DITHER to DDP_COMPONENT_DITHER0.
But its header need to keep DDP_COMPONENT_DITHER enum
until drm/mediatek also changed it.
Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
drivers/soc/mediatek/mt8167-mmsys.h | 2 +-
drivers/soc/mediatek/mt8183-mmsys.h | 2 +-
drivers/soc/mediatek/mt8186-mmsys.h | 4 ++--
drivers/soc/mediatek/mt8192-mmsys.h | 4 ++--
drivers/soc/mediatek/mt8195-mmsys.h | 8 ++++----
drivers/soc/mediatek/mt8365-mmsys.h | 4 ++--
drivers/soc/mediatek/mtk-mutex.c | 10 +++++-----
include/linux/soc/mediatek/mtk-mmsys.h | 1 +
8 files changed, 18 insertions(+), 17 deletions(-)
diff --git a/drivers/soc/mediatek/mt8167-mmsys.h b/drivers/soc/mediatek/mt8167-mmsys.h
index 2772ef5e3934..f7a35b3656bb 100644
--- a/drivers/soc/mediatek/mt8167-mmsys.h
+++ b/drivers/soc/mediatek/mt8167-mmsys.h
@@ -18,7 +18,7 @@ static const struct mtk_mmsys_routes mt8167_mmsys_routing_table[] = {
DDP_COMPONENT_OVL0, DDP_COMPONENT_COLOR0,
MT8167_DISP_REG_CONFIG_DISP_OVL0_MOUT_EN, OVL0_MOUT_EN_COLOR0,
}, {
- DDP_COMPONENT_DITHER, DDP_COMPONENT_RDMA0,
+ DDP_COMPONENT_DITHER0, DDP_COMPONENT_RDMA0,
MT8167_DISP_REG_CONFIG_DISP_DITHER_MOUT_EN, MT8167_DITHER_MOUT_EN_RDMA0
}, {
DDP_COMPONENT_OVL0, DDP_COMPONENT_COLOR0,
diff --git a/drivers/soc/mediatek/mt8183-mmsys.h b/drivers/soc/mediatek/mt8183-mmsys.h
index 0c021f4b76d2..ff6be1703469 100644
--- a/drivers/soc/mediatek/mt8183-mmsys.h
+++ b/drivers/soc/mediatek/mt8183-mmsys.h
@@ -41,7 +41,7 @@ static const struct mtk_mmsys_routes mmsys_mt8183_routing_table[] = {
MT8183_DISP_OVL1_2L_MOUT_EN, MT8183_OVL1_2L_MOUT_EN_RDMA1,
MT8183_OVL1_2L_MOUT_EN_RDMA1
}, {
- DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
+ DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
MT8183_DISP_DITHER0_MOUT_EN, MT8183_DITHER0_MOUT_IN_DSI0,
MT8183_DITHER0_MOUT_IN_DSI0
}, {
diff --git a/drivers/soc/mediatek/mt8186-mmsys.h b/drivers/soc/mediatek/mt8186-mmsys.h
index c72ccf86ea28..eb1ad9c37a9c 100644
--- a/drivers/soc/mediatek/mt8186-mmsys.h
+++ b/drivers/soc/mediatek/mt8186-mmsys.h
@@ -76,12 +76,12 @@ static const struct mtk_mmsys_routes mmsys_mt8186_routing_table[] = {
MT8186_RDMA0_SOUT_TO_COLOR0
},
{
- DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
+ DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
MT8186_DISP_DITHER0_MOUT_EN, MT8186_DITHER0_MOUT_EN_MASK,
MT8186_DITHER0_MOUT_TO_DSI0,
},
{
- DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
+ DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
MT8186_DISP_DSI0_SEL_IN, MT8186_DSI0_SEL_IN_MASK,
MT8186_DSI0_FROM_DITHER0
},
diff --git a/drivers/soc/mediatek/mt8192-mmsys.h b/drivers/soc/mediatek/mt8192-mmsys.h
index 6aae0b12b6ff..a016d80b4bc1 100644
--- a/drivers/soc/mediatek/mt8192-mmsys.h
+++ b/drivers/soc/mediatek/mt8192-mmsys.h
@@ -40,7 +40,7 @@ static const struct mtk_mmsys_routes mmsys_mt8192_routing_table[] = {
MT8192_DISP_OVL2_2L_MOUT_EN, MT8192_OVL2_2L_MOUT_EN_RDMA4,
MT8192_OVL2_2L_MOUT_EN_RDMA4
}, {
- DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
+ DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
MT8192_DISP_DITHER0_MOUT_EN, MT8192_DITHER0_MOUT_IN_DSI0,
MT8192_DITHER0_MOUT_IN_DSI0
}, {
@@ -52,7 +52,7 @@ static const struct mtk_mmsys_routes mmsys_mt8192_routing_table[] = {
MT8192_DISP_AAL0_SEL_IN, MT8192_AAL0_SEL_IN_CCORR0,
MT8192_AAL0_SEL_IN_CCORR0
}, {
- DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
+ DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
MT8192_DISP_DSI0_SEL_IN, MT8192_DSI0_SEL_IN_DITHER0,
MT8192_DSI0_SEL_IN_DITHER0
}, {
diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h
index 13ab0ab64396..abfe94a30248 100644
--- a/drivers/soc/mediatek/mt8195-mmsys.h
+++ b/drivers/soc/mediatek/mt8195-mmsys.h
@@ -113,7 +113,7 @@ static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK,
MT8195_SEL_IN_VPP_MERGE_FROM_VDO1_VIRTUAL0
}, {
- DDP_COMPONENT_DITHER, DDP_COMPONENT_DSC0,
+ DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSC0,
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK,
MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0
}, {
@@ -181,7 +181,7 @@ static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI0_FROM_MASK,
MT8195_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT
}, {
- DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
+ DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI0_FROM_MASK,
MT8195_SEL_IN_DSI0_FROM_DISP_DITHER0
}, {
@@ -245,11 +245,11 @@ static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA0_FROM_MASK,
MT8195_SEL_IN_DISP_WDMA0_FROM_DISP_OVL0
}, {
- DDP_COMPONENT_DITHER, DDP_COMPONENT_DSC0,
+ DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSC0,
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER0_TO_MASK,
MT8195_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN
}, {
- DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
+ DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER0_TO_MASK,
MT8195_SOUT_DISP_DITHER0_TO_DSI0
}, {
diff --git a/drivers/soc/mediatek/mt8365-mmsys.h b/drivers/soc/mediatek/mt8365-mmsys.h
index 690e3fe2dee0..24129a6c25f8 100644
--- a/drivers/soc/mediatek/mt8365-mmsys.h
+++ b/drivers/soc/mediatek/mt8365-mmsys.h
@@ -41,12 +41,12 @@ static const struct mtk_mmsys_routes mt8365_mmsys_routing_table[] = {
MT8365_DISP_COLOR_SEL_IN_COLOR0,MT8365_DISP_COLOR_SEL_IN_COLOR0
},
{
- DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
+ DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
MT8365_DISP_REG_CONFIG_DISP_DITHER0_MOUT_EN,
MT8365_DITHER_MOUT_EN_DSI0, MT8365_DITHER_MOUT_EN_DSI0
},
{
- DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
+ DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
MT8365_DISP_REG_CONFIG_DISP_DSI0_SEL_IN,
MT8365_DSI0_SEL_IN_DITHER, MT8365_DSI0_SEL_IN_DITHER
},
diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c
index 729ee88035ed..9184684baf1d 100644
--- a/drivers/soc/mediatek/mtk-mutex.c
+++ b/drivers/soc/mediatek/mtk-mutex.c
@@ -232,7 +232,7 @@ static const unsigned int mt8167_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_AAL0] = MT8167_MUTEX_MOD_DISP_AAL,
[DDP_COMPONENT_CCORR] = MT8167_MUTEX_MOD_DISP_CCORR,
[DDP_COMPONENT_COLOR0] = MT8167_MUTEX_MOD_DISP_COLOR,
- [DDP_COMPONENT_DITHER] = MT8167_MUTEX_MOD_DISP_DITHER,
+ [DDP_COMPONENT_DITHER0] = MT8167_MUTEX_MOD_DISP_DITHER,
[DDP_COMPONENT_GAMMA] = MT8167_MUTEX_MOD_DISP_GAMMA,
[DDP_COMPONENT_OVL0] = MT8167_MUTEX_MOD_DISP_OVL0,
[DDP_COMPONENT_OVL1] = MT8167_MUTEX_MOD_DISP_OVL1,
@@ -265,7 +265,7 @@ static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_AAL0] = MT8183_MUTEX_MOD_DISP_AAL0,
[DDP_COMPONENT_CCORR] = MT8183_MUTEX_MOD_DISP_CCORR0,
[DDP_COMPONENT_COLOR0] = MT8183_MUTEX_MOD_DISP_COLOR0,
- [DDP_COMPONENT_DITHER] = MT8183_MUTEX_MOD_DISP_DITHER0,
+ [DDP_COMPONENT_DITHER0] = MT8183_MUTEX_MOD_DISP_DITHER0,
[DDP_COMPONENT_GAMMA] = MT8183_MUTEX_MOD_DISP_GAMMA0,
[DDP_COMPONENT_OVL0] = MT8183_MUTEX_MOD_DISP_OVL0,
[DDP_COMPONENT_OVL_2L0] = MT8183_MUTEX_MOD_DISP_OVL0_2L,
@@ -279,7 +279,7 @@ static const unsigned int mt8186_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_AAL0] = MT8186_MUTEX_MOD_DISP_AAL0,
[DDP_COMPONENT_CCORR] = MT8186_MUTEX_MOD_DISP_CCORR0,
[DDP_COMPONENT_COLOR0] = MT8186_MUTEX_MOD_DISP_COLOR0,
- [DDP_COMPONENT_DITHER] = MT8186_MUTEX_MOD_DISP_DITHER0,
+ [DDP_COMPONENT_DITHER0] = MT8186_MUTEX_MOD_DISP_DITHER0,
[DDP_COMPONENT_GAMMA] = MT8186_MUTEX_MOD_DISP_GAMMA0,
[DDP_COMPONENT_OVL0] = MT8186_MUTEX_MOD_DISP_OVL0,
[DDP_COMPONENT_OVL_2L0] = MT8186_MUTEX_MOD_DISP_OVL0_2L,
@@ -292,7 +292,7 @@ static const unsigned int mt8192_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_AAL0] = MT8192_MUTEX_MOD_DISP_AAL0,
[DDP_COMPONENT_CCORR] = MT8192_MUTEX_MOD_DISP_CCORR0,
[DDP_COMPONENT_COLOR0] = MT8192_MUTEX_MOD_DISP_COLOR0,
- [DDP_COMPONENT_DITHER] = MT8192_MUTEX_MOD_DISP_DITHER0,
+ [DDP_COMPONENT_DITHER0] = MT8192_MUTEX_MOD_DISP_DITHER0,
[DDP_COMPONENT_GAMMA] = MT8192_MUTEX_MOD_DISP_GAMMA0,
[DDP_COMPONENT_POSTMASK0] = MT8192_MUTEX_MOD_DISP_POSTMASK0,
[DDP_COMPONENT_OVL0] = MT8192_MUTEX_MOD_DISP_OVL0,
@@ -310,7 +310,7 @@ static const unsigned int mt8195_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_CCORR] = MT8195_MUTEX_MOD_DISP_CCORR0,
[DDP_COMPONENT_AAL0] = MT8195_MUTEX_MOD_DISP_AAL0,
[DDP_COMPONENT_GAMMA] = MT8195_MUTEX_MOD_DISP_GAMMA0,
- [DDP_COMPONENT_DITHER] = MT8195_MUTEX_MOD_DISP_DITHER0,
+ [DDP_COMPONENT_DITHER0] = MT8195_MUTEX_MOD_DISP_DITHER0,
[DDP_COMPONENT_MERGE0] = MT8195_MUTEX_MOD_DISP_VPP_MERGE,
[DDP_COMPONENT_DSC0] = MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0,
[DDP_COMPONENT_DSI0] = MT8195_MUTEX_MOD_DISP_DSI0,
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
index cff5c9adbf46..59117d970daf 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -17,6 +17,7 @@ enum mtk_ddp_comp_id {
DDP_COMPONENT_COLOR0,
DDP_COMPONENT_COLOR1,
DDP_COMPONENT_DITHER,
+ DDP_COMPONENT_DITHER0 = DDP_COMPONENT_DITHER,
DDP_COMPONENT_DITHER1,
DDP_COMPONENT_DP_INTF0,
DDP_COMPONENT_DP_INTF1,
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [PATCH v20 7/8] drm/mediatek: add suffix 0 to DDP_COMPONENT_DITHER for mt8195 vdosys0
2022-04-19 9:41 ` jason-jh.lin
(?)
@ 2022-04-19 9:41 ` jason-jh.lin
-1 siblings, 0 replies; 110+ messages in thread
From: jason-jh.lin @ 2022-04-19 9:41 UTC (permalink / raw)
To: Matthias Brugger, Chun-Kuang Hu, AngeloGioacchino Del Regno
Cc: devicetree, Jason-JH Lin, Singo Chang, linux-kernel, dri-devel,
Project_Global_Chrome_Upstream_Group, Nancy Lin, linux-mediatek,
linux-arm-kernel
Because mt8195 vdosys0 has 2 DITHER components,
so the suffix 0 need to be added to DDP_COMPONENT_DITHER.
Then DITHER enum will become:
DDP_COMPONENT_DITHER0 and DDP_COMPONENT_DITHER1.
Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 2 +-
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 8 ++++----
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index f683e768d61b..95722de4986b 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -420,7 +420,7 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_CCORR] = { MTK_DISP_CCORR, 0, &ddp_ccorr },
[DDP_COMPONENT_COLOR0] = { MTK_DISP_COLOR, 0, &ddp_color },
[DDP_COMPONENT_COLOR1] = { MTK_DISP_COLOR, 1, &ddp_color },
- [DDP_COMPONENT_DITHER] = { MTK_DISP_DITHER, 0, &ddp_dither },
+ [DDP_COMPONENT_DITHER0] = { MTK_DISP_DITHER, 0, &ddp_dither },
[DDP_COMPONENT_DPI0] = { MTK_DPI, 0, &ddp_dpi },
[DDP_COMPONENT_DPI1] = { MTK_DPI, 1, &ddp_dpi },
[DDP_COMPONENT_DSC0] = { MTK_DISP_DSC, 0, &ddp_dsc },
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index a3d01940d4c6..f7c4fa10a235 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -118,7 +118,7 @@ static enum mtk_ddp_comp_id mt8167_mtk_ddp_main[] = {
DDP_COMPONENT_CCORR,
DDP_COMPONENT_AAL0,
DDP_COMPONENT_GAMMA,
- DDP_COMPONENT_DITHER,
+ DDP_COMPONENT_DITHER0,
DDP_COMPONENT_RDMA0,
DDP_COMPONENT_DSI0,
};
@@ -150,7 +150,7 @@ static const enum mtk_ddp_comp_id mt8183_mtk_ddp_main[] = {
DDP_COMPONENT_CCORR,
DDP_COMPONENT_AAL0,
DDP_COMPONENT_GAMMA,
- DDP_COMPONENT_DITHER,
+ DDP_COMPONENT_DITHER0,
DDP_COMPONENT_DSI0,
};
@@ -169,7 +169,7 @@ static const enum mtk_ddp_comp_id mt8192_mtk_ddp_main[] = {
DDP_COMPONENT_AAL0,
DDP_COMPONENT_GAMMA,
DDP_COMPONENT_POSTMASK0,
- DDP_COMPONENT_DITHER,
+ DDP_COMPONENT_DITHER0,
DDP_COMPONENT_DSI0,
};
@@ -186,7 +186,7 @@ static const enum mtk_ddp_comp_id mt8195_mtk_ddp_main[] = {
DDP_COMPONENT_CCORR,
DDP_COMPONENT_AAL0,
DDP_COMPONENT_GAMMA,
- DDP_COMPONENT_DITHER,
+ DDP_COMPONENT_DITHER0,
DDP_COMPONENT_DSC0,
DDP_COMPONENT_MERGE0,
DDP_COMPONENT_DP_INTF0,
--
2.18.0
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [PATCH v20 7/8] drm/mediatek: add suffix 0 to DDP_COMPONENT_DITHER for mt8195 vdosys0
@ 2022-04-19 9:41 ` jason-jh.lin
0 siblings, 0 replies; 110+ messages in thread
From: jason-jh.lin @ 2022-04-19 9:41 UTC (permalink / raw)
To: Matthias Brugger, Chun-Kuang Hu, AngeloGioacchino Del Regno
Cc: CK Hu, Jason-JH Lin, Nancy Lin, Singo Chang, devicetree,
linux-kernel, dri-devel, linux-mediatek, linux-arm-kernel,
Project_Global_Chrome_Upstream_Group
Because mt8195 vdosys0 has 2 DITHER components,
so the suffix 0 need to be added to DDP_COMPONENT_DITHER.
Then DITHER enum will become:
DDP_COMPONENT_DITHER0 and DDP_COMPONENT_DITHER1.
Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 2 +-
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 8 ++++----
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index f683e768d61b..95722de4986b 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -420,7 +420,7 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_CCORR] = { MTK_DISP_CCORR, 0, &ddp_ccorr },
[DDP_COMPONENT_COLOR0] = { MTK_DISP_COLOR, 0, &ddp_color },
[DDP_COMPONENT_COLOR1] = { MTK_DISP_COLOR, 1, &ddp_color },
- [DDP_COMPONENT_DITHER] = { MTK_DISP_DITHER, 0, &ddp_dither },
+ [DDP_COMPONENT_DITHER0] = { MTK_DISP_DITHER, 0, &ddp_dither },
[DDP_COMPONENT_DPI0] = { MTK_DPI, 0, &ddp_dpi },
[DDP_COMPONENT_DPI1] = { MTK_DPI, 1, &ddp_dpi },
[DDP_COMPONENT_DSC0] = { MTK_DISP_DSC, 0, &ddp_dsc },
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index a3d01940d4c6..f7c4fa10a235 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -118,7 +118,7 @@ static enum mtk_ddp_comp_id mt8167_mtk_ddp_main[] = {
DDP_COMPONENT_CCORR,
DDP_COMPONENT_AAL0,
DDP_COMPONENT_GAMMA,
- DDP_COMPONENT_DITHER,
+ DDP_COMPONENT_DITHER0,
DDP_COMPONENT_RDMA0,
DDP_COMPONENT_DSI0,
};
@@ -150,7 +150,7 @@ static const enum mtk_ddp_comp_id mt8183_mtk_ddp_main[] = {
DDP_COMPONENT_CCORR,
DDP_COMPONENT_AAL0,
DDP_COMPONENT_GAMMA,
- DDP_COMPONENT_DITHER,
+ DDP_COMPONENT_DITHER0,
DDP_COMPONENT_DSI0,
};
@@ -169,7 +169,7 @@ static const enum mtk_ddp_comp_id mt8192_mtk_ddp_main[] = {
DDP_COMPONENT_AAL0,
DDP_COMPONENT_GAMMA,
DDP_COMPONENT_POSTMASK0,
- DDP_COMPONENT_DITHER,
+ DDP_COMPONENT_DITHER0,
DDP_COMPONENT_DSI0,
};
@@ -186,7 +186,7 @@ static const enum mtk_ddp_comp_id mt8195_mtk_ddp_main[] = {
DDP_COMPONENT_CCORR,
DDP_COMPONENT_AAL0,
DDP_COMPONENT_GAMMA,
- DDP_COMPONENT_DITHER,
+ DDP_COMPONENT_DITHER0,
DDP_COMPONENT_DSC0,
DDP_COMPONENT_MERGE0,
DDP_COMPONENT_DP_INTF0,
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [PATCH v20 7/8] drm/mediatek: add suffix 0 to DDP_COMPONENT_DITHER for mt8195 vdosys0
@ 2022-04-19 9:41 ` jason-jh.lin
0 siblings, 0 replies; 110+ messages in thread
From: jason-jh.lin @ 2022-04-19 9:41 UTC (permalink / raw)
To: Matthias Brugger, Chun-Kuang Hu, AngeloGioacchino Del Regno
Cc: CK Hu, Jason-JH Lin, Nancy Lin, Singo Chang, devicetree,
linux-kernel, dri-devel, linux-mediatek, linux-arm-kernel,
Project_Global_Chrome_Upstream_Group
Because mt8195 vdosys0 has 2 DITHER components,
so the suffix 0 need to be added to DDP_COMPONENT_DITHER.
Then DITHER enum will become:
DDP_COMPONENT_DITHER0 and DDP_COMPONENT_DITHER1.
Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 2 +-
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 8 ++++----
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index f683e768d61b..95722de4986b 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -420,7 +420,7 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_CCORR] = { MTK_DISP_CCORR, 0, &ddp_ccorr },
[DDP_COMPONENT_COLOR0] = { MTK_DISP_COLOR, 0, &ddp_color },
[DDP_COMPONENT_COLOR1] = { MTK_DISP_COLOR, 1, &ddp_color },
- [DDP_COMPONENT_DITHER] = { MTK_DISP_DITHER, 0, &ddp_dither },
+ [DDP_COMPONENT_DITHER0] = { MTK_DISP_DITHER, 0, &ddp_dither },
[DDP_COMPONENT_DPI0] = { MTK_DPI, 0, &ddp_dpi },
[DDP_COMPONENT_DPI1] = { MTK_DPI, 1, &ddp_dpi },
[DDP_COMPONENT_DSC0] = { MTK_DISP_DSC, 0, &ddp_dsc },
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index a3d01940d4c6..f7c4fa10a235 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -118,7 +118,7 @@ static enum mtk_ddp_comp_id mt8167_mtk_ddp_main[] = {
DDP_COMPONENT_CCORR,
DDP_COMPONENT_AAL0,
DDP_COMPONENT_GAMMA,
- DDP_COMPONENT_DITHER,
+ DDP_COMPONENT_DITHER0,
DDP_COMPONENT_RDMA0,
DDP_COMPONENT_DSI0,
};
@@ -150,7 +150,7 @@ static const enum mtk_ddp_comp_id mt8183_mtk_ddp_main[] = {
DDP_COMPONENT_CCORR,
DDP_COMPONENT_AAL0,
DDP_COMPONENT_GAMMA,
- DDP_COMPONENT_DITHER,
+ DDP_COMPONENT_DITHER0,
DDP_COMPONENT_DSI0,
};
@@ -169,7 +169,7 @@ static const enum mtk_ddp_comp_id mt8192_mtk_ddp_main[] = {
DDP_COMPONENT_AAL0,
DDP_COMPONENT_GAMMA,
DDP_COMPONENT_POSTMASK0,
- DDP_COMPONENT_DITHER,
+ DDP_COMPONENT_DITHER0,
DDP_COMPONENT_DSI0,
};
@@ -186,7 +186,7 @@ static const enum mtk_ddp_comp_id mt8195_mtk_ddp_main[] = {
DDP_COMPONENT_CCORR,
DDP_COMPONENT_AAL0,
DDP_COMPONENT_GAMMA,
- DDP_COMPONENT_DITHER,
+ DDP_COMPONENT_DITHER0,
DDP_COMPONENT_DSC0,
DDP_COMPONENT_MERGE0,
DDP_COMPONENT_DP_INTF0,
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [PATCH v20 8/8] soc: mediatek: remove DDP_DOMPONENT_DITHER from enum
2022-04-19 9:41 ` jason-jh.lin
(?)
@ 2022-04-19 9:41 ` jason-jh.lin
-1 siblings, 0 replies; 110+ messages in thread
From: jason-jh.lin @ 2022-04-19 9:41 UTC (permalink / raw)
To: Matthias Brugger, Chun-Kuang Hu, AngeloGioacchino Del Regno
Cc: devicetree, Jason-JH Lin, Singo Chang, linux-kernel, dri-devel,
Project_Global_Chrome_Upstream_Group, Nancy Lin, linux-mediatek,
linux-arm-kernel
After mmsys and drm change DITHER enum to DDP_COMPONENT_DITHER0,
mmsys header can remove the useless DDP_COMPONENT_DITHER enum.
Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
include/linux/soc/mediatek/mtk-mmsys.h | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
index 59117d970daf..fb719fd1281c 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -16,8 +16,7 @@ enum mtk_ddp_comp_id {
DDP_COMPONENT_CCORR,
DDP_COMPONENT_COLOR0,
DDP_COMPONENT_COLOR1,
- DDP_COMPONENT_DITHER,
- DDP_COMPONENT_DITHER0 = DDP_COMPONENT_DITHER,
+ DDP_COMPONENT_DITHER0,
DDP_COMPONENT_DITHER1,
DDP_COMPONENT_DP_INTF0,
DDP_COMPONENT_DP_INTF1,
--
2.18.0
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [PATCH v20 8/8] soc: mediatek: remove DDP_DOMPONENT_DITHER from enum
@ 2022-04-19 9:41 ` jason-jh.lin
0 siblings, 0 replies; 110+ messages in thread
From: jason-jh.lin @ 2022-04-19 9:41 UTC (permalink / raw)
To: Matthias Brugger, Chun-Kuang Hu, AngeloGioacchino Del Regno
Cc: CK Hu, Jason-JH Lin, Nancy Lin, Singo Chang, devicetree,
linux-kernel, dri-devel, linux-mediatek, linux-arm-kernel,
Project_Global_Chrome_Upstream_Group
After mmsys and drm change DITHER enum to DDP_COMPONENT_DITHER0,
mmsys header can remove the useless DDP_COMPONENT_DITHER enum.
Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
include/linux/soc/mediatek/mtk-mmsys.h | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
index 59117d970daf..fb719fd1281c 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -16,8 +16,7 @@ enum mtk_ddp_comp_id {
DDP_COMPONENT_CCORR,
DDP_COMPONENT_COLOR0,
DDP_COMPONENT_COLOR1,
- DDP_COMPONENT_DITHER,
- DDP_COMPONENT_DITHER0 = DDP_COMPONENT_DITHER,
+ DDP_COMPONENT_DITHER0,
DDP_COMPONENT_DITHER1,
DDP_COMPONENT_DP_INTF0,
DDP_COMPONENT_DP_INTF1,
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 110+ messages in thread
* [PATCH v20 8/8] soc: mediatek: remove DDP_DOMPONENT_DITHER from enum
@ 2022-04-19 9:41 ` jason-jh.lin
0 siblings, 0 replies; 110+ messages in thread
From: jason-jh.lin @ 2022-04-19 9:41 UTC (permalink / raw)
To: Matthias Brugger, Chun-Kuang Hu, AngeloGioacchino Del Regno
Cc: CK Hu, Jason-JH Lin, Nancy Lin, Singo Chang, devicetree,
linux-kernel, dri-devel, linux-mediatek, linux-arm-kernel,
Project_Global_Chrome_Upstream_Group
After mmsys and drm change DITHER enum to DDP_COMPONENT_DITHER0,
mmsys header can remove the useless DDP_COMPONENT_DITHER enum.
Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
include/linux/soc/mediatek/mtk-mmsys.h | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
index 59117d970daf..fb719fd1281c 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -16,8 +16,7 @@ enum mtk_ddp_comp_id {
DDP_COMPONENT_CCORR,
DDP_COMPONENT_COLOR0,
DDP_COMPONENT_COLOR1,
- DDP_COMPONENT_DITHER,
- DDP_COMPONENT_DITHER0 = DDP_COMPONENT_DITHER,
+ DDP_COMPONENT_DITHER0,
DDP_COMPONENT_DITHER1,
DDP_COMPONENT_DP_INTF0,
DDP_COMPONENT_DP_INTF1,
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 110+ messages in thread
* Re: [PATCH v20 1/8] soc: mediatek: add mtk-mmsys support for mt8195 vdosys0
2022-04-19 9:41 ` jason-jh.lin
(?)
@ 2022-04-21 6:06 ` Rex-BC Chen
-1 siblings, 0 replies; 110+ messages in thread
From: Rex-BC Chen @ 2022-04-21 6:06 UTC (permalink / raw)
To: jason-jh.lin, Matthias Brugger, Chun-Kuang Hu,
AngeloGioacchino Del Regno
Cc: devicetree, Singo Chang (張興國),
linux-kernel, dri-devel, Project_Global_Chrome_Upstream_Group,
Nancy Lin (林欣螢),
linux-mediatek, linux-arm-kernel
On Tue, 2022-04-19 at 17:41 +0800, jason-jh.lin wrote:
> 1. Add mt8195 mmsys compatible for 2 vdosys.
> 2. Add io_start into each driver data of mt8195 vdosys.
> 3. Add get match data function to identify mmsys by io_start.
> 4. Add mt8195 routing table settings of vdosys0.
>
> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <
> angelogioacchino.delregno@collabora.com>
> ---
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [PATCH v20 1/8] soc: mediatek: add mtk-mmsys support for mt8195 vdosys0
@ 2022-04-21 6:06 ` Rex-BC Chen
0 siblings, 0 replies; 110+ messages in thread
From: Rex-BC Chen @ 2022-04-21 6:06 UTC (permalink / raw)
To: jason-jh.lin, Matthias Brugger, Chun-Kuang Hu,
AngeloGioacchino Del Regno
Cc: CK Hu (胡俊光),
Nancy Lin (林欣螢),
Singo Chang (張興國),
devicetree, linux-kernel, dri-devel, linux-mediatek,
linux-arm-kernel, Project_Global_Chrome_Upstream_Group
On Tue, 2022-04-19 at 17:41 +0800, jason-jh.lin wrote:
> 1. Add mt8195 mmsys compatible for 2 vdosys.
> 2. Add io_start into each driver data of mt8195 vdosys.
> 3. Add get match data function to identify mmsys by io_start.
> 4. Add mt8195 routing table settings of vdosys0.
>
> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <
> angelogioacchino.delregno@collabora.com>
> ---
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [PATCH v20 1/8] soc: mediatek: add mtk-mmsys support for mt8195 vdosys0
@ 2022-04-21 6:06 ` Rex-BC Chen
0 siblings, 0 replies; 110+ messages in thread
From: Rex-BC Chen @ 2022-04-21 6:06 UTC (permalink / raw)
To: jason-jh.lin, Matthias Brugger, Chun-Kuang Hu,
AngeloGioacchino Del Regno
Cc: CK Hu (胡俊光),
Nancy Lin (林欣螢),
Singo Chang (張興國),
devicetree, linux-kernel, dri-devel, linux-mediatek,
linux-arm-kernel, Project_Global_Chrome_Upstream_Group
On Tue, 2022-04-19 at 17:41 +0800, jason-jh.lin wrote:
> 1. Add mt8195 mmsys compatible for 2 vdosys.
> 2. Add io_start into each driver data of mt8195 vdosys.
> 3. Add get match data function to identify mmsys by io_start.
> 4. Add mt8195 routing table settings of vdosys0.
>
> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <
> angelogioacchino.delregno@collabora.com>
> ---
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [PATCH v20 2/8] soc: mediatek: add mtk-mutex support for mt8195 vdosys0
2022-04-19 9:41 ` jason-jh.lin
(?)
@ 2022-04-21 6:07 ` Rex-BC Chen
-1 siblings, 0 replies; 110+ messages in thread
From: Rex-BC Chen @ 2022-04-21 6:07 UTC (permalink / raw)
To: jason-jh.lin, Matthias Brugger, Chun-Kuang Hu,
AngeloGioacchino Del Regno
Cc: devicetree, Singo Chang (張興國),
linux-kernel, dri-devel, Project_Global_Chrome_Upstream_Group,
Nancy Lin (林欣螢),
linux-mediatek, linux-arm-kernel
On Tue, 2022-04-19 at 17:41 +0800, jason-jh.lin wrote:
> Add mtk-mutex support for mt8195 vdosys0.
>
> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> Acked-by: AngeloGioacchino Del Regno <
> angelogioacchino.delregno@collabora.com>
> Tested-by: Fei Shao <fshao@chromium.org>
> ---
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [PATCH v20 2/8] soc: mediatek: add mtk-mutex support for mt8195 vdosys0
@ 2022-04-21 6:07 ` Rex-BC Chen
0 siblings, 0 replies; 110+ messages in thread
From: Rex-BC Chen @ 2022-04-21 6:07 UTC (permalink / raw)
To: jason-jh.lin, Matthias Brugger, Chun-Kuang Hu,
AngeloGioacchino Del Regno
Cc: CK Hu (胡俊光),
Nancy Lin (林欣螢),
Singo Chang (張興國),
devicetree, linux-kernel, dri-devel, linux-mediatek,
linux-arm-kernel, Project_Global_Chrome_Upstream_Group
On Tue, 2022-04-19 at 17:41 +0800, jason-jh.lin wrote:
> Add mtk-mutex support for mt8195 vdosys0.
>
> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> Acked-by: AngeloGioacchino Del Regno <
> angelogioacchino.delregno@collabora.com>
> Tested-by: Fei Shao <fshao@chromium.org>
> ---
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [PATCH v20 2/8] soc: mediatek: add mtk-mutex support for mt8195 vdosys0
@ 2022-04-21 6:07 ` Rex-BC Chen
0 siblings, 0 replies; 110+ messages in thread
From: Rex-BC Chen @ 2022-04-21 6:07 UTC (permalink / raw)
To: jason-jh.lin, Matthias Brugger, Chun-Kuang Hu,
AngeloGioacchino Del Regno
Cc: CK Hu (胡俊光),
Nancy Lin (林欣螢),
Singo Chang (張興國),
devicetree, linux-kernel, dri-devel, linux-mediatek,
linux-arm-kernel, Project_Global_Chrome_Upstream_Group
On Tue, 2022-04-19 at 17:41 +0800, jason-jh.lin wrote:
> Add mtk-mutex support for mt8195 vdosys0.
>
> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> Acked-by: AngeloGioacchino Del Regno <
> angelogioacchino.delregno@collabora.com>
> Tested-by: Fei Shao <fshao@chromium.org>
> ---
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [PATCH v20 5/8] drm/mediatek: add mediatek-drm of vdosys0 support for mt8195
2022-04-19 9:41 ` jason-jh.lin
(?)
@ 2022-04-21 6:08 ` Rex-BC Chen
-1 siblings, 0 replies; 110+ messages in thread
From: Rex-BC Chen @ 2022-04-21 6:08 UTC (permalink / raw)
To: jason-jh.lin, Matthias Brugger, Chun-Kuang Hu,
AngeloGioacchino Del Regno
Cc: CK Hu (胡俊光),
Nancy Lin (林欣螢),
Singo Chang (張興國),
devicetree, linux-kernel, dri-devel, linux-mediatek,
linux-arm-kernel, Project_Global_Chrome_Upstream_Group
On Tue, 2022-04-19 at 17:41 +0800, jason-jh.lin wrote:
> 1. Add driver data of mt8195 vdosys0 to mediatek-drm and the sub
> driver.
> 2. Add get driver data function to identify which vdosys by io_start.
>
> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <
> angelogioacchino.delregno@collabora.com>
> ---
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [PATCH v20 5/8] drm/mediatek: add mediatek-drm of vdosys0 support for mt8195
@ 2022-04-21 6:08 ` Rex-BC Chen
0 siblings, 0 replies; 110+ messages in thread
From: Rex-BC Chen @ 2022-04-21 6:08 UTC (permalink / raw)
To: jason-jh.lin, Matthias Brugger, Chun-Kuang Hu,
AngeloGioacchino Del Regno
Cc: devicetree, Singo Chang (張興國),
linux-kernel, dri-devel, Project_Global_Chrome_Upstream_Group,
Nancy Lin (林欣螢),
linux-mediatek, linux-arm-kernel
On Tue, 2022-04-19 at 17:41 +0800, jason-jh.lin wrote:
> 1. Add driver data of mt8195 vdosys0 to mediatek-drm and the sub
> driver.
> 2. Add get driver data function to identify which vdosys by io_start.
>
> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <
> angelogioacchino.delregno@collabora.com>
> ---
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [PATCH v20 5/8] drm/mediatek: add mediatek-drm of vdosys0 support for mt8195
@ 2022-04-21 6:08 ` Rex-BC Chen
0 siblings, 0 replies; 110+ messages in thread
From: Rex-BC Chen @ 2022-04-21 6:08 UTC (permalink / raw)
To: jason-jh.lin, Matthias Brugger, Chun-Kuang Hu,
AngeloGioacchino Del Regno
Cc: CK Hu (胡俊光),
Nancy Lin (林欣螢),
Singo Chang (張興國),
devicetree, linux-kernel, dri-devel, linux-mediatek,
linux-arm-kernel, Project_Global_Chrome_Upstream_Group
On Tue, 2022-04-19 at 17:41 +0800, jason-jh.lin wrote:
> 1. Add driver data of mt8195 vdosys0 to mediatek-drm and the sub
> driver.
> 2. Add get driver data function to identify which vdosys by io_start.
>
> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <
> angelogioacchino.delregno@collabora.com>
> ---
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [PATCH v20 6/8] soc: mediatek: add DDP_DOMPONENT_DITHER0 enum for mt8195 vdosys0
2022-04-19 9:41 ` jason-jh.lin
(?)
@ 2022-04-21 6:10 ` Rex-BC Chen
-1 siblings, 0 replies; 110+ messages in thread
From: Rex-BC Chen @ 2022-04-21 6:10 UTC (permalink / raw)
To: jason-jh.lin, Matthias Brugger, Chun-Kuang Hu,
AngeloGioacchino Del Regno
Cc: CK Hu (胡俊光),
Nancy Lin (林欣螢),
Singo Chang (張興國),
devicetree, linux-kernel, dri-devel, linux-mediatek,
linux-arm-kernel, Project_Global_Chrome_Upstream_Group
On Tue, 2022-04-19 at 17:41 +0800, jason-jh.lin wrote:
> The mmsys routing table of mt8195 vdosys0 has 2 DITHER components,
> so mmsys need to add DDP_COMPONENT_DITHER1 and change all usages of
> DITHER enum form DDP_COMPONENT_DITHER to DDP_COMPONENT_DITHER0.
>
> But its header need to keep DDP_COMPONENT_DITHER enum
> until drm/mediatek also changed it.
>
> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <
> angelogioacchino.delregno@collabora.com>
> ---
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [PATCH v20 6/8] soc: mediatek: add DDP_DOMPONENT_DITHER0 enum for mt8195 vdosys0
@ 2022-04-21 6:10 ` Rex-BC Chen
0 siblings, 0 replies; 110+ messages in thread
From: Rex-BC Chen @ 2022-04-21 6:10 UTC (permalink / raw)
To: jason-jh.lin, Matthias Brugger, Chun-Kuang Hu,
AngeloGioacchino Del Regno
Cc: devicetree, Singo Chang (張興國),
linux-kernel, dri-devel, Project_Global_Chrome_Upstream_Group,
Nancy Lin (林欣螢),
linux-mediatek, linux-arm-kernel
On Tue, 2022-04-19 at 17:41 +0800, jason-jh.lin wrote:
> The mmsys routing table of mt8195 vdosys0 has 2 DITHER components,
> so mmsys need to add DDP_COMPONENT_DITHER1 and change all usages of
> DITHER enum form DDP_COMPONENT_DITHER to DDP_COMPONENT_DITHER0.
>
> But its header need to keep DDP_COMPONENT_DITHER enum
> until drm/mediatek also changed it.
>
> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <
> angelogioacchino.delregno@collabora.com>
> ---
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [PATCH v20 6/8] soc: mediatek: add DDP_DOMPONENT_DITHER0 enum for mt8195 vdosys0
@ 2022-04-21 6:10 ` Rex-BC Chen
0 siblings, 0 replies; 110+ messages in thread
From: Rex-BC Chen @ 2022-04-21 6:10 UTC (permalink / raw)
To: jason-jh.lin, Matthias Brugger, Chun-Kuang Hu,
AngeloGioacchino Del Regno
Cc: CK Hu (胡俊光),
Nancy Lin (林欣螢),
Singo Chang (張興國),
devicetree, linux-kernel, dri-devel, linux-mediatek,
linux-arm-kernel, Project_Global_Chrome_Upstream_Group
On Tue, 2022-04-19 at 17:41 +0800, jason-jh.lin wrote:
> The mmsys routing table of mt8195 vdosys0 has 2 DITHER components,
> so mmsys need to add DDP_COMPONENT_DITHER1 and change all usages of
> DITHER enum form DDP_COMPONENT_DITHER to DDP_COMPONENT_DITHER0.
>
> But its header need to keep DDP_COMPONENT_DITHER enum
> until drm/mediatek also changed it.
>
> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <
> angelogioacchino.delregno@collabora.com>
> ---
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [PATCH v20 7/8] drm/mediatek: add suffix 0 to DDP_COMPONENT_DITHER for mt8195 vdosys0
2022-04-19 9:41 ` jason-jh.lin
(?)
@ 2022-04-21 6:11 ` Rex-BC Chen
-1 siblings, 0 replies; 110+ messages in thread
From: Rex-BC Chen @ 2022-04-21 6:11 UTC (permalink / raw)
To: jason-jh.lin, Matthias Brugger, Chun-Kuang Hu,
AngeloGioacchino Del Regno
Cc: devicetree, Singo Chang (張興國),
linux-kernel, dri-devel, Project_Global_Chrome_Upstream_Group,
Nancy Lin (林欣螢),
linux-mediatek, linux-arm-kernel
On Tue, 2022-04-19 at 17:41 +0800, jason-jh.lin wrote:
> Because mt8195 vdosys0 has 2 DITHER components,
> so the suffix 0 need to be added to DDP_COMPONENT_DITHER.
>
> Then DITHER enum will become:
> DDP_COMPONENT_DITHER0 and DDP_COMPONENT_DITHER1.
>
> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <
> angelogioacchino.delregno@collabora.com>
> ---
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [PATCH v20 7/8] drm/mediatek: add suffix 0 to DDP_COMPONENT_DITHER for mt8195 vdosys0
@ 2022-04-21 6:11 ` Rex-BC Chen
0 siblings, 0 replies; 110+ messages in thread
From: Rex-BC Chen @ 2022-04-21 6:11 UTC (permalink / raw)
To: jason-jh.lin, Matthias Brugger, Chun-Kuang Hu,
AngeloGioacchino Del Regno
Cc: CK Hu (胡俊光),
Nancy Lin (林欣螢),
Singo Chang (張興國),
devicetree, linux-kernel, dri-devel, linux-mediatek,
linux-arm-kernel, Project_Global_Chrome_Upstream_Group
On Tue, 2022-04-19 at 17:41 +0800, jason-jh.lin wrote:
> Because mt8195 vdosys0 has 2 DITHER components,
> so the suffix 0 need to be added to DDP_COMPONENT_DITHER.
>
> Then DITHER enum will become:
> DDP_COMPONENT_DITHER0 and DDP_COMPONENT_DITHER1.
>
> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <
> angelogioacchino.delregno@collabora.com>
> ---
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [PATCH v20 7/8] drm/mediatek: add suffix 0 to DDP_COMPONENT_DITHER for mt8195 vdosys0
@ 2022-04-21 6:11 ` Rex-BC Chen
0 siblings, 0 replies; 110+ messages in thread
From: Rex-BC Chen @ 2022-04-21 6:11 UTC (permalink / raw)
To: jason-jh.lin, Matthias Brugger, Chun-Kuang Hu,
AngeloGioacchino Del Regno
Cc: CK Hu (胡俊光),
Nancy Lin (林欣螢),
Singo Chang (張興國),
devicetree, linux-kernel, dri-devel, linux-mediatek,
linux-arm-kernel, Project_Global_Chrome_Upstream_Group
On Tue, 2022-04-19 at 17:41 +0800, jason-jh.lin wrote:
> Because mt8195 vdosys0 has 2 DITHER components,
> so the suffix 0 need to be added to DDP_COMPONENT_DITHER.
>
> Then DITHER enum will become:
> DDP_COMPONENT_DITHER0 and DDP_COMPONENT_DITHER1.
>
> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <
> angelogioacchino.delregno@collabora.com>
> ---
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [PATCH v20 8/8] soc: mediatek: remove DDP_DOMPONENT_DITHER from enum
2022-04-19 9:41 ` jason-jh.lin
(?)
@ 2022-04-21 6:13 ` Rex-BC Chen
-1 siblings, 0 replies; 110+ messages in thread
From: Rex-BC Chen @ 2022-04-21 6:13 UTC (permalink / raw)
To: jason-jh.lin, Matthias Brugger, Chun-Kuang Hu,
AngeloGioacchino Del Regno
Cc: devicetree, Singo Chang, linux-kernel, dri-devel,
Project_Global_Chrome_Upstream_Group, Nancy Lin, linux-mediatek,
linux-arm-kernel
On Tue, 2022-04-19 at 17:41 +0800, jason-jh.lin wrote:
> After mmsys and drm change DITHER enum to DDP_COMPONENT_DITHER0,
> mmsys header can remove the useless DDP_COMPONENT_DITHER enum.
>
> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <
> angelogioacchino.delregno@collabora.com>
> ---
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [PATCH v20 8/8] soc: mediatek: remove DDP_DOMPONENT_DITHER from enum
@ 2022-04-21 6:13 ` Rex-BC Chen
0 siblings, 0 replies; 110+ messages in thread
From: Rex-BC Chen @ 2022-04-21 6:13 UTC (permalink / raw)
To: jason-jh.lin, Matthias Brugger, Chun-Kuang Hu,
AngeloGioacchino Del Regno
Cc: CK Hu, Nancy Lin, Singo Chang, devicetree, linux-kernel,
dri-devel, linux-mediatek, linux-arm-kernel,
Project_Global_Chrome_Upstream_Group
On Tue, 2022-04-19 at 17:41 +0800, jason-jh.lin wrote:
> After mmsys and drm change DITHER enum to DDP_COMPONENT_DITHER0,
> mmsys header can remove the useless DDP_COMPONENT_DITHER enum.
>
> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <
> angelogioacchino.delregno@collabora.com>
> ---
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [PATCH v20 8/8] soc: mediatek: remove DDP_DOMPONENT_DITHER from enum
@ 2022-04-21 6:13 ` Rex-BC Chen
0 siblings, 0 replies; 110+ messages in thread
From: Rex-BC Chen @ 2022-04-21 6:13 UTC (permalink / raw)
To: jason-jh.lin, Matthias Brugger, Chun-Kuang Hu,
AngeloGioacchino Del Regno
Cc: CK Hu, Nancy Lin, Singo Chang, devicetree, linux-kernel,
dri-devel, linux-mediatek, linux-arm-kernel,
Project_Global_Chrome_Upstream_Group
On Tue, 2022-04-19 at 17:41 +0800, jason-jh.lin wrote:
> After mmsys and drm change DITHER enum to DDP_COMPONENT_DITHER0,
> mmsys header can remove the useless DDP_COMPONENT_DITHER enum.
>
> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <
> angelogioacchino.delregno@collabora.com>
> ---
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [PATCH v20 1/8] soc: mediatek: add mtk-mmsys support for mt8195 vdosys0
2022-04-19 9:41 ` jason-jh.lin
(?)
@ 2022-04-21 6:32 ` CK Hu
-1 siblings, 0 replies; 110+ messages in thread
From: CK Hu @ 2022-04-21 6:32 UTC (permalink / raw)
To: jason-jh.lin, Matthias Brugger, Chun-Kuang Hu,
AngeloGioacchino Del Regno
Cc: devicetree, Singo Chang, linux-kernel, dri-devel,
Project_Global_Chrome_Upstream_Group, Nancy Lin, linux-mediatek,
linux-arm-kernel
Hi, Jason:
On Tue, 2022-04-19 at 17:41 +0800, jason-jh.lin wrote:
> 1. Add mt8195 mmsys compatible for 2 vdosys.
> 2. Add io_start into each driver data of mt8195 vdosys.
> 3. Add get match data function to identify mmsys by io_start.
> 4. Add mt8195 routing table settings of vdosys0.
Reviewed-by: CK Hu <ck.hu@mediatek.com>
>
> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <
> angelogioacchino.delregno@collabora.com>
> ---
> Based on series [1]
>
> [1] MediaTek MT8195 display binding
> -
> https://patchwork.ozlabs.org/project/devicetree-bindings/list/?series=295669
> ---
> drivers/soc/mediatek/mt8195-mmsys.h | 370
> +++++++++++++++++++++++++
> drivers/soc/mediatek/mtk-mmsys.c | 152 +++++++++-
> drivers/soc/mediatek/mtk-mmsys.h | 6 +
> include/linux/soc/mediatek/mtk-mmsys.h | 11 +
> 4 files changed, 528 insertions(+), 11 deletions(-)
> create mode 100644 drivers/soc/mediatek/mt8195-mmsys.h
>
>
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [PATCH v20 1/8] soc: mediatek: add mtk-mmsys support for mt8195 vdosys0
@ 2022-04-21 6:32 ` CK Hu
0 siblings, 0 replies; 110+ messages in thread
From: CK Hu @ 2022-04-21 6:32 UTC (permalink / raw)
To: jason-jh.lin, Matthias Brugger, Chun-Kuang Hu,
AngeloGioacchino Del Regno
Cc: Nancy Lin, Singo Chang, devicetree, linux-kernel, dri-devel,
linux-mediatek, linux-arm-kernel,
Project_Global_Chrome_Upstream_Group
Hi, Jason:
On Tue, 2022-04-19 at 17:41 +0800, jason-jh.lin wrote:
> 1. Add mt8195 mmsys compatible for 2 vdosys.
> 2. Add io_start into each driver data of mt8195 vdosys.
> 3. Add get match data function to identify mmsys by io_start.
> 4. Add mt8195 routing table settings of vdosys0.
Reviewed-by: CK Hu <ck.hu@mediatek.com>
>
> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <
> angelogioacchino.delregno@collabora.com>
> ---
> Based on series [1]
>
> [1] MediaTek MT8195 display binding
> -
> https://patchwork.ozlabs.org/project/devicetree-bindings/list/?series=295669
> ---
> drivers/soc/mediatek/mt8195-mmsys.h | 370
> +++++++++++++++++++++++++
> drivers/soc/mediatek/mtk-mmsys.c | 152 +++++++++-
> drivers/soc/mediatek/mtk-mmsys.h | 6 +
> include/linux/soc/mediatek/mtk-mmsys.h | 11 +
> 4 files changed, 528 insertions(+), 11 deletions(-)
> create mode 100644 drivers/soc/mediatek/mt8195-mmsys.h
>
>
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [PATCH v20 1/8] soc: mediatek: add mtk-mmsys support for mt8195 vdosys0
@ 2022-04-21 6:32 ` CK Hu
0 siblings, 0 replies; 110+ messages in thread
From: CK Hu @ 2022-04-21 6:32 UTC (permalink / raw)
To: jason-jh.lin, Matthias Brugger, Chun-Kuang Hu,
AngeloGioacchino Del Regno
Cc: Nancy Lin, Singo Chang, devicetree, linux-kernel, dri-devel,
linux-mediatek, linux-arm-kernel,
Project_Global_Chrome_Upstream_Group
Hi, Jason:
On Tue, 2022-04-19 at 17:41 +0800, jason-jh.lin wrote:
> 1. Add mt8195 mmsys compatible for 2 vdosys.
> 2. Add io_start into each driver data of mt8195 vdosys.
> 3. Add get match data function to identify mmsys by io_start.
> 4. Add mt8195 routing table settings of vdosys0.
Reviewed-by: CK Hu <ck.hu@mediatek.com>
>
> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <
> angelogioacchino.delregno@collabora.com>
> ---
> Based on series [1]
>
> [1] MediaTek MT8195 display binding
> -
> https://patchwork.ozlabs.org/project/devicetree-bindings/list/?series=295669
> ---
> drivers/soc/mediatek/mt8195-mmsys.h | 370
> +++++++++++++++++++++++++
> drivers/soc/mediatek/mtk-mmsys.c | 152 +++++++++-
> drivers/soc/mediatek/mtk-mmsys.h | 6 +
> include/linux/soc/mediatek/mtk-mmsys.h | 11 +
> 4 files changed, 528 insertions(+), 11 deletions(-)
> create mode 100644 drivers/soc/mediatek/mt8195-mmsys.h
>
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [PATCH v20 2/8] soc: mediatek: add mtk-mutex support for mt8195 vdosys0
2022-04-19 9:41 ` jason-jh.lin
(?)
@ 2022-04-21 6:50 ` CK Hu
-1 siblings, 0 replies; 110+ messages in thread
From: CK Hu @ 2022-04-21 6:50 UTC (permalink / raw)
To: jason-jh.lin, Matthias Brugger, Chun-Kuang Hu,
AngeloGioacchino Del Regno
Cc: devicetree, Singo Chang, linux-kernel, dri-devel,
Project_Global_Chrome_Upstream_Group, Nancy Lin, linux-mediatek,
linux-arm-kernel
Hi, Jason:
On Tue, 2022-04-19 at 17:41 +0800, jason-jh.lin wrote:
> Add mtk-mutex support for mt8195 vdosys0.
>
> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> Acked-by: AngeloGioacchino Del Regno <
> angelogioacchino.delregno@collabora.com>
> Tested-by: Fei Shao <fshao@chromium.org>
> ---
> drivers/soc/mediatek/mtk-mutex.c | 87
> ++++++++++++++++++++++++++++++--
> 1 file changed, 84 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/soc/mediatek/mtk-mutex.c
> b/drivers/soc/mediatek/mtk-mutex.c
> index aaf8fc1abb43..729ee88035ed 100644
> --- a/drivers/soc/mediatek/mtk-mutex.c
> +++ b/drivers/soc/mediatek/mtk-mutex.c
> @@ -17,6 +17,9 @@
> #define MT8183_MUTEX0_MOD0 0x30
> #define MT8183_MUTEX0_SOF0 0x2c
>
> +#define MT8195_DISP_MUTEX0_MOD0 0x30
> +#define MT8195_DISP_MUTEX0_SOF 0x2c
This is identical to mt8183, so use mt8183 one instead of creating new
one.
Regards,
CK
>
>
> +static const struct mtk_mutex_data mt8195_mutex_driver_data = {
> + .mutex_mod = mt8195_mutex_mod,
> + .mutex_sof = mt8195_mutex_sof,
> + .mutex_mod_reg = MT8195_DISP_MUTEX0_MOD0,
> + .mutex_sof_reg = MT8195_DISP_MUTEX0_SOF,
> +};
> +
>
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [PATCH v20 2/8] soc: mediatek: add mtk-mutex support for mt8195 vdosys0
@ 2022-04-21 6:50 ` CK Hu
0 siblings, 0 replies; 110+ messages in thread
From: CK Hu @ 2022-04-21 6:50 UTC (permalink / raw)
To: jason-jh.lin, Matthias Brugger, Chun-Kuang Hu,
AngeloGioacchino Del Regno
Cc: Nancy Lin, Singo Chang, devicetree, linux-kernel, dri-devel,
linux-mediatek, linux-arm-kernel,
Project_Global_Chrome_Upstream_Group
Hi, Jason:
On Tue, 2022-04-19 at 17:41 +0800, jason-jh.lin wrote:
> Add mtk-mutex support for mt8195 vdosys0.
>
> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> Acked-by: AngeloGioacchino Del Regno <
> angelogioacchino.delregno@collabora.com>
> Tested-by: Fei Shao <fshao@chromium.org>
> ---
> drivers/soc/mediatek/mtk-mutex.c | 87
> ++++++++++++++++++++++++++++++--
> 1 file changed, 84 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/soc/mediatek/mtk-mutex.c
> b/drivers/soc/mediatek/mtk-mutex.c
> index aaf8fc1abb43..729ee88035ed 100644
> --- a/drivers/soc/mediatek/mtk-mutex.c
> +++ b/drivers/soc/mediatek/mtk-mutex.c
> @@ -17,6 +17,9 @@
> #define MT8183_MUTEX0_MOD0 0x30
> #define MT8183_MUTEX0_SOF0 0x2c
>
> +#define MT8195_DISP_MUTEX0_MOD0 0x30
> +#define MT8195_DISP_MUTEX0_SOF 0x2c
This is identical to mt8183, so use mt8183 one instead of creating new
one.
Regards,
CK
>
>
> +static const struct mtk_mutex_data mt8195_mutex_driver_data = {
> + .mutex_mod = mt8195_mutex_mod,
> + .mutex_sof = mt8195_mutex_sof,
> + .mutex_mod_reg = MT8195_DISP_MUTEX0_MOD0,
> + .mutex_sof_reg = MT8195_DISP_MUTEX0_SOF,
> +};
> +
>
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [PATCH v20 2/8] soc: mediatek: add mtk-mutex support for mt8195 vdosys0
@ 2022-04-21 6:50 ` CK Hu
0 siblings, 0 replies; 110+ messages in thread
From: CK Hu @ 2022-04-21 6:50 UTC (permalink / raw)
To: jason-jh.lin, Matthias Brugger, Chun-Kuang Hu,
AngeloGioacchino Del Regno
Cc: Nancy Lin, Singo Chang, devicetree, linux-kernel, dri-devel,
linux-mediatek, linux-arm-kernel,
Project_Global_Chrome_Upstream_Group
Hi, Jason:
On Tue, 2022-04-19 at 17:41 +0800, jason-jh.lin wrote:
> Add mtk-mutex support for mt8195 vdosys0.
>
> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> Acked-by: AngeloGioacchino Del Regno <
> angelogioacchino.delregno@collabora.com>
> Tested-by: Fei Shao <fshao@chromium.org>
> ---
> drivers/soc/mediatek/mtk-mutex.c | 87
> ++++++++++++++++++++++++++++++--
> 1 file changed, 84 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/soc/mediatek/mtk-mutex.c
> b/drivers/soc/mediatek/mtk-mutex.c
> index aaf8fc1abb43..729ee88035ed 100644
> --- a/drivers/soc/mediatek/mtk-mutex.c
> +++ b/drivers/soc/mediatek/mtk-mutex.c
> @@ -17,6 +17,9 @@
> #define MT8183_MUTEX0_MOD0 0x30
> #define MT8183_MUTEX0_SOF0 0x2c
>
> +#define MT8195_DISP_MUTEX0_MOD0 0x30
> +#define MT8195_DISP_MUTEX0_SOF 0x2c
This is identical to mt8183, so use mt8183 one instead of creating new
one.
Regards,
CK
>
>
> +static const struct mtk_mutex_data mt8195_mutex_driver_data = {
> + .mutex_mod = mt8195_mutex_mod,
> + .mutex_sof = mt8195_mutex_sof,
> + .mutex_mod_reg = MT8195_DISP_MUTEX0_MOD0,
> + .mutex_sof_reg = MT8195_DISP_MUTEX0_SOF,
> +};
> +
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [PATCH v20 2/8] soc: mediatek: add mtk-mutex support for mt8195 vdosys0
2022-04-21 6:50 ` CK Hu
(?)
(?)
@ 2022-04-22 2:32 ` Jason-JH Lin
-1 siblings, 0 replies; 110+ messages in thread
From: Jason-JH Lin @ 2022-04-22 2:32 UTC (permalink / raw)
To: CK Hu, Matthias Brugger, Chun-Kuang Hu, AngeloGioacchino Del Regno
Cc: Nancy Lin, Singo Chang, devicetree, linux-kernel, dri-devel,
linux-mediatek, linux-arm-kernel,
Project_Global_Chrome_Upstream_Group
Hi CK,
Thanks for the reviews.
On Thu, 2022-04-21 at 14:50 +0800, CK Hu wrote:
> Hi, Jason:
>
> On Tue, 2022-04-19 at 17:41 +0800, jason-jh.lin wrote:
> > Add mtk-mutex support for mt8195 vdosys0.
> >
> > Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> > Acked-by: AngeloGioacchino Del Regno <
> > angelogioacchino.delregno@collabora.com>
> > Tested-by: Fei Shao <fshao@chromium.org>
> > ---
> > drivers/soc/mediatek/mtk-mutex.c | 87
> > ++++++++++++++++++++++++++++++--
> > 1 file changed, 84 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/soc/mediatek/mtk-mutex.c
> > b/drivers/soc/mediatek/mtk-mutex.c
> > index aaf8fc1abb43..729ee88035ed 100644
> > --- a/drivers/soc/mediatek/mtk-mutex.c
> > +++ b/drivers/soc/mediatek/mtk-mutex.c
> > @@ -17,6 +17,9 @@
> > #define MT8183_MUTEX0_MOD0 0x30
> > #define MT8183_MUTEX0_SOF0 0x2c
> >
> > +#define MT8195_DISP_MUTEX0_MOD0 0x30
> > +#define MT8195_DISP_MUTEX0_SOF 0x2c
>
> This is identical to mt8183, so use mt8183 one instead of creating
> new
> one.
>
> Regards,
> CK
>
I'll fix this in the next version.
Regards,
Jason-JH.Lin.
> >
> >
> > +static const struct mtk_mutex_data mt8195_mutex_driver_data = {
> > + .mutex_mod = mt8195_mutex_mod,
> > + .mutex_sof = mt8195_mutex_sof,
> > + .mutex_mod_reg = MT8195_DISP_MUTEX0_MOD0,
> > + .mutex_sof_reg = MT8195_DISP_MUTEX0_SOF,
> > +};
> > +
> >
>
>
--
Jason-JH Lin <jason-jh.lin@mediatek.com>
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [PATCH v20 2/8] soc: mediatek: add mtk-mutex support for mt8195 vdosys0
@ 2022-04-22 2:32 ` Jason-JH Lin
0 siblings, 0 replies; 110+ messages in thread
From: Jason-JH Lin @ 2022-04-22 2:32 UTC (permalink / raw)
To: CK Hu, Matthias Brugger, Chun-Kuang Hu, AngeloGioacchino Del Regno
Cc: devicetree, Singo Chang, linux-kernel, dri-devel,
Project_Global_Chrome_Upstream_Group, Nancy Lin, linux-mediatek,
linux-arm-kernel
Hi CK,
Thanks for the reviews.
On Thu, 2022-04-21 at 14:50 +0800, CK Hu wrote:
> Hi, Jason:
>
> On Tue, 2022-04-19 at 17:41 +0800, jason-jh.lin wrote:
> > Add mtk-mutex support for mt8195 vdosys0.
> >
> > Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> > Acked-by: AngeloGioacchino Del Regno <
> > angelogioacchino.delregno@collabora.com>
> > Tested-by: Fei Shao <fshao@chromium.org>
> > ---
> > drivers/soc/mediatek/mtk-mutex.c | 87
> > ++++++++++++++++++++++++++++++--
> > 1 file changed, 84 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/soc/mediatek/mtk-mutex.c
> > b/drivers/soc/mediatek/mtk-mutex.c
> > index aaf8fc1abb43..729ee88035ed 100644
> > --- a/drivers/soc/mediatek/mtk-mutex.c
> > +++ b/drivers/soc/mediatek/mtk-mutex.c
> > @@ -17,6 +17,9 @@
> > #define MT8183_MUTEX0_MOD0 0x30
> > #define MT8183_MUTEX0_SOF0 0x2c
> >
> > +#define MT8195_DISP_MUTEX0_MOD0 0x30
> > +#define MT8195_DISP_MUTEX0_SOF 0x2c
>
> This is identical to mt8183, so use mt8183 one instead of creating
> new
> one.
>
> Regards,
> CK
>
I'll fix this in the next version.
Regards,
Jason-JH.Lin.
> >
> >
> > +static const struct mtk_mutex_data mt8195_mutex_driver_data = {
> > + .mutex_mod = mt8195_mutex_mod,
> > + .mutex_sof = mt8195_mutex_sof,
> > + .mutex_mod_reg = MT8195_DISP_MUTEX0_MOD0,
> > + .mutex_sof_reg = MT8195_DISP_MUTEX0_SOF,
> > +};
> > +
> >
>
>
--
Jason-JH Lin <jason-jh.lin@mediatek.com>
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [PATCH v20 2/8] soc: mediatek: add mtk-mutex support for mt8195 vdosys0
@ 2022-04-22 2:32 ` Jason-JH Lin
0 siblings, 0 replies; 110+ messages in thread
From: Jason-JH Lin @ 2022-04-22 2:32 UTC (permalink / raw)
To: CK Hu, Matthias Brugger, Chun-Kuang Hu, AngeloGioacchino Del Regno
Cc: Nancy Lin, Singo Chang, devicetree, linux-kernel, dri-devel,
linux-mediatek, linux-arm-kernel,
Project_Global_Chrome_Upstream_Group
Hi CK,
Thanks for the reviews.
On Thu, 2022-04-21 at 14:50 +0800, CK Hu wrote:
> Hi, Jason:
>
> On Tue, 2022-04-19 at 17:41 +0800, jason-jh.lin wrote:
> > Add mtk-mutex support for mt8195 vdosys0.
> >
> > Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> > Acked-by: AngeloGioacchino Del Regno <
> > angelogioacchino.delregno@collabora.com>
> > Tested-by: Fei Shao <fshao@chromium.org>
> > ---
> > drivers/soc/mediatek/mtk-mutex.c | 87
> > ++++++++++++++++++++++++++++++--
> > 1 file changed, 84 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/soc/mediatek/mtk-mutex.c
> > b/drivers/soc/mediatek/mtk-mutex.c
> > index aaf8fc1abb43..729ee88035ed 100644
> > --- a/drivers/soc/mediatek/mtk-mutex.c
> > +++ b/drivers/soc/mediatek/mtk-mutex.c
> > @@ -17,6 +17,9 @@
> > #define MT8183_MUTEX0_MOD0 0x30
> > #define MT8183_MUTEX0_SOF0 0x2c
> >
> > +#define MT8195_DISP_MUTEX0_MOD0 0x30
> > +#define MT8195_DISP_MUTEX0_SOF 0x2c
>
> This is identical to mt8183, so use mt8183 one instead of creating
> new
> one.
>
> Regards,
> CK
>
I'll fix this in the next version.
Regards,
Jason-JH.Lin.
> >
> >
> > +static const struct mtk_mutex_data mt8195_mutex_driver_data = {
> > + .mutex_mod = mt8195_mutex_mod,
> > + .mutex_sof = mt8195_mutex_sof,
> > + .mutex_mod_reg = MT8195_DISP_MUTEX0_MOD0,
> > + .mutex_sof_reg = MT8195_DISP_MUTEX0_SOF,
> > +};
> > +
> >
>
>
--
Jason-JH Lin <jason-jh.lin@mediatek.com>
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [PATCH v20 2/8] soc: mediatek: add mtk-mutex support for mt8195 vdosys0
@ 2022-04-22 2:32 ` Jason-JH Lin
0 siblings, 0 replies; 110+ messages in thread
From: Jason-JH Lin @ 2022-04-22 2:32 UTC (permalink / raw)
To: CK Hu, Matthias Brugger, Chun-Kuang Hu, AngeloGioacchino Del Regno
Cc: Nancy Lin, Singo Chang, devicetree, linux-kernel, dri-devel,
linux-mediatek, linux-arm-kernel,
Project_Global_Chrome_Upstream_Group
Hi CK,
Thanks for the reviews.
On Thu, 2022-04-21 at 14:50 +0800, CK Hu wrote:
> Hi, Jason:
>
> On Tue, 2022-04-19 at 17:41 +0800, jason-jh.lin wrote:
> > Add mtk-mutex support for mt8195 vdosys0.
> >
> > Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> > Acked-by: AngeloGioacchino Del Regno <
> > angelogioacchino.delregno@collabora.com>
> > Tested-by: Fei Shao <fshao@chromium.org>
> > ---
> > drivers/soc/mediatek/mtk-mutex.c | 87
> > ++++++++++++++++++++++++++++++--
> > 1 file changed, 84 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/soc/mediatek/mtk-mutex.c
> > b/drivers/soc/mediatek/mtk-mutex.c
> > index aaf8fc1abb43..729ee88035ed 100644
> > --- a/drivers/soc/mediatek/mtk-mutex.c
> > +++ b/drivers/soc/mediatek/mtk-mutex.c
> > @@ -17,6 +17,9 @@
> > #define MT8183_MUTEX0_MOD0 0x30
> > #define MT8183_MUTEX0_SOF0 0x2c
> >
> > +#define MT8195_DISP_MUTEX0_MOD0 0x30
> > +#define MT8195_DISP_MUTEX0_SOF 0x2c
>
> This is identical to mt8183, so use mt8183 one instead of creating
> new
> one.
>
> Regards,
> CK
>
I'll fix this in the next version.
Regards,
Jason-JH.Lin.
> >
> >
> > +static const struct mtk_mutex_data mt8195_mutex_driver_data = {
> > + .mutex_mod = mt8195_mutex_mod,
> > + .mutex_sof = mt8195_mutex_sof,
> > + .mutex_mod_reg = MT8195_DISP_MUTEX0_MOD0,
> > + .mutex_sof_reg = MT8195_DISP_MUTEX0_SOF,
> > +};
> > +
> >
>
>
--
Jason-JH Lin <jason-jh.lin@mediatek.com>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [PATCH v20 5/8] drm/mediatek: add mediatek-drm of vdosys0 support for mt8195
2022-04-19 9:41 ` jason-jh.lin
(?)
@ 2022-04-22 10:05 ` CK Hu
-1 siblings, 0 replies; 110+ messages in thread
From: CK Hu @ 2022-04-22 10:05 UTC (permalink / raw)
To: jason-jh.lin, Matthias Brugger, Chun-Kuang Hu,
AngeloGioacchino Del Regno
Cc: devicetree, Singo Chang, linux-kernel, dri-devel,
Project_Global_Chrome_Upstream_Group, Nancy Lin, linux-mediatek,
linux-arm-kernel
Hi, Jason:
On Tue, 2022-04-19 at 17:41 +0800, jason-jh.lin wrote:
> 1. Add driver data of mt8195 vdosys0 to mediatek-drm and the sub
> driver.
> 2. Add get driver data function to identify which vdosys by io_start.
Reviewed-by: CK Hu <ck.hu@mediatek.com>
>
> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <
> angelogioacchino.delregno@collabora.com>
> ---
> drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 6 +
> drivers/gpu/drm/mediatek/mtk_drm_drv.c | 141
> +++++++++++++++++++++--
> drivers/gpu/drm/mediatek/mtk_drm_drv.h | 6 +
> 3 files changed, 145 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
> b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
> index 662e91d9d45f..8ce60371536e 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
> @@ -364,6 +364,10 @@ static const struct mtk_disp_rdma_data
> mt8192_rdma_driver_data = {
> .fifo_size = 5 * SZ_1K,
> };
>
> +static const struct mtk_disp_rdma_data mt8195_rdma_driver_data = {
> + .fifo_size = 1920,
> +};
> +
> static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = {
> { .compatible = "mediatek,mt2701-disp-rdma",
> .data = &mt2701_rdma_driver_data},
> @@ -373,6 +377,8 @@ static const struct of_device_id
> mtk_disp_rdma_driver_dt_match[] = {
> .data = &mt8183_rdma_driver_data},
> { .compatible = "mediatek,mt8192-disp-rdma",
> .data = &mt8192_rdma_driver_data},
> + { .compatible = "mediatek,mt8195-disp-rdma",
> + .data = &mt8195_rdma_driver_data},
> {},
> };
> MODULE_DEVICE_TABLE(of, mtk_disp_rdma_driver_dt_match);
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> index f54b650a2ea1..a3d01940d4c6 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> @@ -4,6 +4,8 @@
> * Author: YT SHEN <yt.shen@mediatek.com>
> */
>
> +#include <linux/clk.h>
> +#include <linux/clk-provider.h>
> #include <linux/component.h>
> #include <linux/iommu.h>
> #include <linux/module.h>
> @@ -177,6 +179,19 @@ static const enum mtk_ddp_comp_id
> mt8192_mtk_ddp_ext[] = {
> DDP_COMPONENT_DPI0,
> };
>
> +static const enum mtk_ddp_comp_id mt8195_mtk_ddp_main[] = {
> + DDP_COMPONENT_OVL0,
> + DDP_COMPONENT_RDMA0,
> + DDP_COMPONENT_COLOR0,
> + DDP_COMPONENT_CCORR,
> + DDP_COMPONENT_AAL0,
> + DDP_COMPONENT_GAMMA,
> + DDP_COMPONENT_DITHER,
> + DDP_COMPONENT_DSC0,
> + DDP_COMPONENT_MERGE0,
> + DDP_COMPONENT_DP_INTF0,
> +};
> +
> static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data =
> {
> .main_path = mt2701_mtk_ddp_main,
> .main_len = ARRAY_SIZE(mt2701_mtk_ddp_main),
> @@ -185,6 +200,13 @@ static const struct mtk_mmsys_driver_data
> mt2701_mmsys_driver_data = {
> .shadow_register = true,
> };
>
> +static const struct mtk_mmsys_match_data mt2701_mmsys_match_data = {
> + .num_drv_data = 1,
> + .drv_data = {
> + &mt2701_mmsys_driver_data,
> + },
> +};
> +
> static const struct mtk_mmsys_driver_data mt7623_mmsys_driver_data =
> {
> .main_path = mt7623_mtk_ddp_main,
> .main_len = ARRAY_SIZE(mt7623_mtk_ddp_main),
> @@ -193,6 +215,13 @@ static const struct mtk_mmsys_driver_data
> mt7623_mmsys_driver_data = {
> .shadow_register = true,
> };
>
> +static const struct mtk_mmsys_match_data mt7623_mmsys_match_data = {
> + .num_drv_data = 1,
> + .drv_data = {
> + &mt7623_mmsys_driver_data,
> + },
> +};
> +
> static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data =
> {
> .main_path = mt2712_mtk_ddp_main,
> .main_len = ARRAY_SIZE(mt2712_mtk_ddp_main),
> @@ -202,11 +231,25 @@ static const struct mtk_mmsys_driver_data
> mt2712_mmsys_driver_data = {
> .third_len = ARRAY_SIZE(mt2712_mtk_ddp_third),
> };
>
> +static const struct mtk_mmsys_match_data mt2712_mmsys_match_data = {
> + .num_drv_data = 1,
> + .drv_data = {
> + &mt2712_mmsys_driver_data,
> + },
> +};
> +
> static const struct mtk_mmsys_driver_data mt8167_mmsys_driver_data =
> {
> .main_path = mt8167_mtk_ddp_main,
> .main_len = ARRAY_SIZE(mt8167_mtk_ddp_main),
> };
>
> +static const struct mtk_mmsys_match_data mt8167_mmsys_match_data = {
> + .num_drv_data = 1,
> + .drv_data = {
> + &mt8167_mmsys_driver_data,
> + },
> +};
> +
> static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data =
> {
> .main_path = mt8173_mtk_ddp_main,
> .main_len = ARRAY_SIZE(mt8173_mtk_ddp_main),
> @@ -214,6 +257,13 @@ static const struct mtk_mmsys_driver_data
> mt8173_mmsys_driver_data = {
> .ext_len = ARRAY_SIZE(mt8173_mtk_ddp_ext),
> };
>
> +static const struct mtk_mmsys_match_data mt8173_mmsys_match_data = {
> + .num_drv_data = 1,
> + .drv_data = {
> + &mt8173_mmsys_driver_data,
> + },
> +};
> +
> static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data =
> {
> .main_path = mt8183_mtk_ddp_main,
> .main_len = ARRAY_SIZE(mt8183_mtk_ddp_main),
> @@ -221,6 +271,13 @@ static const struct mtk_mmsys_driver_data
> mt8183_mmsys_driver_data = {
> .ext_len = ARRAY_SIZE(mt8183_mtk_ddp_ext),
> };
>
> +static const struct mtk_mmsys_match_data mt8183_mmsys_match_data = {
> + .num_drv_data = 1,
> + .drv_data = {
> + &mt8183_mmsys_driver_data,
> + },
> +};
> +
> static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data =
> {
> .main_path = mt8192_mtk_ddp_main,
> .main_len = ARRAY_SIZE(mt8192_mtk_ddp_main),
> @@ -228,6 +285,31 @@ static const struct mtk_mmsys_driver_data
> mt8192_mmsys_driver_data = {
> .ext_len = ARRAY_SIZE(mt8192_mtk_ddp_ext),
> };
>
> +static const struct mtk_mmsys_match_data mt8192_mmsys_match_data = {
> + .num_drv_data = 1,
> + .drv_data = {
> + &mt8192_mmsys_driver_data,
> + },
> +};
> +
> +static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data
> = {
> + .io_start = 0x1c01a000,
> + .main_path = mt8195_mtk_ddp_main,
> + .main_len = ARRAY_SIZE(mt8195_mtk_ddp_main),
> +};
> +
> +static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data
> = {
> + .io_start = 0x1c100000,
> +};
> +
> +static const struct mtk_mmsys_match_data mt8195_mmsys_match_data = {
> + .num_drv_data = 1,
> + .drv_data = {
> + &mt8195_vdosys0_driver_data,
> + &mt8195_vdosys1_driver_data,
> + },
> +};
> +
> static int mtk_drm_kms_init(struct drm_device *drm)
> {
> struct mtk_drm_private *private = drm->dev_private;
> @@ -445,12 +527,16 @@ static const struct of_device_id
> mtk_ddp_comp_dt_ids[] = {
> .data = (void *)MTK_DISP_DITHER },
> { .compatible = "mediatek,mt8183-disp-dither",
> .data = (void *)MTK_DISP_DITHER },
> + { .compatible = "mediatek,mt8195-disp-dsc",
> + .data = (void *)MTK_DISP_DSC },
> { .compatible = "mediatek,mt8167-disp-gamma",
> .data = (void *)MTK_DISP_GAMMA, },
> { .compatible = "mediatek,mt8173-disp-gamma",
> .data = (void *)MTK_DISP_GAMMA, },
> { .compatible = "mediatek,mt8183-disp-gamma",
> .data = (void *)MTK_DISP_GAMMA, },
> + { .compatible = "mediatek,mt8195-disp-merge",
> + .data = (void *)MTK_DISP_MERGE },
> { .compatible = "mediatek,mt2701-disp-mutex",
> .data = (void *)MTK_DISP_MUTEX },
> { .compatible = "mediatek,mt2712-disp-mutex",
> @@ -463,6 +549,8 @@ static const struct of_device_id
> mtk_ddp_comp_dt_ids[] = {
> .data = (void *)MTK_DISP_MUTEX },
> { .compatible = "mediatek,mt8192-disp-mutex",
> .data = (void *)MTK_DISP_MUTEX },
> + { .compatible = "mediatek,mt8195-disp-mutex",
> + .data = (void *)MTK_DISP_MUTEX },
> { .compatible = "mediatek,mt8173-disp-od",
> .data = (void *)MTK_DISP_OD },
> { .compatible = "mediatek,mt2701-disp-ovl",
> @@ -497,6 +585,8 @@ static const struct of_device_id
> mtk_ddp_comp_dt_ids[] = {
> .data = (void *)MTK_DISP_RDMA },
> { .compatible = "mediatek,mt8192-disp-rdma",
> .data = (void *)MTK_DISP_RDMA },
> + { .compatible = "mediatek,mt8195-disp-rdma",
> + .data = (void *)MTK_DISP_RDMA },
> { .compatible = "mediatek,mt8173-disp-ufoe",
> .data = (void *)MTK_DISP_UFOE },
> { .compatible = "mediatek,mt8173-disp-wdma",
> @@ -520,28 +610,51 @@ static const struct of_device_id
> mtk_ddp_comp_dt_ids[] = {
>
> static const struct of_device_id mtk_drm_of_ids[] = {
> { .compatible = "mediatek,mt2701-mmsys",
> - .data = &mt2701_mmsys_driver_data},
> + .data = &mt2701_mmsys_match_data},
> { .compatible = "mediatek,mt7623-mmsys",
> - .data = &mt7623_mmsys_driver_data},
> + .data = &mt7623_mmsys_match_data},
> { .compatible = "mediatek,mt2712-mmsys",
> - .data = &mt2712_mmsys_driver_data},
> + .data = &mt2712_mmsys_match_data},
> { .compatible = "mediatek,mt8167-mmsys",
> - .data = &mt8167_mmsys_driver_data},
> + .data = &mt8167_mmsys_match_data},
> { .compatible = "mediatek,mt8173-mmsys",
> - .data = &mt8173_mmsys_driver_data},
> + .data = &mt8173_mmsys_match_data},
> { .compatible = "mediatek,mt8183-mmsys",
> - .data = &mt8183_mmsys_driver_data},
> + .data = &mt8183_mmsys_match_data},
> { .compatible = "mediatek,mt8192-mmsys",
> - .data = &mt8192_mmsys_driver_data},
> + .data = &mt8192_mmsys_match_data},
> + { .compatible = "mediatek,mt8195-mmsys",
> + .data = &mt8195_mmsys_match_data},
> { }
> };
> MODULE_DEVICE_TABLE(of, mtk_drm_of_ids);
>
> +static int mtk_drm_find_match_data(struct device *dev,
> + const struct mtk_mmsys_match_data
> *match_data)
> +{
> + int i;
> + struct platform_device *pdev = of_find_device_by_node(dev-
> >parent->of_node);
> + struct resource *res;
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + if (!res) {
> + dev_err(dev, "failed to get parent resource\n");
> + return -EINVAL;
> + }
> +
> + for (i = 0; i < match_data->num_drv_data; i++)
> + if (match_data->drv_data[i]->io_start == res->start)
> + return i;
> +
> + return -EINVAL;
> +}
> +
> static int mtk_drm_probe(struct platform_device *pdev)
> {
> struct device *dev = &pdev->dev;
> struct device_node *phandle = dev->parent->of_node;
> const struct of_device_id *of_id;
> + const struct mtk_mmsys_match_data *match_data;
> struct mtk_drm_private *private;
> struct device_node *node;
> struct component_match *match = NULL;
> @@ -562,7 +675,19 @@ static int mtk_drm_probe(struct platform_device
> *pdev)
> if (!of_id)
> return -ENODEV;
>
> - private->data = of_id->data;
> + match_data = of_id->data;
> + if (match_data->num_drv_data > 1) {
> + /* This SoC has multiple mmsys channels */
> + ret = mtk_drm_find_match_data(dev, match_data);
> + if (ret < 0) {
> + dev_err(dev, "Couldn't get match driver
> data\n");
> + return ret;
> + }
> + private->data = match_data->drv_data[ret];
> + } else {
> + dev_dbg(dev, "Using single mmsys channel\n");
> + private->data = match_data->drv_data[0];
> + }
>
> /* Iterate over sibling DISP function blocks */
> for_each_child_of_node(phandle->parent, node) {
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> index a58cebd01d35..9fc922b1684f 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> @@ -21,6 +21,7 @@ struct drm_property;
> struct regmap;
>
> struct mtk_mmsys_driver_data {
> + const resource_size_t io_start;
> const enum mtk_ddp_comp_id *main_path;
> unsigned int main_len;
> const enum mtk_ddp_comp_id *ext_path;
> @@ -31,6 +32,11 @@ struct mtk_mmsys_driver_data {
> bool shadow_register;
> };
>
> +struct mtk_mmsys_match_data {
> + unsigned short num_drv_data;
> + const struct mtk_mmsys_driver_data *drv_data[];
> +};
> +
> struct mtk_drm_private {
> struct drm_device *drm;
> struct device *dma_dev;
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [PATCH v20 5/8] drm/mediatek: add mediatek-drm of vdosys0 support for mt8195
@ 2022-04-22 10:05 ` CK Hu
0 siblings, 0 replies; 110+ messages in thread
From: CK Hu @ 2022-04-22 10:05 UTC (permalink / raw)
To: jason-jh.lin, Matthias Brugger, Chun-Kuang Hu,
AngeloGioacchino Del Regno
Cc: Nancy Lin, Singo Chang, devicetree, linux-kernel, dri-devel,
linux-mediatek, linux-arm-kernel,
Project_Global_Chrome_Upstream_Group
Hi, Jason:
On Tue, 2022-04-19 at 17:41 +0800, jason-jh.lin wrote:
> 1. Add driver data of mt8195 vdosys0 to mediatek-drm and the sub
> driver.
> 2. Add get driver data function to identify which vdosys by io_start.
Reviewed-by: CK Hu <ck.hu@mediatek.com>
>
> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <
> angelogioacchino.delregno@collabora.com>
> ---
> drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 6 +
> drivers/gpu/drm/mediatek/mtk_drm_drv.c | 141
> +++++++++++++++++++++--
> drivers/gpu/drm/mediatek/mtk_drm_drv.h | 6 +
> 3 files changed, 145 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
> b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
> index 662e91d9d45f..8ce60371536e 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
> @@ -364,6 +364,10 @@ static const struct mtk_disp_rdma_data
> mt8192_rdma_driver_data = {
> .fifo_size = 5 * SZ_1K,
> };
>
> +static const struct mtk_disp_rdma_data mt8195_rdma_driver_data = {
> + .fifo_size = 1920,
> +};
> +
> static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = {
> { .compatible = "mediatek,mt2701-disp-rdma",
> .data = &mt2701_rdma_driver_data},
> @@ -373,6 +377,8 @@ static const struct of_device_id
> mtk_disp_rdma_driver_dt_match[] = {
> .data = &mt8183_rdma_driver_data},
> { .compatible = "mediatek,mt8192-disp-rdma",
> .data = &mt8192_rdma_driver_data},
> + { .compatible = "mediatek,mt8195-disp-rdma",
> + .data = &mt8195_rdma_driver_data},
> {},
> };
> MODULE_DEVICE_TABLE(of, mtk_disp_rdma_driver_dt_match);
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> index f54b650a2ea1..a3d01940d4c6 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> @@ -4,6 +4,8 @@
> * Author: YT SHEN <yt.shen@mediatek.com>
> */
>
> +#include <linux/clk.h>
> +#include <linux/clk-provider.h>
> #include <linux/component.h>
> #include <linux/iommu.h>
> #include <linux/module.h>
> @@ -177,6 +179,19 @@ static const enum mtk_ddp_comp_id
> mt8192_mtk_ddp_ext[] = {
> DDP_COMPONENT_DPI0,
> };
>
> +static const enum mtk_ddp_comp_id mt8195_mtk_ddp_main[] = {
> + DDP_COMPONENT_OVL0,
> + DDP_COMPONENT_RDMA0,
> + DDP_COMPONENT_COLOR0,
> + DDP_COMPONENT_CCORR,
> + DDP_COMPONENT_AAL0,
> + DDP_COMPONENT_GAMMA,
> + DDP_COMPONENT_DITHER,
> + DDP_COMPONENT_DSC0,
> + DDP_COMPONENT_MERGE0,
> + DDP_COMPONENT_DP_INTF0,
> +};
> +
> static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data =
> {
> .main_path = mt2701_mtk_ddp_main,
> .main_len = ARRAY_SIZE(mt2701_mtk_ddp_main),
> @@ -185,6 +200,13 @@ static const struct mtk_mmsys_driver_data
> mt2701_mmsys_driver_data = {
> .shadow_register = true,
> };
>
> +static const struct mtk_mmsys_match_data mt2701_mmsys_match_data = {
> + .num_drv_data = 1,
> + .drv_data = {
> + &mt2701_mmsys_driver_data,
> + },
> +};
> +
> static const struct mtk_mmsys_driver_data mt7623_mmsys_driver_data =
> {
> .main_path = mt7623_mtk_ddp_main,
> .main_len = ARRAY_SIZE(mt7623_mtk_ddp_main),
> @@ -193,6 +215,13 @@ static const struct mtk_mmsys_driver_data
> mt7623_mmsys_driver_data = {
> .shadow_register = true,
> };
>
> +static const struct mtk_mmsys_match_data mt7623_mmsys_match_data = {
> + .num_drv_data = 1,
> + .drv_data = {
> + &mt7623_mmsys_driver_data,
> + },
> +};
> +
> static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data =
> {
> .main_path = mt2712_mtk_ddp_main,
> .main_len = ARRAY_SIZE(mt2712_mtk_ddp_main),
> @@ -202,11 +231,25 @@ static const struct mtk_mmsys_driver_data
> mt2712_mmsys_driver_data = {
> .third_len = ARRAY_SIZE(mt2712_mtk_ddp_third),
> };
>
> +static const struct mtk_mmsys_match_data mt2712_mmsys_match_data = {
> + .num_drv_data = 1,
> + .drv_data = {
> + &mt2712_mmsys_driver_data,
> + },
> +};
> +
> static const struct mtk_mmsys_driver_data mt8167_mmsys_driver_data =
> {
> .main_path = mt8167_mtk_ddp_main,
> .main_len = ARRAY_SIZE(mt8167_mtk_ddp_main),
> };
>
> +static const struct mtk_mmsys_match_data mt8167_mmsys_match_data = {
> + .num_drv_data = 1,
> + .drv_data = {
> + &mt8167_mmsys_driver_data,
> + },
> +};
> +
> static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data =
> {
> .main_path = mt8173_mtk_ddp_main,
> .main_len = ARRAY_SIZE(mt8173_mtk_ddp_main),
> @@ -214,6 +257,13 @@ static const struct mtk_mmsys_driver_data
> mt8173_mmsys_driver_data = {
> .ext_len = ARRAY_SIZE(mt8173_mtk_ddp_ext),
> };
>
> +static const struct mtk_mmsys_match_data mt8173_mmsys_match_data = {
> + .num_drv_data = 1,
> + .drv_data = {
> + &mt8173_mmsys_driver_data,
> + },
> +};
> +
> static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data =
> {
> .main_path = mt8183_mtk_ddp_main,
> .main_len = ARRAY_SIZE(mt8183_mtk_ddp_main),
> @@ -221,6 +271,13 @@ static const struct mtk_mmsys_driver_data
> mt8183_mmsys_driver_data = {
> .ext_len = ARRAY_SIZE(mt8183_mtk_ddp_ext),
> };
>
> +static const struct mtk_mmsys_match_data mt8183_mmsys_match_data = {
> + .num_drv_data = 1,
> + .drv_data = {
> + &mt8183_mmsys_driver_data,
> + },
> +};
> +
> static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data =
> {
> .main_path = mt8192_mtk_ddp_main,
> .main_len = ARRAY_SIZE(mt8192_mtk_ddp_main),
> @@ -228,6 +285,31 @@ static const struct mtk_mmsys_driver_data
> mt8192_mmsys_driver_data = {
> .ext_len = ARRAY_SIZE(mt8192_mtk_ddp_ext),
> };
>
> +static const struct mtk_mmsys_match_data mt8192_mmsys_match_data = {
> + .num_drv_data = 1,
> + .drv_data = {
> + &mt8192_mmsys_driver_data,
> + },
> +};
> +
> +static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data
> = {
> + .io_start = 0x1c01a000,
> + .main_path = mt8195_mtk_ddp_main,
> + .main_len = ARRAY_SIZE(mt8195_mtk_ddp_main),
> +};
> +
> +static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data
> = {
> + .io_start = 0x1c100000,
> +};
> +
> +static const struct mtk_mmsys_match_data mt8195_mmsys_match_data = {
> + .num_drv_data = 1,
> + .drv_data = {
> + &mt8195_vdosys0_driver_data,
> + &mt8195_vdosys1_driver_data,
> + },
> +};
> +
> static int mtk_drm_kms_init(struct drm_device *drm)
> {
> struct mtk_drm_private *private = drm->dev_private;
> @@ -445,12 +527,16 @@ static const struct of_device_id
> mtk_ddp_comp_dt_ids[] = {
> .data = (void *)MTK_DISP_DITHER },
> { .compatible = "mediatek,mt8183-disp-dither",
> .data = (void *)MTK_DISP_DITHER },
> + { .compatible = "mediatek,mt8195-disp-dsc",
> + .data = (void *)MTK_DISP_DSC },
> { .compatible = "mediatek,mt8167-disp-gamma",
> .data = (void *)MTK_DISP_GAMMA, },
> { .compatible = "mediatek,mt8173-disp-gamma",
> .data = (void *)MTK_DISP_GAMMA, },
> { .compatible = "mediatek,mt8183-disp-gamma",
> .data = (void *)MTK_DISP_GAMMA, },
> + { .compatible = "mediatek,mt8195-disp-merge",
> + .data = (void *)MTK_DISP_MERGE },
> { .compatible = "mediatek,mt2701-disp-mutex",
> .data = (void *)MTK_DISP_MUTEX },
> { .compatible = "mediatek,mt2712-disp-mutex",
> @@ -463,6 +549,8 @@ static const struct of_device_id
> mtk_ddp_comp_dt_ids[] = {
> .data = (void *)MTK_DISP_MUTEX },
> { .compatible = "mediatek,mt8192-disp-mutex",
> .data = (void *)MTK_DISP_MUTEX },
> + { .compatible = "mediatek,mt8195-disp-mutex",
> + .data = (void *)MTK_DISP_MUTEX },
> { .compatible = "mediatek,mt8173-disp-od",
> .data = (void *)MTK_DISP_OD },
> { .compatible = "mediatek,mt2701-disp-ovl",
> @@ -497,6 +585,8 @@ static const struct of_device_id
> mtk_ddp_comp_dt_ids[] = {
> .data = (void *)MTK_DISP_RDMA },
> { .compatible = "mediatek,mt8192-disp-rdma",
> .data = (void *)MTK_DISP_RDMA },
> + { .compatible = "mediatek,mt8195-disp-rdma",
> + .data = (void *)MTK_DISP_RDMA },
> { .compatible = "mediatek,mt8173-disp-ufoe",
> .data = (void *)MTK_DISP_UFOE },
> { .compatible = "mediatek,mt8173-disp-wdma",
> @@ -520,28 +610,51 @@ static const struct of_device_id
> mtk_ddp_comp_dt_ids[] = {
>
> static const struct of_device_id mtk_drm_of_ids[] = {
> { .compatible = "mediatek,mt2701-mmsys",
> - .data = &mt2701_mmsys_driver_data},
> + .data = &mt2701_mmsys_match_data},
> { .compatible = "mediatek,mt7623-mmsys",
> - .data = &mt7623_mmsys_driver_data},
> + .data = &mt7623_mmsys_match_data},
> { .compatible = "mediatek,mt2712-mmsys",
> - .data = &mt2712_mmsys_driver_data},
> + .data = &mt2712_mmsys_match_data},
> { .compatible = "mediatek,mt8167-mmsys",
> - .data = &mt8167_mmsys_driver_data},
> + .data = &mt8167_mmsys_match_data},
> { .compatible = "mediatek,mt8173-mmsys",
> - .data = &mt8173_mmsys_driver_data},
> + .data = &mt8173_mmsys_match_data},
> { .compatible = "mediatek,mt8183-mmsys",
> - .data = &mt8183_mmsys_driver_data},
> + .data = &mt8183_mmsys_match_data},
> { .compatible = "mediatek,mt8192-mmsys",
> - .data = &mt8192_mmsys_driver_data},
> + .data = &mt8192_mmsys_match_data},
> + { .compatible = "mediatek,mt8195-mmsys",
> + .data = &mt8195_mmsys_match_data},
> { }
> };
> MODULE_DEVICE_TABLE(of, mtk_drm_of_ids);
>
> +static int mtk_drm_find_match_data(struct device *dev,
> + const struct mtk_mmsys_match_data
> *match_data)
> +{
> + int i;
> + struct platform_device *pdev = of_find_device_by_node(dev-
> >parent->of_node);
> + struct resource *res;
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + if (!res) {
> + dev_err(dev, "failed to get parent resource\n");
> + return -EINVAL;
> + }
> +
> + for (i = 0; i < match_data->num_drv_data; i++)
> + if (match_data->drv_data[i]->io_start == res->start)
> + return i;
> +
> + return -EINVAL;
> +}
> +
> static int mtk_drm_probe(struct platform_device *pdev)
> {
> struct device *dev = &pdev->dev;
> struct device_node *phandle = dev->parent->of_node;
> const struct of_device_id *of_id;
> + const struct mtk_mmsys_match_data *match_data;
> struct mtk_drm_private *private;
> struct device_node *node;
> struct component_match *match = NULL;
> @@ -562,7 +675,19 @@ static int mtk_drm_probe(struct platform_device
> *pdev)
> if (!of_id)
> return -ENODEV;
>
> - private->data = of_id->data;
> + match_data = of_id->data;
> + if (match_data->num_drv_data > 1) {
> + /* This SoC has multiple mmsys channels */
> + ret = mtk_drm_find_match_data(dev, match_data);
> + if (ret < 0) {
> + dev_err(dev, "Couldn't get match driver
> data\n");
> + return ret;
> + }
> + private->data = match_data->drv_data[ret];
> + } else {
> + dev_dbg(dev, "Using single mmsys channel\n");
> + private->data = match_data->drv_data[0];
> + }
>
> /* Iterate over sibling DISP function blocks */
> for_each_child_of_node(phandle->parent, node) {
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> index a58cebd01d35..9fc922b1684f 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> @@ -21,6 +21,7 @@ struct drm_property;
> struct regmap;
>
> struct mtk_mmsys_driver_data {
> + const resource_size_t io_start;
> const enum mtk_ddp_comp_id *main_path;
> unsigned int main_len;
> const enum mtk_ddp_comp_id *ext_path;
> @@ -31,6 +32,11 @@ struct mtk_mmsys_driver_data {
> bool shadow_register;
> };
>
> +struct mtk_mmsys_match_data {
> + unsigned short num_drv_data;
> + const struct mtk_mmsys_driver_data *drv_data[];
> +};
> +
> struct mtk_drm_private {
> struct drm_device *drm;
> struct device *dma_dev;
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^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [PATCH v20 5/8] drm/mediatek: add mediatek-drm of vdosys0 support for mt8195
@ 2022-04-22 10:05 ` CK Hu
0 siblings, 0 replies; 110+ messages in thread
From: CK Hu @ 2022-04-22 10:05 UTC (permalink / raw)
To: jason-jh.lin, Matthias Brugger, Chun-Kuang Hu,
AngeloGioacchino Del Regno
Cc: Nancy Lin, Singo Chang, devicetree, linux-kernel, dri-devel,
linux-mediatek, linux-arm-kernel,
Project_Global_Chrome_Upstream_Group
Hi, Jason:
On Tue, 2022-04-19 at 17:41 +0800, jason-jh.lin wrote:
> 1. Add driver data of mt8195 vdosys0 to mediatek-drm and the sub
> driver.
> 2. Add get driver data function to identify which vdosys by io_start.
Reviewed-by: CK Hu <ck.hu@mediatek.com>
>
> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <
> angelogioacchino.delregno@collabora.com>
> ---
> drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 6 +
> drivers/gpu/drm/mediatek/mtk_drm_drv.c | 141
> +++++++++++++++++++++--
> drivers/gpu/drm/mediatek/mtk_drm_drv.h | 6 +
> 3 files changed, 145 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
> b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
> index 662e91d9d45f..8ce60371536e 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
> @@ -364,6 +364,10 @@ static const struct mtk_disp_rdma_data
> mt8192_rdma_driver_data = {
> .fifo_size = 5 * SZ_1K,
> };
>
> +static const struct mtk_disp_rdma_data mt8195_rdma_driver_data = {
> + .fifo_size = 1920,
> +};
> +
> static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = {
> { .compatible = "mediatek,mt2701-disp-rdma",
> .data = &mt2701_rdma_driver_data},
> @@ -373,6 +377,8 @@ static const struct of_device_id
> mtk_disp_rdma_driver_dt_match[] = {
> .data = &mt8183_rdma_driver_data},
> { .compatible = "mediatek,mt8192-disp-rdma",
> .data = &mt8192_rdma_driver_data},
> + { .compatible = "mediatek,mt8195-disp-rdma",
> + .data = &mt8195_rdma_driver_data},
> {},
> };
> MODULE_DEVICE_TABLE(of, mtk_disp_rdma_driver_dt_match);
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> index f54b650a2ea1..a3d01940d4c6 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> @@ -4,6 +4,8 @@
> * Author: YT SHEN <yt.shen@mediatek.com>
> */
>
> +#include <linux/clk.h>
> +#include <linux/clk-provider.h>
> #include <linux/component.h>
> #include <linux/iommu.h>
> #include <linux/module.h>
> @@ -177,6 +179,19 @@ static const enum mtk_ddp_comp_id
> mt8192_mtk_ddp_ext[] = {
> DDP_COMPONENT_DPI0,
> };
>
> +static const enum mtk_ddp_comp_id mt8195_mtk_ddp_main[] = {
> + DDP_COMPONENT_OVL0,
> + DDP_COMPONENT_RDMA0,
> + DDP_COMPONENT_COLOR0,
> + DDP_COMPONENT_CCORR,
> + DDP_COMPONENT_AAL0,
> + DDP_COMPONENT_GAMMA,
> + DDP_COMPONENT_DITHER,
> + DDP_COMPONENT_DSC0,
> + DDP_COMPONENT_MERGE0,
> + DDP_COMPONENT_DP_INTF0,
> +};
> +
> static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data =
> {
> .main_path = mt2701_mtk_ddp_main,
> .main_len = ARRAY_SIZE(mt2701_mtk_ddp_main),
> @@ -185,6 +200,13 @@ static const struct mtk_mmsys_driver_data
> mt2701_mmsys_driver_data = {
> .shadow_register = true,
> };
>
> +static const struct mtk_mmsys_match_data mt2701_mmsys_match_data = {
> + .num_drv_data = 1,
> + .drv_data = {
> + &mt2701_mmsys_driver_data,
> + },
> +};
> +
> static const struct mtk_mmsys_driver_data mt7623_mmsys_driver_data =
> {
> .main_path = mt7623_mtk_ddp_main,
> .main_len = ARRAY_SIZE(mt7623_mtk_ddp_main),
> @@ -193,6 +215,13 @@ static const struct mtk_mmsys_driver_data
> mt7623_mmsys_driver_data = {
> .shadow_register = true,
> };
>
> +static const struct mtk_mmsys_match_data mt7623_mmsys_match_data = {
> + .num_drv_data = 1,
> + .drv_data = {
> + &mt7623_mmsys_driver_data,
> + },
> +};
> +
> static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data =
> {
> .main_path = mt2712_mtk_ddp_main,
> .main_len = ARRAY_SIZE(mt2712_mtk_ddp_main),
> @@ -202,11 +231,25 @@ static const struct mtk_mmsys_driver_data
> mt2712_mmsys_driver_data = {
> .third_len = ARRAY_SIZE(mt2712_mtk_ddp_third),
> };
>
> +static const struct mtk_mmsys_match_data mt2712_mmsys_match_data = {
> + .num_drv_data = 1,
> + .drv_data = {
> + &mt2712_mmsys_driver_data,
> + },
> +};
> +
> static const struct mtk_mmsys_driver_data mt8167_mmsys_driver_data =
> {
> .main_path = mt8167_mtk_ddp_main,
> .main_len = ARRAY_SIZE(mt8167_mtk_ddp_main),
> };
>
> +static const struct mtk_mmsys_match_data mt8167_mmsys_match_data = {
> + .num_drv_data = 1,
> + .drv_data = {
> + &mt8167_mmsys_driver_data,
> + },
> +};
> +
> static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data =
> {
> .main_path = mt8173_mtk_ddp_main,
> .main_len = ARRAY_SIZE(mt8173_mtk_ddp_main),
> @@ -214,6 +257,13 @@ static const struct mtk_mmsys_driver_data
> mt8173_mmsys_driver_data = {
> .ext_len = ARRAY_SIZE(mt8173_mtk_ddp_ext),
> };
>
> +static const struct mtk_mmsys_match_data mt8173_mmsys_match_data = {
> + .num_drv_data = 1,
> + .drv_data = {
> + &mt8173_mmsys_driver_data,
> + },
> +};
> +
> static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data =
> {
> .main_path = mt8183_mtk_ddp_main,
> .main_len = ARRAY_SIZE(mt8183_mtk_ddp_main),
> @@ -221,6 +271,13 @@ static const struct mtk_mmsys_driver_data
> mt8183_mmsys_driver_data = {
> .ext_len = ARRAY_SIZE(mt8183_mtk_ddp_ext),
> };
>
> +static const struct mtk_mmsys_match_data mt8183_mmsys_match_data = {
> + .num_drv_data = 1,
> + .drv_data = {
> + &mt8183_mmsys_driver_data,
> + },
> +};
> +
> static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data =
> {
> .main_path = mt8192_mtk_ddp_main,
> .main_len = ARRAY_SIZE(mt8192_mtk_ddp_main),
> @@ -228,6 +285,31 @@ static const struct mtk_mmsys_driver_data
> mt8192_mmsys_driver_data = {
> .ext_len = ARRAY_SIZE(mt8192_mtk_ddp_ext),
> };
>
> +static const struct mtk_mmsys_match_data mt8192_mmsys_match_data = {
> + .num_drv_data = 1,
> + .drv_data = {
> + &mt8192_mmsys_driver_data,
> + },
> +};
> +
> +static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data
> = {
> + .io_start = 0x1c01a000,
> + .main_path = mt8195_mtk_ddp_main,
> + .main_len = ARRAY_SIZE(mt8195_mtk_ddp_main),
> +};
> +
> +static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data
> = {
> + .io_start = 0x1c100000,
> +};
> +
> +static const struct mtk_mmsys_match_data mt8195_mmsys_match_data = {
> + .num_drv_data = 1,
> + .drv_data = {
> + &mt8195_vdosys0_driver_data,
> + &mt8195_vdosys1_driver_data,
> + },
> +};
> +
> static int mtk_drm_kms_init(struct drm_device *drm)
> {
> struct mtk_drm_private *private = drm->dev_private;
> @@ -445,12 +527,16 @@ static const struct of_device_id
> mtk_ddp_comp_dt_ids[] = {
> .data = (void *)MTK_DISP_DITHER },
> { .compatible = "mediatek,mt8183-disp-dither",
> .data = (void *)MTK_DISP_DITHER },
> + { .compatible = "mediatek,mt8195-disp-dsc",
> + .data = (void *)MTK_DISP_DSC },
> { .compatible = "mediatek,mt8167-disp-gamma",
> .data = (void *)MTK_DISP_GAMMA, },
> { .compatible = "mediatek,mt8173-disp-gamma",
> .data = (void *)MTK_DISP_GAMMA, },
> { .compatible = "mediatek,mt8183-disp-gamma",
> .data = (void *)MTK_DISP_GAMMA, },
> + { .compatible = "mediatek,mt8195-disp-merge",
> + .data = (void *)MTK_DISP_MERGE },
> { .compatible = "mediatek,mt2701-disp-mutex",
> .data = (void *)MTK_DISP_MUTEX },
> { .compatible = "mediatek,mt2712-disp-mutex",
> @@ -463,6 +549,8 @@ static const struct of_device_id
> mtk_ddp_comp_dt_ids[] = {
> .data = (void *)MTK_DISP_MUTEX },
> { .compatible = "mediatek,mt8192-disp-mutex",
> .data = (void *)MTK_DISP_MUTEX },
> + { .compatible = "mediatek,mt8195-disp-mutex",
> + .data = (void *)MTK_DISP_MUTEX },
> { .compatible = "mediatek,mt8173-disp-od",
> .data = (void *)MTK_DISP_OD },
> { .compatible = "mediatek,mt2701-disp-ovl",
> @@ -497,6 +585,8 @@ static const struct of_device_id
> mtk_ddp_comp_dt_ids[] = {
> .data = (void *)MTK_DISP_RDMA },
> { .compatible = "mediatek,mt8192-disp-rdma",
> .data = (void *)MTK_DISP_RDMA },
> + { .compatible = "mediatek,mt8195-disp-rdma",
> + .data = (void *)MTK_DISP_RDMA },
> { .compatible = "mediatek,mt8173-disp-ufoe",
> .data = (void *)MTK_DISP_UFOE },
> { .compatible = "mediatek,mt8173-disp-wdma",
> @@ -520,28 +610,51 @@ static const struct of_device_id
> mtk_ddp_comp_dt_ids[] = {
>
> static const struct of_device_id mtk_drm_of_ids[] = {
> { .compatible = "mediatek,mt2701-mmsys",
> - .data = &mt2701_mmsys_driver_data},
> + .data = &mt2701_mmsys_match_data},
> { .compatible = "mediatek,mt7623-mmsys",
> - .data = &mt7623_mmsys_driver_data},
> + .data = &mt7623_mmsys_match_data},
> { .compatible = "mediatek,mt2712-mmsys",
> - .data = &mt2712_mmsys_driver_data},
> + .data = &mt2712_mmsys_match_data},
> { .compatible = "mediatek,mt8167-mmsys",
> - .data = &mt8167_mmsys_driver_data},
> + .data = &mt8167_mmsys_match_data},
> { .compatible = "mediatek,mt8173-mmsys",
> - .data = &mt8173_mmsys_driver_data},
> + .data = &mt8173_mmsys_match_data},
> { .compatible = "mediatek,mt8183-mmsys",
> - .data = &mt8183_mmsys_driver_data},
> + .data = &mt8183_mmsys_match_data},
> { .compatible = "mediatek,mt8192-mmsys",
> - .data = &mt8192_mmsys_driver_data},
> + .data = &mt8192_mmsys_match_data},
> + { .compatible = "mediatek,mt8195-mmsys",
> + .data = &mt8195_mmsys_match_data},
> { }
> };
> MODULE_DEVICE_TABLE(of, mtk_drm_of_ids);
>
> +static int mtk_drm_find_match_data(struct device *dev,
> + const struct mtk_mmsys_match_data
> *match_data)
> +{
> + int i;
> + struct platform_device *pdev = of_find_device_by_node(dev-
> >parent->of_node);
> + struct resource *res;
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + if (!res) {
> + dev_err(dev, "failed to get parent resource\n");
> + return -EINVAL;
> + }
> +
> + for (i = 0; i < match_data->num_drv_data; i++)
> + if (match_data->drv_data[i]->io_start == res->start)
> + return i;
> +
> + return -EINVAL;
> +}
> +
> static int mtk_drm_probe(struct platform_device *pdev)
> {
> struct device *dev = &pdev->dev;
> struct device_node *phandle = dev->parent->of_node;
> const struct of_device_id *of_id;
> + const struct mtk_mmsys_match_data *match_data;
> struct mtk_drm_private *private;
> struct device_node *node;
> struct component_match *match = NULL;
> @@ -562,7 +675,19 @@ static int mtk_drm_probe(struct platform_device
> *pdev)
> if (!of_id)
> return -ENODEV;
>
> - private->data = of_id->data;
> + match_data = of_id->data;
> + if (match_data->num_drv_data > 1) {
> + /* This SoC has multiple mmsys channels */
> + ret = mtk_drm_find_match_data(dev, match_data);
> + if (ret < 0) {
> + dev_err(dev, "Couldn't get match driver
> data\n");
> + return ret;
> + }
> + private->data = match_data->drv_data[ret];
> + } else {
> + dev_dbg(dev, "Using single mmsys channel\n");
> + private->data = match_data->drv_data[0];
> + }
>
> /* Iterate over sibling DISP function blocks */
> for_each_child_of_node(phandle->parent, node) {
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> index a58cebd01d35..9fc922b1684f 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> @@ -21,6 +21,7 @@ struct drm_property;
> struct regmap;
>
> struct mtk_mmsys_driver_data {
> + const resource_size_t io_start;
> const enum mtk_ddp_comp_id *main_path;
> unsigned int main_len;
> const enum mtk_ddp_comp_id *ext_path;
> @@ -31,6 +32,11 @@ struct mtk_mmsys_driver_data {
> bool shadow_register;
> };
>
> +struct mtk_mmsys_match_data {
> + unsigned short num_drv_data;
> + const struct mtk_mmsys_driver_data *drv_data[];
> +};
> +
> struct mtk_drm_private {
> struct drm_device *drm;
> struct device *dma_dev;
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^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [PATCH v20 1/8] soc: mediatek: add mtk-mmsys support for mt8195 vdosys0
2022-04-19 9:41 ` jason-jh.lin
(?)
(?)
@ 2022-04-22 12:28 ` Matthias Brugger
-1 siblings, 0 replies; 110+ messages in thread
From: Matthias Brugger @ 2022-04-22 12:28 UTC (permalink / raw)
To: jason-jh.lin, Chun-Kuang Hu, AngeloGioacchino Del Regno
Cc: CK Hu, Nancy Lin, Singo Chang, devicetree, linux-kernel,
dri-devel, linux-mediatek, linux-arm-kernel,
Project_Global_Chrome_Upstream_Group
On 19/04/2022 11:41, jason-jh.lin wrote:
> 1. Add mt8195 mmsys compatible for 2 vdosys.
> 2. Add io_start into each driver data of mt8195 vdosys.
> 3. Add get match data function to identify mmsys by io_start.
> 4. Add mt8195 routing table settings of vdosys0.
>
> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
I'm not very happy with the approach of testing against the reg property to
decide which version of the two mmsys devices we are probing. I think a better
approach would be, if we would have added some mediatek specific ID to the
device tree binding (or use a two compatibles?).
But as we are at v20 I think it wouldn't be fair to ask for such an instrusive
change. So I'll take this patch now, but maybe we can discuss if we can't do
better in a follow-up patch. Especially I don't think it's a good approach to
check for the io_start in the DRM driver. Couldn't we pass the information about
which of the two mmsys blocks we are calling from through the mediatek-drm
platform device spefic data?
I also had a look into the vdosys1 series to better understand why we need to do
things as we do them. But honestly I wasn't able to really understand the
implication of the patch that adds 'multi mmsys support' [1]. For this looks
like a several patches that got squashed into one. But as I don't have to
maintain that it is not my call to complain, the patch has the needed reviews.
For this patch, now applied to v5.18-next/soc
Thanks for all people implicated.
Regards,
Matthias
[1]
https://patchwork.kernel.org/project/linux-mediatek/patch/20220416020749.29010-19-nancy.lin@mediatek.com/
> ---
> Based on series [1]
>
> [1] MediaTek MT8195 display binding
> - https://patchwork.ozlabs.org/project/devicetree-bindings/list/?series=295669
> ---
> drivers/soc/mediatek/mt8195-mmsys.h | 370 +++++++++++++++++++++++++
> drivers/soc/mediatek/mtk-mmsys.c | 152 +++++++++-
> drivers/soc/mediatek/mtk-mmsys.h | 6 +
> include/linux/soc/mediatek/mtk-mmsys.h | 11 +
> 4 files changed, 528 insertions(+), 11 deletions(-)
> create mode 100644 drivers/soc/mediatek/mt8195-mmsys.h
>
> diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h
> new file mode 100644
> index 000000000000..13ab0ab64396
> --- /dev/null
> +++ b/drivers/soc/mediatek/mt8195-mmsys.h
> @@ -0,0 +1,370 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +
> +#ifndef __SOC_MEDIATEK_MT8195_MMSYS_H
> +#define __SOC_MEDIATEK_MT8195_MMSYS_H
> +
> +#define MT8195_VDO0_OVL_MOUT_EN 0xf14
> +#define MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0 BIT(0)
> +#define MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0 BIT(1)
> +#define MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1 BIT(2)
> +#define MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1 BIT(4)
> +#define MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1 BIT(5)
> +#define MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0 BIT(6)
> +
> +#define MT8195_VDO0_SEL_IN 0xf34
> +#define MT8195_SEL_IN_VPP_MERGE_FROM_MASK GENMASK(1, 0)
> +#define MT8195_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT (0 << 0)
> +#define MT8195_SEL_IN_VPP_MERGE_FROM_DISP_DITHER1 (1 << 0)
> +#define MT8195_SEL_IN_VPP_MERGE_FROM_VDO1_VIRTUAL0 (2 << 0)
> +#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK GENMASK(4, 4)
> +#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0 (0 << 4)
> +#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_VPP_MERGE (1 << 4)
> +#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_MASK GENMASK(5, 5)
> +#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_DISP_DITHER1 (0 << 5)
> +#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_VPP_MERGE (1 << 5)
> +#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK GENMASK(8, 8)
> +#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE (0 << 8)
> +#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT (1 << 8)
> +#define MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK GENMASK(9, 9)
> +#define MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT (0 << 9)
> +#define MT8195_SEL_IN_DP_INTF0_FROM_MASK GENMASK(13, 12)
> +#define MT8195_SEL_IN_DP_INTF0_FROM_DSC_WRAP1_OUT (0 << 0)
> +#define MT8195_SEL_IN_DP_INTF0_FROM_VPP_MERGE (1 << 12)
> +#define MT8195_SEL_IN_DP_INTF0_FROM_VDO1_VIRTUAL0 (2 << 12)
> +#define MT8195_SEL_IN_DSI0_FROM_MASK GENMASK(16, 16)
> +#define MT8195_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT (0 << 16)
> +#define MT8195_SEL_IN_DSI0_FROM_DISP_DITHER0 (1 << 16)
> +#define MT8195_SEL_IN_DSI1_FROM_MASK GENMASK(17, 17)
> +#define MT8195_SEL_IN_DSI1_FROM_DSC_WRAP1_OUT (0 << 17)
> +#define MT8195_SEL_IN_DSI1_FROM_VPP_MERGE (1 << 17)
> +#define MT8195_SEL_IN_DISP_WDMA1_FROM_MASK GENMASK(20, 20)
> +#define MT8195_SEL_IN_DISP_WDMA1_FROM_DISP_OVL1 (0 << 20)
> +#define MT8195_SEL_IN_DISP_WDMA1_FROM_VPP_MERGE (1 << 20)
> +#define MT8195_SEL_IN_DSC_WRAP1_FROM_MASK GENMASK(21, 21)
> +#define MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN (0 << 21)
> +#define MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1 (1 << 21)
> +#define MT8195_SEL_IN_DISP_WDMA0_FROM_MASK GENMASK(22, 22)
> +#define MT8195_SEL_IN_DISP_WDMA0_FROM_DISP_OVL0 (0 << 22)
> +
> +#define MT8195_VDO0_SEL_OUT 0xf38
> +#define MT8195_SOUT_DISP_DITHER0_TO_MASK BIT(0)
> +#define MT8195_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN (0 << 0)
> +#define MT8195_SOUT_DISP_DITHER0_TO_DSI0 (1 << 0)
> +#define MT8195_SOUT_DISP_DITHER1_TO_MASK GENMASK(2, 1)
> +#define MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_IN (0 << 1)
> +#define MT8195_SOUT_DISP_DITHER1_TO_VPP_MERGE (1 << 1)
> +#define MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT (2 << 1)
> +#define MT8195_SOUT_VDO1_VIRTUAL0_TO_MASK GENMASK(4, 4)
> +#define MT8195_SOUT_VDO1_VIRTUAL0_TO_VPP_MERGE (0 << 4)
> +#define MT8195_SOUT_VDO1_VIRTUAL0_TO_DP_INTF0 (1 << 4)
> +#define MT8195_SOUT_VPP_MERGE_TO_MASK GENMASK(10, 8)
> +#define MT8195_SOUT_VPP_MERGE_TO_DSI1 (0 << 8)
> +#define MT8195_SOUT_VPP_MERGE_TO_DP_INTF0 (1 << 8)
> +#define MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0 (2 << 8)
> +#define MT8195_SOUT_VPP_MERGE_TO_DISP_WDMA1 (3 << 8)
> +#define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP0_IN (4 << 8)
> +#define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN_MASK GENMASK(11, 11)
> +#define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN (0 << 11)
> +#define MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK GENMASK(13, 12)
> +#define MT8195_SOUT_DSC_WRAP0_OUT_TO_DSI0 (0 << 12)
> +#define MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0 (1 << 12)
> +#define MT8195_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE (2 << 12)
> +#define MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK GENMASK(17, 16)
> +#define MT8195_SOUT_DSC_WRAP1_OUT_TO_DSI1 (0 << 16)
> +#define MT8195_SOUT_DSC_WRAP1_OUT_TO_DP_INTF0 (1 << 16)
> +#define MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0 (2 << 16)
> +#define MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE (3 << 16)
> +
> +static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
> + {
> + DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
> + MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0,
> + MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0
> + }, {
> + DDP_COMPONENT_OVL0, DDP_COMPONENT_WDMA0,
> + MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0,
> + MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0
> + }, {
> + DDP_COMPONENT_OVL0, DDP_COMPONENT_OVL1,
> + MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1,
> + MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1
> + }, {
> + DDP_COMPONENT_OVL1, DDP_COMPONENT_RDMA1,
> + MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1,
> + MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1
> + }, {
> + DDP_COMPONENT_OVL1, DDP_COMPONENT_WDMA1,
> + MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1,
> + MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1
> + }, {
> + DDP_COMPONENT_OVL1, DDP_COMPONENT_OVL0,
> + MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0,
> + MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0
> + }, {
> + DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK,
> + MT8195_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT
> + }, {
> + DDP_COMPONENT_DITHER1, DDP_COMPONENT_MERGE0,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK,
> + MT8195_SEL_IN_VPP_MERGE_FROM_DISP_DITHER1
> + }, {
> + DDP_COMPONENT_MERGE5, DDP_COMPONENT_MERGE0,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK,
> + MT8195_SEL_IN_VPP_MERGE_FROM_VDO1_VIRTUAL0
> + }, {
> + DDP_COMPONENT_DITHER, DDP_COMPONENT_DSC0,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK,
> + MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0
> + }, {
> + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC0,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK,
> + MT8195_SEL_IN_DSC_WRAP0_IN_FROM_VPP_MERGE
> + }, {
> + DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSC1,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_IN_FROM_MASK,
> + MT8195_SEL_IN_DSC_WRAP1_IN_FROM_DISP_DITHER1
> + }, {
> + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC1,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_IN_FROM_MASK,
> + MT8195_SEL_IN_DSC_WRAP1_IN_FROM_VPP_MERGE
> + }, {
> + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF1,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
> + MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE
> + }, {
> + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI0,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
> + MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE
> + }, {
> + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI1,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
> + MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE
> + }, {
> + DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF1,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
> + MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT
> + }, {
> + DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI0,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
> + MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT
> + }, {
> + DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI1,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
> + MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT
> + }, {
> + DDP_COMPONENT_DSC0, DDP_COMPONENT_DP_INTF1,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK,
> + MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT
> + }, {
> + DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI0,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK,
> + MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT
> + }, {
> + DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI1,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK,
> + MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT
> + }, {
> + DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF0,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_MASK,
> + MT8195_SEL_IN_DP_INTF0_FROM_DSC_WRAP1_OUT
> + }, {
> + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF0,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_MASK,
> + MT8195_SEL_IN_DP_INTF0_FROM_VPP_MERGE
> + }, {
> + DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF0,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_MASK,
> + MT8195_SEL_IN_DP_INTF0_FROM_VDO1_VIRTUAL0
> + }, {
> + DDP_COMPONENT_DSC0, DDP_COMPONENT_DSI0,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI0_FROM_MASK,
> + MT8195_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT
> + }, {
> + DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI0_FROM_MASK,
> + MT8195_SEL_IN_DSI0_FROM_DISP_DITHER0
> + }, {
> + DDP_COMPONENT_DSC1, DDP_COMPONENT_DSI1,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI1_FROM_MASK,
> + MT8195_SEL_IN_DSI1_FROM_DSC_WRAP1_OUT
> + }, {
> + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSI1,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI1_FROM_MASK,
> + MT8195_SEL_IN_DSI1_FROM_VPP_MERGE
> + }, {
> + DDP_COMPONENT_OVL1, DDP_COMPONENT_WDMA1,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA1_FROM_MASK,
> + MT8195_SEL_IN_DISP_WDMA1_FROM_DISP_OVL1
> + }, {
> + DDP_COMPONENT_MERGE0, DDP_COMPONENT_WDMA1,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA1_FROM_MASK,
> + MT8195_SEL_IN_DISP_WDMA1_FROM_VPP_MERGE
> + }, {
> + DDP_COMPONENT_DSC1, DDP_COMPONENT_DSI1,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
> + MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
> + }, {
> + DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF0,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
> + MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
> + }, {
> + DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF1,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
> + MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
> + }, {
> + DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI0,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
> + MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
> + }, {
> + DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI1,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
> + MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
> + }, {
> + DDP_COMPONENT_DSC1, DDP_COMPONENT_MERGE0,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
> + MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
> + }, {
> + DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSI1,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
> + MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1
> + }, {
> + DDP_COMPONENT_DITHER1, DDP_COMPONENT_DP_INTF0,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
> + MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1
> + }, {
> + DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI0,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
> + MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1
> + }, {
> + DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI1,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
> + MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1
> + }, {
> + DDP_COMPONENT_OVL0, DDP_COMPONENT_WDMA0,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA0_FROM_MASK,
> + MT8195_SEL_IN_DISP_WDMA0_FROM_DISP_OVL0
> + }, {
> + DDP_COMPONENT_DITHER, DDP_COMPONENT_DSC0,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER0_TO_MASK,
> + MT8195_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN
> + }, {
> + DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER0_TO_MASK,
> + MT8195_SOUT_DISP_DITHER0_TO_DSI0
> + }, {
> + DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSC1,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
> + MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_IN
> + }, {
> + DDP_COMPONENT_DITHER1, DDP_COMPONENT_MERGE0,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
> + MT8195_SOUT_DISP_DITHER1_TO_VPP_MERGE
> + }, {
> + DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSI1,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
> + MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT
> + }, {
> + DDP_COMPONENT_DITHER1, DDP_COMPONENT_DP_INTF0,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
> + MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT
> + }, {
> + DDP_COMPONENT_DITHER1, DDP_COMPONENT_DP_INTF1,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
> + MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT
> + }, {
> + DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI0,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
> + MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT
> + }, {
> + DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI1,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
> + MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT
> + }, {
> + DDP_COMPONENT_MERGE5, DDP_COMPONENT_MERGE0,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_VDO1_VIRTUAL0_TO_MASK,
> + MT8195_SOUT_VDO1_VIRTUAL0_TO_VPP_MERGE
> + }, {
> + DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF0,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_VDO1_VIRTUAL0_TO_MASK,
> + MT8195_SOUT_VDO1_VIRTUAL0_TO_DP_INTF0
> + }, {
> + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSI1,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
> + MT8195_SOUT_VPP_MERGE_TO_DSI1
> + }, {
> + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF0,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
> + MT8195_SOUT_VPP_MERGE_TO_DP_INTF0
> + }, {
> + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF1,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
> + MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0
> + }, {
> + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI0,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
> + MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0
> + }, {
> + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI1,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
> + MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0
> + }, {
> + DDP_COMPONENT_MERGE0, DDP_COMPONENT_WDMA1,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
> + MT8195_SOUT_VPP_MERGE_TO_DISP_WDMA1
> + }, {
> + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC0,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
> + MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP0_IN
> + }, {
> + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC1,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN_MASK,
> + MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN
> + }, {
> + DDP_COMPONENT_DSC0, DDP_COMPONENT_DSI0,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
> + MT8195_SOUT_DSC_WRAP0_OUT_TO_DSI0
> + }, {
> + DDP_COMPONENT_DSC0, DDP_COMPONENT_DP_INTF1,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
> + MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0
> + }, {
> + DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI0,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
> + MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0
> + }, {
> + DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI1,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
> + MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0
> + }, {
> + DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
> + MT8195_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE
> + }, {
> + DDP_COMPONENT_DSC1, DDP_COMPONENT_DSI1,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
> + MT8195_SOUT_DSC_WRAP1_OUT_TO_DSI1
> + }, {
> + DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF0,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
> + MT8195_SOUT_DSC_WRAP1_OUT_TO_DP_INTF0
> + }, {
> + DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF1,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
> + MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0
> + }, {
> + DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI0,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
> + MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0
> + }, {
> + DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI1,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
> + MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0
> + }, {
> + DDP_COMPONENT_DSC1, DDP_COMPONENT_MERGE0,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
> + MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE
> + }
> +};
> +
> +#endif /* __SOC_MEDIATEK_MT8195_MMSYS_H */
> diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
> index 4fc4c2c9ea20..548efed8dc1c 100644
> --- a/drivers/soc/mediatek/mtk-mmsys.c
> +++ b/drivers/soc/mediatek/mtk-mmsys.c
> @@ -17,6 +17,7 @@
> #include "mt8183-mmsys.h"
> #include "mt8186-mmsys.h"
> #include "mt8192-mmsys.h"
> +#include "mt8195-mmsys.h"
> #include "mt8365-mmsys.h"
>
> static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
> @@ -25,26 +26,61 @@ static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
> .num_routes = ARRAY_SIZE(mmsys_default_routing_table),
> };
>
> +static const struct mtk_mmsys_match_data mt2701_mmsys_match_data = {
> + .num_drv_data = 1,
> + .drv_data = {
> + &mt2701_mmsys_driver_data,
> + },
> +};
> +
> static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = {
> .clk_driver = "clk-mt2712-mm",
> .routes = mmsys_default_routing_table,
> .num_routes = ARRAY_SIZE(mmsys_default_routing_table),
> };
>
> +static const struct mtk_mmsys_match_data mt2712_mmsys_match_data = {
> + .num_drv_data = 1,
> + .drv_data = {
> + &mt2712_mmsys_driver_data,
> + },
> +};
> +
> static const struct mtk_mmsys_driver_data mt6779_mmsys_driver_data = {
> .clk_driver = "clk-mt6779-mm",
> };
>
> +static const struct mtk_mmsys_match_data mt6779_mmsys_match_data = {
> + .num_drv_data = 1,
> + .drv_data = {
> + &mt6779_mmsys_driver_data,
> + },
> +};
> +
> static const struct mtk_mmsys_driver_data mt6797_mmsys_driver_data = {
> .clk_driver = "clk-mt6797-mm",
> };
>
> +static const struct mtk_mmsys_match_data mt6797_mmsys_match_data = {
> + .num_drv_data = 1,
> + .drv_data = {
> + &mt6797_mmsys_driver_data,
> + },
> +};
> +
> static const struct mtk_mmsys_driver_data mt8167_mmsys_driver_data = {
> .clk_driver = "clk-mt8167-mm",
> .routes = mt8167_mmsys_routing_table,
> .num_routes = ARRAY_SIZE(mt8167_mmsys_routing_table),
> };
>
> +static const struct mtk_mmsys_match_data mt8167_mmsys_match_data = {
> + .num_drv_data = 1,
> + .drv_data = {
> + &mt8167_mmsys_driver_data,
> + },
> +};
> +
> static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
> .clk_driver = "clk-mt8173-mm",
> .routes = mmsys_default_routing_table,
> @@ -52,6 +88,13 @@ static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
> .sw0_rst_offset = MT8183_MMSYS_SW0_RST_B,
> };
>
> +static const struct mtk_mmsys_match_data mt8173_mmsys_match_data = {
> + .num_drv_data = 1,
> + .drv_data = {
> + &mt8173_mmsys_driver_data,
> + },
> +};
> +
> static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
> .clk_driver = "clk-mt8183-mm",
> .routes = mmsys_mt8183_routing_table,
> @@ -59,6 +102,13 @@ static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
> .sw0_rst_offset = MT8183_MMSYS_SW0_RST_B,
> };
>
> +static const struct mtk_mmsys_match_data mt8183_mmsys_match_data = {
> + .num_drv_data = 1,
> + .drv_data = {
> + &mt8183_mmsys_driver_data,
> + },
> +};
> +
> static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = {
> .clk_driver = "clk-mt8186-mm",
> .routes = mmsys_mt8186_routing_table,
> @@ -66,25 +116,79 @@ static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = {
> .sw0_rst_offset = MT8186_MMSYS_SW0_RST_B,
> };
>
> +static const struct mtk_mmsys_match_data mt8186_mmsys_match_data = {
> + .num_drv_data = 1,
> + .drv_data = {
> + &mt8186_mmsys_driver_data,
> + },
> +};
> +
> static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
> .clk_driver = "clk-mt8192-mm",
> .routes = mmsys_mt8192_routing_table,
> .num_routes = ARRAY_SIZE(mmsys_mt8192_routing_table),
> };
>
> +static const struct mtk_mmsys_match_data mt8192_mmsys_match_data = {
> + .num_drv_data = 1,
> + .drv_data = {
> + &mt8192_mmsys_driver_data,
> + },
> +};
> +
> +static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = {
> + .io_start = 0x1c01a000,
> + .clk_driver = "clk-mt8195-vdo0",
> + .routes = mmsys_mt8195_routing_table,
> + .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
> +};
> +
> +static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
> + .io_start = 0x1c100000,
> + .clk_driver = "clk-mt8195-vdo1",
> +};
> +
> +static const struct mtk_mmsys_match_data mt8195_mmsys_match_data = {
> + .num_drv_data = 2,
> + .drv_data = {
> + &mt8195_vdosys0_driver_data,
> + &mt8195_vdosys1_driver_data,
> + },
> +};
> +
> static const struct mtk_mmsys_driver_data mt8365_mmsys_driver_data = {
> .clk_driver = "clk-mt8365-mm",
> .routes = mt8365_mmsys_routing_table,
> .num_routes = ARRAY_SIZE(mt8365_mmsys_routing_table),
> };
>
> +static const struct mtk_mmsys_match_data mt8365_mmsys_match_data = {
> + .num_drv_data = 1,
> + .drv_data = {
> + &mt8365_mmsys_driver_data,
> + },
> +};
> +
> struct mtk_mmsys {
> void __iomem *regs;
> const struct mtk_mmsys_driver_data *data;
> spinlock_t lock; /* protects mmsys_sw_rst_b reg */
> struct reset_controller_dev rcdev;
> + phys_addr_t io_start;
> };
>
> +static int mtk_mmsys_find_match_drvdata(struct mtk_mmsys *mmsys,
> + const struct mtk_mmsys_match_data *match)
> +{
> + int i;
> +
> + for (i = 0; i < match->num_drv_data; i++)
> + if (mmsys->io_start == match->drv_data[i]->io_start)
> + return i;
> +
> + return -EINVAL;
> +}
> +
> void mtk_mmsys_ddp_connect(struct device *dev,
> enum mtk_ddp_comp_id cur,
> enum mtk_ddp_comp_id next)
> @@ -179,7 +283,9 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
> struct device *dev = &pdev->dev;
> struct platform_device *clks;
> struct platform_device *drm;
> + const struct mtk_mmsys_match_data *match_data;
> struct mtk_mmsys *mmsys;
> + struct resource *res;
> int ret;
>
> mmsys = devm_kzalloc(dev, sizeof(*mmsys), GFP_KERNEL);
> @@ -205,7 +311,27 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
> return ret;
> }
>
> - mmsys->data = of_device_get_match_data(&pdev->dev);
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + if (!res) {
> + dev_err(dev, "Couldn't get mmsys resource\n");
> + return -EINVAL;
> + }
> + mmsys->io_start = res->start;
> +
> + match_data = of_device_get_match_data(dev);
> + if (match_data->num_drv_data > 1) {
> + /* This SoC has multiple mmsys channels */
> + ret = mtk_mmsys_find_match_drvdata(mmsys, match_data);
> + if (ret < 0) {
> + dev_err(dev, "Couldn't get match driver data\n");
> + return ret;
> + }
> + mmsys->data = match_data->drv_data[ret];
> + } else {
> + dev_dbg(dev, "Using single mmsys channel\n");
> + mmsys->data = match_data->drv_data[0];
> + }
> +
> platform_set_drvdata(pdev, mmsys);
>
> clks = platform_device_register_data(&pdev->dev, mmsys->data->clk_driver,
> @@ -226,43 +352,47 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
> static const struct of_device_id of_match_mtk_mmsys[] = {
> {
> .compatible = "mediatek,mt2701-mmsys",
> - .data = &mt2701_mmsys_driver_data,
> + .data = &mt2701_mmsys_match_data,
> },
> {
> .compatible = "mediatek,mt2712-mmsys",
> - .data = &mt2712_mmsys_driver_data,
> + .data = &mt2712_mmsys_match_data,
> },
> {
> .compatible = "mediatek,mt6779-mmsys",
> - .data = &mt6779_mmsys_driver_data,
> + .data = &mt6779_mmsys_match_data,
> },
> {
> .compatible = "mediatek,mt6797-mmsys",
> - .data = &mt6797_mmsys_driver_data,
> + .data = &mt6797_mmsys_match_data,
> },
> {
> .compatible = "mediatek,mt8167-mmsys",
> - .data = &mt8167_mmsys_driver_data,
> + .data = &mt8167_mmsys_match_data,
> },
> {
> .compatible = "mediatek,mt8173-mmsys",
> - .data = &mt8173_mmsys_driver_data,
> + .data = &mt8173_mmsys_match_data,
> },
> {
> .compatible = "mediatek,mt8183-mmsys",
> - .data = &mt8183_mmsys_driver_data,
> + .data = &mt8183_mmsys_match_data,
> },
> {
> .compatible = "mediatek,mt8186-mmsys",
> - .data = &mt8186_mmsys_driver_data,
> + .data = &mt8186_mmsys_match_data,
> },
> {
> .compatible = "mediatek,mt8192-mmsys",
> - .data = &mt8192_mmsys_driver_data,
> + .data = &mt8192_mmsys_match_data,
> + },
> + {
> + .compatible = "mediatek,mt8195-mmsys",
> + .data = &mt8195_mmsys_match_data,
> },
> {
> .compatible = "mediatek,mt8365-mmsys",
> - .data = &mt8365_mmsys_driver_data,
> + .data = &mt8365_mmsys_match_data,
> },
> { }
> };
> diff --git a/drivers/soc/mediatek/mtk-mmsys.h b/drivers/soc/mediatek/mtk-mmsys.h
> index 77f37f8c715b..f01ba206481d 100644
> --- a/drivers/soc/mediatek/mtk-mmsys.h
> +++ b/drivers/soc/mediatek/mtk-mmsys.h
> @@ -87,12 +87,18 @@ struct mtk_mmsys_routes {
> };
>
> struct mtk_mmsys_driver_data {
> + const resource_size_t io_start;
> const char *clk_driver;
> const struct mtk_mmsys_routes *routes;
> const unsigned int num_routes;
> const u16 sw0_rst_offset;
> };
>
> +struct mtk_mmsys_match_data {
> + unsigned short num_drv_data;
> + const struct mtk_mmsys_driver_data *drv_data[];
> +};
> +
> /*
> * Routes in mt8173, mt2701, mt2712 are different. That means
> * in the same register address, it controls different input/output
> diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
> index 4bba275e235a..cff5c9adbf46 100644
> --- a/include/linux/soc/mediatek/mtk-mmsys.h
> +++ b/include/linux/soc/mediatek/mtk-mmsys.h
> @@ -17,13 +17,24 @@ enum mtk_ddp_comp_id {
> DDP_COMPONENT_COLOR0,
> DDP_COMPONENT_COLOR1,
> DDP_COMPONENT_DITHER,
> + DDP_COMPONENT_DITHER1,
> + DDP_COMPONENT_DP_INTF0,
> + DDP_COMPONENT_DP_INTF1,
> DDP_COMPONENT_DPI0,
> DDP_COMPONENT_DPI1,
> + DDP_COMPONENT_DSC0,
> + DDP_COMPONENT_DSC1,
> DDP_COMPONENT_DSI0,
> DDP_COMPONENT_DSI1,
> DDP_COMPONENT_DSI2,
> DDP_COMPONENT_DSI3,
> DDP_COMPONENT_GAMMA,
> + DDP_COMPONENT_MERGE0,
> + DDP_COMPONENT_MERGE1,
> + DDP_COMPONENT_MERGE2,
> + DDP_COMPONENT_MERGE3,
> + DDP_COMPONENT_MERGE4,
> + DDP_COMPONENT_MERGE5,
> DDP_COMPONENT_OD0,
> DDP_COMPONENT_OD1,
> DDP_COMPONENT_OVL0,
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [PATCH v20 1/8] soc: mediatek: add mtk-mmsys support for mt8195 vdosys0
@ 2022-04-22 12:28 ` Matthias Brugger
0 siblings, 0 replies; 110+ messages in thread
From: Matthias Brugger @ 2022-04-22 12:28 UTC (permalink / raw)
To: jason-jh.lin, Chun-Kuang Hu, AngeloGioacchino Del Regno
Cc: CK Hu, Nancy Lin, Singo Chang, devicetree, linux-kernel,
dri-devel, linux-mediatek, linux-arm-kernel,
Project_Global_Chrome_Upstream_Group
On 19/04/2022 11:41, jason-jh.lin wrote:
> 1. Add mt8195 mmsys compatible for 2 vdosys.
> 2. Add io_start into each driver data of mt8195 vdosys.
> 3. Add get match data function to identify mmsys by io_start.
> 4. Add mt8195 routing table settings of vdosys0.
>
> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
I'm not very happy with the approach of testing against the reg property to
decide which version of the two mmsys devices we are probing. I think a better
approach would be, if we would have added some mediatek specific ID to the
device tree binding (or use a two compatibles?).
But as we are at v20 I think it wouldn't be fair to ask for such an instrusive
change. So I'll take this patch now, but maybe we can discuss if we can't do
better in a follow-up patch. Especially I don't think it's a good approach to
check for the io_start in the DRM driver. Couldn't we pass the information about
which of the two mmsys blocks we are calling from through the mediatek-drm
platform device spefic data?
I also had a look into the vdosys1 series to better understand why we need to do
things as we do them. But honestly I wasn't able to really understand the
implication of the patch that adds 'multi mmsys support' [1]. For this looks
like a several patches that got squashed into one. But as I don't have to
maintain that it is not my call to complain, the patch has the needed reviews.
For this patch, now applied to v5.18-next/soc
Thanks for all people implicated.
Regards,
Matthias
[1]
https://patchwork.kernel.org/project/linux-mediatek/patch/20220416020749.29010-19-nancy.lin@mediatek.com/
> ---
> Based on series [1]
>
> [1] MediaTek MT8195 display binding
> - https://patchwork.ozlabs.org/project/devicetree-bindings/list/?series=295669
> ---
> drivers/soc/mediatek/mt8195-mmsys.h | 370 +++++++++++++++++++++++++
> drivers/soc/mediatek/mtk-mmsys.c | 152 +++++++++-
> drivers/soc/mediatek/mtk-mmsys.h | 6 +
> include/linux/soc/mediatek/mtk-mmsys.h | 11 +
> 4 files changed, 528 insertions(+), 11 deletions(-)
> create mode 100644 drivers/soc/mediatek/mt8195-mmsys.h
>
> diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h
> new file mode 100644
> index 000000000000..13ab0ab64396
> --- /dev/null
> +++ b/drivers/soc/mediatek/mt8195-mmsys.h
> @@ -0,0 +1,370 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +
> +#ifndef __SOC_MEDIATEK_MT8195_MMSYS_H
> +#define __SOC_MEDIATEK_MT8195_MMSYS_H
> +
> +#define MT8195_VDO0_OVL_MOUT_EN 0xf14
> +#define MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0 BIT(0)
> +#define MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0 BIT(1)
> +#define MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1 BIT(2)
> +#define MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1 BIT(4)
> +#define MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1 BIT(5)
> +#define MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0 BIT(6)
> +
> +#define MT8195_VDO0_SEL_IN 0xf34
> +#define MT8195_SEL_IN_VPP_MERGE_FROM_MASK GENMASK(1, 0)
> +#define MT8195_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT (0 << 0)
> +#define MT8195_SEL_IN_VPP_MERGE_FROM_DISP_DITHER1 (1 << 0)
> +#define MT8195_SEL_IN_VPP_MERGE_FROM_VDO1_VIRTUAL0 (2 << 0)
> +#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK GENMASK(4, 4)
> +#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0 (0 << 4)
> +#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_VPP_MERGE (1 << 4)
> +#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_MASK GENMASK(5, 5)
> +#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_DISP_DITHER1 (0 << 5)
> +#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_VPP_MERGE (1 << 5)
> +#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK GENMASK(8, 8)
> +#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE (0 << 8)
> +#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT (1 << 8)
> +#define MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK GENMASK(9, 9)
> +#define MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT (0 << 9)
> +#define MT8195_SEL_IN_DP_INTF0_FROM_MASK GENMASK(13, 12)
> +#define MT8195_SEL_IN_DP_INTF0_FROM_DSC_WRAP1_OUT (0 << 0)
> +#define MT8195_SEL_IN_DP_INTF0_FROM_VPP_MERGE (1 << 12)
> +#define MT8195_SEL_IN_DP_INTF0_FROM_VDO1_VIRTUAL0 (2 << 12)
> +#define MT8195_SEL_IN_DSI0_FROM_MASK GENMASK(16, 16)
> +#define MT8195_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT (0 << 16)
> +#define MT8195_SEL_IN_DSI0_FROM_DISP_DITHER0 (1 << 16)
> +#define MT8195_SEL_IN_DSI1_FROM_MASK GENMASK(17, 17)
> +#define MT8195_SEL_IN_DSI1_FROM_DSC_WRAP1_OUT (0 << 17)
> +#define MT8195_SEL_IN_DSI1_FROM_VPP_MERGE (1 << 17)
> +#define MT8195_SEL_IN_DISP_WDMA1_FROM_MASK GENMASK(20, 20)
> +#define MT8195_SEL_IN_DISP_WDMA1_FROM_DISP_OVL1 (0 << 20)
> +#define MT8195_SEL_IN_DISP_WDMA1_FROM_VPP_MERGE (1 << 20)
> +#define MT8195_SEL_IN_DSC_WRAP1_FROM_MASK GENMASK(21, 21)
> +#define MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN (0 << 21)
> +#define MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1 (1 << 21)
> +#define MT8195_SEL_IN_DISP_WDMA0_FROM_MASK GENMASK(22, 22)
> +#define MT8195_SEL_IN_DISP_WDMA0_FROM_DISP_OVL0 (0 << 22)
> +
> +#define MT8195_VDO0_SEL_OUT 0xf38
> +#define MT8195_SOUT_DISP_DITHER0_TO_MASK BIT(0)
> +#define MT8195_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN (0 << 0)
> +#define MT8195_SOUT_DISP_DITHER0_TO_DSI0 (1 << 0)
> +#define MT8195_SOUT_DISP_DITHER1_TO_MASK GENMASK(2, 1)
> +#define MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_IN (0 << 1)
> +#define MT8195_SOUT_DISP_DITHER1_TO_VPP_MERGE (1 << 1)
> +#define MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT (2 << 1)
> +#define MT8195_SOUT_VDO1_VIRTUAL0_TO_MASK GENMASK(4, 4)
> +#define MT8195_SOUT_VDO1_VIRTUAL0_TO_VPP_MERGE (0 << 4)
> +#define MT8195_SOUT_VDO1_VIRTUAL0_TO_DP_INTF0 (1 << 4)
> +#define MT8195_SOUT_VPP_MERGE_TO_MASK GENMASK(10, 8)
> +#define MT8195_SOUT_VPP_MERGE_TO_DSI1 (0 << 8)
> +#define MT8195_SOUT_VPP_MERGE_TO_DP_INTF0 (1 << 8)
> +#define MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0 (2 << 8)
> +#define MT8195_SOUT_VPP_MERGE_TO_DISP_WDMA1 (3 << 8)
> +#define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP0_IN (4 << 8)
> +#define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN_MASK GENMASK(11, 11)
> +#define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN (0 << 11)
> +#define MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK GENMASK(13, 12)
> +#define MT8195_SOUT_DSC_WRAP0_OUT_TO_DSI0 (0 << 12)
> +#define MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0 (1 << 12)
> +#define MT8195_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE (2 << 12)
> +#define MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK GENMASK(17, 16)
> +#define MT8195_SOUT_DSC_WRAP1_OUT_TO_DSI1 (0 << 16)
> +#define MT8195_SOUT_DSC_WRAP1_OUT_TO_DP_INTF0 (1 << 16)
> +#define MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0 (2 << 16)
> +#define MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE (3 << 16)
> +
> +static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
> + {
> + DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
> + MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0,
> + MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0
> + }, {
> + DDP_COMPONENT_OVL0, DDP_COMPONENT_WDMA0,
> + MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0,
> + MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0
> + }, {
> + DDP_COMPONENT_OVL0, DDP_COMPONENT_OVL1,
> + MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1,
> + MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1
> + }, {
> + DDP_COMPONENT_OVL1, DDP_COMPONENT_RDMA1,
> + MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1,
> + MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1
> + }, {
> + DDP_COMPONENT_OVL1, DDP_COMPONENT_WDMA1,
> + MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1,
> + MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1
> + }, {
> + DDP_COMPONENT_OVL1, DDP_COMPONENT_OVL0,
> + MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0,
> + MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0
> + }, {
> + DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK,
> + MT8195_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT
> + }, {
> + DDP_COMPONENT_DITHER1, DDP_COMPONENT_MERGE0,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK,
> + MT8195_SEL_IN_VPP_MERGE_FROM_DISP_DITHER1
> + }, {
> + DDP_COMPONENT_MERGE5, DDP_COMPONENT_MERGE0,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK,
> + MT8195_SEL_IN_VPP_MERGE_FROM_VDO1_VIRTUAL0
> + }, {
> + DDP_COMPONENT_DITHER, DDP_COMPONENT_DSC0,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK,
> + MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0
> + }, {
> + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC0,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK,
> + MT8195_SEL_IN_DSC_WRAP0_IN_FROM_VPP_MERGE
> + }, {
> + DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSC1,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_IN_FROM_MASK,
> + MT8195_SEL_IN_DSC_WRAP1_IN_FROM_DISP_DITHER1
> + }, {
> + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC1,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_IN_FROM_MASK,
> + MT8195_SEL_IN_DSC_WRAP1_IN_FROM_VPP_MERGE
> + }, {
> + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF1,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
> + MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE
> + }, {
> + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI0,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
> + MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE
> + }, {
> + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI1,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
> + MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE
> + }, {
> + DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF1,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
> + MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT
> + }, {
> + DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI0,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
> + MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT
> + }, {
> + DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI1,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
> + MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT
> + }, {
> + DDP_COMPONENT_DSC0, DDP_COMPONENT_DP_INTF1,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK,
> + MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT
> + }, {
> + DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI0,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK,
> + MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT
> + }, {
> + DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI1,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK,
> + MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT
> + }, {
> + DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF0,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_MASK,
> + MT8195_SEL_IN_DP_INTF0_FROM_DSC_WRAP1_OUT
> + }, {
> + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF0,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_MASK,
> + MT8195_SEL_IN_DP_INTF0_FROM_VPP_MERGE
> + }, {
> + DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF0,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_MASK,
> + MT8195_SEL_IN_DP_INTF0_FROM_VDO1_VIRTUAL0
> + }, {
> + DDP_COMPONENT_DSC0, DDP_COMPONENT_DSI0,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI0_FROM_MASK,
> + MT8195_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT
> + }, {
> + DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI0_FROM_MASK,
> + MT8195_SEL_IN_DSI0_FROM_DISP_DITHER0
> + }, {
> + DDP_COMPONENT_DSC1, DDP_COMPONENT_DSI1,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI1_FROM_MASK,
> + MT8195_SEL_IN_DSI1_FROM_DSC_WRAP1_OUT
> + }, {
> + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSI1,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI1_FROM_MASK,
> + MT8195_SEL_IN_DSI1_FROM_VPP_MERGE
> + }, {
> + DDP_COMPONENT_OVL1, DDP_COMPONENT_WDMA1,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA1_FROM_MASK,
> + MT8195_SEL_IN_DISP_WDMA1_FROM_DISP_OVL1
> + }, {
> + DDP_COMPONENT_MERGE0, DDP_COMPONENT_WDMA1,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA1_FROM_MASK,
> + MT8195_SEL_IN_DISP_WDMA1_FROM_VPP_MERGE
> + }, {
> + DDP_COMPONENT_DSC1, DDP_COMPONENT_DSI1,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
> + MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
> + }, {
> + DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF0,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
> + MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
> + }, {
> + DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF1,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
> + MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
> + }, {
> + DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI0,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
> + MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
> + }, {
> + DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI1,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
> + MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
> + }, {
> + DDP_COMPONENT_DSC1, DDP_COMPONENT_MERGE0,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
> + MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
> + }, {
> + DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSI1,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
> + MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1
> + }, {
> + DDP_COMPONENT_DITHER1, DDP_COMPONENT_DP_INTF0,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
> + MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1
> + }, {
> + DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI0,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
> + MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1
> + }, {
> + DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI1,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
> + MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1
> + }, {
> + DDP_COMPONENT_OVL0, DDP_COMPONENT_WDMA0,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA0_FROM_MASK,
> + MT8195_SEL_IN_DISP_WDMA0_FROM_DISP_OVL0
> + }, {
> + DDP_COMPONENT_DITHER, DDP_COMPONENT_DSC0,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER0_TO_MASK,
> + MT8195_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN
> + }, {
> + DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER0_TO_MASK,
> + MT8195_SOUT_DISP_DITHER0_TO_DSI0
> + }, {
> + DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSC1,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
> + MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_IN
> + }, {
> + DDP_COMPONENT_DITHER1, DDP_COMPONENT_MERGE0,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
> + MT8195_SOUT_DISP_DITHER1_TO_VPP_MERGE
> + }, {
> + DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSI1,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
> + MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT
> + }, {
> + DDP_COMPONENT_DITHER1, DDP_COMPONENT_DP_INTF0,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
> + MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT
> + }, {
> + DDP_COMPONENT_DITHER1, DDP_COMPONENT_DP_INTF1,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
> + MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT
> + }, {
> + DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI0,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
> + MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT
> + }, {
> + DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI1,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
> + MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT
> + }, {
> + DDP_COMPONENT_MERGE5, DDP_COMPONENT_MERGE0,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_VDO1_VIRTUAL0_TO_MASK,
> + MT8195_SOUT_VDO1_VIRTUAL0_TO_VPP_MERGE
> + }, {
> + DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF0,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_VDO1_VIRTUAL0_TO_MASK,
> + MT8195_SOUT_VDO1_VIRTUAL0_TO_DP_INTF0
> + }, {
> + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSI1,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
> + MT8195_SOUT_VPP_MERGE_TO_DSI1
> + }, {
> + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF0,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
> + MT8195_SOUT_VPP_MERGE_TO_DP_INTF0
> + }, {
> + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF1,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
> + MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0
> + }, {
> + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI0,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
> + MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0
> + }, {
> + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI1,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
> + MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0
> + }, {
> + DDP_COMPONENT_MERGE0, DDP_COMPONENT_WDMA1,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
> + MT8195_SOUT_VPP_MERGE_TO_DISP_WDMA1
> + }, {
> + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC0,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
> + MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP0_IN
> + }, {
> + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC1,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN_MASK,
> + MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN
> + }, {
> + DDP_COMPONENT_DSC0, DDP_COMPONENT_DSI0,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
> + MT8195_SOUT_DSC_WRAP0_OUT_TO_DSI0
> + }, {
> + DDP_COMPONENT_DSC0, DDP_COMPONENT_DP_INTF1,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
> + MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0
> + }, {
> + DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI0,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
> + MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0
> + }, {
> + DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI1,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
> + MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0
> + }, {
> + DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
> + MT8195_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE
> + }, {
> + DDP_COMPONENT_DSC1, DDP_COMPONENT_DSI1,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
> + MT8195_SOUT_DSC_WRAP1_OUT_TO_DSI1
> + }, {
> + DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF0,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
> + MT8195_SOUT_DSC_WRAP1_OUT_TO_DP_INTF0
> + }, {
> + DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF1,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
> + MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0
> + }, {
> + DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI0,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
> + MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0
> + }, {
> + DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI1,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
> + MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0
> + }, {
> + DDP_COMPONENT_DSC1, DDP_COMPONENT_MERGE0,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
> + MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE
> + }
> +};
> +
> +#endif /* __SOC_MEDIATEK_MT8195_MMSYS_H */
> diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
> index 4fc4c2c9ea20..548efed8dc1c 100644
> --- a/drivers/soc/mediatek/mtk-mmsys.c
> +++ b/drivers/soc/mediatek/mtk-mmsys.c
> @@ -17,6 +17,7 @@
> #include "mt8183-mmsys.h"
> #include "mt8186-mmsys.h"
> #include "mt8192-mmsys.h"
> +#include "mt8195-mmsys.h"
> #include "mt8365-mmsys.h"
>
> static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
> @@ -25,26 +26,61 @@ static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
> .num_routes = ARRAY_SIZE(mmsys_default_routing_table),
> };
>
> +static const struct mtk_mmsys_match_data mt2701_mmsys_match_data = {
> + .num_drv_data = 1,
> + .drv_data = {
> + &mt2701_mmsys_driver_data,
> + },
> +};
> +
> static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = {
> .clk_driver = "clk-mt2712-mm",
> .routes = mmsys_default_routing_table,
> .num_routes = ARRAY_SIZE(mmsys_default_routing_table),
> };
>
> +static const struct mtk_mmsys_match_data mt2712_mmsys_match_data = {
> + .num_drv_data = 1,
> + .drv_data = {
> + &mt2712_mmsys_driver_data,
> + },
> +};
> +
> static const struct mtk_mmsys_driver_data mt6779_mmsys_driver_data = {
> .clk_driver = "clk-mt6779-mm",
> };
>
> +static const struct mtk_mmsys_match_data mt6779_mmsys_match_data = {
> + .num_drv_data = 1,
> + .drv_data = {
> + &mt6779_mmsys_driver_data,
> + },
> +};
> +
> static const struct mtk_mmsys_driver_data mt6797_mmsys_driver_data = {
> .clk_driver = "clk-mt6797-mm",
> };
>
> +static const struct mtk_mmsys_match_data mt6797_mmsys_match_data = {
> + .num_drv_data = 1,
> + .drv_data = {
> + &mt6797_mmsys_driver_data,
> + },
> +};
> +
> static const struct mtk_mmsys_driver_data mt8167_mmsys_driver_data = {
> .clk_driver = "clk-mt8167-mm",
> .routes = mt8167_mmsys_routing_table,
> .num_routes = ARRAY_SIZE(mt8167_mmsys_routing_table),
> };
>
> +static const struct mtk_mmsys_match_data mt8167_mmsys_match_data = {
> + .num_drv_data = 1,
> + .drv_data = {
> + &mt8167_mmsys_driver_data,
> + },
> +};
> +
> static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
> .clk_driver = "clk-mt8173-mm",
> .routes = mmsys_default_routing_table,
> @@ -52,6 +88,13 @@ static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
> .sw0_rst_offset = MT8183_MMSYS_SW0_RST_B,
> };
>
> +static const struct mtk_mmsys_match_data mt8173_mmsys_match_data = {
> + .num_drv_data = 1,
> + .drv_data = {
> + &mt8173_mmsys_driver_data,
> + },
> +};
> +
> static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
> .clk_driver = "clk-mt8183-mm",
> .routes = mmsys_mt8183_routing_table,
> @@ -59,6 +102,13 @@ static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
> .sw0_rst_offset = MT8183_MMSYS_SW0_RST_B,
> };
>
> +static const struct mtk_mmsys_match_data mt8183_mmsys_match_data = {
> + .num_drv_data = 1,
> + .drv_data = {
> + &mt8183_mmsys_driver_data,
> + },
> +};
> +
> static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = {
> .clk_driver = "clk-mt8186-mm",
> .routes = mmsys_mt8186_routing_table,
> @@ -66,25 +116,79 @@ static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = {
> .sw0_rst_offset = MT8186_MMSYS_SW0_RST_B,
> };
>
> +static const struct mtk_mmsys_match_data mt8186_mmsys_match_data = {
> + .num_drv_data = 1,
> + .drv_data = {
> + &mt8186_mmsys_driver_data,
> + },
> +};
> +
> static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
> .clk_driver = "clk-mt8192-mm",
> .routes = mmsys_mt8192_routing_table,
> .num_routes = ARRAY_SIZE(mmsys_mt8192_routing_table),
> };
>
> +static const struct mtk_mmsys_match_data mt8192_mmsys_match_data = {
> + .num_drv_data = 1,
> + .drv_data = {
> + &mt8192_mmsys_driver_data,
> + },
> +};
> +
> +static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = {
> + .io_start = 0x1c01a000,
> + .clk_driver = "clk-mt8195-vdo0",
> + .routes = mmsys_mt8195_routing_table,
> + .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
> +};
> +
> +static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
> + .io_start = 0x1c100000,
> + .clk_driver = "clk-mt8195-vdo1",
> +};
> +
> +static const struct mtk_mmsys_match_data mt8195_mmsys_match_data = {
> + .num_drv_data = 2,
> + .drv_data = {
> + &mt8195_vdosys0_driver_data,
> + &mt8195_vdosys1_driver_data,
> + },
> +};
> +
> static const struct mtk_mmsys_driver_data mt8365_mmsys_driver_data = {
> .clk_driver = "clk-mt8365-mm",
> .routes = mt8365_mmsys_routing_table,
> .num_routes = ARRAY_SIZE(mt8365_mmsys_routing_table),
> };
>
> +static const struct mtk_mmsys_match_data mt8365_mmsys_match_data = {
> + .num_drv_data = 1,
> + .drv_data = {
> + &mt8365_mmsys_driver_data,
> + },
> +};
> +
> struct mtk_mmsys {
> void __iomem *regs;
> const struct mtk_mmsys_driver_data *data;
> spinlock_t lock; /* protects mmsys_sw_rst_b reg */
> struct reset_controller_dev rcdev;
> + phys_addr_t io_start;
> };
>
> +static int mtk_mmsys_find_match_drvdata(struct mtk_mmsys *mmsys,
> + const struct mtk_mmsys_match_data *match)
> +{
> + int i;
> +
> + for (i = 0; i < match->num_drv_data; i++)
> + if (mmsys->io_start == match->drv_data[i]->io_start)
> + return i;
> +
> + return -EINVAL;
> +}
> +
> void mtk_mmsys_ddp_connect(struct device *dev,
> enum mtk_ddp_comp_id cur,
> enum mtk_ddp_comp_id next)
> @@ -179,7 +283,9 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
> struct device *dev = &pdev->dev;
> struct platform_device *clks;
> struct platform_device *drm;
> + const struct mtk_mmsys_match_data *match_data;
> struct mtk_mmsys *mmsys;
> + struct resource *res;
> int ret;
>
> mmsys = devm_kzalloc(dev, sizeof(*mmsys), GFP_KERNEL);
> @@ -205,7 +311,27 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
> return ret;
> }
>
> - mmsys->data = of_device_get_match_data(&pdev->dev);
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + if (!res) {
> + dev_err(dev, "Couldn't get mmsys resource\n");
> + return -EINVAL;
> + }
> + mmsys->io_start = res->start;
> +
> + match_data = of_device_get_match_data(dev);
> + if (match_data->num_drv_data > 1) {
> + /* This SoC has multiple mmsys channels */
> + ret = mtk_mmsys_find_match_drvdata(mmsys, match_data);
> + if (ret < 0) {
> + dev_err(dev, "Couldn't get match driver data\n");
> + return ret;
> + }
> + mmsys->data = match_data->drv_data[ret];
> + } else {
> + dev_dbg(dev, "Using single mmsys channel\n");
> + mmsys->data = match_data->drv_data[0];
> + }
> +
> platform_set_drvdata(pdev, mmsys);
>
> clks = platform_device_register_data(&pdev->dev, mmsys->data->clk_driver,
> @@ -226,43 +352,47 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
> static const struct of_device_id of_match_mtk_mmsys[] = {
> {
> .compatible = "mediatek,mt2701-mmsys",
> - .data = &mt2701_mmsys_driver_data,
> + .data = &mt2701_mmsys_match_data,
> },
> {
> .compatible = "mediatek,mt2712-mmsys",
> - .data = &mt2712_mmsys_driver_data,
> + .data = &mt2712_mmsys_match_data,
> },
> {
> .compatible = "mediatek,mt6779-mmsys",
> - .data = &mt6779_mmsys_driver_data,
> + .data = &mt6779_mmsys_match_data,
> },
> {
> .compatible = "mediatek,mt6797-mmsys",
> - .data = &mt6797_mmsys_driver_data,
> + .data = &mt6797_mmsys_match_data,
> },
> {
> .compatible = "mediatek,mt8167-mmsys",
> - .data = &mt8167_mmsys_driver_data,
> + .data = &mt8167_mmsys_match_data,
> },
> {
> .compatible = "mediatek,mt8173-mmsys",
> - .data = &mt8173_mmsys_driver_data,
> + .data = &mt8173_mmsys_match_data,
> },
> {
> .compatible = "mediatek,mt8183-mmsys",
> - .data = &mt8183_mmsys_driver_data,
> + .data = &mt8183_mmsys_match_data,
> },
> {
> .compatible = "mediatek,mt8186-mmsys",
> - .data = &mt8186_mmsys_driver_data,
> + .data = &mt8186_mmsys_match_data,
> },
> {
> .compatible = "mediatek,mt8192-mmsys",
> - .data = &mt8192_mmsys_driver_data,
> + .data = &mt8192_mmsys_match_data,
> + },
> + {
> + .compatible = "mediatek,mt8195-mmsys",
> + .data = &mt8195_mmsys_match_data,
> },
> {
> .compatible = "mediatek,mt8365-mmsys",
> - .data = &mt8365_mmsys_driver_data,
> + .data = &mt8365_mmsys_match_data,
> },
> { }
> };
> diff --git a/drivers/soc/mediatek/mtk-mmsys.h b/drivers/soc/mediatek/mtk-mmsys.h
> index 77f37f8c715b..f01ba206481d 100644
> --- a/drivers/soc/mediatek/mtk-mmsys.h
> +++ b/drivers/soc/mediatek/mtk-mmsys.h
> @@ -87,12 +87,18 @@ struct mtk_mmsys_routes {
> };
>
> struct mtk_mmsys_driver_data {
> + const resource_size_t io_start;
> const char *clk_driver;
> const struct mtk_mmsys_routes *routes;
> const unsigned int num_routes;
> const u16 sw0_rst_offset;
> };
>
> +struct mtk_mmsys_match_data {
> + unsigned short num_drv_data;
> + const struct mtk_mmsys_driver_data *drv_data[];
> +};
> +
> /*
> * Routes in mt8173, mt2701, mt2712 are different. That means
> * in the same register address, it controls different input/output
> diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
> index 4bba275e235a..cff5c9adbf46 100644
> --- a/include/linux/soc/mediatek/mtk-mmsys.h
> +++ b/include/linux/soc/mediatek/mtk-mmsys.h
> @@ -17,13 +17,24 @@ enum mtk_ddp_comp_id {
> DDP_COMPONENT_COLOR0,
> DDP_COMPONENT_COLOR1,
> DDP_COMPONENT_DITHER,
> + DDP_COMPONENT_DITHER1,
> + DDP_COMPONENT_DP_INTF0,
> + DDP_COMPONENT_DP_INTF1,
> DDP_COMPONENT_DPI0,
> DDP_COMPONENT_DPI1,
> + DDP_COMPONENT_DSC0,
> + DDP_COMPONENT_DSC1,
> DDP_COMPONENT_DSI0,
> DDP_COMPONENT_DSI1,
> DDP_COMPONENT_DSI2,
> DDP_COMPONENT_DSI3,
> DDP_COMPONENT_GAMMA,
> + DDP_COMPONENT_MERGE0,
> + DDP_COMPONENT_MERGE1,
> + DDP_COMPONENT_MERGE2,
> + DDP_COMPONENT_MERGE3,
> + DDP_COMPONENT_MERGE4,
> + DDP_COMPONENT_MERGE5,
> DDP_COMPONENT_OD0,
> DDP_COMPONENT_OD1,
> DDP_COMPONENT_OVL0,
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^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [PATCH v20 1/8] soc: mediatek: add mtk-mmsys support for mt8195 vdosys0
@ 2022-04-22 12:28 ` Matthias Brugger
0 siblings, 0 replies; 110+ messages in thread
From: Matthias Brugger @ 2022-04-22 12:28 UTC (permalink / raw)
To: jason-jh.lin, Chun-Kuang Hu, AngeloGioacchino Del Regno
Cc: devicetree, Singo Chang, linux-kernel, dri-devel,
Project_Global_Chrome_Upstream_Group, Nancy Lin, linux-mediatek,
linux-arm-kernel
On 19/04/2022 11:41, jason-jh.lin wrote:
> 1. Add mt8195 mmsys compatible for 2 vdosys.
> 2. Add io_start into each driver data of mt8195 vdosys.
> 3. Add get match data function to identify mmsys by io_start.
> 4. Add mt8195 routing table settings of vdosys0.
>
> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
I'm not very happy with the approach of testing against the reg property to
decide which version of the two mmsys devices we are probing. I think a better
approach would be, if we would have added some mediatek specific ID to the
device tree binding (or use a two compatibles?).
But as we are at v20 I think it wouldn't be fair to ask for such an instrusive
change. So I'll take this patch now, but maybe we can discuss if we can't do
better in a follow-up patch. Especially I don't think it's a good approach to
check for the io_start in the DRM driver. Couldn't we pass the information about
which of the two mmsys blocks we are calling from through the mediatek-drm
platform device spefic data?
I also had a look into the vdosys1 series to better understand why we need to do
things as we do them. But honestly I wasn't able to really understand the
implication of the patch that adds 'multi mmsys support' [1]. For this looks
like a several patches that got squashed into one. But as I don't have to
maintain that it is not my call to complain, the patch has the needed reviews.
For this patch, now applied to v5.18-next/soc
Thanks for all people implicated.
Regards,
Matthias
[1]
https://patchwork.kernel.org/project/linux-mediatek/patch/20220416020749.29010-19-nancy.lin@mediatek.com/
> ---
> Based on series [1]
>
> [1] MediaTek MT8195 display binding
> - https://patchwork.ozlabs.org/project/devicetree-bindings/list/?series=295669
> ---
> drivers/soc/mediatek/mt8195-mmsys.h | 370 +++++++++++++++++++++++++
> drivers/soc/mediatek/mtk-mmsys.c | 152 +++++++++-
> drivers/soc/mediatek/mtk-mmsys.h | 6 +
> include/linux/soc/mediatek/mtk-mmsys.h | 11 +
> 4 files changed, 528 insertions(+), 11 deletions(-)
> create mode 100644 drivers/soc/mediatek/mt8195-mmsys.h
>
> diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h
> new file mode 100644
> index 000000000000..13ab0ab64396
> --- /dev/null
> +++ b/drivers/soc/mediatek/mt8195-mmsys.h
> @@ -0,0 +1,370 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +
> +#ifndef __SOC_MEDIATEK_MT8195_MMSYS_H
> +#define __SOC_MEDIATEK_MT8195_MMSYS_H
> +
> +#define MT8195_VDO0_OVL_MOUT_EN 0xf14
> +#define MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0 BIT(0)
> +#define MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0 BIT(1)
> +#define MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1 BIT(2)
> +#define MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1 BIT(4)
> +#define MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1 BIT(5)
> +#define MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0 BIT(6)
> +
> +#define MT8195_VDO0_SEL_IN 0xf34
> +#define MT8195_SEL_IN_VPP_MERGE_FROM_MASK GENMASK(1, 0)
> +#define MT8195_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT (0 << 0)
> +#define MT8195_SEL_IN_VPP_MERGE_FROM_DISP_DITHER1 (1 << 0)
> +#define MT8195_SEL_IN_VPP_MERGE_FROM_VDO1_VIRTUAL0 (2 << 0)
> +#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK GENMASK(4, 4)
> +#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0 (0 << 4)
> +#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_VPP_MERGE (1 << 4)
> +#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_MASK GENMASK(5, 5)
> +#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_DISP_DITHER1 (0 << 5)
> +#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_VPP_MERGE (1 << 5)
> +#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK GENMASK(8, 8)
> +#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE (0 << 8)
> +#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT (1 << 8)
> +#define MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK GENMASK(9, 9)
> +#define MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT (0 << 9)
> +#define MT8195_SEL_IN_DP_INTF0_FROM_MASK GENMASK(13, 12)
> +#define MT8195_SEL_IN_DP_INTF0_FROM_DSC_WRAP1_OUT (0 << 0)
> +#define MT8195_SEL_IN_DP_INTF0_FROM_VPP_MERGE (1 << 12)
> +#define MT8195_SEL_IN_DP_INTF0_FROM_VDO1_VIRTUAL0 (2 << 12)
> +#define MT8195_SEL_IN_DSI0_FROM_MASK GENMASK(16, 16)
> +#define MT8195_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT (0 << 16)
> +#define MT8195_SEL_IN_DSI0_FROM_DISP_DITHER0 (1 << 16)
> +#define MT8195_SEL_IN_DSI1_FROM_MASK GENMASK(17, 17)
> +#define MT8195_SEL_IN_DSI1_FROM_DSC_WRAP1_OUT (0 << 17)
> +#define MT8195_SEL_IN_DSI1_FROM_VPP_MERGE (1 << 17)
> +#define MT8195_SEL_IN_DISP_WDMA1_FROM_MASK GENMASK(20, 20)
> +#define MT8195_SEL_IN_DISP_WDMA1_FROM_DISP_OVL1 (0 << 20)
> +#define MT8195_SEL_IN_DISP_WDMA1_FROM_VPP_MERGE (1 << 20)
> +#define MT8195_SEL_IN_DSC_WRAP1_FROM_MASK GENMASK(21, 21)
> +#define MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN (0 << 21)
> +#define MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1 (1 << 21)
> +#define MT8195_SEL_IN_DISP_WDMA0_FROM_MASK GENMASK(22, 22)
> +#define MT8195_SEL_IN_DISP_WDMA0_FROM_DISP_OVL0 (0 << 22)
> +
> +#define MT8195_VDO0_SEL_OUT 0xf38
> +#define MT8195_SOUT_DISP_DITHER0_TO_MASK BIT(0)
> +#define MT8195_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN (0 << 0)
> +#define MT8195_SOUT_DISP_DITHER0_TO_DSI0 (1 << 0)
> +#define MT8195_SOUT_DISP_DITHER1_TO_MASK GENMASK(2, 1)
> +#define MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_IN (0 << 1)
> +#define MT8195_SOUT_DISP_DITHER1_TO_VPP_MERGE (1 << 1)
> +#define MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT (2 << 1)
> +#define MT8195_SOUT_VDO1_VIRTUAL0_TO_MASK GENMASK(4, 4)
> +#define MT8195_SOUT_VDO1_VIRTUAL0_TO_VPP_MERGE (0 << 4)
> +#define MT8195_SOUT_VDO1_VIRTUAL0_TO_DP_INTF0 (1 << 4)
> +#define MT8195_SOUT_VPP_MERGE_TO_MASK GENMASK(10, 8)
> +#define MT8195_SOUT_VPP_MERGE_TO_DSI1 (0 << 8)
> +#define MT8195_SOUT_VPP_MERGE_TO_DP_INTF0 (1 << 8)
> +#define MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0 (2 << 8)
> +#define MT8195_SOUT_VPP_MERGE_TO_DISP_WDMA1 (3 << 8)
> +#define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP0_IN (4 << 8)
> +#define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN_MASK GENMASK(11, 11)
> +#define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN (0 << 11)
> +#define MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK GENMASK(13, 12)
> +#define MT8195_SOUT_DSC_WRAP0_OUT_TO_DSI0 (0 << 12)
> +#define MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0 (1 << 12)
> +#define MT8195_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE (2 << 12)
> +#define MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK GENMASK(17, 16)
> +#define MT8195_SOUT_DSC_WRAP1_OUT_TO_DSI1 (0 << 16)
> +#define MT8195_SOUT_DSC_WRAP1_OUT_TO_DP_INTF0 (1 << 16)
> +#define MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0 (2 << 16)
> +#define MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE (3 << 16)
> +
> +static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
> + {
> + DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
> + MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0,
> + MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0
> + }, {
> + DDP_COMPONENT_OVL0, DDP_COMPONENT_WDMA0,
> + MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0,
> + MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0
> + }, {
> + DDP_COMPONENT_OVL0, DDP_COMPONENT_OVL1,
> + MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1,
> + MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1
> + }, {
> + DDP_COMPONENT_OVL1, DDP_COMPONENT_RDMA1,
> + MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1,
> + MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1
> + }, {
> + DDP_COMPONENT_OVL1, DDP_COMPONENT_WDMA1,
> + MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1,
> + MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1
> + }, {
> + DDP_COMPONENT_OVL1, DDP_COMPONENT_OVL0,
> + MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0,
> + MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0
> + }, {
> + DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK,
> + MT8195_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT
> + }, {
> + DDP_COMPONENT_DITHER1, DDP_COMPONENT_MERGE0,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK,
> + MT8195_SEL_IN_VPP_MERGE_FROM_DISP_DITHER1
> + }, {
> + DDP_COMPONENT_MERGE5, DDP_COMPONENT_MERGE0,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK,
> + MT8195_SEL_IN_VPP_MERGE_FROM_VDO1_VIRTUAL0
> + }, {
> + DDP_COMPONENT_DITHER, DDP_COMPONENT_DSC0,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK,
> + MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0
> + }, {
> + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC0,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK,
> + MT8195_SEL_IN_DSC_WRAP0_IN_FROM_VPP_MERGE
> + }, {
> + DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSC1,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_IN_FROM_MASK,
> + MT8195_SEL_IN_DSC_WRAP1_IN_FROM_DISP_DITHER1
> + }, {
> + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC1,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_IN_FROM_MASK,
> + MT8195_SEL_IN_DSC_WRAP1_IN_FROM_VPP_MERGE
> + }, {
> + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF1,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
> + MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE
> + }, {
> + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI0,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
> + MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE
> + }, {
> + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI1,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
> + MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE
> + }, {
> + DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF1,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
> + MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT
> + }, {
> + DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI0,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
> + MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT
> + }, {
> + DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI1,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
> + MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT
> + }, {
> + DDP_COMPONENT_DSC0, DDP_COMPONENT_DP_INTF1,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK,
> + MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT
> + }, {
> + DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI0,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK,
> + MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT
> + }, {
> + DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI1,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK,
> + MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT
> + }, {
> + DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF0,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_MASK,
> + MT8195_SEL_IN_DP_INTF0_FROM_DSC_WRAP1_OUT
> + }, {
> + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF0,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_MASK,
> + MT8195_SEL_IN_DP_INTF0_FROM_VPP_MERGE
> + }, {
> + DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF0,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_MASK,
> + MT8195_SEL_IN_DP_INTF0_FROM_VDO1_VIRTUAL0
> + }, {
> + DDP_COMPONENT_DSC0, DDP_COMPONENT_DSI0,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI0_FROM_MASK,
> + MT8195_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT
> + }, {
> + DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI0_FROM_MASK,
> + MT8195_SEL_IN_DSI0_FROM_DISP_DITHER0
> + }, {
> + DDP_COMPONENT_DSC1, DDP_COMPONENT_DSI1,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI1_FROM_MASK,
> + MT8195_SEL_IN_DSI1_FROM_DSC_WRAP1_OUT
> + }, {
> + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSI1,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI1_FROM_MASK,
> + MT8195_SEL_IN_DSI1_FROM_VPP_MERGE
> + }, {
> + DDP_COMPONENT_OVL1, DDP_COMPONENT_WDMA1,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA1_FROM_MASK,
> + MT8195_SEL_IN_DISP_WDMA1_FROM_DISP_OVL1
> + }, {
> + DDP_COMPONENT_MERGE0, DDP_COMPONENT_WDMA1,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA1_FROM_MASK,
> + MT8195_SEL_IN_DISP_WDMA1_FROM_VPP_MERGE
> + }, {
> + DDP_COMPONENT_DSC1, DDP_COMPONENT_DSI1,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
> + MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
> + }, {
> + DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF0,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
> + MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
> + }, {
> + DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF1,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
> + MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
> + }, {
> + DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI0,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
> + MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
> + }, {
> + DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI1,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
> + MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
> + }, {
> + DDP_COMPONENT_DSC1, DDP_COMPONENT_MERGE0,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
> + MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
> + }, {
> + DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSI1,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
> + MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1
> + }, {
> + DDP_COMPONENT_DITHER1, DDP_COMPONENT_DP_INTF0,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
> + MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1
> + }, {
> + DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI0,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
> + MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1
> + }, {
> + DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI1,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
> + MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1
> + }, {
> + DDP_COMPONENT_OVL0, DDP_COMPONENT_WDMA0,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA0_FROM_MASK,
> + MT8195_SEL_IN_DISP_WDMA0_FROM_DISP_OVL0
> + }, {
> + DDP_COMPONENT_DITHER, DDP_COMPONENT_DSC0,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER0_TO_MASK,
> + MT8195_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN
> + }, {
> + DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER0_TO_MASK,
> + MT8195_SOUT_DISP_DITHER0_TO_DSI0
> + }, {
> + DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSC1,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
> + MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_IN
> + }, {
> + DDP_COMPONENT_DITHER1, DDP_COMPONENT_MERGE0,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
> + MT8195_SOUT_DISP_DITHER1_TO_VPP_MERGE
> + }, {
> + DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSI1,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
> + MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT
> + }, {
> + DDP_COMPONENT_DITHER1, DDP_COMPONENT_DP_INTF0,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
> + MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT
> + }, {
> + DDP_COMPONENT_DITHER1, DDP_COMPONENT_DP_INTF1,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
> + MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT
> + }, {
> + DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI0,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
> + MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT
> + }, {
> + DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI1,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
> + MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT
> + }, {
> + DDP_COMPONENT_MERGE5, DDP_COMPONENT_MERGE0,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_VDO1_VIRTUAL0_TO_MASK,
> + MT8195_SOUT_VDO1_VIRTUAL0_TO_VPP_MERGE
> + }, {
> + DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF0,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_VDO1_VIRTUAL0_TO_MASK,
> + MT8195_SOUT_VDO1_VIRTUAL0_TO_DP_INTF0
> + }, {
> + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSI1,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
> + MT8195_SOUT_VPP_MERGE_TO_DSI1
> + }, {
> + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF0,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
> + MT8195_SOUT_VPP_MERGE_TO_DP_INTF0
> + }, {
> + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF1,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
> + MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0
> + }, {
> + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI0,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
> + MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0
> + }, {
> + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI1,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
> + MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0
> + }, {
> + DDP_COMPONENT_MERGE0, DDP_COMPONENT_WDMA1,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
> + MT8195_SOUT_VPP_MERGE_TO_DISP_WDMA1
> + }, {
> + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC0,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
> + MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP0_IN
> + }, {
> + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC1,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN_MASK,
> + MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN
> + }, {
> + DDP_COMPONENT_DSC0, DDP_COMPONENT_DSI0,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
> + MT8195_SOUT_DSC_WRAP0_OUT_TO_DSI0
> + }, {
> + DDP_COMPONENT_DSC0, DDP_COMPONENT_DP_INTF1,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
> + MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0
> + }, {
> + DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI0,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
> + MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0
> + }, {
> + DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI1,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
> + MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0
> + }, {
> + DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
> + MT8195_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE
> + }, {
> + DDP_COMPONENT_DSC1, DDP_COMPONENT_DSI1,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
> + MT8195_SOUT_DSC_WRAP1_OUT_TO_DSI1
> + }, {
> + DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF0,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
> + MT8195_SOUT_DSC_WRAP1_OUT_TO_DP_INTF0
> + }, {
> + DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF1,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
> + MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0
> + }, {
> + DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI0,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
> + MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0
> + }, {
> + DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI1,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
> + MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0
> + }, {
> + DDP_COMPONENT_DSC1, DDP_COMPONENT_MERGE0,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
> + MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE
> + }
> +};
> +
> +#endif /* __SOC_MEDIATEK_MT8195_MMSYS_H */
> diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
> index 4fc4c2c9ea20..548efed8dc1c 100644
> --- a/drivers/soc/mediatek/mtk-mmsys.c
> +++ b/drivers/soc/mediatek/mtk-mmsys.c
> @@ -17,6 +17,7 @@
> #include "mt8183-mmsys.h"
> #include "mt8186-mmsys.h"
> #include "mt8192-mmsys.h"
> +#include "mt8195-mmsys.h"
> #include "mt8365-mmsys.h"
>
> static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
> @@ -25,26 +26,61 @@ static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
> .num_routes = ARRAY_SIZE(mmsys_default_routing_table),
> };
>
> +static const struct mtk_mmsys_match_data mt2701_mmsys_match_data = {
> + .num_drv_data = 1,
> + .drv_data = {
> + &mt2701_mmsys_driver_data,
> + },
> +};
> +
> static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = {
> .clk_driver = "clk-mt2712-mm",
> .routes = mmsys_default_routing_table,
> .num_routes = ARRAY_SIZE(mmsys_default_routing_table),
> };
>
> +static const struct mtk_mmsys_match_data mt2712_mmsys_match_data = {
> + .num_drv_data = 1,
> + .drv_data = {
> + &mt2712_mmsys_driver_data,
> + },
> +};
> +
> static const struct mtk_mmsys_driver_data mt6779_mmsys_driver_data = {
> .clk_driver = "clk-mt6779-mm",
> };
>
> +static const struct mtk_mmsys_match_data mt6779_mmsys_match_data = {
> + .num_drv_data = 1,
> + .drv_data = {
> + &mt6779_mmsys_driver_data,
> + },
> +};
> +
> static const struct mtk_mmsys_driver_data mt6797_mmsys_driver_data = {
> .clk_driver = "clk-mt6797-mm",
> };
>
> +static const struct mtk_mmsys_match_data mt6797_mmsys_match_data = {
> + .num_drv_data = 1,
> + .drv_data = {
> + &mt6797_mmsys_driver_data,
> + },
> +};
> +
> static const struct mtk_mmsys_driver_data mt8167_mmsys_driver_data = {
> .clk_driver = "clk-mt8167-mm",
> .routes = mt8167_mmsys_routing_table,
> .num_routes = ARRAY_SIZE(mt8167_mmsys_routing_table),
> };
>
> +static const struct mtk_mmsys_match_data mt8167_mmsys_match_data = {
> + .num_drv_data = 1,
> + .drv_data = {
> + &mt8167_mmsys_driver_data,
> + },
> +};
> +
> static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
> .clk_driver = "clk-mt8173-mm",
> .routes = mmsys_default_routing_table,
> @@ -52,6 +88,13 @@ static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
> .sw0_rst_offset = MT8183_MMSYS_SW0_RST_B,
> };
>
> +static const struct mtk_mmsys_match_data mt8173_mmsys_match_data = {
> + .num_drv_data = 1,
> + .drv_data = {
> + &mt8173_mmsys_driver_data,
> + },
> +};
> +
> static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
> .clk_driver = "clk-mt8183-mm",
> .routes = mmsys_mt8183_routing_table,
> @@ -59,6 +102,13 @@ static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
> .sw0_rst_offset = MT8183_MMSYS_SW0_RST_B,
> };
>
> +static const struct mtk_mmsys_match_data mt8183_mmsys_match_data = {
> + .num_drv_data = 1,
> + .drv_data = {
> + &mt8183_mmsys_driver_data,
> + },
> +};
> +
> static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = {
> .clk_driver = "clk-mt8186-mm",
> .routes = mmsys_mt8186_routing_table,
> @@ -66,25 +116,79 @@ static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = {
> .sw0_rst_offset = MT8186_MMSYS_SW0_RST_B,
> };
>
> +static const struct mtk_mmsys_match_data mt8186_mmsys_match_data = {
> + .num_drv_data = 1,
> + .drv_data = {
> + &mt8186_mmsys_driver_data,
> + },
> +};
> +
> static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
> .clk_driver = "clk-mt8192-mm",
> .routes = mmsys_mt8192_routing_table,
> .num_routes = ARRAY_SIZE(mmsys_mt8192_routing_table),
> };
>
> +static const struct mtk_mmsys_match_data mt8192_mmsys_match_data = {
> + .num_drv_data = 1,
> + .drv_data = {
> + &mt8192_mmsys_driver_data,
> + },
> +};
> +
> +static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = {
> + .io_start = 0x1c01a000,
> + .clk_driver = "clk-mt8195-vdo0",
> + .routes = mmsys_mt8195_routing_table,
> + .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
> +};
> +
> +static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
> + .io_start = 0x1c100000,
> + .clk_driver = "clk-mt8195-vdo1",
> +};
> +
> +static const struct mtk_mmsys_match_data mt8195_mmsys_match_data = {
> + .num_drv_data = 2,
> + .drv_data = {
> + &mt8195_vdosys0_driver_data,
> + &mt8195_vdosys1_driver_data,
> + },
> +};
> +
> static const struct mtk_mmsys_driver_data mt8365_mmsys_driver_data = {
> .clk_driver = "clk-mt8365-mm",
> .routes = mt8365_mmsys_routing_table,
> .num_routes = ARRAY_SIZE(mt8365_mmsys_routing_table),
> };
>
> +static const struct mtk_mmsys_match_data mt8365_mmsys_match_data = {
> + .num_drv_data = 1,
> + .drv_data = {
> + &mt8365_mmsys_driver_data,
> + },
> +};
> +
> struct mtk_mmsys {
> void __iomem *regs;
> const struct mtk_mmsys_driver_data *data;
> spinlock_t lock; /* protects mmsys_sw_rst_b reg */
> struct reset_controller_dev rcdev;
> + phys_addr_t io_start;
> };
>
> +static int mtk_mmsys_find_match_drvdata(struct mtk_mmsys *mmsys,
> + const struct mtk_mmsys_match_data *match)
> +{
> + int i;
> +
> + for (i = 0; i < match->num_drv_data; i++)
> + if (mmsys->io_start == match->drv_data[i]->io_start)
> + return i;
> +
> + return -EINVAL;
> +}
> +
> void mtk_mmsys_ddp_connect(struct device *dev,
> enum mtk_ddp_comp_id cur,
> enum mtk_ddp_comp_id next)
> @@ -179,7 +283,9 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
> struct device *dev = &pdev->dev;
> struct platform_device *clks;
> struct platform_device *drm;
> + const struct mtk_mmsys_match_data *match_data;
> struct mtk_mmsys *mmsys;
> + struct resource *res;
> int ret;
>
> mmsys = devm_kzalloc(dev, sizeof(*mmsys), GFP_KERNEL);
> @@ -205,7 +311,27 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
> return ret;
> }
>
> - mmsys->data = of_device_get_match_data(&pdev->dev);
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + if (!res) {
> + dev_err(dev, "Couldn't get mmsys resource\n");
> + return -EINVAL;
> + }
> + mmsys->io_start = res->start;
> +
> + match_data = of_device_get_match_data(dev);
> + if (match_data->num_drv_data > 1) {
> + /* This SoC has multiple mmsys channels */
> + ret = mtk_mmsys_find_match_drvdata(mmsys, match_data);
> + if (ret < 0) {
> + dev_err(dev, "Couldn't get match driver data\n");
> + return ret;
> + }
> + mmsys->data = match_data->drv_data[ret];
> + } else {
> + dev_dbg(dev, "Using single mmsys channel\n");
> + mmsys->data = match_data->drv_data[0];
> + }
> +
> platform_set_drvdata(pdev, mmsys);
>
> clks = platform_device_register_data(&pdev->dev, mmsys->data->clk_driver,
> @@ -226,43 +352,47 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
> static const struct of_device_id of_match_mtk_mmsys[] = {
> {
> .compatible = "mediatek,mt2701-mmsys",
> - .data = &mt2701_mmsys_driver_data,
> + .data = &mt2701_mmsys_match_data,
> },
> {
> .compatible = "mediatek,mt2712-mmsys",
> - .data = &mt2712_mmsys_driver_data,
> + .data = &mt2712_mmsys_match_data,
> },
> {
> .compatible = "mediatek,mt6779-mmsys",
> - .data = &mt6779_mmsys_driver_data,
> + .data = &mt6779_mmsys_match_data,
> },
> {
> .compatible = "mediatek,mt6797-mmsys",
> - .data = &mt6797_mmsys_driver_data,
> + .data = &mt6797_mmsys_match_data,
> },
> {
> .compatible = "mediatek,mt8167-mmsys",
> - .data = &mt8167_mmsys_driver_data,
> + .data = &mt8167_mmsys_match_data,
> },
> {
> .compatible = "mediatek,mt8173-mmsys",
> - .data = &mt8173_mmsys_driver_data,
> + .data = &mt8173_mmsys_match_data,
> },
> {
> .compatible = "mediatek,mt8183-mmsys",
> - .data = &mt8183_mmsys_driver_data,
> + .data = &mt8183_mmsys_match_data,
> },
> {
> .compatible = "mediatek,mt8186-mmsys",
> - .data = &mt8186_mmsys_driver_data,
> + .data = &mt8186_mmsys_match_data,
> },
> {
> .compatible = "mediatek,mt8192-mmsys",
> - .data = &mt8192_mmsys_driver_data,
> + .data = &mt8192_mmsys_match_data,
> + },
> + {
> + .compatible = "mediatek,mt8195-mmsys",
> + .data = &mt8195_mmsys_match_data,
> },
> {
> .compatible = "mediatek,mt8365-mmsys",
> - .data = &mt8365_mmsys_driver_data,
> + .data = &mt8365_mmsys_match_data,
> },
> { }
> };
> diff --git a/drivers/soc/mediatek/mtk-mmsys.h b/drivers/soc/mediatek/mtk-mmsys.h
> index 77f37f8c715b..f01ba206481d 100644
> --- a/drivers/soc/mediatek/mtk-mmsys.h
> +++ b/drivers/soc/mediatek/mtk-mmsys.h
> @@ -87,12 +87,18 @@ struct mtk_mmsys_routes {
> };
>
> struct mtk_mmsys_driver_data {
> + const resource_size_t io_start;
> const char *clk_driver;
> const struct mtk_mmsys_routes *routes;
> const unsigned int num_routes;
> const u16 sw0_rst_offset;
> };
>
> +struct mtk_mmsys_match_data {
> + unsigned short num_drv_data;
> + const struct mtk_mmsys_driver_data *drv_data[];
> +};
> +
> /*
> * Routes in mt8173, mt2701, mt2712 are different. That means
> * in the same register address, it controls different input/output
> diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
> index 4bba275e235a..cff5c9adbf46 100644
> --- a/include/linux/soc/mediatek/mtk-mmsys.h
> +++ b/include/linux/soc/mediatek/mtk-mmsys.h
> @@ -17,13 +17,24 @@ enum mtk_ddp_comp_id {
> DDP_COMPONENT_COLOR0,
> DDP_COMPONENT_COLOR1,
> DDP_COMPONENT_DITHER,
> + DDP_COMPONENT_DITHER1,
> + DDP_COMPONENT_DP_INTF0,
> + DDP_COMPONENT_DP_INTF1,
> DDP_COMPONENT_DPI0,
> DDP_COMPONENT_DPI1,
> + DDP_COMPONENT_DSC0,
> + DDP_COMPONENT_DSC1,
> DDP_COMPONENT_DSI0,
> DDP_COMPONENT_DSI1,
> DDP_COMPONENT_DSI2,
> DDP_COMPONENT_DSI3,
> DDP_COMPONENT_GAMMA,
> + DDP_COMPONENT_MERGE0,
> + DDP_COMPONENT_MERGE1,
> + DDP_COMPONENT_MERGE2,
> + DDP_COMPONENT_MERGE3,
> + DDP_COMPONENT_MERGE4,
> + DDP_COMPONENT_MERGE5,
> DDP_COMPONENT_OD0,
> DDP_COMPONENT_OD1,
> DDP_COMPONENT_OVL0,
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [PATCH v20 1/8] soc: mediatek: add mtk-mmsys support for mt8195 vdosys0
@ 2022-04-22 12:28 ` Matthias Brugger
0 siblings, 0 replies; 110+ messages in thread
From: Matthias Brugger @ 2022-04-22 12:28 UTC (permalink / raw)
To: jason-jh.lin, Chun-Kuang Hu, AngeloGioacchino Del Regno
Cc: CK Hu, Nancy Lin, Singo Chang, devicetree, linux-kernel,
dri-devel, linux-mediatek, linux-arm-kernel,
Project_Global_Chrome_Upstream_Group
On 19/04/2022 11:41, jason-jh.lin wrote:
> 1. Add mt8195 mmsys compatible for 2 vdosys.
> 2. Add io_start into each driver data of mt8195 vdosys.
> 3. Add get match data function to identify mmsys by io_start.
> 4. Add mt8195 routing table settings of vdosys0.
>
> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
I'm not very happy with the approach of testing against the reg property to
decide which version of the two mmsys devices we are probing. I think a better
approach would be, if we would have added some mediatek specific ID to the
device tree binding (or use a two compatibles?).
But as we are at v20 I think it wouldn't be fair to ask for such an instrusive
change. So I'll take this patch now, but maybe we can discuss if we can't do
better in a follow-up patch. Especially I don't think it's a good approach to
check for the io_start in the DRM driver. Couldn't we pass the information about
which of the two mmsys blocks we are calling from through the mediatek-drm
platform device spefic data?
I also had a look into the vdosys1 series to better understand why we need to do
things as we do them. But honestly I wasn't able to really understand the
implication of the patch that adds 'multi mmsys support' [1]. For this looks
like a several patches that got squashed into one. But as I don't have to
maintain that it is not my call to complain, the patch has the needed reviews.
For this patch, now applied to v5.18-next/soc
Thanks for all people implicated.
Regards,
Matthias
[1]
https://patchwork.kernel.org/project/linux-mediatek/patch/20220416020749.29010-19-nancy.lin@mediatek.com/
> ---
> Based on series [1]
>
> [1] MediaTek MT8195 display binding
> - https://patchwork.ozlabs.org/project/devicetree-bindings/list/?series=295669
> ---
> drivers/soc/mediatek/mt8195-mmsys.h | 370 +++++++++++++++++++++++++
> drivers/soc/mediatek/mtk-mmsys.c | 152 +++++++++-
> drivers/soc/mediatek/mtk-mmsys.h | 6 +
> include/linux/soc/mediatek/mtk-mmsys.h | 11 +
> 4 files changed, 528 insertions(+), 11 deletions(-)
> create mode 100644 drivers/soc/mediatek/mt8195-mmsys.h
>
> diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h
> new file mode 100644
> index 000000000000..13ab0ab64396
> --- /dev/null
> +++ b/drivers/soc/mediatek/mt8195-mmsys.h
> @@ -0,0 +1,370 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +
> +#ifndef __SOC_MEDIATEK_MT8195_MMSYS_H
> +#define __SOC_MEDIATEK_MT8195_MMSYS_H
> +
> +#define MT8195_VDO0_OVL_MOUT_EN 0xf14
> +#define MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0 BIT(0)
> +#define MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0 BIT(1)
> +#define MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1 BIT(2)
> +#define MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1 BIT(4)
> +#define MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1 BIT(5)
> +#define MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0 BIT(6)
> +
> +#define MT8195_VDO0_SEL_IN 0xf34
> +#define MT8195_SEL_IN_VPP_MERGE_FROM_MASK GENMASK(1, 0)
> +#define MT8195_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT (0 << 0)
> +#define MT8195_SEL_IN_VPP_MERGE_FROM_DISP_DITHER1 (1 << 0)
> +#define MT8195_SEL_IN_VPP_MERGE_FROM_VDO1_VIRTUAL0 (2 << 0)
> +#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK GENMASK(4, 4)
> +#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0 (0 << 4)
> +#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_VPP_MERGE (1 << 4)
> +#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_MASK GENMASK(5, 5)
> +#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_DISP_DITHER1 (0 << 5)
> +#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_VPP_MERGE (1 << 5)
> +#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK GENMASK(8, 8)
> +#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE (0 << 8)
> +#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT (1 << 8)
> +#define MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK GENMASK(9, 9)
> +#define MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT (0 << 9)
> +#define MT8195_SEL_IN_DP_INTF0_FROM_MASK GENMASK(13, 12)
> +#define MT8195_SEL_IN_DP_INTF0_FROM_DSC_WRAP1_OUT (0 << 0)
> +#define MT8195_SEL_IN_DP_INTF0_FROM_VPP_MERGE (1 << 12)
> +#define MT8195_SEL_IN_DP_INTF0_FROM_VDO1_VIRTUAL0 (2 << 12)
> +#define MT8195_SEL_IN_DSI0_FROM_MASK GENMASK(16, 16)
> +#define MT8195_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT (0 << 16)
> +#define MT8195_SEL_IN_DSI0_FROM_DISP_DITHER0 (1 << 16)
> +#define MT8195_SEL_IN_DSI1_FROM_MASK GENMASK(17, 17)
> +#define MT8195_SEL_IN_DSI1_FROM_DSC_WRAP1_OUT (0 << 17)
> +#define MT8195_SEL_IN_DSI1_FROM_VPP_MERGE (1 << 17)
> +#define MT8195_SEL_IN_DISP_WDMA1_FROM_MASK GENMASK(20, 20)
> +#define MT8195_SEL_IN_DISP_WDMA1_FROM_DISP_OVL1 (0 << 20)
> +#define MT8195_SEL_IN_DISP_WDMA1_FROM_VPP_MERGE (1 << 20)
> +#define MT8195_SEL_IN_DSC_WRAP1_FROM_MASK GENMASK(21, 21)
> +#define MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN (0 << 21)
> +#define MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1 (1 << 21)
> +#define MT8195_SEL_IN_DISP_WDMA0_FROM_MASK GENMASK(22, 22)
> +#define MT8195_SEL_IN_DISP_WDMA0_FROM_DISP_OVL0 (0 << 22)
> +
> +#define MT8195_VDO0_SEL_OUT 0xf38
> +#define MT8195_SOUT_DISP_DITHER0_TO_MASK BIT(0)
> +#define MT8195_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN (0 << 0)
> +#define MT8195_SOUT_DISP_DITHER0_TO_DSI0 (1 << 0)
> +#define MT8195_SOUT_DISP_DITHER1_TO_MASK GENMASK(2, 1)
> +#define MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_IN (0 << 1)
> +#define MT8195_SOUT_DISP_DITHER1_TO_VPP_MERGE (1 << 1)
> +#define MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT (2 << 1)
> +#define MT8195_SOUT_VDO1_VIRTUAL0_TO_MASK GENMASK(4, 4)
> +#define MT8195_SOUT_VDO1_VIRTUAL0_TO_VPP_MERGE (0 << 4)
> +#define MT8195_SOUT_VDO1_VIRTUAL0_TO_DP_INTF0 (1 << 4)
> +#define MT8195_SOUT_VPP_MERGE_TO_MASK GENMASK(10, 8)
> +#define MT8195_SOUT_VPP_MERGE_TO_DSI1 (0 << 8)
> +#define MT8195_SOUT_VPP_MERGE_TO_DP_INTF0 (1 << 8)
> +#define MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0 (2 << 8)
> +#define MT8195_SOUT_VPP_MERGE_TO_DISP_WDMA1 (3 << 8)
> +#define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP0_IN (4 << 8)
> +#define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN_MASK GENMASK(11, 11)
> +#define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN (0 << 11)
> +#define MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK GENMASK(13, 12)
> +#define MT8195_SOUT_DSC_WRAP0_OUT_TO_DSI0 (0 << 12)
> +#define MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0 (1 << 12)
> +#define MT8195_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE (2 << 12)
> +#define MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK GENMASK(17, 16)
> +#define MT8195_SOUT_DSC_WRAP1_OUT_TO_DSI1 (0 << 16)
> +#define MT8195_SOUT_DSC_WRAP1_OUT_TO_DP_INTF0 (1 << 16)
> +#define MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0 (2 << 16)
> +#define MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE (3 << 16)
> +
> +static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
> + {
> + DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
> + MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0,
> + MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0
> + }, {
> + DDP_COMPONENT_OVL0, DDP_COMPONENT_WDMA0,
> + MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0,
> + MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0
> + }, {
> + DDP_COMPONENT_OVL0, DDP_COMPONENT_OVL1,
> + MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1,
> + MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1
> + }, {
> + DDP_COMPONENT_OVL1, DDP_COMPONENT_RDMA1,
> + MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1,
> + MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1
> + }, {
> + DDP_COMPONENT_OVL1, DDP_COMPONENT_WDMA1,
> + MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1,
> + MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1
> + }, {
> + DDP_COMPONENT_OVL1, DDP_COMPONENT_OVL0,
> + MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0,
> + MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0
> + }, {
> + DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK,
> + MT8195_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT
> + }, {
> + DDP_COMPONENT_DITHER1, DDP_COMPONENT_MERGE0,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK,
> + MT8195_SEL_IN_VPP_MERGE_FROM_DISP_DITHER1
> + }, {
> + DDP_COMPONENT_MERGE5, DDP_COMPONENT_MERGE0,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK,
> + MT8195_SEL_IN_VPP_MERGE_FROM_VDO1_VIRTUAL0
> + }, {
> + DDP_COMPONENT_DITHER, DDP_COMPONENT_DSC0,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK,
> + MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0
> + }, {
> + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC0,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK,
> + MT8195_SEL_IN_DSC_WRAP0_IN_FROM_VPP_MERGE
> + }, {
> + DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSC1,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_IN_FROM_MASK,
> + MT8195_SEL_IN_DSC_WRAP1_IN_FROM_DISP_DITHER1
> + }, {
> + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC1,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_IN_FROM_MASK,
> + MT8195_SEL_IN_DSC_WRAP1_IN_FROM_VPP_MERGE
> + }, {
> + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF1,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
> + MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE
> + }, {
> + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI0,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
> + MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE
> + }, {
> + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI1,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
> + MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE
> + }, {
> + DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF1,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
> + MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT
> + }, {
> + DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI0,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
> + MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT
> + }, {
> + DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI1,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
> + MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT
> + }, {
> + DDP_COMPONENT_DSC0, DDP_COMPONENT_DP_INTF1,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK,
> + MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT
> + }, {
> + DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI0,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK,
> + MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT
> + }, {
> + DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI1,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK,
> + MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT
> + }, {
> + DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF0,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_MASK,
> + MT8195_SEL_IN_DP_INTF0_FROM_DSC_WRAP1_OUT
> + }, {
> + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF0,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_MASK,
> + MT8195_SEL_IN_DP_INTF0_FROM_VPP_MERGE
> + }, {
> + DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF0,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_MASK,
> + MT8195_SEL_IN_DP_INTF0_FROM_VDO1_VIRTUAL0
> + }, {
> + DDP_COMPONENT_DSC0, DDP_COMPONENT_DSI0,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI0_FROM_MASK,
> + MT8195_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT
> + }, {
> + DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI0_FROM_MASK,
> + MT8195_SEL_IN_DSI0_FROM_DISP_DITHER0
> + }, {
> + DDP_COMPONENT_DSC1, DDP_COMPONENT_DSI1,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI1_FROM_MASK,
> + MT8195_SEL_IN_DSI1_FROM_DSC_WRAP1_OUT
> + }, {
> + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSI1,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI1_FROM_MASK,
> + MT8195_SEL_IN_DSI1_FROM_VPP_MERGE
> + }, {
> + DDP_COMPONENT_OVL1, DDP_COMPONENT_WDMA1,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA1_FROM_MASK,
> + MT8195_SEL_IN_DISP_WDMA1_FROM_DISP_OVL1
> + }, {
> + DDP_COMPONENT_MERGE0, DDP_COMPONENT_WDMA1,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA1_FROM_MASK,
> + MT8195_SEL_IN_DISP_WDMA1_FROM_VPP_MERGE
> + }, {
> + DDP_COMPONENT_DSC1, DDP_COMPONENT_DSI1,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
> + MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
> + }, {
> + DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF0,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
> + MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
> + }, {
> + DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF1,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
> + MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
> + }, {
> + DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI0,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
> + MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
> + }, {
> + DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI1,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
> + MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
> + }, {
> + DDP_COMPONENT_DSC1, DDP_COMPONENT_MERGE0,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
> + MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
> + }, {
> + DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSI1,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
> + MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1
> + }, {
> + DDP_COMPONENT_DITHER1, DDP_COMPONENT_DP_INTF0,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
> + MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1
> + }, {
> + DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI0,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
> + MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1
> + }, {
> + DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI1,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
> + MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1
> + }, {
> + DDP_COMPONENT_OVL0, DDP_COMPONENT_WDMA0,
> + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA0_FROM_MASK,
> + MT8195_SEL_IN_DISP_WDMA0_FROM_DISP_OVL0
> + }, {
> + DDP_COMPONENT_DITHER, DDP_COMPONENT_DSC0,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER0_TO_MASK,
> + MT8195_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN
> + }, {
> + DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER0_TO_MASK,
> + MT8195_SOUT_DISP_DITHER0_TO_DSI0
> + }, {
> + DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSC1,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
> + MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_IN
> + }, {
> + DDP_COMPONENT_DITHER1, DDP_COMPONENT_MERGE0,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
> + MT8195_SOUT_DISP_DITHER1_TO_VPP_MERGE
> + }, {
> + DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSI1,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
> + MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT
> + }, {
> + DDP_COMPONENT_DITHER1, DDP_COMPONENT_DP_INTF0,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
> + MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT
> + }, {
> + DDP_COMPONENT_DITHER1, DDP_COMPONENT_DP_INTF1,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
> + MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT
> + }, {
> + DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI0,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
> + MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT
> + }, {
> + DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI1,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
> + MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT
> + }, {
> + DDP_COMPONENT_MERGE5, DDP_COMPONENT_MERGE0,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_VDO1_VIRTUAL0_TO_MASK,
> + MT8195_SOUT_VDO1_VIRTUAL0_TO_VPP_MERGE
> + }, {
> + DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF0,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_VDO1_VIRTUAL0_TO_MASK,
> + MT8195_SOUT_VDO1_VIRTUAL0_TO_DP_INTF0
> + }, {
> + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSI1,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
> + MT8195_SOUT_VPP_MERGE_TO_DSI1
> + }, {
> + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF0,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
> + MT8195_SOUT_VPP_MERGE_TO_DP_INTF0
> + }, {
> + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF1,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
> + MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0
> + }, {
> + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI0,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
> + MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0
> + }, {
> + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI1,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
> + MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0
> + }, {
> + DDP_COMPONENT_MERGE0, DDP_COMPONENT_WDMA1,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
> + MT8195_SOUT_VPP_MERGE_TO_DISP_WDMA1
> + }, {
> + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC0,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
> + MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP0_IN
> + }, {
> + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC1,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN_MASK,
> + MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN
> + }, {
> + DDP_COMPONENT_DSC0, DDP_COMPONENT_DSI0,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
> + MT8195_SOUT_DSC_WRAP0_OUT_TO_DSI0
> + }, {
> + DDP_COMPONENT_DSC0, DDP_COMPONENT_DP_INTF1,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
> + MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0
> + }, {
> + DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI0,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
> + MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0
> + }, {
> + DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI1,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
> + MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0
> + }, {
> + DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
> + MT8195_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE
> + }, {
> + DDP_COMPONENT_DSC1, DDP_COMPONENT_DSI1,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
> + MT8195_SOUT_DSC_WRAP1_OUT_TO_DSI1
> + }, {
> + DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF0,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
> + MT8195_SOUT_DSC_WRAP1_OUT_TO_DP_INTF0
> + }, {
> + DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF1,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
> + MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0
> + }, {
> + DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI0,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
> + MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0
> + }, {
> + DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI1,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
> + MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0
> + }, {
> + DDP_COMPONENT_DSC1, DDP_COMPONENT_MERGE0,
> + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
> + MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE
> + }
> +};
> +
> +#endif /* __SOC_MEDIATEK_MT8195_MMSYS_H */
> diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
> index 4fc4c2c9ea20..548efed8dc1c 100644
> --- a/drivers/soc/mediatek/mtk-mmsys.c
> +++ b/drivers/soc/mediatek/mtk-mmsys.c
> @@ -17,6 +17,7 @@
> #include "mt8183-mmsys.h"
> #include "mt8186-mmsys.h"
> #include "mt8192-mmsys.h"
> +#include "mt8195-mmsys.h"
> #include "mt8365-mmsys.h"
>
> static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
> @@ -25,26 +26,61 @@ static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
> .num_routes = ARRAY_SIZE(mmsys_default_routing_table),
> };
>
> +static const struct mtk_mmsys_match_data mt2701_mmsys_match_data = {
> + .num_drv_data = 1,
> + .drv_data = {
> + &mt2701_mmsys_driver_data,
> + },
> +};
> +
> static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = {
> .clk_driver = "clk-mt2712-mm",
> .routes = mmsys_default_routing_table,
> .num_routes = ARRAY_SIZE(mmsys_default_routing_table),
> };
>
> +static const struct mtk_mmsys_match_data mt2712_mmsys_match_data = {
> + .num_drv_data = 1,
> + .drv_data = {
> + &mt2712_mmsys_driver_data,
> + },
> +};
> +
> static const struct mtk_mmsys_driver_data mt6779_mmsys_driver_data = {
> .clk_driver = "clk-mt6779-mm",
> };
>
> +static const struct mtk_mmsys_match_data mt6779_mmsys_match_data = {
> + .num_drv_data = 1,
> + .drv_data = {
> + &mt6779_mmsys_driver_data,
> + },
> +};
> +
> static const struct mtk_mmsys_driver_data mt6797_mmsys_driver_data = {
> .clk_driver = "clk-mt6797-mm",
> };
>
> +static const struct mtk_mmsys_match_data mt6797_mmsys_match_data = {
> + .num_drv_data = 1,
> + .drv_data = {
> + &mt6797_mmsys_driver_data,
> + },
> +};
> +
> static const struct mtk_mmsys_driver_data mt8167_mmsys_driver_data = {
> .clk_driver = "clk-mt8167-mm",
> .routes = mt8167_mmsys_routing_table,
> .num_routes = ARRAY_SIZE(mt8167_mmsys_routing_table),
> };
>
> +static const struct mtk_mmsys_match_data mt8167_mmsys_match_data = {
> + .num_drv_data = 1,
> + .drv_data = {
> + &mt8167_mmsys_driver_data,
> + },
> +};
> +
> static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
> .clk_driver = "clk-mt8173-mm",
> .routes = mmsys_default_routing_table,
> @@ -52,6 +88,13 @@ static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
> .sw0_rst_offset = MT8183_MMSYS_SW0_RST_B,
> };
>
> +static const struct mtk_mmsys_match_data mt8173_mmsys_match_data = {
> + .num_drv_data = 1,
> + .drv_data = {
> + &mt8173_mmsys_driver_data,
> + },
> +};
> +
> static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
> .clk_driver = "clk-mt8183-mm",
> .routes = mmsys_mt8183_routing_table,
> @@ -59,6 +102,13 @@ static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
> .sw0_rst_offset = MT8183_MMSYS_SW0_RST_B,
> };
>
> +static const struct mtk_mmsys_match_data mt8183_mmsys_match_data = {
> + .num_drv_data = 1,
> + .drv_data = {
> + &mt8183_mmsys_driver_data,
> + },
> +};
> +
> static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = {
> .clk_driver = "clk-mt8186-mm",
> .routes = mmsys_mt8186_routing_table,
> @@ -66,25 +116,79 @@ static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = {
> .sw0_rst_offset = MT8186_MMSYS_SW0_RST_B,
> };
>
> +static const struct mtk_mmsys_match_data mt8186_mmsys_match_data = {
> + .num_drv_data = 1,
> + .drv_data = {
> + &mt8186_mmsys_driver_data,
> + },
> +};
> +
> static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
> .clk_driver = "clk-mt8192-mm",
> .routes = mmsys_mt8192_routing_table,
> .num_routes = ARRAY_SIZE(mmsys_mt8192_routing_table),
> };
>
> +static const struct mtk_mmsys_match_data mt8192_mmsys_match_data = {
> + .num_drv_data = 1,
> + .drv_data = {
> + &mt8192_mmsys_driver_data,
> + },
> +};
> +
> +static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = {
> + .io_start = 0x1c01a000,
> + .clk_driver = "clk-mt8195-vdo0",
> + .routes = mmsys_mt8195_routing_table,
> + .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
> +};
> +
> +static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
> + .io_start = 0x1c100000,
> + .clk_driver = "clk-mt8195-vdo1",
> +};
> +
> +static const struct mtk_mmsys_match_data mt8195_mmsys_match_data = {
> + .num_drv_data = 2,
> + .drv_data = {
> + &mt8195_vdosys0_driver_data,
> + &mt8195_vdosys1_driver_data,
> + },
> +};
> +
> static const struct mtk_mmsys_driver_data mt8365_mmsys_driver_data = {
> .clk_driver = "clk-mt8365-mm",
> .routes = mt8365_mmsys_routing_table,
> .num_routes = ARRAY_SIZE(mt8365_mmsys_routing_table),
> };
>
> +static const struct mtk_mmsys_match_data mt8365_mmsys_match_data = {
> + .num_drv_data = 1,
> + .drv_data = {
> + &mt8365_mmsys_driver_data,
> + },
> +};
> +
> struct mtk_mmsys {
> void __iomem *regs;
> const struct mtk_mmsys_driver_data *data;
> spinlock_t lock; /* protects mmsys_sw_rst_b reg */
> struct reset_controller_dev rcdev;
> + phys_addr_t io_start;
> };
>
> +static int mtk_mmsys_find_match_drvdata(struct mtk_mmsys *mmsys,
> + const struct mtk_mmsys_match_data *match)
> +{
> + int i;
> +
> + for (i = 0; i < match->num_drv_data; i++)
> + if (mmsys->io_start == match->drv_data[i]->io_start)
> + return i;
> +
> + return -EINVAL;
> +}
> +
> void mtk_mmsys_ddp_connect(struct device *dev,
> enum mtk_ddp_comp_id cur,
> enum mtk_ddp_comp_id next)
> @@ -179,7 +283,9 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
> struct device *dev = &pdev->dev;
> struct platform_device *clks;
> struct platform_device *drm;
> + const struct mtk_mmsys_match_data *match_data;
> struct mtk_mmsys *mmsys;
> + struct resource *res;
> int ret;
>
> mmsys = devm_kzalloc(dev, sizeof(*mmsys), GFP_KERNEL);
> @@ -205,7 +311,27 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
> return ret;
> }
>
> - mmsys->data = of_device_get_match_data(&pdev->dev);
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + if (!res) {
> + dev_err(dev, "Couldn't get mmsys resource\n");
> + return -EINVAL;
> + }
> + mmsys->io_start = res->start;
> +
> + match_data = of_device_get_match_data(dev);
> + if (match_data->num_drv_data > 1) {
> + /* This SoC has multiple mmsys channels */
> + ret = mtk_mmsys_find_match_drvdata(mmsys, match_data);
> + if (ret < 0) {
> + dev_err(dev, "Couldn't get match driver data\n");
> + return ret;
> + }
> + mmsys->data = match_data->drv_data[ret];
> + } else {
> + dev_dbg(dev, "Using single mmsys channel\n");
> + mmsys->data = match_data->drv_data[0];
> + }
> +
> platform_set_drvdata(pdev, mmsys);
>
> clks = platform_device_register_data(&pdev->dev, mmsys->data->clk_driver,
> @@ -226,43 +352,47 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
> static const struct of_device_id of_match_mtk_mmsys[] = {
> {
> .compatible = "mediatek,mt2701-mmsys",
> - .data = &mt2701_mmsys_driver_data,
> + .data = &mt2701_mmsys_match_data,
> },
> {
> .compatible = "mediatek,mt2712-mmsys",
> - .data = &mt2712_mmsys_driver_data,
> + .data = &mt2712_mmsys_match_data,
> },
> {
> .compatible = "mediatek,mt6779-mmsys",
> - .data = &mt6779_mmsys_driver_data,
> + .data = &mt6779_mmsys_match_data,
> },
> {
> .compatible = "mediatek,mt6797-mmsys",
> - .data = &mt6797_mmsys_driver_data,
> + .data = &mt6797_mmsys_match_data,
> },
> {
> .compatible = "mediatek,mt8167-mmsys",
> - .data = &mt8167_mmsys_driver_data,
> + .data = &mt8167_mmsys_match_data,
> },
> {
> .compatible = "mediatek,mt8173-mmsys",
> - .data = &mt8173_mmsys_driver_data,
> + .data = &mt8173_mmsys_match_data,
> },
> {
> .compatible = "mediatek,mt8183-mmsys",
> - .data = &mt8183_mmsys_driver_data,
> + .data = &mt8183_mmsys_match_data,
> },
> {
> .compatible = "mediatek,mt8186-mmsys",
> - .data = &mt8186_mmsys_driver_data,
> + .data = &mt8186_mmsys_match_data,
> },
> {
> .compatible = "mediatek,mt8192-mmsys",
> - .data = &mt8192_mmsys_driver_data,
> + .data = &mt8192_mmsys_match_data,
> + },
> + {
> + .compatible = "mediatek,mt8195-mmsys",
> + .data = &mt8195_mmsys_match_data,
> },
> {
> .compatible = "mediatek,mt8365-mmsys",
> - .data = &mt8365_mmsys_driver_data,
> + .data = &mt8365_mmsys_match_data,
> },
> { }
> };
> diff --git a/drivers/soc/mediatek/mtk-mmsys.h b/drivers/soc/mediatek/mtk-mmsys.h
> index 77f37f8c715b..f01ba206481d 100644
> --- a/drivers/soc/mediatek/mtk-mmsys.h
> +++ b/drivers/soc/mediatek/mtk-mmsys.h
> @@ -87,12 +87,18 @@ struct mtk_mmsys_routes {
> };
>
> struct mtk_mmsys_driver_data {
> + const resource_size_t io_start;
> const char *clk_driver;
> const struct mtk_mmsys_routes *routes;
> const unsigned int num_routes;
> const u16 sw0_rst_offset;
> };
>
> +struct mtk_mmsys_match_data {
> + unsigned short num_drv_data;
> + const struct mtk_mmsys_driver_data *drv_data[];
> +};
> +
> /*
> * Routes in mt8173, mt2701, mt2712 are different. That means
> * in the same register address, it controls different input/output
> diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
> index 4bba275e235a..cff5c9adbf46 100644
> --- a/include/linux/soc/mediatek/mtk-mmsys.h
> +++ b/include/linux/soc/mediatek/mtk-mmsys.h
> @@ -17,13 +17,24 @@ enum mtk_ddp_comp_id {
> DDP_COMPONENT_COLOR0,
> DDP_COMPONENT_COLOR1,
> DDP_COMPONENT_DITHER,
> + DDP_COMPONENT_DITHER1,
> + DDP_COMPONENT_DP_INTF0,
> + DDP_COMPONENT_DP_INTF1,
> DDP_COMPONENT_DPI0,
> DDP_COMPONENT_DPI1,
> + DDP_COMPONENT_DSC0,
> + DDP_COMPONENT_DSC1,
> DDP_COMPONENT_DSI0,
> DDP_COMPONENT_DSI1,
> DDP_COMPONENT_DSI2,
> DDP_COMPONENT_DSI3,
> DDP_COMPONENT_GAMMA,
> + DDP_COMPONENT_MERGE0,
> + DDP_COMPONENT_MERGE1,
> + DDP_COMPONENT_MERGE2,
> + DDP_COMPONENT_MERGE3,
> + DDP_COMPONENT_MERGE4,
> + DDP_COMPONENT_MERGE5,
> DDP_COMPONENT_OD0,
> DDP_COMPONENT_OD1,
> DDP_COMPONENT_OVL0,
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^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [PATCH v20 2/8] soc: mediatek: add mtk-mutex support for mt8195 vdosys0
2022-04-19 9:41 ` jason-jh.lin
(?)
(?)
@ 2022-04-22 12:29 ` Matthias Brugger
-1 siblings, 0 replies; 110+ messages in thread
From: Matthias Brugger @ 2022-04-22 12:29 UTC (permalink / raw)
To: jason-jh.lin, Chun-Kuang Hu, AngeloGioacchino Del Regno
Cc: CK Hu, Nancy Lin, Singo Chang, devicetree, linux-kernel,
dri-devel, linux-mediatek, linux-arm-kernel,
Project_Global_Chrome_Upstream_Group
On 19/04/2022 11:41, jason-jh.lin wrote:
> Add mtk-mutex support for mt8195 vdosys0.
>
> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> Acked-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> Tested-by: Fei Shao <fshao@chromium.org>
Applied thanks!
Matthias
> ---
> drivers/soc/mediatek/mtk-mutex.c | 87 ++++++++++++++++++++++++++++++--
> 1 file changed, 84 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c
> index aaf8fc1abb43..729ee88035ed 100644
> --- a/drivers/soc/mediatek/mtk-mutex.c
> +++ b/drivers/soc/mediatek/mtk-mutex.c
> @@ -17,6 +17,9 @@
> #define MT8183_MUTEX0_MOD0 0x30
> #define MT8183_MUTEX0_SOF0 0x2c
>
> +#define MT8195_DISP_MUTEX0_MOD0 0x30
> +#define MT8195_DISP_MUTEX0_SOF 0x2c
> +
> #define DISP_REG_MUTEX_EN(n) (0x20 + 0x20 * (n))
> #define DISP_REG_MUTEX(n) (0x24 + 0x20 * (n))
> #define DISP_REG_MUTEX_RST(n) (0x28 + 0x20 * (n))
> @@ -96,6 +99,20 @@
> #define MT8173_MUTEX_MOD_DISP_PWM1 24
> #define MT8173_MUTEX_MOD_DISP_OD 25
>
> +#define MT8195_MUTEX_MOD_DISP_OVL0 0
> +#define MT8195_MUTEX_MOD_DISP_WDMA0 1
> +#define MT8195_MUTEX_MOD_DISP_RDMA0 2
> +#define MT8195_MUTEX_MOD_DISP_COLOR0 3
> +#define MT8195_MUTEX_MOD_DISP_CCORR0 4
> +#define MT8195_MUTEX_MOD_DISP_AAL0 5
> +#define MT8195_MUTEX_MOD_DISP_GAMMA0 6
> +#define MT8195_MUTEX_MOD_DISP_DITHER0 7
> +#define MT8195_MUTEX_MOD_DISP_DSI0 8
> +#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0 9
> +#define MT8195_MUTEX_MOD_DISP_VPP_MERGE 20
> +#define MT8195_MUTEX_MOD_DISP_DP_INTF0 21
> +#define MT8195_MUTEX_MOD_DISP_PWM0 27
> +
> #define MT2712_MUTEX_MOD_DISP_PWM2 10
> #define MT2712_MUTEX_MOD_DISP_OVL0 11
> #define MT2712_MUTEX_MOD_DISP_OVL1 12
> @@ -132,9 +149,21 @@
> #define MT8167_MUTEX_SOF_DPI1 3
> #define MT8183_MUTEX_SOF_DSI0 1
> #define MT8183_MUTEX_SOF_DPI0 2
> +#define MT8195_MUTEX_SOF_DSI0 1
> +#define MT8195_MUTEX_SOF_DSI1 2
> +#define MT8195_MUTEX_SOF_DP_INTF0 3
> +#define MT8195_MUTEX_SOF_DP_INTF1 4
> +#define MT8195_MUTEX_SOF_DPI0 6 /* for HDMI_TX */
> +#define MT8195_MUTEX_SOF_DPI1 5 /* for digital video out */
>
> #define MT8183_MUTEX_EOF_DSI0 (MT8183_MUTEX_SOF_DSI0 << 6)
> #define MT8183_MUTEX_EOF_DPI0 (MT8183_MUTEX_SOF_DPI0 << 6)
> +#define MT8195_MUTEX_EOF_DSI0 (MT8195_MUTEX_SOF_DSI0 << 7)
> +#define MT8195_MUTEX_EOF_DSI1 (MT8195_MUTEX_SOF_DSI1 << 7)
> +#define MT8195_MUTEX_EOF_DP_INTF0 (MT8195_MUTEX_SOF_DP_INTF0 << 7)
> +#define MT8195_MUTEX_EOF_DP_INTF1 (MT8195_MUTEX_SOF_DP_INTF1 << 7)
> +#define MT8195_MUTEX_EOF_DPI0 (MT8195_MUTEX_SOF_DPI0 << 7)
> +#define MT8195_MUTEX_EOF_DPI1 (MT8195_MUTEX_SOF_DPI1 << 7)
>
> struct mtk_mutex {
> int id;
> @@ -149,6 +178,9 @@ enum mtk_mutex_sof_id {
> MUTEX_SOF_DPI1,
> MUTEX_SOF_DSI2,
> MUTEX_SOF_DSI3,
> + MUTEX_SOF_DP_INTF0,
> + MUTEX_SOF_DP_INTF1,
> + DDP_MUTEX_SOF_MAX,
> };
>
> struct mtk_mutex_data {
> @@ -270,7 +302,23 @@ static const unsigned int mt8192_mutex_mod[DDP_COMPONENT_ID_MAX] = {
> [DDP_COMPONENT_RDMA4] = MT8192_MUTEX_MOD_DISP_RDMA4,
> };
>
> -static const unsigned int mt2712_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
> +static const unsigned int mt8195_mutex_mod[DDP_COMPONENT_ID_MAX] = {
> + [DDP_COMPONENT_OVL0] = MT8195_MUTEX_MOD_DISP_OVL0,
> + [DDP_COMPONENT_WDMA0] = MT8195_MUTEX_MOD_DISP_WDMA0,
> + [DDP_COMPONENT_RDMA0] = MT8195_MUTEX_MOD_DISP_RDMA0,
> + [DDP_COMPONENT_COLOR0] = MT8195_MUTEX_MOD_DISP_COLOR0,
> + [DDP_COMPONENT_CCORR] = MT8195_MUTEX_MOD_DISP_CCORR0,
> + [DDP_COMPONENT_AAL0] = MT8195_MUTEX_MOD_DISP_AAL0,
> + [DDP_COMPONENT_GAMMA] = MT8195_MUTEX_MOD_DISP_GAMMA0,
> + [DDP_COMPONENT_DITHER] = MT8195_MUTEX_MOD_DISP_DITHER0,
> + [DDP_COMPONENT_MERGE0] = MT8195_MUTEX_MOD_DISP_VPP_MERGE,
> + [DDP_COMPONENT_DSC0] = MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0,
> + [DDP_COMPONENT_DSI0] = MT8195_MUTEX_MOD_DISP_DSI0,
> + [DDP_COMPONENT_PWM0] = MT8195_MUTEX_MOD_DISP_PWM0,
> + [DDP_COMPONENT_DP_INTF0] = MT8195_MUTEX_MOD_DISP_DP_INTF0,
> +};
> +
> +static const unsigned int mt2712_mutex_sof[DDP_MUTEX_SOF_MAX] = {
> [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
> [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0,
> [MUTEX_SOF_DSI1] = MUTEX_SOF_DSI1,
> @@ -280,7 +328,7 @@ static const unsigned int mt2712_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
> [MUTEX_SOF_DSI3] = MUTEX_SOF_DSI3,
> };
>
> -static const unsigned int mt8167_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
> +static const unsigned int mt8167_mutex_sof[DDP_MUTEX_SOF_MAX] = {
> [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
> [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0,
> [MUTEX_SOF_DPI0] = MT8167_MUTEX_SOF_DPI0,
> @@ -288,7 +336,7 @@ static const unsigned int mt8167_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
> };
>
> /* Add EOF setting so overlay hardware can receive frame done irq */
> -static const unsigned int mt8183_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
> +static const unsigned int mt8183_mutex_sof[DDP_MUTEX_SOF_MAX] = {
> [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
> [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0 | MT8183_MUTEX_EOF_DSI0,
> [MUTEX_SOF_DPI0] = MT8183_MUTEX_SOF_DPI0 | MT8183_MUTEX_EOF_DPI0,
> @@ -300,6 +348,26 @@ static const unsigned int mt8186_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
> [MUTEX_SOF_DPI0] = MT8186_MUTEX_SOF_DPI0 | MT8186_MUTEX_EOF_DPI0,
> };
>
> +/*
> + * To support refresh mode(video mode), DISP_REG_MUTEX_SOF should
> + * select the EOF source and configure the EOF plus timing from the
> + * module that provides the timing signal.
> + * So that MUTEX can not only send a STREAM_DONE event to GCE
> + * but also detect the error at end of frame(EAEOF) when EOF signal
> + * arrives.
> + */
> +static const unsigned int mt8195_mutex_sof[DDP_MUTEX_SOF_MAX] = {
> + [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
> + [MUTEX_SOF_DSI0] = MT8195_MUTEX_SOF_DSI0 | MT8195_MUTEX_EOF_DSI0,
> + [MUTEX_SOF_DSI1] = MT8195_MUTEX_SOF_DSI1 | MT8195_MUTEX_EOF_DSI1,
> + [MUTEX_SOF_DPI0] = MT8195_MUTEX_SOF_DPI0 | MT8195_MUTEX_EOF_DPI0,
> + [MUTEX_SOF_DPI1] = MT8195_MUTEX_SOF_DPI1 | MT8195_MUTEX_EOF_DPI1,
> + [MUTEX_SOF_DP_INTF0] =
> + MT8195_MUTEX_SOF_DP_INTF0 | MT8195_MUTEX_EOF_DP_INTF0,
> + [MUTEX_SOF_DP_INTF1] =
> + MT8195_MUTEX_SOF_DP_INTF1 | MT8195_MUTEX_EOF_DP_INTF1,
> +};
> +
> static const struct mtk_mutex_data mt2701_mutex_driver_data = {
> .mutex_mod = mt2701_mutex_mod,
> .mutex_sof = mt2712_mutex_sof,
> @@ -351,6 +419,13 @@ static const struct mtk_mutex_data mt8192_mutex_driver_data = {
> .mutex_sof_reg = MT8183_MUTEX0_SOF0,
> };
>
> +static const struct mtk_mutex_data mt8195_mutex_driver_data = {
> + .mutex_mod = mt8195_mutex_mod,
> + .mutex_sof = mt8195_mutex_sof,
> + .mutex_mod_reg = MT8195_DISP_MUTEX0_MOD0,
> + .mutex_sof_reg = MT8195_DISP_MUTEX0_SOF,
> +};
> +
> struct mtk_mutex *mtk_mutex_get(struct device *dev)
> {
> struct mtk_mutex_ctx *mtx = dev_get_drvdata(dev);
> @@ -423,6 +498,9 @@ void mtk_mutex_add_comp(struct mtk_mutex *mutex,
> case DDP_COMPONENT_DPI1:
> sof_id = MUTEX_SOF_DPI1;
> break;
> + case DDP_COMPONENT_DP_INTF0:
> + sof_id = MUTEX_SOF_DP_INTF0;
> + break;
> default:
> if (mtx->data->mutex_mod[id] < 32) {
> offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg,
> @@ -462,6 +540,7 @@ void mtk_mutex_remove_comp(struct mtk_mutex *mutex,
> case DDP_COMPONENT_DSI3:
> case DDP_COMPONENT_DPI0:
> case DDP_COMPONENT_DPI1:
> + case DDP_COMPONENT_DP_INTF0:
> writel_relaxed(MUTEX_SOF_SINGLE_MODE,
> mtx->regs +
> DISP_REG_MUTEX_SOF(mtx->data->mutex_sof_reg,
> @@ -587,6 +666,8 @@ static const struct of_device_id mutex_driver_dt_match[] = {
> .data = &mt8186_mutex_driver_data},
> { .compatible = "mediatek,mt8192-disp-mutex",
> .data = &mt8192_mutex_driver_data},
> + { .compatible = "mediatek,mt8195-disp-mutex",
> + .data = &mt8195_mutex_driver_data},
> {},
> };
> MODULE_DEVICE_TABLE(of, mutex_driver_dt_match);
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [PATCH v20 2/8] soc: mediatek: add mtk-mutex support for mt8195 vdosys0
@ 2022-04-22 12:29 ` Matthias Brugger
0 siblings, 0 replies; 110+ messages in thread
From: Matthias Brugger @ 2022-04-22 12:29 UTC (permalink / raw)
To: jason-jh.lin, Chun-Kuang Hu, AngeloGioacchino Del Regno
Cc: CK Hu, Nancy Lin, Singo Chang, devicetree, linux-kernel,
dri-devel, linux-mediatek, linux-arm-kernel,
Project_Global_Chrome_Upstream_Group
On 19/04/2022 11:41, jason-jh.lin wrote:
> Add mtk-mutex support for mt8195 vdosys0.
>
> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> Acked-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> Tested-by: Fei Shao <fshao@chromium.org>
Applied thanks!
Matthias
> ---
> drivers/soc/mediatek/mtk-mutex.c | 87 ++++++++++++++++++++++++++++++--
> 1 file changed, 84 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c
> index aaf8fc1abb43..729ee88035ed 100644
> --- a/drivers/soc/mediatek/mtk-mutex.c
> +++ b/drivers/soc/mediatek/mtk-mutex.c
> @@ -17,6 +17,9 @@
> #define MT8183_MUTEX0_MOD0 0x30
> #define MT8183_MUTEX0_SOF0 0x2c
>
> +#define MT8195_DISP_MUTEX0_MOD0 0x30
> +#define MT8195_DISP_MUTEX0_SOF 0x2c
> +
> #define DISP_REG_MUTEX_EN(n) (0x20 + 0x20 * (n))
> #define DISP_REG_MUTEX(n) (0x24 + 0x20 * (n))
> #define DISP_REG_MUTEX_RST(n) (0x28 + 0x20 * (n))
> @@ -96,6 +99,20 @@
> #define MT8173_MUTEX_MOD_DISP_PWM1 24
> #define MT8173_MUTEX_MOD_DISP_OD 25
>
> +#define MT8195_MUTEX_MOD_DISP_OVL0 0
> +#define MT8195_MUTEX_MOD_DISP_WDMA0 1
> +#define MT8195_MUTEX_MOD_DISP_RDMA0 2
> +#define MT8195_MUTEX_MOD_DISP_COLOR0 3
> +#define MT8195_MUTEX_MOD_DISP_CCORR0 4
> +#define MT8195_MUTEX_MOD_DISP_AAL0 5
> +#define MT8195_MUTEX_MOD_DISP_GAMMA0 6
> +#define MT8195_MUTEX_MOD_DISP_DITHER0 7
> +#define MT8195_MUTEX_MOD_DISP_DSI0 8
> +#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0 9
> +#define MT8195_MUTEX_MOD_DISP_VPP_MERGE 20
> +#define MT8195_MUTEX_MOD_DISP_DP_INTF0 21
> +#define MT8195_MUTEX_MOD_DISP_PWM0 27
> +
> #define MT2712_MUTEX_MOD_DISP_PWM2 10
> #define MT2712_MUTEX_MOD_DISP_OVL0 11
> #define MT2712_MUTEX_MOD_DISP_OVL1 12
> @@ -132,9 +149,21 @@
> #define MT8167_MUTEX_SOF_DPI1 3
> #define MT8183_MUTEX_SOF_DSI0 1
> #define MT8183_MUTEX_SOF_DPI0 2
> +#define MT8195_MUTEX_SOF_DSI0 1
> +#define MT8195_MUTEX_SOF_DSI1 2
> +#define MT8195_MUTEX_SOF_DP_INTF0 3
> +#define MT8195_MUTEX_SOF_DP_INTF1 4
> +#define MT8195_MUTEX_SOF_DPI0 6 /* for HDMI_TX */
> +#define MT8195_MUTEX_SOF_DPI1 5 /* for digital video out */
>
> #define MT8183_MUTEX_EOF_DSI0 (MT8183_MUTEX_SOF_DSI0 << 6)
> #define MT8183_MUTEX_EOF_DPI0 (MT8183_MUTEX_SOF_DPI0 << 6)
> +#define MT8195_MUTEX_EOF_DSI0 (MT8195_MUTEX_SOF_DSI0 << 7)
> +#define MT8195_MUTEX_EOF_DSI1 (MT8195_MUTEX_SOF_DSI1 << 7)
> +#define MT8195_MUTEX_EOF_DP_INTF0 (MT8195_MUTEX_SOF_DP_INTF0 << 7)
> +#define MT8195_MUTEX_EOF_DP_INTF1 (MT8195_MUTEX_SOF_DP_INTF1 << 7)
> +#define MT8195_MUTEX_EOF_DPI0 (MT8195_MUTEX_SOF_DPI0 << 7)
> +#define MT8195_MUTEX_EOF_DPI1 (MT8195_MUTEX_SOF_DPI1 << 7)
>
> struct mtk_mutex {
> int id;
> @@ -149,6 +178,9 @@ enum mtk_mutex_sof_id {
> MUTEX_SOF_DPI1,
> MUTEX_SOF_DSI2,
> MUTEX_SOF_DSI3,
> + MUTEX_SOF_DP_INTF0,
> + MUTEX_SOF_DP_INTF1,
> + DDP_MUTEX_SOF_MAX,
> };
>
> struct mtk_mutex_data {
> @@ -270,7 +302,23 @@ static const unsigned int mt8192_mutex_mod[DDP_COMPONENT_ID_MAX] = {
> [DDP_COMPONENT_RDMA4] = MT8192_MUTEX_MOD_DISP_RDMA4,
> };
>
> -static const unsigned int mt2712_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
> +static const unsigned int mt8195_mutex_mod[DDP_COMPONENT_ID_MAX] = {
> + [DDP_COMPONENT_OVL0] = MT8195_MUTEX_MOD_DISP_OVL0,
> + [DDP_COMPONENT_WDMA0] = MT8195_MUTEX_MOD_DISP_WDMA0,
> + [DDP_COMPONENT_RDMA0] = MT8195_MUTEX_MOD_DISP_RDMA0,
> + [DDP_COMPONENT_COLOR0] = MT8195_MUTEX_MOD_DISP_COLOR0,
> + [DDP_COMPONENT_CCORR] = MT8195_MUTEX_MOD_DISP_CCORR0,
> + [DDP_COMPONENT_AAL0] = MT8195_MUTEX_MOD_DISP_AAL0,
> + [DDP_COMPONENT_GAMMA] = MT8195_MUTEX_MOD_DISP_GAMMA0,
> + [DDP_COMPONENT_DITHER] = MT8195_MUTEX_MOD_DISP_DITHER0,
> + [DDP_COMPONENT_MERGE0] = MT8195_MUTEX_MOD_DISP_VPP_MERGE,
> + [DDP_COMPONENT_DSC0] = MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0,
> + [DDP_COMPONENT_DSI0] = MT8195_MUTEX_MOD_DISP_DSI0,
> + [DDP_COMPONENT_PWM0] = MT8195_MUTEX_MOD_DISP_PWM0,
> + [DDP_COMPONENT_DP_INTF0] = MT8195_MUTEX_MOD_DISP_DP_INTF0,
> +};
> +
> +static const unsigned int mt2712_mutex_sof[DDP_MUTEX_SOF_MAX] = {
> [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
> [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0,
> [MUTEX_SOF_DSI1] = MUTEX_SOF_DSI1,
> @@ -280,7 +328,7 @@ static const unsigned int mt2712_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
> [MUTEX_SOF_DSI3] = MUTEX_SOF_DSI3,
> };
>
> -static const unsigned int mt8167_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
> +static const unsigned int mt8167_mutex_sof[DDP_MUTEX_SOF_MAX] = {
> [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
> [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0,
> [MUTEX_SOF_DPI0] = MT8167_MUTEX_SOF_DPI0,
> @@ -288,7 +336,7 @@ static const unsigned int mt8167_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
> };
>
> /* Add EOF setting so overlay hardware can receive frame done irq */
> -static const unsigned int mt8183_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
> +static const unsigned int mt8183_mutex_sof[DDP_MUTEX_SOF_MAX] = {
> [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
> [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0 | MT8183_MUTEX_EOF_DSI0,
> [MUTEX_SOF_DPI0] = MT8183_MUTEX_SOF_DPI0 | MT8183_MUTEX_EOF_DPI0,
> @@ -300,6 +348,26 @@ static const unsigned int mt8186_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
> [MUTEX_SOF_DPI0] = MT8186_MUTEX_SOF_DPI0 | MT8186_MUTEX_EOF_DPI0,
> };
>
> +/*
> + * To support refresh mode(video mode), DISP_REG_MUTEX_SOF should
> + * select the EOF source and configure the EOF plus timing from the
> + * module that provides the timing signal.
> + * So that MUTEX can not only send a STREAM_DONE event to GCE
> + * but also detect the error at end of frame(EAEOF) when EOF signal
> + * arrives.
> + */
> +static const unsigned int mt8195_mutex_sof[DDP_MUTEX_SOF_MAX] = {
> + [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
> + [MUTEX_SOF_DSI0] = MT8195_MUTEX_SOF_DSI0 | MT8195_MUTEX_EOF_DSI0,
> + [MUTEX_SOF_DSI1] = MT8195_MUTEX_SOF_DSI1 | MT8195_MUTEX_EOF_DSI1,
> + [MUTEX_SOF_DPI0] = MT8195_MUTEX_SOF_DPI0 | MT8195_MUTEX_EOF_DPI0,
> + [MUTEX_SOF_DPI1] = MT8195_MUTEX_SOF_DPI1 | MT8195_MUTEX_EOF_DPI1,
> + [MUTEX_SOF_DP_INTF0] =
> + MT8195_MUTEX_SOF_DP_INTF0 | MT8195_MUTEX_EOF_DP_INTF0,
> + [MUTEX_SOF_DP_INTF1] =
> + MT8195_MUTEX_SOF_DP_INTF1 | MT8195_MUTEX_EOF_DP_INTF1,
> +};
> +
> static const struct mtk_mutex_data mt2701_mutex_driver_data = {
> .mutex_mod = mt2701_mutex_mod,
> .mutex_sof = mt2712_mutex_sof,
> @@ -351,6 +419,13 @@ static const struct mtk_mutex_data mt8192_mutex_driver_data = {
> .mutex_sof_reg = MT8183_MUTEX0_SOF0,
> };
>
> +static const struct mtk_mutex_data mt8195_mutex_driver_data = {
> + .mutex_mod = mt8195_mutex_mod,
> + .mutex_sof = mt8195_mutex_sof,
> + .mutex_mod_reg = MT8195_DISP_MUTEX0_MOD0,
> + .mutex_sof_reg = MT8195_DISP_MUTEX0_SOF,
> +};
> +
> struct mtk_mutex *mtk_mutex_get(struct device *dev)
> {
> struct mtk_mutex_ctx *mtx = dev_get_drvdata(dev);
> @@ -423,6 +498,9 @@ void mtk_mutex_add_comp(struct mtk_mutex *mutex,
> case DDP_COMPONENT_DPI1:
> sof_id = MUTEX_SOF_DPI1;
> break;
> + case DDP_COMPONENT_DP_INTF0:
> + sof_id = MUTEX_SOF_DP_INTF0;
> + break;
> default:
> if (mtx->data->mutex_mod[id] < 32) {
> offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg,
> @@ -462,6 +540,7 @@ void mtk_mutex_remove_comp(struct mtk_mutex *mutex,
> case DDP_COMPONENT_DSI3:
> case DDP_COMPONENT_DPI0:
> case DDP_COMPONENT_DPI1:
> + case DDP_COMPONENT_DP_INTF0:
> writel_relaxed(MUTEX_SOF_SINGLE_MODE,
> mtx->regs +
> DISP_REG_MUTEX_SOF(mtx->data->mutex_sof_reg,
> @@ -587,6 +666,8 @@ static const struct of_device_id mutex_driver_dt_match[] = {
> .data = &mt8186_mutex_driver_data},
> { .compatible = "mediatek,mt8192-disp-mutex",
> .data = &mt8192_mutex_driver_data},
> + { .compatible = "mediatek,mt8195-disp-mutex",
> + .data = &mt8195_mutex_driver_data},
> {},
> };
> MODULE_DEVICE_TABLE(of, mutex_driver_dt_match);
_______________________________________________
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^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [PATCH v20 2/8] soc: mediatek: add mtk-mutex support for mt8195 vdosys0
@ 2022-04-22 12:29 ` Matthias Brugger
0 siblings, 0 replies; 110+ messages in thread
From: Matthias Brugger @ 2022-04-22 12:29 UTC (permalink / raw)
To: jason-jh.lin, Chun-Kuang Hu, AngeloGioacchino Del Regno
Cc: devicetree, Singo Chang, linux-kernel, dri-devel,
Project_Global_Chrome_Upstream_Group, Nancy Lin, linux-mediatek,
linux-arm-kernel
On 19/04/2022 11:41, jason-jh.lin wrote:
> Add mtk-mutex support for mt8195 vdosys0.
>
> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> Acked-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> Tested-by: Fei Shao <fshao@chromium.org>
Applied thanks!
Matthias
> ---
> drivers/soc/mediatek/mtk-mutex.c | 87 ++++++++++++++++++++++++++++++--
> 1 file changed, 84 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c
> index aaf8fc1abb43..729ee88035ed 100644
> --- a/drivers/soc/mediatek/mtk-mutex.c
> +++ b/drivers/soc/mediatek/mtk-mutex.c
> @@ -17,6 +17,9 @@
> #define MT8183_MUTEX0_MOD0 0x30
> #define MT8183_MUTEX0_SOF0 0x2c
>
> +#define MT8195_DISP_MUTEX0_MOD0 0x30
> +#define MT8195_DISP_MUTEX0_SOF 0x2c
> +
> #define DISP_REG_MUTEX_EN(n) (0x20 + 0x20 * (n))
> #define DISP_REG_MUTEX(n) (0x24 + 0x20 * (n))
> #define DISP_REG_MUTEX_RST(n) (0x28 + 0x20 * (n))
> @@ -96,6 +99,20 @@
> #define MT8173_MUTEX_MOD_DISP_PWM1 24
> #define MT8173_MUTEX_MOD_DISP_OD 25
>
> +#define MT8195_MUTEX_MOD_DISP_OVL0 0
> +#define MT8195_MUTEX_MOD_DISP_WDMA0 1
> +#define MT8195_MUTEX_MOD_DISP_RDMA0 2
> +#define MT8195_MUTEX_MOD_DISP_COLOR0 3
> +#define MT8195_MUTEX_MOD_DISP_CCORR0 4
> +#define MT8195_MUTEX_MOD_DISP_AAL0 5
> +#define MT8195_MUTEX_MOD_DISP_GAMMA0 6
> +#define MT8195_MUTEX_MOD_DISP_DITHER0 7
> +#define MT8195_MUTEX_MOD_DISP_DSI0 8
> +#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0 9
> +#define MT8195_MUTEX_MOD_DISP_VPP_MERGE 20
> +#define MT8195_MUTEX_MOD_DISP_DP_INTF0 21
> +#define MT8195_MUTEX_MOD_DISP_PWM0 27
> +
> #define MT2712_MUTEX_MOD_DISP_PWM2 10
> #define MT2712_MUTEX_MOD_DISP_OVL0 11
> #define MT2712_MUTEX_MOD_DISP_OVL1 12
> @@ -132,9 +149,21 @@
> #define MT8167_MUTEX_SOF_DPI1 3
> #define MT8183_MUTEX_SOF_DSI0 1
> #define MT8183_MUTEX_SOF_DPI0 2
> +#define MT8195_MUTEX_SOF_DSI0 1
> +#define MT8195_MUTEX_SOF_DSI1 2
> +#define MT8195_MUTEX_SOF_DP_INTF0 3
> +#define MT8195_MUTEX_SOF_DP_INTF1 4
> +#define MT8195_MUTEX_SOF_DPI0 6 /* for HDMI_TX */
> +#define MT8195_MUTEX_SOF_DPI1 5 /* for digital video out */
>
> #define MT8183_MUTEX_EOF_DSI0 (MT8183_MUTEX_SOF_DSI0 << 6)
> #define MT8183_MUTEX_EOF_DPI0 (MT8183_MUTEX_SOF_DPI0 << 6)
> +#define MT8195_MUTEX_EOF_DSI0 (MT8195_MUTEX_SOF_DSI0 << 7)
> +#define MT8195_MUTEX_EOF_DSI1 (MT8195_MUTEX_SOF_DSI1 << 7)
> +#define MT8195_MUTEX_EOF_DP_INTF0 (MT8195_MUTEX_SOF_DP_INTF0 << 7)
> +#define MT8195_MUTEX_EOF_DP_INTF1 (MT8195_MUTEX_SOF_DP_INTF1 << 7)
> +#define MT8195_MUTEX_EOF_DPI0 (MT8195_MUTEX_SOF_DPI0 << 7)
> +#define MT8195_MUTEX_EOF_DPI1 (MT8195_MUTEX_SOF_DPI1 << 7)
>
> struct mtk_mutex {
> int id;
> @@ -149,6 +178,9 @@ enum mtk_mutex_sof_id {
> MUTEX_SOF_DPI1,
> MUTEX_SOF_DSI2,
> MUTEX_SOF_DSI3,
> + MUTEX_SOF_DP_INTF0,
> + MUTEX_SOF_DP_INTF1,
> + DDP_MUTEX_SOF_MAX,
> };
>
> struct mtk_mutex_data {
> @@ -270,7 +302,23 @@ static const unsigned int mt8192_mutex_mod[DDP_COMPONENT_ID_MAX] = {
> [DDP_COMPONENT_RDMA4] = MT8192_MUTEX_MOD_DISP_RDMA4,
> };
>
> -static const unsigned int mt2712_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
> +static const unsigned int mt8195_mutex_mod[DDP_COMPONENT_ID_MAX] = {
> + [DDP_COMPONENT_OVL0] = MT8195_MUTEX_MOD_DISP_OVL0,
> + [DDP_COMPONENT_WDMA0] = MT8195_MUTEX_MOD_DISP_WDMA0,
> + [DDP_COMPONENT_RDMA0] = MT8195_MUTEX_MOD_DISP_RDMA0,
> + [DDP_COMPONENT_COLOR0] = MT8195_MUTEX_MOD_DISP_COLOR0,
> + [DDP_COMPONENT_CCORR] = MT8195_MUTEX_MOD_DISP_CCORR0,
> + [DDP_COMPONENT_AAL0] = MT8195_MUTEX_MOD_DISP_AAL0,
> + [DDP_COMPONENT_GAMMA] = MT8195_MUTEX_MOD_DISP_GAMMA0,
> + [DDP_COMPONENT_DITHER] = MT8195_MUTEX_MOD_DISP_DITHER0,
> + [DDP_COMPONENT_MERGE0] = MT8195_MUTEX_MOD_DISP_VPP_MERGE,
> + [DDP_COMPONENT_DSC0] = MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0,
> + [DDP_COMPONENT_DSI0] = MT8195_MUTEX_MOD_DISP_DSI0,
> + [DDP_COMPONENT_PWM0] = MT8195_MUTEX_MOD_DISP_PWM0,
> + [DDP_COMPONENT_DP_INTF0] = MT8195_MUTEX_MOD_DISP_DP_INTF0,
> +};
> +
> +static const unsigned int mt2712_mutex_sof[DDP_MUTEX_SOF_MAX] = {
> [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
> [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0,
> [MUTEX_SOF_DSI1] = MUTEX_SOF_DSI1,
> @@ -280,7 +328,7 @@ static const unsigned int mt2712_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
> [MUTEX_SOF_DSI3] = MUTEX_SOF_DSI3,
> };
>
> -static const unsigned int mt8167_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
> +static const unsigned int mt8167_mutex_sof[DDP_MUTEX_SOF_MAX] = {
> [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
> [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0,
> [MUTEX_SOF_DPI0] = MT8167_MUTEX_SOF_DPI0,
> @@ -288,7 +336,7 @@ static const unsigned int mt8167_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
> };
>
> /* Add EOF setting so overlay hardware can receive frame done irq */
> -static const unsigned int mt8183_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
> +static const unsigned int mt8183_mutex_sof[DDP_MUTEX_SOF_MAX] = {
> [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
> [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0 | MT8183_MUTEX_EOF_DSI0,
> [MUTEX_SOF_DPI0] = MT8183_MUTEX_SOF_DPI0 | MT8183_MUTEX_EOF_DPI0,
> @@ -300,6 +348,26 @@ static const unsigned int mt8186_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
> [MUTEX_SOF_DPI0] = MT8186_MUTEX_SOF_DPI0 | MT8186_MUTEX_EOF_DPI0,
> };
>
> +/*
> + * To support refresh mode(video mode), DISP_REG_MUTEX_SOF should
> + * select the EOF source and configure the EOF plus timing from the
> + * module that provides the timing signal.
> + * So that MUTEX can not only send a STREAM_DONE event to GCE
> + * but also detect the error at end of frame(EAEOF) when EOF signal
> + * arrives.
> + */
> +static const unsigned int mt8195_mutex_sof[DDP_MUTEX_SOF_MAX] = {
> + [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
> + [MUTEX_SOF_DSI0] = MT8195_MUTEX_SOF_DSI0 | MT8195_MUTEX_EOF_DSI0,
> + [MUTEX_SOF_DSI1] = MT8195_MUTEX_SOF_DSI1 | MT8195_MUTEX_EOF_DSI1,
> + [MUTEX_SOF_DPI0] = MT8195_MUTEX_SOF_DPI0 | MT8195_MUTEX_EOF_DPI0,
> + [MUTEX_SOF_DPI1] = MT8195_MUTEX_SOF_DPI1 | MT8195_MUTEX_EOF_DPI1,
> + [MUTEX_SOF_DP_INTF0] =
> + MT8195_MUTEX_SOF_DP_INTF0 | MT8195_MUTEX_EOF_DP_INTF0,
> + [MUTEX_SOF_DP_INTF1] =
> + MT8195_MUTEX_SOF_DP_INTF1 | MT8195_MUTEX_EOF_DP_INTF1,
> +};
> +
> static const struct mtk_mutex_data mt2701_mutex_driver_data = {
> .mutex_mod = mt2701_mutex_mod,
> .mutex_sof = mt2712_mutex_sof,
> @@ -351,6 +419,13 @@ static const struct mtk_mutex_data mt8192_mutex_driver_data = {
> .mutex_sof_reg = MT8183_MUTEX0_SOF0,
> };
>
> +static const struct mtk_mutex_data mt8195_mutex_driver_data = {
> + .mutex_mod = mt8195_mutex_mod,
> + .mutex_sof = mt8195_mutex_sof,
> + .mutex_mod_reg = MT8195_DISP_MUTEX0_MOD0,
> + .mutex_sof_reg = MT8195_DISP_MUTEX0_SOF,
> +};
> +
> struct mtk_mutex *mtk_mutex_get(struct device *dev)
> {
> struct mtk_mutex_ctx *mtx = dev_get_drvdata(dev);
> @@ -423,6 +498,9 @@ void mtk_mutex_add_comp(struct mtk_mutex *mutex,
> case DDP_COMPONENT_DPI1:
> sof_id = MUTEX_SOF_DPI1;
> break;
> + case DDP_COMPONENT_DP_INTF0:
> + sof_id = MUTEX_SOF_DP_INTF0;
> + break;
> default:
> if (mtx->data->mutex_mod[id] < 32) {
> offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg,
> @@ -462,6 +540,7 @@ void mtk_mutex_remove_comp(struct mtk_mutex *mutex,
> case DDP_COMPONENT_DSI3:
> case DDP_COMPONENT_DPI0:
> case DDP_COMPONENT_DPI1:
> + case DDP_COMPONENT_DP_INTF0:
> writel_relaxed(MUTEX_SOF_SINGLE_MODE,
> mtx->regs +
> DISP_REG_MUTEX_SOF(mtx->data->mutex_sof_reg,
> @@ -587,6 +666,8 @@ static const struct of_device_id mutex_driver_dt_match[] = {
> .data = &mt8186_mutex_driver_data},
> { .compatible = "mediatek,mt8192-disp-mutex",
> .data = &mt8192_mutex_driver_data},
> + { .compatible = "mediatek,mt8195-disp-mutex",
> + .data = &mt8195_mutex_driver_data},
> {},
> };
> MODULE_DEVICE_TABLE(of, mutex_driver_dt_match);
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [PATCH v20 2/8] soc: mediatek: add mtk-mutex support for mt8195 vdosys0
@ 2022-04-22 12:29 ` Matthias Brugger
0 siblings, 0 replies; 110+ messages in thread
From: Matthias Brugger @ 2022-04-22 12:29 UTC (permalink / raw)
To: jason-jh.lin, Chun-Kuang Hu, AngeloGioacchino Del Regno
Cc: CK Hu, Nancy Lin, Singo Chang, devicetree, linux-kernel,
dri-devel, linux-mediatek, linux-arm-kernel,
Project_Global_Chrome_Upstream_Group
On 19/04/2022 11:41, jason-jh.lin wrote:
> Add mtk-mutex support for mt8195 vdosys0.
>
> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> Acked-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> Tested-by: Fei Shao <fshao@chromium.org>
Applied thanks!
Matthias
> ---
> drivers/soc/mediatek/mtk-mutex.c | 87 ++++++++++++++++++++++++++++++--
> 1 file changed, 84 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c
> index aaf8fc1abb43..729ee88035ed 100644
> --- a/drivers/soc/mediatek/mtk-mutex.c
> +++ b/drivers/soc/mediatek/mtk-mutex.c
> @@ -17,6 +17,9 @@
> #define MT8183_MUTEX0_MOD0 0x30
> #define MT8183_MUTEX0_SOF0 0x2c
>
> +#define MT8195_DISP_MUTEX0_MOD0 0x30
> +#define MT8195_DISP_MUTEX0_SOF 0x2c
> +
> #define DISP_REG_MUTEX_EN(n) (0x20 + 0x20 * (n))
> #define DISP_REG_MUTEX(n) (0x24 + 0x20 * (n))
> #define DISP_REG_MUTEX_RST(n) (0x28 + 0x20 * (n))
> @@ -96,6 +99,20 @@
> #define MT8173_MUTEX_MOD_DISP_PWM1 24
> #define MT8173_MUTEX_MOD_DISP_OD 25
>
> +#define MT8195_MUTEX_MOD_DISP_OVL0 0
> +#define MT8195_MUTEX_MOD_DISP_WDMA0 1
> +#define MT8195_MUTEX_MOD_DISP_RDMA0 2
> +#define MT8195_MUTEX_MOD_DISP_COLOR0 3
> +#define MT8195_MUTEX_MOD_DISP_CCORR0 4
> +#define MT8195_MUTEX_MOD_DISP_AAL0 5
> +#define MT8195_MUTEX_MOD_DISP_GAMMA0 6
> +#define MT8195_MUTEX_MOD_DISP_DITHER0 7
> +#define MT8195_MUTEX_MOD_DISP_DSI0 8
> +#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0 9
> +#define MT8195_MUTEX_MOD_DISP_VPP_MERGE 20
> +#define MT8195_MUTEX_MOD_DISP_DP_INTF0 21
> +#define MT8195_MUTEX_MOD_DISP_PWM0 27
> +
> #define MT2712_MUTEX_MOD_DISP_PWM2 10
> #define MT2712_MUTEX_MOD_DISP_OVL0 11
> #define MT2712_MUTEX_MOD_DISP_OVL1 12
> @@ -132,9 +149,21 @@
> #define MT8167_MUTEX_SOF_DPI1 3
> #define MT8183_MUTEX_SOF_DSI0 1
> #define MT8183_MUTEX_SOF_DPI0 2
> +#define MT8195_MUTEX_SOF_DSI0 1
> +#define MT8195_MUTEX_SOF_DSI1 2
> +#define MT8195_MUTEX_SOF_DP_INTF0 3
> +#define MT8195_MUTEX_SOF_DP_INTF1 4
> +#define MT8195_MUTEX_SOF_DPI0 6 /* for HDMI_TX */
> +#define MT8195_MUTEX_SOF_DPI1 5 /* for digital video out */
>
> #define MT8183_MUTEX_EOF_DSI0 (MT8183_MUTEX_SOF_DSI0 << 6)
> #define MT8183_MUTEX_EOF_DPI0 (MT8183_MUTEX_SOF_DPI0 << 6)
> +#define MT8195_MUTEX_EOF_DSI0 (MT8195_MUTEX_SOF_DSI0 << 7)
> +#define MT8195_MUTEX_EOF_DSI1 (MT8195_MUTEX_SOF_DSI1 << 7)
> +#define MT8195_MUTEX_EOF_DP_INTF0 (MT8195_MUTEX_SOF_DP_INTF0 << 7)
> +#define MT8195_MUTEX_EOF_DP_INTF1 (MT8195_MUTEX_SOF_DP_INTF1 << 7)
> +#define MT8195_MUTEX_EOF_DPI0 (MT8195_MUTEX_SOF_DPI0 << 7)
> +#define MT8195_MUTEX_EOF_DPI1 (MT8195_MUTEX_SOF_DPI1 << 7)
>
> struct mtk_mutex {
> int id;
> @@ -149,6 +178,9 @@ enum mtk_mutex_sof_id {
> MUTEX_SOF_DPI1,
> MUTEX_SOF_DSI2,
> MUTEX_SOF_DSI3,
> + MUTEX_SOF_DP_INTF0,
> + MUTEX_SOF_DP_INTF1,
> + DDP_MUTEX_SOF_MAX,
> };
>
> struct mtk_mutex_data {
> @@ -270,7 +302,23 @@ static const unsigned int mt8192_mutex_mod[DDP_COMPONENT_ID_MAX] = {
> [DDP_COMPONENT_RDMA4] = MT8192_MUTEX_MOD_DISP_RDMA4,
> };
>
> -static const unsigned int mt2712_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
> +static const unsigned int mt8195_mutex_mod[DDP_COMPONENT_ID_MAX] = {
> + [DDP_COMPONENT_OVL0] = MT8195_MUTEX_MOD_DISP_OVL0,
> + [DDP_COMPONENT_WDMA0] = MT8195_MUTEX_MOD_DISP_WDMA0,
> + [DDP_COMPONENT_RDMA0] = MT8195_MUTEX_MOD_DISP_RDMA0,
> + [DDP_COMPONENT_COLOR0] = MT8195_MUTEX_MOD_DISP_COLOR0,
> + [DDP_COMPONENT_CCORR] = MT8195_MUTEX_MOD_DISP_CCORR0,
> + [DDP_COMPONENT_AAL0] = MT8195_MUTEX_MOD_DISP_AAL0,
> + [DDP_COMPONENT_GAMMA] = MT8195_MUTEX_MOD_DISP_GAMMA0,
> + [DDP_COMPONENT_DITHER] = MT8195_MUTEX_MOD_DISP_DITHER0,
> + [DDP_COMPONENT_MERGE0] = MT8195_MUTEX_MOD_DISP_VPP_MERGE,
> + [DDP_COMPONENT_DSC0] = MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0,
> + [DDP_COMPONENT_DSI0] = MT8195_MUTEX_MOD_DISP_DSI0,
> + [DDP_COMPONENT_PWM0] = MT8195_MUTEX_MOD_DISP_PWM0,
> + [DDP_COMPONENT_DP_INTF0] = MT8195_MUTEX_MOD_DISP_DP_INTF0,
> +};
> +
> +static const unsigned int mt2712_mutex_sof[DDP_MUTEX_SOF_MAX] = {
> [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
> [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0,
> [MUTEX_SOF_DSI1] = MUTEX_SOF_DSI1,
> @@ -280,7 +328,7 @@ static const unsigned int mt2712_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
> [MUTEX_SOF_DSI3] = MUTEX_SOF_DSI3,
> };
>
> -static const unsigned int mt8167_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
> +static const unsigned int mt8167_mutex_sof[DDP_MUTEX_SOF_MAX] = {
> [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
> [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0,
> [MUTEX_SOF_DPI0] = MT8167_MUTEX_SOF_DPI0,
> @@ -288,7 +336,7 @@ static const unsigned int mt8167_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
> };
>
> /* Add EOF setting so overlay hardware can receive frame done irq */
> -static const unsigned int mt8183_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
> +static const unsigned int mt8183_mutex_sof[DDP_MUTEX_SOF_MAX] = {
> [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
> [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0 | MT8183_MUTEX_EOF_DSI0,
> [MUTEX_SOF_DPI0] = MT8183_MUTEX_SOF_DPI0 | MT8183_MUTEX_EOF_DPI0,
> @@ -300,6 +348,26 @@ static const unsigned int mt8186_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
> [MUTEX_SOF_DPI0] = MT8186_MUTEX_SOF_DPI0 | MT8186_MUTEX_EOF_DPI0,
> };
>
> +/*
> + * To support refresh mode(video mode), DISP_REG_MUTEX_SOF should
> + * select the EOF source and configure the EOF plus timing from the
> + * module that provides the timing signal.
> + * So that MUTEX can not only send a STREAM_DONE event to GCE
> + * but also detect the error at end of frame(EAEOF) when EOF signal
> + * arrives.
> + */
> +static const unsigned int mt8195_mutex_sof[DDP_MUTEX_SOF_MAX] = {
> + [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
> + [MUTEX_SOF_DSI0] = MT8195_MUTEX_SOF_DSI0 | MT8195_MUTEX_EOF_DSI0,
> + [MUTEX_SOF_DSI1] = MT8195_MUTEX_SOF_DSI1 | MT8195_MUTEX_EOF_DSI1,
> + [MUTEX_SOF_DPI0] = MT8195_MUTEX_SOF_DPI0 | MT8195_MUTEX_EOF_DPI0,
> + [MUTEX_SOF_DPI1] = MT8195_MUTEX_SOF_DPI1 | MT8195_MUTEX_EOF_DPI1,
> + [MUTEX_SOF_DP_INTF0] =
> + MT8195_MUTEX_SOF_DP_INTF0 | MT8195_MUTEX_EOF_DP_INTF0,
> + [MUTEX_SOF_DP_INTF1] =
> + MT8195_MUTEX_SOF_DP_INTF1 | MT8195_MUTEX_EOF_DP_INTF1,
> +};
> +
> static const struct mtk_mutex_data mt2701_mutex_driver_data = {
> .mutex_mod = mt2701_mutex_mod,
> .mutex_sof = mt2712_mutex_sof,
> @@ -351,6 +419,13 @@ static const struct mtk_mutex_data mt8192_mutex_driver_data = {
> .mutex_sof_reg = MT8183_MUTEX0_SOF0,
> };
>
> +static const struct mtk_mutex_data mt8195_mutex_driver_data = {
> + .mutex_mod = mt8195_mutex_mod,
> + .mutex_sof = mt8195_mutex_sof,
> + .mutex_mod_reg = MT8195_DISP_MUTEX0_MOD0,
> + .mutex_sof_reg = MT8195_DISP_MUTEX0_SOF,
> +};
> +
> struct mtk_mutex *mtk_mutex_get(struct device *dev)
> {
> struct mtk_mutex_ctx *mtx = dev_get_drvdata(dev);
> @@ -423,6 +498,9 @@ void mtk_mutex_add_comp(struct mtk_mutex *mutex,
> case DDP_COMPONENT_DPI1:
> sof_id = MUTEX_SOF_DPI1;
> break;
> + case DDP_COMPONENT_DP_INTF0:
> + sof_id = MUTEX_SOF_DP_INTF0;
> + break;
> default:
> if (mtx->data->mutex_mod[id] < 32) {
> offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg,
> @@ -462,6 +540,7 @@ void mtk_mutex_remove_comp(struct mtk_mutex *mutex,
> case DDP_COMPONENT_DSI3:
> case DDP_COMPONENT_DPI0:
> case DDP_COMPONENT_DPI1:
> + case DDP_COMPONENT_DP_INTF0:
> writel_relaxed(MUTEX_SOF_SINGLE_MODE,
> mtx->regs +
> DISP_REG_MUTEX_SOF(mtx->data->mutex_sof_reg,
> @@ -587,6 +666,8 @@ static const struct of_device_id mutex_driver_dt_match[] = {
> .data = &mt8186_mutex_driver_data},
> { .compatible = "mediatek,mt8192-disp-mutex",
> .data = &mt8192_mutex_driver_data},
> + { .compatible = "mediatek,mt8195-disp-mutex",
> + .data = &mt8195_mutex_driver_data},
> {},
> };
> MODULE_DEVICE_TABLE(of, mutex_driver_dt_match);
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [PATCH v20 2/8] soc: mediatek: add mtk-mutex support for mt8195 vdosys0
2022-04-22 2:32 ` Jason-JH Lin
(?)
(?)
@ 2022-04-22 12:31 ` Matthias Brugger
-1 siblings, 0 replies; 110+ messages in thread
From: Matthias Brugger @ 2022-04-22 12:31 UTC (permalink / raw)
To: Jason-JH Lin, CK Hu, Chun-Kuang Hu, AngeloGioacchino Del Regno
Cc: Nancy Lin, Singo Chang, devicetree, linux-kernel, dri-devel,
linux-mediatek, linux-arm-kernel,
Project_Global_Chrome_Upstream_Group
On 22/04/2022 04:32, Jason-JH Lin wrote:
> Hi CK,
>
> Thanks for the reviews.
>
> On Thu, 2022-04-21 at 14:50 +0800, CK Hu wrote:
>> Hi, Jason:
>>
>> On Tue, 2022-04-19 at 17:41 +0800, jason-jh.lin wrote:
>>> Add mtk-mutex support for mt8195 vdosys0.
>>>
>>> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
>>> Acked-by: AngeloGioacchino Del Regno <
>>> angelogioacchino.delregno@collabora.com>
>>> Tested-by: Fei Shao <fshao@chromium.org>
>>> ---
>>> drivers/soc/mediatek/mtk-mutex.c | 87
>>> ++++++++++++++++++++++++++++++--
>>> 1 file changed, 84 insertions(+), 3 deletions(-)
>>>
>>> diff --git a/drivers/soc/mediatek/mtk-mutex.c
>>> b/drivers/soc/mediatek/mtk-mutex.c
>>> index aaf8fc1abb43..729ee88035ed 100644
>>> --- a/drivers/soc/mediatek/mtk-mutex.c
>>> +++ b/drivers/soc/mediatek/mtk-mutex.c
>>> @@ -17,6 +17,9 @@
>>> #define MT8183_MUTEX0_MOD0 0x30
>>> #define MT8183_MUTEX0_SOF0 0x2c
>>>
>>> +#define MT8195_DISP_MUTEX0_MOD0 0x30
>>> +#define MT8195_DISP_MUTEX0_SOF 0x2c
>>
>> This is identical to mt8183, so use mt8183 one instead of creating
>> new
>> one.
>>
>> Regards,
>> CK
>>
> I'll fix this in the next version.
Please send this as a follow-up fix on top of:
https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux.git/log/?h=v5.18-next/soc
Regards,
Matthias
>
> Regards,
> Jason-JH.Lin.
>>>
>>>
>>> +static const struct mtk_mutex_data mt8195_mutex_driver_data = {
>>> + .mutex_mod = mt8195_mutex_mod,
>>> + .mutex_sof = mt8195_mutex_sof,
>>> + .mutex_mod_reg = MT8195_DISP_MUTEX0_MOD0,
>>> + .mutex_sof_reg = MT8195_DISP_MUTEX0_SOF,
>>> +};
>>> +
>>>
>>
>>
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [PATCH v20 2/8] soc: mediatek: add mtk-mutex support for mt8195 vdosys0
@ 2022-04-22 12:31 ` Matthias Brugger
0 siblings, 0 replies; 110+ messages in thread
From: Matthias Brugger @ 2022-04-22 12:31 UTC (permalink / raw)
To: Jason-JH Lin, CK Hu, Chun-Kuang Hu, AngeloGioacchino Del Regno
Cc: devicetree, Singo Chang, linux-kernel, dri-devel,
Project_Global_Chrome_Upstream_Group, Nancy Lin, linux-mediatek,
linux-arm-kernel
On 22/04/2022 04:32, Jason-JH Lin wrote:
> Hi CK,
>
> Thanks for the reviews.
>
> On Thu, 2022-04-21 at 14:50 +0800, CK Hu wrote:
>> Hi, Jason:
>>
>> On Tue, 2022-04-19 at 17:41 +0800, jason-jh.lin wrote:
>>> Add mtk-mutex support for mt8195 vdosys0.
>>>
>>> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
>>> Acked-by: AngeloGioacchino Del Regno <
>>> angelogioacchino.delregno@collabora.com>
>>> Tested-by: Fei Shao <fshao@chromium.org>
>>> ---
>>> drivers/soc/mediatek/mtk-mutex.c | 87
>>> ++++++++++++++++++++++++++++++--
>>> 1 file changed, 84 insertions(+), 3 deletions(-)
>>>
>>> diff --git a/drivers/soc/mediatek/mtk-mutex.c
>>> b/drivers/soc/mediatek/mtk-mutex.c
>>> index aaf8fc1abb43..729ee88035ed 100644
>>> --- a/drivers/soc/mediatek/mtk-mutex.c
>>> +++ b/drivers/soc/mediatek/mtk-mutex.c
>>> @@ -17,6 +17,9 @@
>>> #define MT8183_MUTEX0_MOD0 0x30
>>> #define MT8183_MUTEX0_SOF0 0x2c
>>>
>>> +#define MT8195_DISP_MUTEX0_MOD0 0x30
>>> +#define MT8195_DISP_MUTEX0_SOF 0x2c
>>
>> This is identical to mt8183, so use mt8183 one instead of creating
>> new
>> one.
>>
>> Regards,
>> CK
>>
> I'll fix this in the next version.
Please send this as a follow-up fix on top of:
https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux.git/log/?h=v5.18-next/soc
Regards,
Matthias
>
> Regards,
> Jason-JH.Lin.
>>>
>>>
>>> +static const struct mtk_mutex_data mt8195_mutex_driver_data = {
>>> + .mutex_mod = mt8195_mutex_mod,
>>> + .mutex_sof = mt8195_mutex_sof,
>>> + .mutex_mod_reg = MT8195_DISP_MUTEX0_MOD0,
>>> + .mutex_sof_reg = MT8195_DISP_MUTEX0_SOF,
>>> +};
>>> +
>>>
>>
>>
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [PATCH v20 2/8] soc: mediatek: add mtk-mutex support for mt8195 vdosys0
@ 2022-04-22 12:31 ` Matthias Brugger
0 siblings, 0 replies; 110+ messages in thread
From: Matthias Brugger @ 2022-04-22 12:31 UTC (permalink / raw)
To: Jason-JH Lin, CK Hu, Chun-Kuang Hu, AngeloGioacchino Del Regno
Cc: Nancy Lin, Singo Chang, devicetree, linux-kernel, dri-devel,
linux-mediatek, linux-arm-kernel,
Project_Global_Chrome_Upstream_Group
On 22/04/2022 04:32, Jason-JH Lin wrote:
> Hi CK,
>
> Thanks for the reviews.
>
> On Thu, 2022-04-21 at 14:50 +0800, CK Hu wrote:
>> Hi, Jason:
>>
>> On Tue, 2022-04-19 at 17:41 +0800, jason-jh.lin wrote:
>>> Add mtk-mutex support for mt8195 vdosys0.
>>>
>>> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
>>> Acked-by: AngeloGioacchino Del Regno <
>>> angelogioacchino.delregno@collabora.com>
>>> Tested-by: Fei Shao <fshao@chromium.org>
>>> ---
>>> drivers/soc/mediatek/mtk-mutex.c | 87
>>> ++++++++++++++++++++++++++++++--
>>> 1 file changed, 84 insertions(+), 3 deletions(-)
>>>
>>> diff --git a/drivers/soc/mediatek/mtk-mutex.c
>>> b/drivers/soc/mediatek/mtk-mutex.c
>>> index aaf8fc1abb43..729ee88035ed 100644
>>> --- a/drivers/soc/mediatek/mtk-mutex.c
>>> +++ b/drivers/soc/mediatek/mtk-mutex.c
>>> @@ -17,6 +17,9 @@
>>> #define MT8183_MUTEX0_MOD0 0x30
>>> #define MT8183_MUTEX0_SOF0 0x2c
>>>
>>> +#define MT8195_DISP_MUTEX0_MOD0 0x30
>>> +#define MT8195_DISP_MUTEX0_SOF 0x2c
>>
>> This is identical to mt8183, so use mt8183 one instead of creating
>> new
>> one.
>>
>> Regards,
>> CK
>>
> I'll fix this in the next version.
Please send this as a follow-up fix on top of:
https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux.git/log/?h=v5.18-next/soc
Regards,
Matthias
>
> Regards,
> Jason-JH.Lin.
>>>
>>>
>>> +static const struct mtk_mutex_data mt8195_mutex_driver_data = {
>>> + .mutex_mod = mt8195_mutex_mod,
>>> + .mutex_sof = mt8195_mutex_sof,
>>> + .mutex_mod_reg = MT8195_DISP_MUTEX0_MOD0,
>>> + .mutex_sof_reg = MT8195_DISP_MUTEX0_SOF,
>>> +};
>>> +
>>>
>>
>>
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [PATCH v20 2/8] soc: mediatek: add mtk-mutex support for mt8195 vdosys0
@ 2022-04-22 12:31 ` Matthias Brugger
0 siblings, 0 replies; 110+ messages in thread
From: Matthias Brugger @ 2022-04-22 12:31 UTC (permalink / raw)
To: Jason-JH Lin, CK Hu, Chun-Kuang Hu, AngeloGioacchino Del Regno
Cc: Nancy Lin, Singo Chang, devicetree, linux-kernel, dri-devel,
linux-mediatek, linux-arm-kernel,
Project_Global_Chrome_Upstream_Group
On 22/04/2022 04:32, Jason-JH Lin wrote:
> Hi CK,
>
> Thanks for the reviews.
>
> On Thu, 2022-04-21 at 14:50 +0800, CK Hu wrote:
>> Hi, Jason:
>>
>> On Tue, 2022-04-19 at 17:41 +0800, jason-jh.lin wrote:
>>> Add mtk-mutex support for mt8195 vdosys0.
>>>
>>> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
>>> Acked-by: AngeloGioacchino Del Regno <
>>> angelogioacchino.delregno@collabora.com>
>>> Tested-by: Fei Shao <fshao@chromium.org>
>>> ---
>>> drivers/soc/mediatek/mtk-mutex.c | 87
>>> ++++++++++++++++++++++++++++++--
>>> 1 file changed, 84 insertions(+), 3 deletions(-)
>>>
>>> diff --git a/drivers/soc/mediatek/mtk-mutex.c
>>> b/drivers/soc/mediatek/mtk-mutex.c
>>> index aaf8fc1abb43..729ee88035ed 100644
>>> --- a/drivers/soc/mediatek/mtk-mutex.c
>>> +++ b/drivers/soc/mediatek/mtk-mutex.c
>>> @@ -17,6 +17,9 @@
>>> #define MT8183_MUTEX0_MOD0 0x30
>>> #define MT8183_MUTEX0_SOF0 0x2c
>>>
>>> +#define MT8195_DISP_MUTEX0_MOD0 0x30
>>> +#define MT8195_DISP_MUTEX0_SOF 0x2c
>>
>> This is identical to mt8183, so use mt8183 one instead of creating
>> new
>> one.
>>
>> Regards,
>> CK
>>
> I'll fix this in the next version.
Please send this as a follow-up fix on top of:
https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux.git/log/?h=v5.18-next/soc
Regards,
Matthias
>
> Regards,
> Jason-JH.Lin.
>>>
>>>
>>> +static const struct mtk_mutex_data mt8195_mutex_driver_data = {
>>> + .mutex_mod = mt8195_mutex_mod,
>>> + .mutex_sof = mt8195_mutex_sof,
>>> + .mutex_mod_reg = MT8195_DISP_MUTEX0_MOD0,
>>> + .mutex_sof_reg = MT8195_DISP_MUTEX0_SOF,
>>> +};
>>> +
>>>
>>
>>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [PATCH v20 6/8] soc: mediatek: add DDP_DOMPONENT_DITHER0 enum for mt8195 vdosys0
2022-04-19 9:41 ` jason-jh.lin
(?)
(?)
@ 2022-04-22 12:32 ` Matthias Brugger
-1 siblings, 0 replies; 110+ messages in thread
From: Matthias Brugger @ 2022-04-22 12:32 UTC (permalink / raw)
To: jason-jh.lin, Chun-Kuang Hu, AngeloGioacchino Del Regno
Cc: CK Hu, Nancy Lin, Singo Chang, devicetree, linux-kernel,
dri-devel, linux-mediatek, linux-arm-kernel,
Project_Global_Chrome_Upstream_Group
On 19/04/2022 11:41, jason-jh.lin wrote:
> The mmsys routing table of mt8195 vdosys0 has 2 DITHER components,
> so mmsys need to add DDP_COMPONENT_DITHER1 and change all usages of
> DITHER enum form DDP_COMPONENT_DITHER to DDP_COMPONENT_DITHER0.
>
> But its header need to keep DDP_COMPONENT_DITHER enum
> until drm/mediatek also changed it.
>
> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Applied, thanks!
> ---
> drivers/soc/mediatek/mt8167-mmsys.h | 2 +-
> drivers/soc/mediatek/mt8183-mmsys.h | 2 +-
> drivers/soc/mediatek/mt8186-mmsys.h | 4 ++--
> drivers/soc/mediatek/mt8192-mmsys.h | 4 ++--
> drivers/soc/mediatek/mt8195-mmsys.h | 8 ++++----
> drivers/soc/mediatek/mt8365-mmsys.h | 4 ++--
> drivers/soc/mediatek/mtk-mutex.c | 10 +++++-----
> include/linux/soc/mediatek/mtk-mmsys.h | 1 +
> 8 files changed, 18 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/soc/mediatek/mt8167-mmsys.h b/drivers/soc/mediatek/mt8167-mmsys.h
> index 2772ef5e3934..f7a35b3656bb 100644
> --- a/drivers/soc/mediatek/mt8167-mmsys.h
> +++ b/drivers/soc/mediatek/mt8167-mmsys.h
> @@ -18,7 +18,7 @@ static const struct mtk_mmsys_routes mt8167_mmsys_routing_table[] = {
> DDP_COMPONENT_OVL0, DDP_COMPONENT_COLOR0,
> MT8167_DISP_REG_CONFIG_DISP_OVL0_MOUT_EN, OVL0_MOUT_EN_COLOR0,
> }, {
> - DDP_COMPONENT_DITHER, DDP_COMPONENT_RDMA0,
> + DDP_COMPONENT_DITHER0, DDP_COMPONENT_RDMA0,
> MT8167_DISP_REG_CONFIG_DISP_DITHER_MOUT_EN, MT8167_DITHER_MOUT_EN_RDMA0
> }, {
> DDP_COMPONENT_OVL0, DDP_COMPONENT_COLOR0,
> diff --git a/drivers/soc/mediatek/mt8183-mmsys.h b/drivers/soc/mediatek/mt8183-mmsys.h
> index 0c021f4b76d2..ff6be1703469 100644
> --- a/drivers/soc/mediatek/mt8183-mmsys.h
> +++ b/drivers/soc/mediatek/mt8183-mmsys.h
> @@ -41,7 +41,7 @@ static const struct mtk_mmsys_routes mmsys_mt8183_routing_table[] = {
> MT8183_DISP_OVL1_2L_MOUT_EN, MT8183_OVL1_2L_MOUT_EN_RDMA1,
> MT8183_OVL1_2L_MOUT_EN_RDMA1
> }, {
> - DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
> + DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
> MT8183_DISP_DITHER0_MOUT_EN, MT8183_DITHER0_MOUT_IN_DSI0,
> MT8183_DITHER0_MOUT_IN_DSI0
> }, {
> diff --git a/drivers/soc/mediatek/mt8186-mmsys.h b/drivers/soc/mediatek/mt8186-mmsys.h
> index c72ccf86ea28..eb1ad9c37a9c 100644
> --- a/drivers/soc/mediatek/mt8186-mmsys.h
> +++ b/drivers/soc/mediatek/mt8186-mmsys.h
> @@ -76,12 +76,12 @@ static const struct mtk_mmsys_routes mmsys_mt8186_routing_table[] = {
> MT8186_RDMA0_SOUT_TO_COLOR0
> },
> {
> - DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
> + DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
> MT8186_DISP_DITHER0_MOUT_EN, MT8186_DITHER0_MOUT_EN_MASK,
> MT8186_DITHER0_MOUT_TO_DSI0,
> },
> {
> - DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
> + DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
> MT8186_DISP_DSI0_SEL_IN, MT8186_DSI0_SEL_IN_MASK,
> MT8186_DSI0_FROM_DITHER0
> },
> diff --git a/drivers/soc/mediatek/mt8192-mmsys.h b/drivers/soc/mediatek/mt8192-mmsys.h
> index 6aae0b12b6ff..a016d80b4bc1 100644
> --- a/drivers/soc/mediatek/mt8192-mmsys.h
> +++ b/drivers/soc/mediatek/mt8192-mmsys.h
> @@ -40,7 +40,7 @@ static const struct mtk_mmsys_routes mmsys_mt8192_routing_table[] = {
> MT8192_DISP_OVL2_2L_MOUT_EN, MT8192_OVL2_2L_MOUT_EN_RDMA4,
> MT8192_OVL2_2L_MOUT_EN_RDMA4
> }, {
> - DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
> + DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
> MT8192_DISP_DITHER0_MOUT_EN, MT8192_DITHER0_MOUT_IN_DSI0,
> MT8192_DITHER0_MOUT_IN_DSI0
> }, {
> @@ -52,7 +52,7 @@ static const struct mtk_mmsys_routes mmsys_mt8192_routing_table[] = {
> MT8192_DISP_AAL0_SEL_IN, MT8192_AAL0_SEL_IN_CCORR0,
> MT8192_AAL0_SEL_IN_CCORR0
> }, {
> - DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
> + DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
> MT8192_DISP_DSI0_SEL_IN, MT8192_DSI0_SEL_IN_DITHER0,
> MT8192_DSI0_SEL_IN_DITHER0
> }, {
> diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h
> index 13ab0ab64396..abfe94a30248 100644
> --- a/drivers/soc/mediatek/mt8195-mmsys.h
> +++ b/drivers/soc/mediatek/mt8195-mmsys.h
> @@ -113,7 +113,7 @@ static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
> MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK,
> MT8195_SEL_IN_VPP_MERGE_FROM_VDO1_VIRTUAL0
> }, {
> - DDP_COMPONENT_DITHER, DDP_COMPONENT_DSC0,
> + DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSC0,
> MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK,
> MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0
> }, {
> @@ -181,7 +181,7 @@ static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
> MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI0_FROM_MASK,
> MT8195_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT
> }, {
> - DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
> + DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
> MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI0_FROM_MASK,
> MT8195_SEL_IN_DSI0_FROM_DISP_DITHER0
> }, {
> @@ -245,11 +245,11 @@ static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
> MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA0_FROM_MASK,
> MT8195_SEL_IN_DISP_WDMA0_FROM_DISP_OVL0
> }, {
> - DDP_COMPONENT_DITHER, DDP_COMPONENT_DSC0,
> + DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSC0,
> MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER0_TO_MASK,
> MT8195_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN
> }, {
> - DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
> + DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
> MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER0_TO_MASK,
> MT8195_SOUT_DISP_DITHER0_TO_DSI0
> }, {
> diff --git a/drivers/soc/mediatek/mt8365-mmsys.h b/drivers/soc/mediatek/mt8365-mmsys.h
> index 690e3fe2dee0..24129a6c25f8 100644
> --- a/drivers/soc/mediatek/mt8365-mmsys.h
> +++ b/drivers/soc/mediatek/mt8365-mmsys.h
> @@ -41,12 +41,12 @@ static const struct mtk_mmsys_routes mt8365_mmsys_routing_table[] = {
> MT8365_DISP_COLOR_SEL_IN_COLOR0,MT8365_DISP_COLOR_SEL_IN_COLOR0
> },
> {
> - DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
> + DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
> MT8365_DISP_REG_CONFIG_DISP_DITHER0_MOUT_EN,
> MT8365_DITHER_MOUT_EN_DSI0, MT8365_DITHER_MOUT_EN_DSI0
> },
> {
> - DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
> + DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
> MT8365_DISP_REG_CONFIG_DISP_DSI0_SEL_IN,
> MT8365_DSI0_SEL_IN_DITHER, MT8365_DSI0_SEL_IN_DITHER
> },
> diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c
> index 729ee88035ed..9184684baf1d 100644
> --- a/drivers/soc/mediatek/mtk-mutex.c
> +++ b/drivers/soc/mediatek/mtk-mutex.c
> @@ -232,7 +232,7 @@ static const unsigned int mt8167_mutex_mod[DDP_COMPONENT_ID_MAX] = {
> [DDP_COMPONENT_AAL0] = MT8167_MUTEX_MOD_DISP_AAL,
> [DDP_COMPONENT_CCORR] = MT8167_MUTEX_MOD_DISP_CCORR,
> [DDP_COMPONENT_COLOR0] = MT8167_MUTEX_MOD_DISP_COLOR,
> - [DDP_COMPONENT_DITHER] = MT8167_MUTEX_MOD_DISP_DITHER,
> + [DDP_COMPONENT_DITHER0] = MT8167_MUTEX_MOD_DISP_DITHER,
> [DDP_COMPONENT_GAMMA] = MT8167_MUTEX_MOD_DISP_GAMMA,
> [DDP_COMPONENT_OVL0] = MT8167_MUTEX_MOD_DISP_OVL0,
> [DDP_COMPONENT_OVL1] = MT8167_MUTEX_MOD_DISP_OVL1,
> @@ -265,7 +265,7 @@ static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = {
> [DDP_COMPONENT_AAL0] = MT8183_MUTEX_MOD_DISP_AAL0,
> [DDP_COMPONENT_CCORR] = MT8183_MUTEX_MOD_DISP_CCORR0,
> [DDP_COMPONENT_COLOR0] = MT8183_MUTEX_MOD_DISP_COLOR0,
> - [DDP_COMPONENT_DITHER] = MT8183_MUTEX_MOD_DISP_DITHER0,
> + [DDP_COMPONENT_DITHER0] = MT8183_MUTEX_MOD_DISP_DITHER0,
> [DDP_COMPONENT_GAMMA] = MT8183_MUTEX_MOD_DISP_GAMMA0,
> [DDP_COMPONENT_OVL0] = MT8183_MUTEX_MOD_DISP_OVL0,
> [DDP_COMPONENT_OVL_2L0] = MT8183_MUTEX_MOD_DISP_OVL0_2L,
> @@ -279,7 +279,7 @@ static const unsigned int mt8186_mutex_mod[DDP_COMPONENT_ID_MAX] = {
> [DDP_COMPONENT_AAL0] = MT8186_MUTEX_MOD_DISP_AAL0,
> [DDP_COMPONENT_CCORR] = MT8186_MUTEX_MOD_DISP_CCORR0,
> [DDP_COMPONENT_COLOR0] = MT8186_MUTEX_MOD_DISP_COLOR0,
> - [DDP_COMPONENT_DITHER] = MT8186_MUTEX_MOD_DISP_DITHER0,
> + [DDP_COMPONENT_DITHER0] = MT8186_MUTEX_MOD_DISP_DITHER0,
> [DDP_COMPONENT_GAMMA] = MT8186_MUTEX_MOD_DISP_GAMMA0,
> [DDP_COMPONENT_OVL0] = MT8186_MUTEX_MOD_DISP_OVL0,
> [DDP_COMPONENT_OVL_2L0] = MT8186_MUTEX_MOD_DISP_OVL0_2L,
> @@ -292,7 +292,7 @@ static const unsigned int mt8192_mutex_mod[DDP_COMPONENT_ID_MAX] = {
> [DDP_COMPONENT_AAL0] = MT8192_MUTEX_MOD_DISP_AAL0,
> [DDP_COMPONENT_CCORR] = MT8192_MUTEX_MOD_DISP_CCORR0,
> [DDP_COMPONENT_COLOR0] = MT8192_MUTEX_MOD_DISP_COLOR0,
> - [DDP_COMPONENT_DITHER] = MT8192_MUTEX_MOD_DISP_DITHER0,
> + [DDP_COMPONENT_DITHER0] = MT8192_MUTEX_MOD_DISP_DITHER0,
> [DDP_COMPONENT_GAMMA] = MT8192_MUTEX_MOD_DISP_GAMMA0,
> [DDP_COMPONENT_POSTMASK0] = MT8192_MUTEX_MOD_DISP_POSTMASK0,
> [DDP_COMPONENT_OVL0] = MT8192_MUTEX_MOD_DISP_OVL0,
> @@ -310,7 +310,7 @@ static const unsigned int mt8195_mutex_mod[DDP_COMPONENT_ID_MAX] = {
> [DDP_COMPONENT_CCORR] = MT8195_MUTEX_MOD_DISP_CCORR0,
> [DDP_COMPONENT_AAL0] = MT8195_MUTEX_MOD_DISP_AAL0,
> [DDP_COMPONENT_GAMMA] = MT8195_MUTEX_MOD_DISP_GAMMA0,
> - [DDP_COMPONENT_DITHER] = MT8195_MUTEX_MOD_DISP_DITHER0,
> + [DDP_COMPONENT_DITHER0] = MT8195_MUTEX_MOD_DISP_DITHER0,
> [DDP_COMPONENT_MERGE0] = MT8195_MUTEX_MOD_DISP_VPP_MERGE,
> [DDP_COMPONENT_DSC0] = MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0,
> [DDP_COMPONENT_DSI0] = MT8195_MUTEX_MOD_DISP_DSI0,
> diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
> index cff5c9adbf46..59117d970daf 100644
> --- a/include/linux/soc/mediatek/mtk-mmsys.h
> +++ b/include/linux/soc/mediatek/mtk-mmsys.h
> @@ -17,6 +17,7 @@ enum mtk_ddp_comp_id {
> DDP_COMPONENT_COLOR0,
> DDP_COMPONENT_COLOR1,
> DDP_COMPONENT_DITHER,
> + DDP_COMPONENT_DITHER0 = DDP_COMPONENT_DITHER,
> DDP_COMPONENT_DITHER1,
> DDP_COMPONENT_DP_INTF0,
> DDP_COMPONENT_DP_INTF1,
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [PATCH v20 6/8] soc: mediatek: add DDP_DOMPONENT_DITHER0 enum for mt8195 vdosys0
@ 2022-04-22 12:32 ` Matthias Brugger
0 siblings, 0 replies; 110+ messages in thread
From: Matthias Brugger @ 2022-04-22 12:32 UTC (permalink / raw)
To: jason-jh.lin, Chun-Kuang Hu, AngeloGioacchino Del Regno
Cc: devicetree, Singo Chang, linux-kernel, dri-devel,
Project_Global_Chrome_Upstream_Group, Nancy Lin, linux-mediatek,
linux-arm-kernel
On 19/04/2022 11:41, jason-jh.lin wrote:
> The mmsys routing table of mt8195 vdosys0 has 2 DITHER components,
> so mmsys need to add DDP_COMPONENT_DITHER1 and change all usages of
> DITHER enum form DDP_COMPONENT_DITHER to DDP_COMPONENT_DITHER0.
>
> But its header need to keep DDP_COMPONENT_DITHER enum
> until drm/mediatek also changed it.
>
> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Applied, thanks!
> ---
> drivers/soc/mediatek/mt8167-mmsys.h | 2 +-
> drivers/soc/mediatek/mt8183-mmsys.h | 2 +-
> drivers/soc/mediatek/mt8186-mmsys.h | 4 ++--
> drivers/soc/mediatek/mt8192-mmsys.h | 4 ++--
> drivers/soc/mediatek/mt8195-mmsys.h | 8 ++++----
> drivers/soc/mediatek/mt8365-mmsys.h | 4 ++--
> drivers/soc/mediatek/mtk-mutex.c | 10 +++++-----
> include/linux/soc/mediatek/mtk-mmsys.h | 1 +
> 8 files changed, 18 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/soc/mediatek/mt8167-mmsys.h b/drivers/soc/mediatek/mt8167-mmsys.h
> index 2772ef5e3934..f7a35b3656bb 100644
> --- a/drivers/soc/mediatek/mt8167-mmsys.h
> +++ b/drivers/soc/mediatek/mt8167-mmsys.h
> @@ -18,7 +18,7 @@ static const struct mtk_mmsys_routes mt8167_mmsys_routing_table[] = {
> DDP_COMPONENT_OVL0, DDP_COMPONENT_COLOR0,
> MT8167_DISP_REG_CONFIG_DISP_OVL0_MOUT_EN, OVL0_MOUT_EN_COLOR0,
> }, {
> - DDP_COMPONENT_DITHER, DDP_COMPONENT_RDMA0,
> + DDP_COMPONENT_DITHER0, DDP_COMPONENT_RDMA0,
> MT8167_DISP_REG_CONFIG_DISP_DITHER_MOUT_EN, MT8167_DITHER_MOUT_EN_RDMA0
> }, {
> DDP_COMPONENT_OVL0, DDP_COMPONENT_COLOR0,
> diff --git a/drivers/soc/mediatek/mt8183-mmsys.h b/drivers/soc/mediatek/mt8183-mmsys.h
> index 0c021f4b76d2..ff6be1703469 100644
> --- a/drivers/soc/mediatek/mt8183-mmsys.h
> +++ b/drivers/soc/mediatek/mt8183-mmsys.h
> @@ -41,7 +41,7 @@ static const struct mtk_mmsys_routes mmsys_mt8183_routing_table[] = {
> MT8183_DISP_OVL1_2L_MOUT_EN, MT8183_OVL1_2L_MOUT_EN_RDMA1,
> MT8183_OVL1_2L_MOUT_EN_RDMA1
> }, {
> - DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
> + DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
> MT8183_DISP_DITHER0_MOUT_EN, MT8183_DITHER0_MOUT_IN_DSI0,
> MT8183_DITHER0_MOUT_IN_DSI0
> }, {
> diff --git a/drivers/soc/mediatek/mt8186-mmsys.h b/drivers/soc/mediatek/mt8186-mmsys.h
> index c72ccf86ea28..eb1ad9c37a9c 100644
> --- a/drivers/soc/mediatek/mt8186-mmsys.h
> +++ b/drivers/soc/mediatek/mt8186-mmsys.h
> @@ -76,12 +76,12 @@ static const struct mtk_mmsys_routes mmsys_mt8186_routing_table[] = {
> MT8186_RDMA0_SOUT_TO_COLOR0
> },
> {
> - DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
> + DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
> MT8186_DISP_DITHER0_MOUT_EN, MT8186_DITHER0_MOUT_EN_MASK,
> MT8186_DITHER0_MOUT_TO_DSI0,
> },
> {
> - DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
> + DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
> MT8186_DISP_DSI0_SEL_IN, MT8186_DSI0_SEL_IN_MASK,
> MT8186_DSI0_FROM_DITHER0
> },
> diff --git a/drivers/soc/mediatek/mt8192-mmsys.h b/drivers/soc/mediatek/mt8192-mmsys.h
> index 6aae0b12b6ff..a016d80b4bc1 100644
> --- a/drivers/soc/mediatek/mt8192-mmsys.h
> +++ b/drivers/soc/mediatek/mt8192-mmsys.h
> @@ -40,7 +40,7 @@ static const struct mtk_mmsys_routes mmsys_mt8192_routing_table[] = {
> MT8192_DISP_OVL2_2L_MOUT_EN, MT8192_OVL2_2L_MOUT_EN_RDMA4,
> MT8192_OVL2_2L_MOUT_EN_RDMA4
> }, {
> - DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
> + DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
> MT8192_DISP_DITHER0_MOUT_EN, MT8192_DITHER0_MOUT_IN_DSI0,
> MT8192_DITHER0_MOUT_IN_DSI0
> }, {
> @@ -52,7 +52,7 @@ static const struct mtk_mmsys_routes mmsys_mt8192_routing_table[] = {
> MT8192_DISP_AAL0_SEL_IN, MT8192_AAL0_SEL_IN_CCORR0,
> MT8192_AAL0_SEL_IN_CCORR0
> }, {
> - DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
> + DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
> MT8192_DISP_DSI0_SEL_IN, MT8192_DSI0_SEL_IN_DITHER0,
> MT8192_DSI0_SEL_IN_DITHER0
> }, {
> diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h
> index 13ab0ab64396..abfe94a30248 100644
> --- a/drivers/soc/mediatek/mt8195-mmsys.h
> +++ b/drivers/soc/mediatek/mt8195-mmsys.h
> @@ -113,7 +113,7 @@ static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
> MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK,
> MT8195_SEL_IN_VPP_MERGE_FROM_VDO1_VIRTUAL0
> }, {
> - DDP_COMPONENT_DITHER, DDP_COMPONENT_DSC0,
> + DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSC0,
> MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK,
> MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0
> }, {
> @@ -181,7 +181,7 @@ static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
> MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI0_FROM_MASK,
> MT8195_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT
> }, {
> - DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
> + DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
> MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI0_FROM_MASK,
> MT8195_SEL_IN_DSI0_FROM_DISP_DITHER0
> }, {
> @@ -245,11 +245,11 @@ static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
> MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA0_FROM_MASK,
> MT8195_SEL_IN_DISP_WDMA0_FROM_DISP_OVL0
> }, {
> - DDP_COMPONENT_DITHER, DDP_COMPONENT_DSC0,
> + DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSC0,
> MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER0_TO_MASK,
> MT8195_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN
> }, {
> - DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
> + DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
> MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER0_TO_MASK,
> MT8195_SOUT_DISP_DITHER0_TO_DSI0
> }, {
> diff --git a/drivers/soc/mediatek/mt8365-mmsys.h b/drivers/soc/mediatek/mt8365-mmsys.h
> index 690e3fe2dee0..24129a6c25f8 100644
> --- a/drivers/soc/mediatek/mt8365-mmsys.h
> +++ b/drivers/soc/mediatek/mt8365-mmsys.h
> @@ -41,12 +41,12 @@ static const struct mtk_mmsys_routes mt8365_mmsys_routing_table[] = {
> MT8365_DISP_COLOR_SEL_IN_COLOR0,MT8365_DISP_COLOR_SEL_IN_COLOR0
> },
> {
> - DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
> + DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
> MT8365_DISP_REG_CONFIG_DISP_DITHER0_MOUT_EN,
> MT8365_DITHER_MOUT_EN_DSI0, MT8365_DITHER_MOUT_EN_DSI0
> },
> {
> - DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
> + DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
> MT8365_DISP_REG_CONFIG_DISP_DSI0_SEL_IN,
> MT8365_DSI0_SEL_IN_DITHER, MT8365_DSI0_SEL_IN_DITHER
> },
> diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c
> index 729ee88035ed..9184684baf1d 100644
> --- a/drivers/soc/mediatek/mtk-mutex.c
> +++ b/drivers/soc/mediatek/mtk-mutex.c
> @@ -232,7 +232,7 @@ static const unsigned int mt8167_mutex_mod[DDP_COMPONENT_ID_MAX] = {
> [DDP_COMPONENT_AAL0] = MT8167_MUTEX_MOD_DISP_AAL,
> [DDP_COMPONENT_CCORR] = MT8167_MUTEX_MOD_DISP_CCORR,
> [DDP_COMPONENT_COLOR0] = MT8167_MUTEX_MOD_DISP_COLOR,
> - [DDP_COMPONENT_DITHER] = MT8167_MUTEX_MOD_DISP_DITHER,
> + [DDP_COMPONENT_DITHER0] = MT8167_MUTEX_MOD_DISP_DITHER,
> [DDP_COMPONENT_GAMMA] = MT8167_MUTEX_MOD_DISP_GAMMA,
> [DDP_COMPONENT_OVL0] = MT8167_MUTEX_MOD_DISP_OVL0,
> [DDP_COMPONENT_OVL1] = MT8167_MUTEX_MOD_DISP_OVL1,
> @@ -265,7 +265,7 @@ static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = {
> [DDP_COMPONENT_AAL0] = MT8183_MUTEX_MOD_DISP_AAL0,
> [DDP_COMPONENT_CCORR] = MT8183_MUTEX_MOD_DISP_CCORR0,
> [DDP_COMPONENT_COLOR0] = MT8183_MUTEX_MOD_DISP_COLOR0,
> - [DDP_COMPONENT_DITHER] = MT8183_MUTEX_MOD_DISP_DITHER0,
> + [DDP_COMPONENT_DITHER0] = MT8183_MUTEX_MOD_DISP_DITHER0,
> [DDP_COMPONENT_GAMMA] = MT8183_MUTEX_MOD_DISP_GAMMA0,
> [DDP_COMPONENT_OVL0] = MT8183_MUTEX_MOD_DISP_OVL0,
> [DDP_COMPONENT_OVL_2L0] = MT8183_MUTEX_MOD_DISP_OVL0_2L,
> @@ -279,7 +279,7 @@ static const unsigned int mt8186_mutex_mod[DDP_COMPONENT_ID_MAX] = {
> [DDP_COMPONENT_AAL0] = MT8186_MUTEX_MOD_DISP_AAL0,
> [DDP_COMPONENT_CCORR] = MT8186_MUTEX_MOD_DISP_CCORR0,
> [DDP_COMPONENT_COLOR0] = MT8186_MUTEX_MOD_DISP_COLOR0,
> - [DDP_COMPONENT_DITHER] = MT8186_MUTEX_MOD_DISP_DITHER0,
> + [DDP_COMPONENT_DITHER0] = MT8186_MUTEX_MOD_DISP_DITHER0,
> [DDP_COMPONENT_GAMMA] = MT8186_MUTEX_MOD_DISP_GAMMA0,
> [DDP_COMPONENT_OVL0] = MT8186_MUTEX_MOD_DISP_OVL0,
> [DDP_COMPONENT_OVL_2L0] = MT8186_MUTEX_MOD_DISP_OVL0_2L,
> @@ -292,7 +292,7 @@ static const unsigned int mt8192_mutex_mod[DDP_COMPONENT_ID_MAX] = {
> [DDP_COMPONENT_AAL0] = MT8192_MUTEX_MOD_DISP_AAL0,
> [DDP_COMPONENT_CCORR] = MT8192_MUTEX_MOD_DISP_CCORR0,
> [DDP_COMPONENT_COLOR0] = MT8192_MUTEX_MOD_DISP_COLOR0,
> - [DDP_COMPONENT_DITHER] = MT8192_MUTEX_MOD_DISP_DITHER0,
> + [DDP_COMPONENT_DITHER0] = MT8192_MUTEX_MOD_DISP_DITHER0,
> [DDP_COMPONENT_GAMMA] = MT8192_MUTEX_MOD_DISP_GAMMA0,
> [DDP_COMPONENT_POSTMASK0] = MT8192_MUTEX_MOD_DISP_POSTMASK0,
> [DDP_COMPONENT_OVL0] = MT8192_MUTEX_MOD_DISP_OVL0,
> @@ -310,7 +310,7 @@ static const unsigned int mt8195_mutex_mod[DDP_COMPONENT_ID_MAX] = {
> [DDP_COMPONENT_CCORR] = MT8195_MUTEX_MOD_DISP_CCORR0,
> [DDP_COMPONENT_AAL0] = MT8195_MUTEX_MOD_DISP_AAL0,
> [DDP_COMPONENT_GAMMA] = MT8195_MUTEX_MOD_DISP_GAMMA0,
> - [DDP_COMPONENT_DITHER] = MT8195_MUTEX_MOD_DISP_DITHER0,
> + [DDP_COMPONENT_DITHER0] = MT8195_MUTEX_MOD_DISP_DITHER0,
> [DDP_COMPONENT_MERGE0] = MT8195_MUTEX_MOD_DISP_VPP_MERGE,
> [DDP_COMPONENT_DSC0] = MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0,
> [DDP_COMPONENT_DSI0] = MT8195_MUTEX_MOD_DISP_DSI0,
> diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
> index cff5c9adbf46..59117d970daf 100644
> --- a/include/linux/soc/mediatek/mtk-mmsys.h
> +++ b/include/linux/soc/mediatek/mtk-mmsys.h
> @@ -17,6 +17,7 @@ enum mtk_ddp_comp_id {
> DDP_COMPONENT_COLOR0,
> DDP_COMPONENT_COLOR1,
> DDP_COMPONENT_DITHER,
> + DDP_COMPONENT_DITHER0 = DDP_COMPONENT_DITHER,
> DDP_COMPONENT_DITHER1,
> DDP_COMPONENT_DP_INTF0,
> DDP_COMPONENT_DP_INTF1,
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [PATCH v20 6/8] soc: mediatek: add DDP_DOMPONENT_DITHER0 enum for mt8195 vdosys0
@ 2022-04-22 12:32 ` Matthias Brugger
0 siblings, 0 replies; 110+ messages in thread
From: Matthias Brugger @ 2022-04-22 12:32 UTC (permalink / raw)
To: jason-jh.lin, Chun-Kuang Hu, AngeloGioacchino Del Regno
Cc: CK Hu, Nancy Lin, Singo Chang, devicetree, linux-kernel,
dri-devel, linux-mediatek, linux-arm-kernel,
Project_Global_Chrome_Upstream_Group
On 19/04/2022 11:41, jason-jh.lin wrote:
> The mmsys routing table of mt8195 vdosys0 has 2 DITHER components,
> so mmsys need to add DDP_COMPONENT_DITHER1 and change all usages of
> DITHER enum form DDP_COMPONENT_DITHER to DDP_COMPONENT_DITHER0.
>
> But its header need to keep DDP_COMPONENT_DITHER enum
> until drm/mediatek also changed it.
>
> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Applied, thanks!
> ---
> drivers/soc/mediatek/mt8167-mmsys.h | 2 +-
> drivers/soc/mediatek/mt8183-mmsys.h | 2 +-
> drivers/soc/mediatek/mt8186-mmsys.h | 4 ++--
> drivers/soc/mediatek/mt8192-mmsys.h | 4 ++--
> drivers/soc/mediatek/mt8195-mmsys.h | 8 ++++----
> drivers/soc/mediatek/mt8365-mmsys.h | 4 ++--
> drivers/soc/mediatek/mtk-mutex.c | 10 +++++-----
> include/linux/soc/mediatek/mtk-mmsys.h | 1 +
> 8 files changed, 18 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/soc/mediatek/mt8167-mmsys.h b/drivers/soc/mediatek/mt8167-mmsys.h
> index 2772ef5e3934..f7a35b3656bb 100644
> --- a/drivers/soc/mediatek/mt8167-mmsys.h
> +++ b/drivers/soc/mediatek/mt8167-mmsys.h
> @@ -18,7 +18,7 @@ static const struct mtk_mmsys_routes mt8167_mmsys_routing_table[] = {
> DDP_COMPONENT_OVL0, DDP_COMPONENT_COLOR0,
> MT8167_DISP_REG_CONFIG_DISP_OVL0_MOUT_EN, OVL0_MOUT_EN_COLOR0,
> }, {
> - DDP_COMPONENT_DITHER, DDP_COMPONENT_RDMA0,
> + DDP_COMPONENT_DITHER0, DDP_COMPONENT_RDMA0,
> MT8167_DISP_REG_CONFIG_DISP_DITHER_MOUT_EN, MT8167_DITHER_MOUT_EN_RDMA0
> }, {
> DDP_COMPONENT_OVL0, DDP_COMPONENT_COLOR0,
> diff --git a/drivers/soc/mediatek/mt8183-mmsys.h b/drivers/soc/mediatek/mt8183-mmsys.h
> index 0c021f4b76d2..ff6be1703469 100644
> --- a/drivers/soc/mediatek/mt8183-mmsys.h
> +++ b/drivers/soc/mediatek/mt8183-mmsys.h
> @@ -41,7 +41,7 @@ static const struct mtk_mmsys_routes mmsys_mt8183_routing_table[] = {
> MT8183_DISP_OVL1_2L_MOUT_EN, MT8183_OVL1_2L_MOUT_EN_RDMA1,
> MT8183_OVL1_2L_MOUT_EN_RDMA1
> }, {
> - DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
> + DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
> MT8183_DISP_DITHER0_MOUT_EN, MT8183_DITHER0_MOUT_IN_DSI0,
> MT8183_DITHER0_MOUT_IN_DSI0
> }, {
> diff --git a/drivers/soc/mediatek/mt8186-mmsys.h b/drivers/soc/mediatek/mt8186-mmsys.h
> index c72ccf86ea28..eb1ad9c37a9c 100644
> --- a/drivers/soc/mediatek/mt8186-mmsys.h
> +++ b/drivers/soc/mediatek/mt8186-mmsys.h
> @@ -76,12 +76,12 @@ static const struct mtk_mmsys_routes mmsys_mt8186_routing_table[] = {
> MT8186_RDMA0_SOUT_TO_COLOR0
> },
> {
> - DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
> + DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
> MT8186_DISP_DITHER0_MOUT_EN, MT8186_DITHER0_MOUT_EN_MASK,
> MT8186_DITHER0_MOUT_TO_DSI0,
> },
> {
> - DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
> + DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
> MT8186_DISP_DSI0_SEL_IN, MT8186_DSI0_SEL_IN_MASK,
> MT8186_DSI0_FROM_DITHER0
> },
> diff --git a/drivers/soc/mediatek/mt8192-mmsys.h b/drivers/soc/mediatek/mt8192-mmsys.h
> index 6aae0b12b6ff..a016d80b4bc1 100644
> --- a/drivers/soc/mediatek/mt8192-mmsys.h
> +++ b/drivers/soc/mediatek/mt8192-mmsys.h
> @@ -40,7 +40,7 @@ static const struct mtk_mmsys_routes mmsys_mt8192_routing_table[] = {
> MT8192_DISP_OVL2_2L_MOUT_EN, MT8192_OVL2_2L_MOUT_EN_RDMA4,
> MT8192_OVL2_2L_MOUT_EN_RDMA4
> }, {
> - DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
> + DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
> MT8192_DISP_DITHER0_MOUT_EN, MT8192_DITHER0_MOUT_IN_DSI0,
> MT8192_DITHER0_MOUT_IN_DSI0
> }, {
> @@ -52,7 +52,7 @@ static const struct mtk_mmsys_routes mmsys_mt8192_routing_table[] = {
> MT8192_DISP_AAL0_SEL_IN, MT8192_AAL0_SEL_IN_CCORR0,
> MT8192_AAL0_SEL_IN_CCORR0
> }, {
> - DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
> + DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
> MT8192_DISP_DSI0_SEL_IN, MT8192_DSI0_SEL_IN_DITHER0,
> MT8192_DSI0_SEL_IN_DITHER0
> }, {
> diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h
> index 13ab0ab64396..abfe94a30248 100644
> --- a/drivers/soc/mediatek/mt8195-mmsys.h
> +++ b/drivers/soc/mediatek/mt8195-mmsys.h
> @@ -113,7 +113,7 @@ static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
> MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK,
> MT8195_SEL_IN_VPP_MERGE_FROM_VDO1_VIRTUAL0
> }, {
> - DDP_COMPONENT_DITHER, DDP_COMPONENT_DSC0,
> + DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSC0,
> MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK,
> MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0
> }, {
> @@ -181,7 +181,7 @@ static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
> MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI0_FROM_MASK,
> MT8195_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT
> }, {
> - DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
> + DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
> MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI0_FROM_MASK,
> MT8195_SEL_IN_DSI0_FROM_DISP_DITHER0
> }, {
> @@ -245,11 +245,11 @@ static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
> MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA0_FROM_MASK,
> MT8195_SEL_IN_DISP_WDMA0_FROM_DISP_OVL0
> }, {
> - DDP_COMPONENT_DITHER, DDP_COMPONENT_DSC0,
> + DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSC0,
> MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER0_TO_MASK,
> MT8195_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN
> }, {
> - DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
> + DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
> MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER0_TO_MASK,
> MT8195_SOUT_DISP_DITHER0_TO_DSI0
> }, {
> diff --git a/drivers/soc/mediatek/mt8365-mmsys.h b/drivers/soc/mediatek/mt8365-mmsys.h
> index 690e3fe2dee0..24129a6c25f8 100644
> --- a/drivers/soc/mediatek/mt8365-mmsys.h
> +++ b/drivers/soc/mediatek/mt8365-mmsys.h
> @@ -41,12 +41,12 @@ static const struct mtk_mmsys_routes mt8365_mmsys_routing_table[] = {
> MT8365_DISP_COLOR_SEL_IN_COLOR0,MT8365_DISP_COLOR_SEL_IN_COLOR0
> },
> {
> - DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
> + DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
> MT8365_DISP_REG_CONFIG_DISP_DITHER0_MOUT_EN,
> MT8365_DITHER_MOUT_EN_DSI0, MT8365_DITHER_MOUT_EN_DSI0
> },
> {
> - DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
> + DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
> MT8365_DISP_REG_CONFIG_DISP_DSI0_SEL_IN,
> MT8365_DSI0_SEL_IN_DITHER, MT8365_DSI0_SEL_IN_DITHER
> },
> diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c
> index 729ee88035ed..9184684baf1d 100644
> --- a/drivers/soc/mediatek/mtk-mutex.c
> +++ b/drivers/soc/mediatek/mtk-mutex.c
> @@ -232,7 +232,7 @@ static const unsigned int mt8167_mutex_mod[DDP_COMPONENT_ID_MAX] = {
> [DDP_COMPONENT_AAL0] = MT8167_MUTEX_MOD_DISP_AAL,
> [DDP_COMPONENT_CCORR] = MT8167_MUTEX_MOD_DISP_CCORR,
> [DDP_COMPONENT_COLOR0] = MT8167_MUTEX_MOD_DISP_COLOR,
> - [DDP_COMPONENT_DITHER] = MT8167_MUTEX_MOD_DISP_DITHER,
> + [DDP_COMPONENT_DITHER0] = MT8167_MUTEX_MOD_DISP_DITHER,
> [DDP_COMPONENT_GAMMA] = MT8167_MUTEX_MOD_DISP_GAMMA,
> [DDP_COMPONENT_OVL0] = MT8167_MUTEX_MOD_DISP_OVL0,
> [DDP_COMPONENT_OVL1] = MT8167_MUTEX_MOD_DISP_OVL1,
> @@ -265,7 +265,7 @@ static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = {
> [DDP_COMPONENT_AAL0] = MT8183_MUTEX_MOD_DISP_AAL0,
> [DDP_COMPONENT_CCORR] = MT8183_MUTEX_MOD_DISP_CCORR0,
> [DDP_COMPONENT_COLOR0] = MT8183_MUTEX_MOD_DISP_COLOR0,
> - [DDP_COMPONENT_DITHER] = MT8183_MUTEX_MOD_DISP_DITHER0,
> + [DDP_COMPONENT_DITHER0] = MT8183_MUTEX_MOD_DISP_DITHER0,
> [DDP_COMPONENT_GAMMA] = MT8183_MUTEX_MOD_DISP_GAMMA0,
> [DDP_COMPONENT_OVL0] = MT8183_MUTEX_MOD_DISP_OVL0,
> [DDP_COMPONENT_OVL_2L0] = MT8183_MUTEX_MOD_DISP_OVL0_2L,
> @@ -279,7 +279,7 @@ static const unsigned int mt8186_mutex_mod[DDP_COMPONENT_ID_MAX] = {
> [DDP_COMPONENT_AAL0] = MT8186_MUTEX_MOD_DISP_AAL0,
> [DDP_COMPONENT_CCORR] = MT8186_MUTEX_MOD_DISP_CCORR0,
> [DDP_COMPONENT_COLOR0] = MT8186_MUTEX_MOD_DISP_COLOR0,
> - [DDP_COMPONENT_DITHER] = MT8186_MUTEX_MOD_DISP_DITHER0,
> + [DDP_COMPONENT_DITHER0] = MT8186_MUTEX_MOD_DISP_DITHER0,
> [DDP_COMPONENT_GAMMA] = MT8186_MUTEX_MOD_DISP_GAMMA0,
> [DDP_COMPONENT_OVL0] = MT8186_MUTEX_MOD_DISP_OVL0,
> [DDP_COMPONENT_OVL_2L0] = MT8186_MUTEX_MOD_DISP_OVL0_2L,
> @@ -292,7 +292,7 @@ static const unsigned int mt8192_mutex_mod[DDP_COMPONENT_ID_MAX] = {
> [DDP_COMPONENT_AAL0] = MT8192_MUTEX_MOD_DISP_AAL0,
> [DDP_COMPONENT_CCORR] = MT8192_MUTEX_MOD_DISP_CCORR0,
> [DDP_COMPONENT_COLOR0] = MT8192_MUTEX_MOD_DISP_COLOR0,
> - [DDP_COMPONENT_DITHER] = MT8192_MUTEX_MOD_DISP_DITHER0,
> + [DDP_COMPONENT_DITHER0] = MT8192_MUTEX_MOD_DISP_DITHER0,
> [DDP_COMPONENT_GAMMA] = MT8192_MUTEX_MOD_DISP_GAMMA0,
> [DDP_COMPONENT_POSTMASK0] = MT8192_MUTEX_MOD_DISP_POSTMASK0,
> [DDP_COMPONENT_OVL0] = MT8192_MUTEX_MOD_DISP_OVL0,
> @@ -310,7 +310,7 @@ static const unsigned int mt8195_mutex_mod[DDP_COMPONENT_ID_MAX] = {
> [DDP_COMPONENT_CCORR] = MT8195_MUTEX_MOD_DISP_CCORR0,
> [DDP_COMPONENT_AAL0] = MT8195_MUTEX_MOD_DISP_AAL0,
> [DDP_COMPONENT_GAMMA] = MT8195_MUTEX_MOD_DISP_GAMMA0,
> - [DDP_COMPONENT_DITHER] = MT8195_MUTEX_MOD_DISP_DITHER0,
> + [DDP_COMPONENT_DITHER0] = MT8195_MUTEX_MOD_DISP_DITHER0,
> [DDP_COMPONENT_MERGE0] = MT8195_MUTEX_MOD_DISP_VPP_MERGE,
> [DDP_COMPONENT_DSC0] = MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0,
> [DDP_COMPONENT_DSI0] = MT8195_MUTEX_MOD_DISP_DSI0,
> diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
> index cff5c9adbf46..59117d970daf 100644
> --- a/include/linux/soc/mediatek/mtk-mmsys.h
> +++ b/include/linux/soc/mediatek/mtk-mmsys.h
> @@ -17,6 +17,7 @@ enum mtk_ddp_comp_id {
> DDP_COMPONENT_COLOR0,
> DDP_COMPONENT_COLOR1,
> DDP_COMPONENT_DITHER,
> + DDP_COMPONENT_DITHER0 = DDP_COMPONENT_DITHER,
> DDP_COMPONENT_DITHER1,
> DDP_COMPONENT_DP_INTF0,
> DDP_COMPONENT_DP_INTF1,
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^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [PATCH v20 6/8] soc: mediatek: add DDP_DOMPONENT_DITHER0 enum for mt8195 vdosys0
@ 2022-04-22 12:32 ` Matthias Brugger
0 siblings, 0 replies; 110+ messages in thread
From: Matthias Brugger @ 2022-04-22 12:32 UTC (permalink / raw)
To: jason-jh.lin, Chun-Kuang Hu, AngeloGioacchino Del Regno
Cc: CK Hu, Nancy Lin, Singo Chang, devicetree, linux-kernel,
dri-devel, linux-mediatek, linux-arm-kernel,
Project_Global_Chrome_Upstream_Group
On 19/04/2022 11:41, jason-jh.lin wrote:
> The mmsys routing table of mt8195 vdosys0 has 2 DITHER components,
> so mmsys need to add DDP_COMPONENT_DITHER1 and change all usages of
> DITHER enum form DDP_COMPONENT_DITHER to DDP_COMPONENT_DITHER0.
>
> But its header need to keep DDP_COMPONENT_DITHER enum
> until drm/mediatek also changed it.
>
> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Applied, thanks!
> ---
> drivers/soc/mediatek/mt8167-mmsys.h | 2 +-
> drivers/soc/mediatek/mt8183-mmsys.h | 2 +-
> drivers/soc/mediatek/mt8186-mmsys.h | 4 ++--
> drivers/soc/mediatek/mt8192-mmsys.h | 4 ++--
> drivers/soc/mediatek/mt8195-mmsys.h | 8 ++++----
> drivers/soc/mediatek/mt8365-mmsys.h | 4 ++--
> drivers/soc/mediatek/mtk-mutex.c | 10 +++++-----
> include/linux/soc/mediatek/mtk-mmsys.h | 1 +
> 8 files changed, 18 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/soc/mediatek/mt8167-mmsys.h b/drivers/soc/mediatek/mt8167-mmsys.h
> index 2772ef5e3934..f7a35b3656bb 100644
> --- a/drivers/soc/mediatek/mt8167-mmsys.h
> +++ b/drivers/soc/mediatek/mt8167-mmsys.h
> @@ -18,7 +18,7 @@ static const struct mtk_mmsys_routes mt8167_mmsys_routing_table[] = {
> DDP_COMPONENT_OVL0, DDP_COMPONENT_COLOR0,
> MT8167_DISP_REG_CONFIG_DISP_OVL0_MOUT_EN, OVL0_MOUT_EN_COLOR0,
> }, {
> - DDP_COMPONENT_DITHER, DDP_COMPONENT_RDMA0,
> + DDP_COMPONENT_DITHER0, DDP_COMPONENT_RDMA0,
> MT8167_DISP_REG_CONFIG_DISP_DITHER_MOUT_EN, MT8167_DITHER_MOUT_EN_RDMA0
> }, {
> DDP_COMPONENT_OVL0, DDP_COMPONENT_COLOR0,
> diff --git a/drivers/soc/mediatek/mt8183-mmsys.h b/drivers/soc/mediatek/mt8183-mmsys.h
> index 0c021f4b76d2..ff6be1703469 100644
> --- a/drivers/soc/mediatek/mt8183-mmsys.h
> +++ b/drivers/soc/mediatek/mt8183-mmsys.h
> @@ -41,7 +41,7 @@ static const struct mtk_mmsys_routes mmsys_mt8183_routing_table[] = {
> MT8183_DISP_OVL1_2L_MOUT_EN, MT8183_OVL1_2L_MOUT_EN_RDMA1,
> MT8183_OVL1_2L_MOUT_EN_RDMA1
> }, {
> - DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
> + DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
> MT8183_DISP_DITHER0_MOUT_EN, MT8183_DITHER0_MOUT_IN_DSI0,
> MT8183_DITHER0_MOUT_IN_DSI0
> }, {
> diff --git a/drivers/soc/mediatek/mt8186-mmsys.h b/drivers/soc/mediatek/mt8186-mmsys.h
> index c72ccf86ea28..eb1ad9c37a9c 100644
> --- a/drivers/soc/mediatek/mt8186-mmsys.h
> +++ b/drivers/soc/mediatek/mt8186-mmsys.h
> @@ -76,12 +76,12 @@ static const struct mtk_mmsys_routes mmsys_mt8186_routing_table[] = {
> MT8186_RDMA0_SOUT_TO_COLOR0
> },
> {
> - DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
> + DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
> MT8186_DISP_DITHER0_MOUT_EN, MT8186_DITHER0_MOUT_EN_MASK,
> MT8186_DITHER0_MOUT_TO_DSI0,
> },
> {
> - DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
> + DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
> MT8186_DISP_DSI0_SEL_IN, MT8186_DSI0_SEL_IN_MASK,
> MT8186_DSI0_FROM_DITHER0
> },
> diff --git a/drivers/soc/mediatek/mt8192-mmsys.h b/drivers/soc/mediatek/mt8192-mmsys.h
> index 6aae0b12b6ff..a016d80b4bc1 100644
> --- a/drivers/soc/mediatek/mt8192-mmsys.h
> +++ b/drivers/soc/mediatek/mt8192-mmsys.h
> @@ -40,7 +40,7 @@ static const struct mtk_mmsys_routes mmsys_mt8192_routing_table[] = {
> MT8192_DISP_OVL2_2L_MOUT_EN, MT8192_OVL2_2L_MOUT_EN_RDMA4,
> MT8192_OVL2_2L_MOUT_EN_RDMA4
> }, {
> - DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
> + DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
> MT8192_DISP_DITHER0_MOUT_EN, MT8192_DITHER0_MOUT_IN_DSI0,
> MT8192_DITHER0_MOUT_IN_DSI0
> }, {
> @@ -52,7 +52,7 @@ static const struct mtk_mmsys_routes mmsys_mt8192_routing_table[] = {
> MT8192_DISP_AAL0_SEL_IN, MT8192_AAL0_SEL_IN_CCORR0,
> MT8192_AAL0_SEL_IN_CCORR0
> }, {
> - DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
> + DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
> MT8192_DISP_DSI0_SEL_IN, MT8192_DSI0_SEL_IN_DITHER0,
> MT8192_DSI0_SEL_IN_DITHER0
> }, {
> diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h
> index 13ab0ab64396..abfe94a30248 100644
> --- a/drivers/soc/mediatek/mt8195-mmsys.h
> +++ b/drivers/soc/mediatek/mt8195-mmsys.h
> @@ -113,7 +113,7 @@ static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
> MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK,
> MT8195_SEL_IN_VPP_MERGE_FROM_VDO1_VIRTUAL0
> }, {
> - DDP_COMPONENT_DITHER, DDP_COMPONENT_DSC0,
> + DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSC0,
> MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK,
> MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0
> }, {
> @@ -181,7 +181,7 @@ static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
> MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI0_FROM_MASK,
> MT8195_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT
> }, {
> - DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
> + DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
> MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI0_FROM_MASK,
> MT8195_SEL_IN_DSI0_FROM_DISP_DITHER0
> }, {
> @@ -245,11 +245,11 @@ static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
> MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA0_FROM_MASK,
> MT8195_SEL_IN_DISP_WDMA0_FROM_DISP_OVL0
> }, {
> - DDP_COMPONENT_DITHER, DDP_COMPONENT_DSC0,
> + DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSC0,
> MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER0_TO_MASK,
> MT8195_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN
> }, {
> - DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
> + DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
> MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER0_TO_MASK,
> MT8195_SOUT_DISP_DITHER0_TO_DSI0
> }, {
> diff --git a/drivers/soc/mediatek/mt8365-mmsys.h b/drivers/soc/mediatek/mt8365-mmsys.h
> index 690e3fe2dee0..24129a6c25f8 100644
> --- a/drivers/soc/mediatek/mt8365-mmsys.h
> +++ b/drivers/soc/mediatek/mt8365-mmsys.h
> @@ -41,12 +41,12 @@ static const struct mtk_mmsys_routes mt8365_mmsys_routing_table[] = {
> MT8365_DISP_COLOR_SEL_IN_COLOR0,MT8365_DISP_COLOR_SEL_IN_COLOR0
> },
> {
> - DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
> + DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
> MT8365_DISP_REG_CONFIG_DISP_DITHER0_MOUT_EN,
> MT8365_DITHER_MOUT_EN_DSI0, MT8365_DITHER_MOUT_EN_DSI0
> },
> {
> - DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
> + DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
> MT8365_DISP_REG_CONFIG_DISP_DSI0_SEL_IN,
> MT8365_DSI0_SEL_IN_DITHER, MT8365_DSI0_SEL_IN_DITHER
> },
> diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c
> index 729ee88035ed..9184684baf1d 100644
> --- a/drivers/soc/mediatek/mtk-mutex.c
> +++ b/drivers/soc/mediatek/mtk-mutex.c
> @@ -232,7 +232,7 @@ static const unsigned int mt8167_mutex_mod[DDP_COMPONENT_ID_MAX] = {
> [DDP_COMPONENT_AAL0] = MT8167_MUTEX_MOD_DISP_AAL,
> [DDP_COMPONENT_CCORR] = MT8167_MUTEX_MOD_DISP_CCORR,
> [DDP_COMPONENT_COLOR0] = MT8167_MUTEX_MOD_DISP_COLOR,
> - [DDP_COMPONENT_DITHER] = MT8167_MUTEX_MOD_DISP_DITHER,
> + [DDP_COMPONENT_DITHER0] = MT8167_MUTEX_MOD_DISP_DITHER,
> [DDP_COMPONENT_GAMMA] = MT8167_MUTEX_MOD_DISP_GAMMA,
> [DDP_COMPONENT_OVL0] = MT8167_MUTEX_MOD_DISP_OVL0,
> [DDP_COMPONENT_OVL1] = MT8167_MUTEX_MOD_DISP_OVL1,
> @@ -265,7 +265,7 @@ static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = {
> [DDP_COMPONENT_AAL0] = MT8183_MUTEX_MOD_DISP_AAL0,
> [DDP_COMPONENT_CCORR] = MT8183_MUTEX_MOD_DISP_CCORR0,
> [DDP_COMPONENT_COLOR0] = MT8183_MUTEX_MOD_DISP_COLOR0,
> - [DDP_COMPONENT_DITHER] = MT8183_MUTEX_MOD_DISP_DITHER0,
> + [DDP_COMPONENT_DITHER0] = MT8183_MUTEX_MOD_DISP_DITHER0,
> [DDP_COMPONENT_GAMMA] = MT8183_MUTEX_MOD_DISP_GAMMA0,
> [DDP_COMPONENT_OVL0] = MT8183_MUTEX_MOD_DISP_OVL0,
> [DDP_COMPONENT_OVL_2L0] = MT8183_MUTEX_MOD_DISP_OVL0_2L,
> @@ -279,7 +279,7 @@ static const unsigned int mt8186_mutex_mod[DDP_COMPONENT_ID_MAX] = {
> [DDP_COMPONENT_AAL0] = MT8186_MUTEX_MOD_DISP_AAL0,
> [DDP_COMPONENT_CCORR] = MT8186_MUTEX_MOD_DISP_CCORR0,
> [DDP_COMPONENT_COLOR0] = MT8186_MUTEX_MOD_DISP_COLOR0,
> - [DDP_COMPONENT_DITHER] = MT8186_MUTEX_MOD_DISP_DITHER0,
> + [DDP_COMPONENT_DITHER0] = MT8186_MUTEX_MOD_DISP_DITHER0,
> [DDP_COMPONENT_GAMMA] = MT8186_MUTEX_MOD_DISP_GAMMA0,
> [DDP_COMPONENT_OVL0] = MT8186_MUTEX_MOD_DISP_OVL0,
> [DDP_COMPONENT_OVL_2L0] = MT8186_MUTEX_MOD_DISP_OVL0_2L,
> @@ -292,7 +292,7 @@ static const unsigned int mt8192_mutex_mod[DDP_COMPONENT_ID_MAX] = {
> [DDP_COMPONENT_AAL0] = MT8192_MUTEX_MOD_DISP_AAL0,
> [DDP_COMPONENT_CCORR] = MT8192_MUTEX_MOD_DISP_CCORR0,
> [DDP_COMPONENT_COLOR0] = MT8192_MUTEX_MOD_DISP_COLOR0,
> - [DDP_COMPONENT_DITHER] = MT8192_MUTEX_MOD_DISP_DITHER0,
> + [DDP_COMPONENT_DITHER0] = MT8192_MUTEX_MOD_DISP_DITHER0,
> [DDP_COMPONENT_GAMMA] = MT8192_MUTEX_MOD_DISP_GAMMA0,
> [DDP_COMPONENT_POSTMASK0] = MT8192_MUTEX_MOD_DISP_POSTMASK0,
> [DDP_COMPONENT_OVL0] = MT8192_MUTEX_MOD_DISP_OVL0,
> @@ -310,7 +310,7 @@ static const unsigned int mt8195_mutex_mod[DDP_COMPONENT_ID_MAX] = {
> [DDP_COMPONENT_CCORR] = MT8195_MUTEX_MOD_DISP_CCORR0,
> [DDP_COMPONENT_AAL0] = MT8195_MUTEX_MOD_DISP_AAL0,
> [DDP_COMPONENT_GAMMA] = MT8195_MUTEX_MOD_DISP_GAMMA0,
> - [DDP_COMPONENT_DITHER] = MT8195_MUTEX_MOD_DISP_DITHER0,
> + [DDP_COMPONENT_DITHER0] = MT8195_MUTEX_MOD_DISP_DITHER0,
> [DDP_COMPONENT_MERGE0] = MT8195_MUTEX_MOD_DISP_VPP_MERGE,
> [DDP_COMPONENT_DSC0] = MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0,
> [DDP_COMPONENT_DSI0] = MT8195_MUTEX_MOD_DISP_DSI0,
> diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
> index cff5c9adbf46..59117d970daf 100644
> --- a/include/linux/soc/mediatek/mtk-mmsys.h
> +++ b/include/linux/soc/mediatek/mtk-mmsys.h
> @@ -17,6 +17,7 @@ enum mtk_ddp_comp_id {
> DDP_COMPONENT_COLOR0,
> DDP_COMPONENT_COLOR1,
> DDP_COMPONENT_DITHER,
> + DDP_COMPONENT_DITHER0 = DDP_COMPONENT_DITHER,
> DDP_COMPONENT_DITHER1,
> DDP_COMPONENT_DP_INTF0,
> DDP_COMPONENT_DP_INTF1,
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [PATCH v20 8/8] soc: mediatek: remove DDP_DOMPONENT_DITHER from enum
2022-04-19 9:41 ` jason-jh.lin
(?)
(?)
@ 2022-04-22 12:42 ` Matthias Brugger
-1 siblings, 0 replies; 110+ messages in thread
From: Matthias Brugger @ 2022-04-22 12:42 UTC (permalink / raw)
To: jason-jh.lin, Chun-Kuang Hu, AngeloGioacchino Del Regno
Cc: CK Hu, Nancy Lin, Singo Chang, devicetree, linux-kernel,
dri-devel, linux-mediatek, linux-arm-kernel,
Project_Global_Chrome_Upstream_Group
On 19/04/2022 11:41, jason-jh.lin wrote:
> After mmsys and drm change DITHER enum to DDP_COMPONENT_DITHER0,
> mmsys header can remove the useless DDP_COMPONENT_DITHER enum.
>
> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Acked-by: Matthias Brugger <matthias.bgg@gmail.com>
Chun-Kuang, I think it would make sense to take that through your tree as it
depends on the previous patches.
I provide you a stable tag so that you can take it:
v5.18-next-vdso0-stable-tag
Regards,
Matthias
> ---
> include/linux/soc/mediatek/mtk-mmsys.h | 3 +--
> 1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
> index 59117d970daf..fb719fd1281c 100644
> --- a/include/linux/soc/mediatek/mtk-mmsys.h
> +++ b/include/linux/soc/mediatek/mtk-mmsys.h
> @@ -16,8 +16,7 @@ enum mtk_ddp_comp_id {
> DDP_COMPONENT_CCORR,
> DDP_COMPONENT_COLOR0,
> DDP_COMPONENT_COLOR1,
> - DDP_COMPONENT_DITHER,
> - DDP_COMPONENT_DITHER0 = DDP_COMPONENT_DITHER,
> + DDP_COMPONENT_DITHER0,
> DDP_COMPONENT_DITHER1,
> DDP_COMPONENT_DP_INTF0,
> DDP_COMPONENT_DP_INTF1,
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [PATCH v20 8/8] soc: mediatek: remove DDP_DOMPONENT_DITHER from enum
@ 2022-04-22 12:42 ` Matthias Brugger
0 siblings, 0 replies; 110+ messages in thread
From: Matthias Brugger @ 2022-04-22 12:42 UTC (permalink / raw)
To: jason-jh.lin, Chun-Kuang Hu, AngeloGioacchino Del Regno
Cc: devicetree, Singo Chang, linux-kernel, dri-devel,
Project_Global_Chrome_Upstream_Group, Nancy Lin, linux-mediatek,
linux-arm-kernel
On 19/04/2022 11:41, jason-jh.lin wrote:
> After mmsys and drm change DITHER enum to DDP_COMPONENT_DITHER0,
> mmsys header can remove the useless DDP_COMPONENT_DITHER enum.
>
> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Acked-by: Matthias Brugger <matthias.bgg@gmail.com>
Chun-Kuang, I think it would make sense to take that through your tree as it
depends on the previous patches.
I provide you a stable tag so that you can take it:
v5.18-next-vdso0-stable-tag
Regards,
Matthias
> ---
> include/linux/soc/mediatek/mtk-mmsys.h | 3 +--
> 1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
> index 59117d970daf..fb719fd1281c 100644
> --- a/include/linux/soc/mediatek/mtk-mmsys.h
> +++ b/include/linux/soc/mediatek/mtk-mmsys.h
> @@ -16,8 +16,7 @@ enum mtk_ddp_comp_id {
> DDP_COMPONENT_CCORR,
> DDP_COMPONENT_COLOR0,
> DDP_COMPONENT_COLOR1,
> - DDP_COMPONENT_DITHER,
> - DDP_COMPONENT_DITHER0 = DDP_COMPONENT_DITHER,
> + DDP_COMPONENT_DITHER0,
> DDP_COMPONENT_DITHER1,
> DDP_COMPONENT_DP_INTF0,
> DDP_COMPONENT_DP_INTF1,
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [PATCH v20 8/8] soc: mediatek: remove DDP_DOMPONENT_DITHER from enum
@ 2022-04-22 12:42 ` Matthias Brugger
0 siblings, 0 replies; 110+ messages in thread
From: Matthias Brugger @ 2022-04-22 12:42 UTC (permalink / raw)
To: jason-jh.lin, Chun-Kuang Hu, AngeloGioacchino Del Regno
Cc: CK Hu, Nancy Lin, Singo Chang, devicetree, linux-kernel,
dri-devel, linux-mediatek, linux-arm-kernel,
Project_Global_Chrome_Upstream_Group
On 19/04/2022 11:41, jason-jh.lin wrote:
> After mmsys and drm change DITHER enum to DDP_COMPONENT_DITHER0,
> mmsys header can remove the useless DDP_COMPONENT_DITHER enum.
>
> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Acked-by: Matthias Brugger <matthias.bgg@gmail.com>
Chun-Kuang, I think it would make sense to take that through your tree as it
depends on the previous patches.
I provide you a stable tag so that you can take it:
v5.18-next-vdso0-stable-tag
Regards,
Matthias
> ---
> include/linux/soc/mediatek/mtk-mmsys.h | 3 +--
> 1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
> index 59117d970daf..fb719fd1281c 100644
> --- a/include/linux/soc/mediatek/mtk-mmsys.h
> +++ b/include/linux/soc/mediatek/mtk-mmsys.h
> @@ -16,8 +16,7 @@ enum mtk_ddp_comp_id {
> DDP_COMPONENT_CCORR,
> DDP_COMPONENT_COLOR0,
> DDP_COMPONENT_COLOR1,
> - DDP_COMPONENT_DITHER,
> - DDP_COMPONENT_DITHER0 = DDP_COMPONENT_DITHER,
> + DDP_COMPONENT_DITHER0,
> DDP_COMPONENT_DITHER1,
> DDP_COMPONENT_DP_INTF0,
> DDP_COMPONENT_DP_INTF1,
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [PATCH v20 8/8] soc: mediatek: remove DDP_DOMPONENT_DITHER from enum
@ 2022-04-22 12:42 ` Matthias Brugger
0 siblings, 0 replies; 110+ messages in thread
From: Matthias Brugger @ 2022-04-22 12:42 UTC (permalink / raw)
To: jason-jh.lin, Chun-Kuang Hu, AngeloGioacchino Del Regno
Cc: CK Hu, Nancy Lin, Singo Chang, devicetree, linux-kernel,
dri-devel, linux-mediatek, linux-arm-kernel,
Project_Global_Chrome_Upstream_Group
On 19/04/2022 11:41, jason-jh.lin wrote:
> After mmsys and drm change DITHER enum to DDP_COMPONENT_DITHER0,
> mmsys header can remove the useless DDP_COMPONENT_DITHER enum.
>
> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Acked-by: Matthias Brugger <matthias.bgg@gmail.com>
Chun-Kuang, I think it would make sense to take that through your tree as it
depends on the previous patches.
I provide you a stable tag so that you can take it:
v5.18-next-vdso0-stable-tag
Regards,
Matthias
> ---
> include/linux/soc/mediatek/mtk-mmsys.h | 3 +--
> 1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
> index 59117d970daf..fb719fd1281c 100644
> --- a/include/linux/soc/mediatek/mtk-mmsys.h
> +++ b/include/linux/soc/mediatek/mtk-mmsys.h
> @@ -16,8 +16,7 @@ enum mtk_ddp_comp_id {
> DDP_COMPONENT_CCORR,
> DDP_COMPONENT_COLOR0,
> DDP_COMPONENT_COLOR1,
> - DDP_COMPONENT_DITHER,
> - DDP_COMPONENT_DITHER0 = DDP_COMPONENT_DITHER,
> + DDP_COMPONENT_DITHER0,
> DDP_COMPONENT_DITHER1,
> DDP_COMPONENT_DP_INTF0,
> DDP_COMPONENT_DP_INTF1,
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [PATCH v20 1/8] soc: mediatek: add mtk-mmsys support for mt8195 vdosys0
2022-04-22 12:28 ` Matthias Brugger
(?)
(?)
@ 2022-04-24 8:47 ` Jason-JH Lin
-1 siblings, 0 replies; 110+ messages in thread
From: Jason-JH Lin @ 2022-04-24 8:47 UTC (permalink / raw)
To: Matthias Brugger, Chun-Kuang Hu, AngeloGioacchino Del Regno
Cc: CK Hu, Nancy Lin, Singo Chang, devicetree, linux-kernel,
dri-devel, linux-mediatek, linux-arm-kernel,
Project_Global_Chrome_Upstream_Group
Hi Matthias,
Thanks for the reviews.
On Fri, 2022-04-22 at 14:28 +0200, Matthias Brugger wrote:
>
> On 19/04/2022 11:41, jason-jh.lin wrote:
> > 1. Add mt8195 mmsys compatible for 2 vdosys.
> > 2. Add io_start into each driver data of mt8195 vdosys.
> > 3. Add get match data function to identify mmsys by io_start.
> > 4. Add mt8195 routing table settings of vdosys0.
> >
> > Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> > Reviewed-by: AngeloGioacchino Del Regno <
> > angelogioacchino.delregno@collabora.com>
>
> I'm not very happy with the approach of testing against the reg
> property to
> decide which version of the two mmsys devices we are probing. I think
> a better
> approach would be, if we would have added some mediatek specific ID
> to the
> device tree binding (or use a two compatibles?).
>
We uses two compatibles in previous version(before v16) of this series.
https://patchwork.kernel.org/project/linux-mediatek/patch/20220307032859.3275-5-jason-jh.lin@mediatek.com/
Since we received the comment of VPPSYS from Rob:
https://patchwork.kernel.org/project/linux-mediatek/patch/20220117055254.9777-15-roy-cw.yeh@mediatek.com/#24707362
we're trying to figure out the way to use the same compatible for
different mmsys.
> But as we are at v20 I think it wouldn't be fair to ask for such an
> instrusive
> change. So I'll take this patch now, but maybe we can discuss if we
> can't do
> better in a follow-up patch. Especially I don't think it's a good
> approach to
> check for the io_start in the DRM driver. Couldn't we pass the
> information about
> which of the two mmsys blocks we are calling from through the
> mediatek-drm
> platform device spefic data?
>
But we can't find a suitable property to identify the different mmsys
directly.
In mt8195, 2 pipelines are binding to different mmsys, such as vdosys0
and vdosys1. Each mmsys uses different clock drivers and different
power domain.
Since each mmsys has its own clock, I have tried to differentiate
vdosys0, vdosys1 by the clock names:
https://patchwork.kernel.org/project/linux-mediatek/patch/20220407030409.9664-4-jason-jh.lin@mediatek.com/
But it seems not robust enough.
Then we refer to this io_start solution, the idea from Angelo:
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c?h=next-20220408#n789
I'm not sure if there is another more suitable idea to fit in this
problem.
But I believe, if using different compatibles for each mmsys is
acceptable, then we can keep the original compatible method for
mediatek-drm and mmsys, and also make these works easier.
If you have any ideas to simplify it, please help us :-)
Thanks for your reviews again.
Regards,
Jason-JH.Lin
> I also had a look into the vdosys1 series to better understand why we
> need to do
> things as we do them. But honestly I wasn't able to really understand
> the
> implication of the patch that adds 'multi mmsys support' [1]. For
> this looks
> like a several patches that got squashed into one. But as I don't
> have to
> maintain that it is not my call to complain, the patch has the needed
> reviews.
>
> For this patch, now applied to v5.18-next/soc
>
> Thanks for all people implicated.
>
> Regards,
> Matthias
>
> [1]
>
https://urldefense.com/v3/__https://patchwork.kernel.org/project/linux-mediatek/patch/20220416020749.29010-19-nancy.lin@mediatek.com/__;!!CTRNKA9wMg0ARbw!zwfxXhyNG9gAnlrIB72IpyBFsLEm6pzLdRVgomyZ5tLat_Ddf3e3LenemQDeRVLWEf_p$
>
>
> > ---
> > Based on series [1]
> >
> > [1] MediaTek MT8195 display binding
> > -
> > https://urldefense.com/v3/__https://patchwork.ozlabs.org/project/devicetree-bindings/list/?series=295669__;!!CTRNKA9wMg0ARbw!zwfxXhyNG9gAnlrIB72IpyBFsLEm6pzLdRVgomyZ5tLat_Ddf3e3LenemQDeRXN1cxii$
> >
> > ---
> > drivers/soc/mediatek/mt8195-mmsys.h | 370
> > +++++++++++++++++++++++++
> > drivers/soc/mediatek/mtk-mmsys.c | 152 +++++++++-
> > drivers/soc/mediatek/mtk-mmsys.h | 6 +
> > include/linux/soc/mediatek/mtk-mmsys.h | 11 +
> > 4 files changed, 528 insertions(+), 11 deletions(-)
> > create mode 100644 drivers/soc/mediatek/mt8195-mmsys.h
> >
> > diff --git a/drivers/soc/mediatek/mt8195-mmsys.h
> > b/drivers/soc/mediatek/mt8195-mmsys.h
> > new file mode 100644
> > index 000000000000..13ab0ab64396
> > --- /dev/null
> > +++ b/drivers/soc/mediatek/mt8195-mmsys.h
> > @@ -0,0 +1,370 @@
> > +/* SPDX-License-Identifier: GPL-2.0-only */
> > +
> > +#ifndef __SOC_MEDIATEK_MT8195_MMSYS_H
> > +#define __SOC_MEDIATEK_MT8195_MMSYS_H
> > +
> > +#define MT8195_VDO0_OVL_MOUT_EN
> > 0xf14
> > +#define MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0
> > BIT(0)
> > +#define MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0
> > BIT(1)
> > +#define MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1 BIT(2)
> > +#define MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1
> > BIT(4)
> > +#define MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1
> > BIT(5)
> > +#define MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0 BIT(6)
> > +
> > +#define MT8195_VDO0_SEL_IN 0xf34
> > +#define MT8195_SEL_IN_VPP_MERGE_FROM_MASK GENMASK
> > (1, 0)
> > +#define MT8195_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT (0 <<
> > 0)
> > +#define MT8195_SEL_IN_VPP_MERGE_FROM_DISP_DITHER1 (1 <<
> > 0)
> > +#define MT8195_SEL_IN_VPP_MERGE_FROM_VDO1_VIRTUAL0 (2 <<
> > 0)
> > +#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK
> > GENMASK(4, 4)
> > +#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0
> > (0 << 4)
> > +#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_VPP_MERGE (1 <<
> > 4)
> > +#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_MASK
> > GENMASK(5, 5)
> > +#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_DISP_DITHER1
> > (0 << 5)
> > +#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_VPP_MERGE (1 <<
> > 5)
> > +#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK
> > GENMASK(8, 8)
> > +#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE (0 <<
> > 8)
> > +#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT
> > (1 << 8)
> > +#define MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK
> > GENMASK(9, 9)
> > +#define MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT
> > (0 << 9)
> > +#define MT8195_SEL_IN_DP_INTF0_FROM_MASK GENMASK
> > (13, 12)
> > +#define MT8195_SEL_IN_DP_INTF0_FROM_DSC_WRAP1_OUT (0 <<
> > 0)
> > +#define MT8195_SEL_IN_DP_INTF0_FROM_VPP_MERGE
> > (1 << 12)
> > +#define MT8195_SEL_IN_DP_INTF0_FROM_VDO1_VIRTUAL0 (2 <<
> > 12)
> > +#define MT8195_SEL_IN_DSI0_FROM_MASK
> > GENMASK(16, 16)
> > +#define MT8195_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT
> > (0 << 16)
> > +#define MT8195_SEL_IN_DSI0_FROM_DISP_DITHER0
> > (1 << 16)
> > +#define MT8195_SEL_IN_DSI1_FROM_MASK
> > GENMASK(17, 17)
> > +#define MT8195_SEL_IN_DSI1_FROM_DSC_WRAP1_OUT
> > (0 << 17)
> > +#define MT8195_SEL_IN_DSI1_FROM_VPP_MERGE (1 <<
> > 17)
> > +#define MT8195_SEL_IN_DISP_WDMA1_FROM_MASK GENMASK
> > (20, 20)
> > +#define MT8195_SEL_IN_DISP_WDMA1_FROM_DISP_OVL1
> > (0 << 20)
> > +#define MT8195_SEL_IN_DISP_WDMA1_FROM_VPP_MERGE
> > (1 << 20)
> > +#define MT8195_SEL_IN_DSC_WRAP1_FROM_MASK GENMASK
> > (21, 21)
> > +#define MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
> > (0 << 21)
> > +#define MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1
> > (1 << 21)
> > +#define MT8195_SEL_IN_DISP_WDMA0_FROM_MASK GENMASK
> > (22, 22)
> > +#define MT8195_SEL_IN_DISP_WDMA0_FROM_DISP_OVL0
> > (0 << 22)
> > +
> > +#define MT8195_VDO0_SEL_OUT
> > 0xf38
> > +#define MT8195_SOUT_DISP_DITHER0_TO_MASK BIT(0)
> > +#define MT8195_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN (0 <<
> > 0)
> > +#define MT8195_SOUT_DISP_DITHER0_TO_DSI0 (1 <<
> > 0)
> > +#define MT8195_SOUT_DISP_DITHER1_TO_MASK GENMASK
> > (2, 1)
> > +#define MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_IN (0 <<
> > 1)
> > +#define MT8195_SOUT_DISP_DITHER1_TO_VPP_MERGE
> > (1 << 1)
> > +#define MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT (2 <<
> > 1)
> > +#define MT8195_SOUT_VDO1_VIRTUAL0_TO_MASK GENMASK
> > (4, 4)
> > +#define MT8195_SOUT_VDO1_VIRTUAL0_TO_VPP_MERGE
> > (0 << 4)
> > +#define MT8195_SOUT_VDO1_VIRTUAL0_TO_DP_INTF0
> > (1 << 4)
> > +#define MT8195_SOUT_VPP_MERGE_TO_MASK
> > GENMASK(10, 8)
> > +#define MT8195_SOUT_VPP_MERGE_TO_DSI1
> > (0 << 8)
> > +#define MT8195_SOUT_VPP_MERGE_TO_DP_INTF0 (1 <<
> > 8)
> > +#define MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0
> > (2 << 8)
> > +#define MT8195_SOUT_VPP_MERGE_TO_DISP_WDMA1
> > (3 << 8)
> > +#define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP0_IN
> > (4 << 8)
> > +#define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN_MASK GENMASK
> > (11, 11)
> > +#define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN
> > (0 << 11)
> > +#define MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK GENMASK
> > (13, 12)
> > +#define MT8195_SOUT_DSC_WRAP0_OUT_TO_DSI0 (0 <<
> > 12)
> > +#define MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0 (1 <<
> > 12)
> > +#define MT8195_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE
> > (2 << 12)
> > +#define MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK GENMASK
> > (17, 16)
> > +#define MT8195_SOUT_DSC_WRAP1_OUT_TO_DSI1 (0 <<
> > 16)
> > +#define MT8195_SOUT_DSC_WRAP1_OUT_TO_DP_INTF0
> > (1 << 16)
> > +#define MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0 (2 <<
> > 16)
> > +#define MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE
> > (3 << 16)
> > +
> > +static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[]
> > = {
> > + {
> > + DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
> > + MT8195_VDO0_OVL_MOUT_EN,
> > MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0,
> > + MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0
> > + }, {
> > + DDP_COMPONENT_OVL0, DDP_COMPONENT_WDMA0,
> > + MT8195_VDO0_OVL_MOUT_EN,
> > MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0,
> > + MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0
> > + }, {
> > + DDP_COMPONENT_OVL0, DDP_COMPONENT_OVL1,
> > + MT8195_VDO0_OVL_MOUT_EN,
> > MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1,
> > + MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1
> > + }, {
> > + DDP_COMPONENT_OVL1, DDP_COMPONENT_RDMA1,
> > + MT8195_VDO0_OVL_MOUT_EN,
> > MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1,
> > + MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1
> > + }, {
> > + DDP_COMPONENT_OVL1, DDP_COMPONENT_WDMA1,
> > + MT8195_VDO0_OVL_MOUT_EN,
> > MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1,
> > + MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1
> > + }, {
> > + DDP_COMPONENT_OVL1, DDP_COMPONENT_OVL0,
> > + MT8195_VDO0_OVL_MOUT_EN,
> > MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0,
> > + MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0
> > + }, {
> > + DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0,
> > + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK,
> > + MT8195_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT
> > + }, {
> > + DDP_COMPONENT_DITHER1, DDP_COMPONENT_MERGE0,
> > + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK,
> > + MT8195_SEL_IN_VPP_MERGE_FROM_DISP_DITHER1
> > + }, {
> > + DDP_COMPONENT_MERGE5, DDP_COMPONENT_MERGE0,
> > + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK,
> > + MT8195_SEL_IN_VPP_MERGE_FROM_VDO1_VIRTUAL0
> > + }, {
> > + DDP_COMPONENT_DITHER, DDP_COMPONENT_DSC0,
> > + MT8195_VDO0_SEL_IN,
> > MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK,
> > + MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0
> > + }, {
> > + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC0,
> > + MT8195_VDO0_SEL_IN,
> > MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK,
> > + MT8195_SEL_IN_DSC_WRAP0_IN_FROM_VPP_MERGE
> > + }, {
> > + DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSC1,
> > + MT8195_VDO0_SEL_IN,
> > MT8195_SEL_IN_DSC_WRAP1_IN_FROM_MASK,
> > + MT8195_SEL_IN_DSC_WRAP1_IN_FROM_DISP_DITHER1
> > + }, {
> > + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC1,
> > + MT8195_VDO0_SEL_IN,
> > MT8195_SEL_IN_DSC_WRAP1_IN_FROM_MASK,
> > + MT8195_SEL_IN_DSC_WRAP1_IN_FROM_VPP_MERGE
> > + }, {
> > + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF1,
> > + MT8195_VDO0_SEL_IN,
> > MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
> > + MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE
> > + }, {
> > + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI0,
> > + MT8195_VDO0_SEL_IN,
> > MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
> > + MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE
> > + }, {
> > + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI1,
> > + MT8195_VDO0_SEL_IN,
> > MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
> > + MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE
> > + }, {
> > + DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF1,
> > + MT8195_VDO0_SEL_IN,
> > MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
> > + MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT
> > + }, {
> > + DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI0,
> > + MT8195_VDO0_SEL_IN,
> > MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
> > + MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT
> > + }, {
> > + DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI1,
> > + MT8195_VDO0_SEL_IN,
> > MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
> > + MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT
> > + }, {
> > + DDP_COMPONENT_DSC0, DDP_COMPONENT_DP_INTF1,
> > + MT8195_VDO0_SEL_IN,
> > MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK,
> > + MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT
> > + }, {
> > + DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI0,
> > + MT8195_VDO0_SEL_IN,
> > MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK,
> > + MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT
> > + }, {
> > + DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI1,
> > + MT8195_VDO0_SEL_IN,
> > MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK,
> > + MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT
> > + }, {
> > + DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF0,
> > + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_MASK,
> > + MT8195_SEL_IN_DP_INTF0_FROM_DSC_WRAP1_OUT
> > + }, {
> > + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF0,
> > + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_MASK,
> > + MT8195_SEL_IN_DP_INTF0_FROM_VPP_MERGE
> > + }, {
> > + DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF0,
> > + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_MASK,
> > + MT8195_SEL_IN_DP_INTF0_FROM_VDO1_VIRTUAL0
> > + }, {
> > + DDP_COMPONENT_DSC0, DDP_COMPONENT_DSI0,
> > + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI0_FROM_MASK,
> > + MT8195_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT
> > + }, {
> > + DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
> > + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI0_FROM_MASK,
> > + MT8195_SEL_IN_DSI0_FROM_DISP_DITHER0
> > + }, {
> > + DDP_COMPONENT_DSC1, DDP_COMPONENT_DSI1,
> > + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI1_FROM_MASK,
> > + MT8195_SEL_IN_DSI1_FROM_DSC_WRAP1_OUT
> > + }, {
> > + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSI1,
> > + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI1_FROM_MASK,
> > + MT8195_SEL_IN_DSI1_FROM_VPP_MERGE
> > + }, {
> > + DDP_COMPONENT_OVL1, DDP_COMPONENT_WDMA1,
> > + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA1_FROM_MASK,
> > + MT8195_SEL_IN_DISP_WDMA1_FROM_DISP_OVL1
> > + }, {
> > + DDP_COMPONENT_MERGE0, DDP_COMPONENT_WDMA1,
> > + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA1_FROM_MASK,
> > + MT8195_SEL_IN_DISP_WDMA1_FROM_VPP_MERGE
> > + }, {
> > + DDP_COMPONENT_DSC1, DDP_COMPONENT_DSI1,
> > + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
> > + MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
> > + }, {
> > + DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF0,
> > + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
> > + MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
> > + }, {
> > + DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF1,
> > + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
> > + MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
> > + }, {
> > + DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI0,
> > + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
> > + MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
> > + }, {
> > + DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI1,
> > + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
> > + MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
> > + }, {
> > + DDP_COMPONENT_DSC1, DDP_COMPONENT_MERGE0,
> > + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
> > + MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
> > + }, {
> > + DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSI1,
> > + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
> > + MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1
> > + }, {
> > + DDP_COMPONENT_DITHER1, DDP_COMPONENT_DP_INTF0,
> > + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
> > + MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1
> > + }, {
> > + DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI0,
> > + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
> > + MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1
> > + }, {
> > + DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI1,
> > + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
> > + MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1
> > + }, {
> > + DDP_COMPONENT_OVL0, DDP_COMPONENT_WDMA0,
> > + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA0_FROM_MASK,
> > + MT8195_SEL_IN_DISP_WDMA0_FROM_DISP_OVL0
> > + }, {
> > + DDP_COMPONENT_DITHER, DDP_COMPONENT_DSC0,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER0_TO_MASK,
> > + MT8195_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN
> > + }, {
> > + DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER0_TO_MASK,
> > + MT8195_SOUT_DISP_DITHER0_TO_DSI0
> > + }, {
> > + DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSC1,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
> > + MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_IN
> > + }, {
> > + DDP_COMPONENT_DITHER1, DDP_COMPONENT_MERGE0,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
> > + MT8195_SOUT_DISP_DITHER1_TO_VPP_MERGE
> > + }, {
> > + DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSI1,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
> > + MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT
> > + }, {
> > + DDP_COMPONENT_DITHER1, DDP_COMPONENT_DP_INTF0,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
> > + MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT
> > + }, {
> > + DDP_COMPONENT_DITHER1, DDP_COMPONENT_DP_INTF1,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
> > + MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT
> > + }, {
> > + DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI0,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
> > + MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT
> > + }, {
> > + DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI1,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
> > + MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT
> > + }, {
> > + DDP_COMPONENT_MERGE5, DDP_COMPONENT_MERGE0,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_VDO1_VIRTUAL0_TO_MASK,
> > + MT8195_SOUT_VDO1_VIRTUAL0_TO_VPP_MERGE
> > + }, {
> > + DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF0,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_VDO1_VIRTUAL0_TO_MASK,
> > + MT8195_SOUT_VDO1_VIRTUAL0_TO_DP_INTF0
> > + }, {
> > + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSI1,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
> > + MT8195_SOUT_VPP_MERGE_TO_DSI1
> > + }, {
> > + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF0,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
> > + MT8195_SOUT_VPP_MERGE_TO_DP_INTF0
> > + }, {
> > + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF1,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
> > + MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0
> > + }, {
> > + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI0,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
> > + MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0
> > + }, {
> > + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI1,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
> > + MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0
> > + }, {
> > + DDP_COMPONENT_MERGE0, DDP_COMPONENT_WDMA1,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
> > + MT8195_SOUT_VPP_MERGE_TO_DISP_WDMA1
> > + }, {
> > + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC0,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
> > + MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP0_IN
> > + }, {
> > + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC1,
> > + MT8195_VDO0_SEL_OUT,
> > MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN_MASK,
> > + MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN
> > + }, {
> > + DDP_COMPONENT_DSC0, DDP_COMPONENT_DSI0,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
> > + MT8195_SOUT_DSC_WRAP0_OUT_TO_DSI0
> > + }, {
> > + DDP_COMPONENT_DSC0, DDP_COMPONENT_DP_INTF1,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
> > + MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0
> > + }, {
> > + DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI0,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
> > + MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0
> > + }, {
> > + DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI1,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
> > + MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0
> > + }, {
> > + DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
> > + MT8195_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE
> > + }, {
> > + DDP_COMPONENT_DSC1, DDP_COMPONENT_DSI1,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
> > + MT8195_SOUT_DSC_WRAP1_OUT_TO_DSI1
> > + }, {
> > + DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF0,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
> > + MT8195_SOUT_DSC_WRAP1_OUT_TO_DP_INTF0
> > + }, {
> > + DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF1,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
> > + MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0
> > + }, {
> > + DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI0,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
> > + MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0
> > + }, {
> > + DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI1,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
> > + MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0
> > + }, {
> > + DDP_COMPONENT_DSC1, DDP_COMPONENT_MERGE0,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
> > + MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE
> > + }
> > +};
> > +
> > +#endif /* __SOC_MEDIATEK_MT8195_MMSYS_H */
> > diff --git a/drivers/soc/mediatek/mtk-mmsys.c
> > b/drivers/soc/mediatek/mtk-mmsys.c
> > index 4fc4c2c9ea20..548efed8dc1c 100644
> > --- a/drivers/soc/mediatek/mtk-mmsys.c
> > +++ b/drivers/soc/mediatek/mtk-mmsys.c
> > @@ -17,6 +17,7 @@
> > #include "mt8183-mmsys.h"
> > #include "mt8186-mmsys.h"
> > #include "mt8192-mmsys.h"
> > +#include "mt8195-mmsys.h"
> > #include "mt8365-mmsys.h"
> >
> > static const struct mtk_mmsys_driver_data
> > mt2701_mmsys_driver_data = {
> > @@ -25,26 +26,61 @@ static const struct mtk_mmsys_driver_data
> > mt2701_mmsys_driver_data = {
> > .num_routes = ARRAY_SIZE(mmsys_default_routing_table),
> > };
> >
> > +static const struct mtk_mmsys_match_data mt2701_mmsys_match_data =
> > {
> > + .num_drv_data = 1,
> > + .drv_data = {
> > + &mt2701_mmsys_driver_data,
> > + },
> > +};
> > +
> > static const struct mtk_mmsys_driver_data
> > mt2712_mmsys_driver_data = {
> > .clk_driver = "clk-mt2712-mm",
> > .routes = mmsys_default_routing_table,
> > .num_routes = ARRAY_SIZE(mmsys_default_routing_table),
> > };
> >
> > +static const struct mtk_mmsys_match_data mt2712_mmsys_match_data =
> > {
> > + .num_drv_data = 1,
> > + .drv_data = {
> > + &mt2712_mmsys_driver_data,
> > + },
> > +};
> > +
> > static const struct mtk_mmsys_driver_data
> > mt6779_mmsys_driver_data = {
> > .clk_driver = "clk-mt6779-mm",
> > };
> >
> > +static const struct mtk_mmsys_match_data mt6779_mmsys_match_data =
> > {
> > + .num_drv_data = 1,
> > + .drv_data = {
> > + &mt6779_mmsys_driver_data,
> > + },
> > +};
> > +
> > static const struct mtk_mmsys_driver_data
> > mt6797_mmsys_driver_data = {
> > .clk_driver = "clk-mt6797-mm",
> > };
> >
> > +static const struct mtk_mmsys_match_data mt6797_mmsys_match_data =
> > {
> > + .num_drv_data = 1,
> > + .drv_data = {
> > + &mt6797_mmsys_driver_data,
> > + },
> > +};
> > +
> > static const struct mtk_mmsys_driver_data
> > mt8167_mmsys_driver_data = {
> > .clk_driver = "clk-mt8167-mm",
> > .routes = mt8167_mmsys_routing_table,
> > .num_routes = ARRAY_SIZE(mt8167_mmsys_routing_table),
> > };
> >
> > +static const struct mtk_mmsys_match_data mt8167_mmsys_match_data =
> > {
> > + .num_drv_data = 1,
> > + .drv_data = {
> > + &mt8167_mmsys_driver_data,
> > + },
> > +};
> > +
> > static const struct mtk_mmsys_driver_data
> > mt8173_mmsys_driver_data = {
> > .clk_driver = "clk-mt8173-mm",
> > .routes = mmsys_default_routing_table,
> > @@ -52,6 +88,13 @@ static const struct mtk_mmsys_driver_data
> > mt8173_mmsys_driver_data = {
> > .sw0_rst_offset = MT8183_MMSYS_SW0_RST_B,
> > };
> >
> > +static const struct mtk_mmsys_match_data mt8173_mmsys_match_data =
> > {
> > + .num_drv_data = 1,
> > + .drv_data = {
> > + &mt8173_mmsys_driver_data,
> > + },
> > +};
> > +
> > static const struct mtk_mmsys_driver_data
> > mt8183_mmsys_driver_data = {
> > .clk_driver = "clk-mt8183-mm",
> > .routes = mmsys_mt8183_routing_table,
> > @@ -59,6 +102,13 @@ static const struct mtk_mmsys_driver_data
> > mt8183_mmsys_driver_data = {
> > .sw0_rst_offset = MT8183_MMSYS_SW0_RST_B,
> > };
> >
> > +static const struct mtk_mmsys_match_data mt8183_mmsys_match_data =
> > {
> > + .num_drv_data = 1,
> > + .drv_data = {
> > + &mt8183_mmsys_driver_data,
> > + },
> > +};
> > +
> > static const struct mtk_mmsys_driver_data
> > mt8186_mmsys_driver_data = {
> > .clk_driver = "clk-mt8186-mm",
> > .routes = mmsys_mt8186_routing_table,
> > @@ -66,25 +116,79 @@ static const struct mtk_mmsys_driver_data
> > mt8186_mmsys_driver_data = {
> > .sw0_rst_offset = MT8186_MMSYS_SW0_RST_B,
> > };
> >
> > +static const struct mtk_mmsys_match_data mt8186_mmsys_match_data =
> > {
> > + .num_drv_data = 1,
> > + .drv_data = {
> > + &mt8186_mmsys_driver_data,
> > + },
> > +};
> > +
> > static const struct mtk_mmsys_driver_data
> > mt8192_mmsys_driver_data = {
> > .clk_driver = "clk-mt8192-mm",
> > .routes = mmsys_mt8192_routing_table,
> > .num_routes = ARRAY_SIZE(mmsys_mt8192_routing_table),
> > };
> >
> > +static const struct mtk_mmsys_match_data mt8192_mmsys_match_data =
> > {
> > + .num_drv_data = 1,
> > + .drv_data = {
> > + &mt8192_mmsys_driver_data,
> > + },
> > +};
> > +
> > +static const struct mtk_mmsys_driver_data
> > mt8195_vdosys0_driver_data = {
> > + .io_start = 0x1c01a000,
> > + .clk_driver = "clk-mt8195-vdo0",
> > + .routes = mmsys_mt8195_routing_table,
> > + .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
> > +};
> > +
> > +static const struct mtk_mmsys_driver_data
> > mt8195_vdosys1_driver_data = {
> > + .io_start = 0x1c100000,
> > + .clk_driver = "clk-mt8195-vdo1",
> > +};
> > +
> > +static const struct mtk_mmsys_match_data mt8195_mmsys_match_data =
> > {
> > + .num_drv_data = 2,
> > + .drv_data = {
> > + &mt8195_vdosys0_driver_data,
> > + &mt8195_vdosys1_driver_data,
> > + },
> > +};
> > +
> > static const struct mtk_mmsys_driver_data
> > mt8365_mmsys_driver_data = {
> > .clk_driver = "clk-mt8365-mm",
> > .routes = mt8365_mmsys_routing_table,
> > .num_routes = ARRAY_SIZE(mt8365_mmsys_routing_table),
> > };
> >
> > +static const struct mtk_mmsys_match_data mt8365_mmsys_match_data =
> > {
> > + .num_drv_data = 1,
> > + .drv_data = {
> > + &mt8365_mmsys_driver_data,
> > + },
> > +};
> > +
> > struct mtk_mmsys {
> > void __iomem *regs;
> > const struct mtk_mmsys_driver_data *data;
> > spinlock_t lock; /* protects mmsys_sw_rst_b reg */
> > struct reset_controller_dev rcdev;
> > + phys_addr_t io_start;
> > };
> >
> > +static int mtk_mmsys_find_match_drvdata(struct mtk_mmsys *mmsys,
> > + const struct
> > mtk_mmsys_match_data *match)
> > +{
> > + int i;
> > +
> > + for (i = 0; i < match->num_drv_data; i++)
> > + if (mmsys->io_start == match->drv_data[i]->io_start)
> > + return i;
> > +
> > + return -EINVAL;
> > +}
> > +
> > void mtk_mmsys_ddp_connect(struct device *dev,
> > enum mtk_ddp_comp_id cur,
> > enum mtk_ddp_comp_id next)
> > @@ -179,7 +283,9 @@ static int mtk_mmsys_probe(struct
> > platform_device *pdev)
> > struct device *dev = &pdev->dev;
> > struct platform_device *clks;
> > struct platform_device *drm;
> > + const struct mtk_mmsys_match_data *match_data;
> > struct mtk_mmsys *mmsys;
> > + struct resource *res;
> > int ret;
> >
> > mmsys = devm_kzalloc(dev, sizeof(*mmsys), GFP_KERNEL);
> > @@ -205,7 +311,27 @@ static int mtk_mmsys_probe(struct
> > platform_device *pdev)
> > return ret;
> > }
> >
> > - mmsys->data = of_device_get_match_data(&pdev->dev);
> > + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > + if (!res) {
> > + dev_err(dev, "Couldn't get mmsys resource\n");
> > + return -EINVAL;
> > + }
> > + mmsys->io_start = res->start;
> > +
> > + match_data = of_device_get_match_data(dev);
> > + if (match_data->num_drv_data > 1) {
> > + /* This SoC has multiple mmsys channels */
> > + ret = mtk_mmsys_find_match_drvdata(mmsys, match_data);
> > + if (ret < 0) {
> > + dev_err(dev, "Couldn't get match driver
> > data\n");
> > + return ret;
> > + }
> > + mmsys->data = match_data->drv_data[ret];
> > + } else {
> > + dev_dbg(dev, "Using single mmsys channel\n");
> > + mmsys->data = match_data->drv_data[0];
> > + }
> > +
> > platform_set_drvdata(pdev, mmsys);
> >
> > clks = platform_device_register_data(&pdev->dev, mmsys->data-
> > >clk_driver,
> > @@ -226,43 +352,47 @@ static int mtk_mmsys_probe(struct
> > platform_device *pdev)
> > static const struct of_device_id of_match_mtk_mmsys[] = {
> > {
> > .compatible = "mediatek,mt2701-mmsys",
> > - .data = &mt2701_mmsys_driver_data,
> > + .data = &mt2701_mmsys_match_data,
> > },
> > {
> > .compatible = "mediatek,mt2712-mmsys",
> > - .data = &mt2712_mmsys_driver_data,
> > + .data = &mt2712_mmsys_match_data,
> > },
> > {
> > .compatible = "mediatek,mt6779-mmsys",
> > - .data = &mt6779_mmsys_driver_data,
> > + .data = &mt6779_mmsys_match_data,
> > },
> > {
> > .compatible = "mediatek,mt6797-mmsys",
> > - .data = &mt6797_mmsys_driver_data,
> > + .data = &mt6797_mmsys_match_data,
> > },
> > {
> > .compatible = "mediatek,mt8167-mmsys",
> > - .data = &mt8167_mmsys_driver_data,
> > + .data = &mt8167_mmsys_match_data,
> > },
> > {
> > .compatible = "mediatek,mt8173-mmsys",
> > - .data = &mt8173_mmsys_driver_data,
> > + .data = &mt8173_mmsys_match_data,
> > },
> > {
> > .compatible = "mediatek,mt8183-mmsys",
> > - .data = &mt8183_mmsys_driver_data,
> > + .data = &mt8183_mmsys_match_data,
> > },
> > {
> > .compatible = "mediatek,mt8186-mmsys",
> > - .data = &mt8186_mmsys_driver_data,
> > + .data = &mt8186_mmsys_match_data,
> > },
> > {
> > .compatible = "mediatek,mt8192-mmsys",
> > - .data = &mt8192_mmsys_driver_data,
> > + .data = &mt8192_mmsys_match_data,
> > + },
> > + {
> > + .compatible = "mediatek,mt8195-mmsys",
> > + .data = &mt8195_mmsys_match_data,
> > },
> > {
> > .compatible = "mediatek,mt8365-mmsys",
> > - .data = &mt8365_mmsys_driver_data,
> > + .data = &mt8365_mmsys_match_data,
> > },
> > { }
> > };
> > diff --git a/drivers/soc/mediatek/mtk-mmsys.h
> > b/drivers/soc/mediatek/mtk-mmsys.h
> > index 77f37f8c715b..f01ba206481d 100644
> > --- a/drivers/soc/mediatek/mtk-mmsys.h
> > +++ b/drivers/soc/mediatek/mtk-mmsys.h
> > @@ -87,12 +87,18 @@ struct mtk_mmsys_routes {
> > };
> >
> > struct mtk_mmsys_driver_data {
> > + const resource_size_t io_start;
> > const char *clk_driver;
> > const struct mtk_mmsys_routes *routes;
> > const unsigned int num_routes;
> > const u16 sw0_rst_offset;
> > };
> >
> > +struct mtk_mmsys_match_data {
> > + unsigned short num_drv_data;
> > + const struct mtk_mmsys_driver_data *drv_data[];
> > +};
> > +
> > /*
> > * Routes in mt8173, mt2701, mt2712 are different. That means
> > * in the same register address, it controls different
> > input/output
> > diff --git a/include/linux/soc/mediatek/mtk-mmsys.h
> > b/include/linux/soc/mediatek/mtk-mmsys.h
> > index 4bba275e235a..cff5c9adbf46 100644
> > --- a/include/linux/soc/mediatek/mtk-mmsys.h
> > +++ b/include/linux/soc/mediatek/mtk-mmsys.h
> > @@ -17,13 +17,24 @@ enum mtk_ddp_comp_id {
> > DDP_COMPONENT_COLOR0,
> > DDP_COMPONENT_COLOR1,
> > DDP_COMPONENT_DITHER,
> > + DDP_COMPONENT_DITHER1,
> > + DDP_COMPONENT_DP_INTF0,
> > + DDP_COMPONENT_DP_INTF1,
> > DDP_COMPONENT_DPI0,
> > DDP_COMPONENT_DPI1,
> > + DDP_COMPONENT_DSC0,
> > + DDP_COMPONENT_DSC1,
> > DDP_COMPONENT_DSI0,
> > DDP_COMPONENT_DSI1,
> > DDP_COMPONENT_DSI2,
> > DDP_COMPONENT_DSI3,
> > DDP_COMPONENT_GAMMA,
> > + DDP_COMPONENT_MERGE0,
> > + DDP_COMPONENT_MERGE1,
> > + DDP_COMPONENT_MERGE2,
> > + DDP_COMPONENT_MERGE3,
> > + DDP_COMPONENT_MERGE4,
> > + DDP_COMPONENT_MERGE5,
> > DDP_COMPONENT_OD0,
> > DDP_COMPONENT_OD1,
> > DDP_COMPONENT_OVL0,
c--
Jason-JH Lin <jason-jh.lin@mediatek.com>
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [PATCH v20 1/8] soc: mediatek: add mtk-mmsys support for mt8195 vdosys0
@ 2022-04-24 8:47 ` Jason-JH Lin
0 siblings, 0 replies; 110+ messages in thread
From: Jason-JH Lin @ 2022-04-24 8:47 UTC (permalink / raw)
To: Matthias Brugger, Chun-Kuang Hu, AngeloGioacchino Del Regno
Cc: CK Hu, Nancy Lin, Singo Chang, devicetree, linux-kernel,
dri-devel, linux-mediatek, linux-arm-kernel,
Project_Global_Chrome_Upstream_Group
Hi Matthias,
Thanks for the reviews.
On Fri, 2022-04-22 at 14:28 +0200, Matthias Brugger wrote:
>
> On 19/04/2022 11:41, jason-jh.lin wrote:
> > 1. Add mt8195 mmsys compatible for 2 vdosys.
> > 2. Add io_start into each driver data of mt8195 vdosys.
> > 3. Add get match data function to identify mmsys by io_start.
> > 4. Add mt8195 routing table settings of vdosys0.
> >
> > Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> > Reviewed-by: AngeloGioacchino Del Regno <
> > angelogioacchino.delregno@collabora.com>
>
> I'm not very happy with the approach of testing against the reg
> property to
> decide which version of the two mmsys devices we are probing. I think
> a better
> approach would be, if we would have added some mediatek specific ID
> to the
> device tree binding (or use a two compatibles?).
>
We uses two compatibles in previous version(before v16) of this series.
https://patchwork.kernel.org/project/linux-mediatek/patch/20220307032859.3275-5-jason-jh.lin@mediatek.com/
Since we received the comment of VPPSYS from Rob:
https://patchwork.kernel.org/project/linux-mediatek/patch/20220117055254.9777-15-roy-cw.yeh@mediatek.com/#24707362
we're trying to figure out the way to use the same compatible for
different mmsys.
> But as we are at v20 I think it wouldn't be fair to ask for such an
> instrusive
> change. So I'll take this patch now, but maybe we can discuss if we
> can't do
> better in a follow-up patch. Especially I don't think it's a good
> approach to
> check for the io_start in the DRM driver. Couldn't we pass the
> information about
> which of the two mmsys blocks we are calling from through the
> mediatek-drm
> platform device spefic data?
>
But we can't find a suitable property to identify the different mmsys
directly.
In mt8195, 2 pipelines are binding to different mmsys, such as vdosys0
and vdosys1. Each mmsys uses different clock drivers and different
power domain.
Since each mmsys has its own clock, I have tried to differentiate
vdosys0, vdosys1 by the clock names:
https://patchwork.kernel.org/project/linux-mediatek/patch/20220407030409.9664-4-jason-jh.lin@mediatek.com/
But it seems not robust enough.
Then we refer to this io_start solution, the idea from Angelo:
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c?h=next-20220408#n789
I'm not sure if there is another more suitable idea to fit in this
problem.
But I believe, if using different compatibles for each mmsys is
acceptable, then we can keep the original compatible method for
mediatek-drm and mmsys, and also make these works easier.
If you have any ideas to simplify it, please help us :-)
Thanks for your reviews again.
Regards,
Jason-JH.Lin
> I also had a look into the vdosys1 series to better understand why we
> need to do
> things as we do them. But honestly I wasn't able to really understand
> the
> implication of the patch that adds 'multi mmsys support' [1]. For
> this looks
> like a several patches that got squashed into one. But as I don't
> have to
> maintain that it is not my call to complain, the patch has the needed
> reviews.
>
> For this patch, now applied to v5.18-next/soc
>
> Thanks for all people implicated.
>
> Regards,
> Matthias
>
> [1]
>
https://urldefense.com/v3/__https://patchwork.kernel.org/project/linux-mediatek/patch/20220416020749.29010-19-nancy.lin@mediatek.com/__;!!CTRNKA9wMg0ARbw!zwfxXhyNG9gAnlrIB72IpyBFsLEm6pzLdRVgomyZ5tLat_Ddf3e3LenemQDeRVLWEf_p$
>
>
> > ---
> > Based on series [1]
> >
> > [1] MediaTek MT8195 display binding
> > -
> > https://urldefense.com/v3/__https://patchwork.ozlabs.org/project/devicetree-bindings/list/?series=295669__;!!CTRNKA9wMg0ARbw!zwfxXhyNG9gAnlrIB72IpyBFsLEm6pzLdRVgomyZ5tLat_Ddf3e3LenemQDeRXN1cxii$
> >
> > ---
> > drivers/soc/mediatek/mt8195-mmsys.h | 370
> > +++++++++++++++++++++++++
> > drivers/soc/mediatek/mtk-mmsys.c | 152 +++++++++-
> > drivers/soc/mediatek/mtk-mmsys.h | 6 +
> > include/linux/soc/mediatek/mtk-mmsys.h | 11 +
> > 4 files changed, 528 insertions(+), 11 deletions(-)
> > create mode 100644 drivers/soc/mediatek/mt8195-mmsys.h
> >
> > diff --git a/drivers/soc/mediatek/mt8195-mmsys.h
> > b/drivers/soc/mediatek/mt8195-mmsys.h
> > new file mode 100644
> > index 000000000000..13ab0ab64396
> > --- /dev/null
> > +++ b/drivers/soc/mediatek/mt8195-mmsys.h
> > @@ -0,0 +1,370 @@
> > +/* SPDX-License-Identifier: GPL-2.0-only */
> > +
> > +#ifndef __SOC_MEDIATEK_MT8195_MMSYS_H
> > +#define __SOC_MEDIATEK_MT8195_MMSYS_H
> > +
> > +#define MT8195_VDO0_OVL_MOUT_EN
> > 0xf14
> > +#define MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0
> > BIT(0)
> > +#define MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0
> > BIT(1)
> > +#define MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1 BIT(2)
> > +#define MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1
> > BIT(4)
> > +#define MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1
> > BIT(5)
> > +#define MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0 BIT(6)
> > +
> > +#define MT8195_VDO0_SEL_IN 0xf34
> > +#define MT8195_SEL_IN_VPP_MERGE_FROM_MASK GENMASK
> > (1, 0)
> > +#define MT8195_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT (0 <<
> > 0)
> > +#define MT8195_SEL_IN_VPP_MERGE_FROM_DISP_DITHER1 (1 <<
> > 0)
> > +#define MT8195_SEL_IN_VPP_MERGE_FROM_VDO1_VIRTUAL0 (2 <<
> > 0)
> > +#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK
> > GENMASK(4, 4)
> > +#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0
> > (0 << 4)
> > +#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_VPP_MERGE (1 <<
> > 4)
> > +#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_MASK
> > GENMASK(5, 5)
> > +#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_DISP_DITHER1
> > (0 << 5)
> > +#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_VPP_MERGE (1 <<
> > 5)
> > +#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK
> > GENMASK(8, 8)
> > +#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE (0 <<
> > 8)
> > +#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT
> > (1 << 8)
> > +#define MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK
> > GENMASK(9, 9)
> > +#define MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT
> > (0 << 9)
> > +#define MT8195_SEL_IN_DP_INTF0_FROM_MASK GENMASK
> > (13, 12)
> > +#define MT8195_SEL_IN_DP_INTF0_FROM_DSC_WRAP1_OUT (0 <<
> > 0)
> > +#define MT8195_SEL_IN_DP_INTF0_FROM_VPP_MERGE
> > (1 << 12)
> > +#define MT8195_SEL_IN_DP_INTF0_FROM_VDO1_VIRTUAL0 (2 <<
> > 12)
> > +#define MT8195_SEL_IN_DSI0_FROM_MASK
> > GENMASK(16, 16)
> > +#define MT8195_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT
> > (0 << 16)
> > +#define MT8195_SEL_IN_DSI0_FROM_DISP_DITHER0
> > (1 << 16)
> > +#define MT8195_SEL_IN_DSI1_FROM_MASK
> > GENMASK(17, 17)
> > +#define MT8195_SEL_IN_DSI1_FROM_DSC_WRAP1_OUT
> > (0 << 17)
> > +#define MT8195_SEL_IN_DSI1_FROM_VPP_MERGE (1 <<
> > 17)
> > +#define MT8195_SEL_IN_DISP_WDMA1_FROM_MASK GENMASK
> > (20, 20)
> > +#define MT8195_SEL_IN_DISP_WDMA1_FROM_DISP_OVL1
> > (0 << 20)
> > +#define MT8195_SEL_IN_DISP_WDMA1_FROM_VPP_MERGE
> > (1 << 20)
> > +#define MT8195_SEL_IN_DSC_WRAP1_FROM_MASK GENMASK
> > (21, 21)
> > +#define MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
> > (0 << 21)
> > +#define MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1
> > (1 << 21)
> > +#define MT8195_SEL_IN_DISP_WDMA0_FROM_MASK GENMASK
> > (22, 22)
> > +#define MT8195_SEL_IN_DISP_WDMA0_FROM_DISP_OVL0
> > (0 << 22)
> > +
> > +#define MT8195_VDO0_SEL_OUT
> > 0xf38
> > +#define MT8195_SOUT_DISP_DITHER0_TO_MASK BIT(0)
> > +#define MT8195_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN (0 <<
> > 0)
> > +#define MT8195_SOUT_DISP_DITHER0_TO_DSI0 (1 <<
> > 0)
> > +#define MT8195_SOUT_DISP_DITHER1_TO_MASK GENMASK
> > (2, 1)
> > +#define MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_IN (0 <<
> > 1)
> > +#define MT8195_SOUT_DISP_DITHER1_TO_VPP_MERGE
> > (1 << 1)
> > +#define MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT (2 <<
> > 1)
> > +#define MT8195_SOUT_VDO1_VIRTUAL0_TO_MASK GENMASK
> > (4, 4)
> > +#define MT8195_SOUT_VDO1_VIRTUAL0_TO_VPP_MERGE
> > (0 << 4)
> > +#define MT8195_SOUT_VDO1_VIRTUAL0_TO_DP_INTF0
> > (1 << 4)
> > +#define MT8195_SOUT_VPP_MERGE_TO_MASK
> > GENMASK(10, 8)
> > +#define MT8195_SOUT_VPP_MERGE_TO_DSI1
> > (0 << 8)
> > +#define MT8195_SOUT_VPP_MERGE_TO_DP_INTF0 (1 <<
> > 8)
> > +#define MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0
> > (2 << 8)
> > +#define MT8195_SOUT_VPP_MERGE_TO_DISP_WDMA1
> > (3 << 8)
> > +#define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP0_IN
> > (4 << 8)
> > +#define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN_MASK GENMASK
> > (11, 11)
> > +#define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN
> > (0 << 11)
> > +#define MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK GENMASK
> > (13, 12)
> > +#define MT8195_SOUT_DSC_WRAP0_OUT_TO_DSI0 (0 <<
> > 12)
> > +#define MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0 (1 <<
> > 12)
> > +#define MT8195_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE
> > (2 << 12)
> > +#define MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK GENMASK
> > (17, 16)
> > +#define MT8195_SOUT_DSC_WRAP1_OUT_TO_DSI1 (0 <<
> > 16)
> > +#define MT8195_SOUT_DSC_WRAP1_OUT_TO_DP_INTF0
> > (1 << 16)
> > +#define MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0 (2 <<
> > 16)
> > +#define MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE
> > (3 << 16)
> > +
> > +static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[]
> > = {
> > + {
> > + DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
> > + MT8195_VDO0_OVL_MOUT_EN,
> > MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0,
> > + MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0
> > + }, {
> > + DDP_COMPONENT_OVL0, DDP_COMPONENT_WDMA0,
> > + MT8195_VDO0_OVL_MOUT_EN,
> > MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0,
> > + MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0
> > + }, {
> > + DDP_COMPONENT_OVL0, DDP_COMPONENT_OVL1,
> > + MT8195_VDO0_OVL_MOUT_EN,
> > MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1,
> > + MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1
> > + }, {
> > + DDP_COMPONENT_OVL1, DDP_COMPONENT_RDMA1,
> > + MT8195_VDO0_OVL_MOUT_EN,
> > MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1,
> > + MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1
> > + }, {
> > + DDP_COMPONENT_OVL1, DDP_COMPONENT_WDMA1,
> > + MT8195_VDO0_OVL_MOUT_EN,
> > MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1,
> > + MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1
> > + }, {
> > + DDP_COMPONENT_OVL1, DDP_COMPONENT_OVL0,
> > + MT8195_VDO0_OVL_MOUT_EN,
> > MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0,
> > + MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0
> > + }, {
> > + DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0,
> > + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK,
> > + MT8195_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT
> > + }, {
> > + DDP_COMPONENT_DITHER1, DDP_COMPONENT_MERGE0,
> > + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK,
> > + MT8195_SEL_IN_VPP_MERGE_FROM_DISP_DITHER1
> > + }, {
> > + DDP_COMPONENT_MERGE5, DDP_COMPONENT_MERGE0,
> > + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK,
> > + MT8195_SEL_IN_VPP_MERGE_FROM_VDO1_VIRTUAL0
> > + }, {
> > + DDP_COMPONENT_DITHER, DDP_COMPONENT_DSC0,
> > + MT8195_VDO0_SEL_IN,
> > MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK,
> > + MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0
> > + }, {
> > + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC0,
> > + MT8195_VDO0_SEL_IN,
> > MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK,
> > + MT8195_SEL_IN_DSC_WRAP0_IN_FROM_VPP_MERGE
> > + }, {
> > + DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSC1,
> > + MT8195_VDO0_SEL_IN,
> > MT8195_SEL_IN_DSC_WRAP1_IN_FROM_MASK,
> > + MT8195_SEL_IN_DSC_WRAP1_IN_FROM_DISP_DITHER1
> > + }, {
> > + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC1,
> > + MT8195_VDO0_SEL_IN,
> > MT8195_SEL_IN_DSC_WRAP1_IN_FROM_MASK,
> > + MT8195_SEL_IN_DSC_WRAP1_IN_FROM_VPP_MERGE
> > + }, {
> > + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF1,
> > + MT8195_VDO0_SEL_IN,
> > MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
> > + MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE
> > + }, {
> > + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI0,
> > + MT8195_VDO0_SEL_IN,
> > MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
> > + MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE
> > + }, {
> > + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI1,
> > + MT8195_VDO0_SEL_IN,
> > MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
> > + MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE
> > + }, {
> > + DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF1,
> > + MT8195_VDO0_SEL_IN,
> > MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
> > + MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT
> > + }, {
> > + DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI0,
> > + MT8195_VDO0_SEL_IN,
> > MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
> > + MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT
> > + }, {
> > + DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI1,
> > + MT8195_VDO0_SEL_IN,
> > MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
> > + MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT
> > + }, {
> > + DDP_COMPONENT_DSC0, DDP_COMPONENT_DP_INTF1,
> > + MT8195_VDO0_SEL_IN,
> > MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK,
> > + MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT
> > + }, {
> > + DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI0,
> > + MT8195_VDO0_SEL_IN,
> > MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK,
> > + MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT
> > + }, {
> > + DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI1,
> > + MT8195_VDO0_SEL_IN,
> > MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK,
> > + MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT
> > + }, {
> > + DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF0,
> > + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_MASK,
> > + MT8195_SEL_IN_DP_INTF0_FROM_DSC_WRAP1_OUT
> > + }, {
> > + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF0,
> > + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_MASK,
> > + MT8195_SEL_IN_DP_INTF0_FROM_VPP_MERGE
> > + }, {
> > + DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF0,
> > + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_MASK,
> > + MT8195_SEL_IN_DP_INTF0_FROM_VDO1_VIRTUAL0
> > + }, {
> > + DDP_COMPONENT_DSC0, DDP_COMPONENT_DSI0,
> > + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI0_FROM_MASK,
> > + MT8195_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT
> > + }, {
> > + DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
> > + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI0_FROM_MASK,
> > + MT8195_SEL_IN_DSI0_FROM_DISP_DITHER0
> > + }, {
> > + DDP_COMPONENT_DSC1, DDP_COMPONENT_DSI1,
> > + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI1_FROM_MASK,
> > + MT8195_SEL_IN_DSI1_FROM_DSC_WRAP1_OUT
> > + }, {
> > + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSI1,
> > + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI1_FROM_MASK,
> > + MT8195_SEL_IN_DSI1_FROM_VPP_MERGE
> > + }, {
> > + DDP_COMPONENT_OVL1, DDP_COMPONENT_WDMA1,
> > + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA1_FROM_MASK,
> > + MT8195_SEL_IN_DISP_WDMA1_FROM_DISP_OVL1
> > + }, {
> > + DDP_COMPONENT_MERGE0, DDP_COMPONENT_WDMA1,
> > + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA1_FROM_MASK,
> > + MT8195_SEL_IN_DISP_WDMA1_FROM_VPP_MERGE
> > + }, {
> > + DDP_COMPONENT_DSC1, DDP_COMPONENT_DSI1,
> > + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
> > + MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
> > + }, {
> > + DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF0,
> > + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
> > + MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
> > + }, {
> > + DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF1,
> > + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
> > + MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
> > + }, {
> > + DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI0,
> > + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
> > + MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
> > + }, {
> > + DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI1,
> > + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
> > + MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
> > + }, {
> > + DDP_COMPONENT_DSC1, DDP_COMPONENT_MERGE0,
> > + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
> > + MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
> > + }, {
> > + DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSI1,
> > + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
> > + MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1
> > + }, {
> > + DDP_COMPONENT_DITHER1, DDP_COMPONENT_DP_INTF0,
> > + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
> > + MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1
> > + }, {
> > + DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI0,
> > + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
> > + MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1
> > + }, {
> > + DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI1,
> > + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
> > + MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1
> > + }, {
> > + DDP_COMPONENT_OVL0, DDP_COMPONENT_WDMA0,
> > + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA0_FROM_MASK,
> > + MT8195_SEL_IN_DISP_WDMA0_FROM_DISP_OVL0
> > + }, {
> > + DDP_COMPONENT_DITHER, DDP_COMPONENT_DSC0,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER0_TO_MASK,
> > + MT8195_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN
> > + }, {
> > + DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER0_TO_MASK,
> > + MT8195_SOUT_DISP_DITHER0_TO_DSI0
> > + }, {
> > + DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSC1,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
> > + MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_IN
> > + }, {
> > + DDP_COMPONENT_DITHER1, DDP_COMPONENT_MERGE0,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
> > + MT8195_SOUT_DISP_DITHER1_TO_VPP_MERGE
> > + }, {
> > + DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSI1,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
> > + MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT
> > + }, {
> > + DDP_COMPONENT_DITHER1, DDP_COMPONENT_DP_INTF0,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
> > + MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT
> > + }, {
> > + DDP_COMPONENT_DITHER1, DDP_COMPONENT_DP_INTF1,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
> > + MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT
> > + }, {
> > + DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI0,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
> > + MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT
> > + }, {
> > + DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI1,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
> > + MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT
> > + }, {
> > + DDP_COMPONENT_MERGE5, DDP_COMPONENT_MERGE0,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_VDO1_VIRTUAL0_TO_MASK,
> > + MT8195_SOUT_VDO1_VIRTUAL0_TO_VPP_MERGE
> > + }, {
> > + DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF0,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_VDO1_VIRTUAL0_TO_MASK,
> > + MT8195_SOUT_VDO1_VIRTUAL0_TO_DP_INTF0
> > + }, {
> > + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSI1,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
> > + MT8195_SOUT_VPP_MERGE_TO_DSI1
> > + }, {
> > + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF0,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
> > + MT8195_SOUT_VPP_MERGE_TO_DP_INTF0
> > + }, {
> > + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF1,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
> > + MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0
> > + }, {
> > + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI0,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
> > + MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0
> > + }, {
> > + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI1,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
> > + MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0
> > + }, {
> > + DDP_COMPONENT_MERGE0, DDP_COMPONENT_WDMA1,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
> > + MT8195_SOUT_VPP_MERGE_TO_DISP_WDMA1
> > + }, {
> > + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC0,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
> > + MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP0_IN
> > + }, {
> > + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC1,
> > + MT8195_VDO0_SEL_OUT,
> > MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN_MASK,
> > + MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN
> > + }, {
> > + DDP_COMPONENT_DSC0, DDP_COMPONENT_DSI0,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
> > + MT8195_SOUT_DSC_WRAP0_OUT_TO_DSI0
> > + }, {
> > + DDP_COMPONENT_DSC0, DDP_COMPONENT_DP_INTF1,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
> > + MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0
> > + }, {
> > + DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI0,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
> > + MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0
> > + }, {
> > + DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI1,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
> > + MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0
> > + }, {
> > + DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
> > + MT8195_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE
> > + }, {
> > + DDP_COMPONENT_DSC1, DDP_COMPONENT_DSI1,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
> > + MT8195_SOUT_DSC_WRAP1_OUT_TO_DSI1
> > + }, {
> > + DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF0,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
> > + MT8195_SOUT_DSC_WRAP1_OUT_TO_DP_INTF0
> > + }, {
> > + DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF1,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
> > + MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0
> > + }, {
> > + DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI0,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
> > + MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0
> > + }, {
> > + DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI1,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
> > + MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0
> > + }, {
> > + DDP_COMPONENT_DSC1, DDP_COMPONENT_MERGE0,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
> > + MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE
> > + }
> > +};
> > +
> > +#endif /* __SOC_MEDIATEK_MT8195_MMSYS_H */
> > diff --git a/drivers/soc/mediatek/mtk-mmsys.c
> > b/drivers/soc/mediatek/mtk-mmsys.c
> > index 4fc4c2c9ea20..548efed8dc1c 100644
> > --- a/drivers/soc/mediatek/mtk-mmsys.c
> > +++ b/drivers/soc/mediatek/mtk-mmsys.c
> > @@ -17,6 +17,7 @@
> > #include "mt8183-mmsys.h"
> > #include "mt8186-mmsys.h"
> > #include "mt8192-mmsys.h"
> > +#include "mt8195-mmsys.h"
> > #include "mt8365-mmsys.h"
> >
> > static const struct mtk_mmsys_driver_data
> > mt2701_mmsys_driver_data = {
> > @@ -25,26 +26,61 @@ static const struct mtk_mmsys_driver_data
> > mt2701_mmsys_driver_data = {
> > .num_routes = ARRAY_SIZE(mmsys_default_routing_table),
> > };
> >
> > +static const struct mtk_mmsys_match_data mt2701_mmsys_match_data =
> > {
> > + .num_drv_data = 1,
> > + .drv_data = {
> > + &mt2701_mmsys_driver_data,
> > + },
> > +};
> > +
> > static const struct mtk_mmsys_driver_data
> > mt2712_mmsys_driver_data = {
> > .clk_driver = "clk-mt2712-mm",
> > .routes = mmsys_default_routing_table,
> > .num_routes = ARRAY_SIZE(mmsys_default_routing_table),
> > };
> >
> > +static const struct mtk_mmsys_match_data mt2712_mmsys_match_data =
> > {
> > + .num_drv_data = 1,
> > + .drv_data = {
> > + &mt2712_mmsys_driver_data,
> > + },
> > +};
> > +
> > static const struct mtk_mmsys_driver_data
> > mt6779_mmsys_driver_data = {
> > .clk_driver = "clk-mt6779-mm",
> > };
> >
> > +static const struct mtk_mmsys_match_data mt6779_mmsys_match_data =
> > {
> > + .num_drv_data = 1,
> > + .drv_data = {
> > + &mt6779_mmsys_driver_data,
> > + },
> > +};
> > +
> > static const struct mtk_mmsys_driver_data
> > mt6797_mmsys_driver_data = {
> > .clk_driver = "clk-mt6797-mm",
> > };
> >
> > +static const struct mtk_mmsys_match_data mt6797_mmsys_match_data =
> > {
> > + .num_drv_data = 1,
> > + .drv_data = {
> > + &mt6797_mmsys_driver_data,
> > + },
> > +};
> > +
> > static const struct mtk_mmsys_driver_data
> > mt8167_mmsys_driver_data = {
> > .clk_driver = "clk-mt8167-mm",
> > .routes = mt8167_mmsys_routing_table,
> > .num_routes = ARRAY_SIZE(mt8167_mmsys_routing_table),
> > };
> >
> > +static const struct mtk_mmsys_match_data mt8167_mmsys_match_data =
> > {
> > + .num_drv_data = 1,
> > + .drv_data = {
> > + &mt8167_mmsys_driver_data,
> > + },
> > +};
> > +
> > static const struct mtk_mmsys_driver_data
> > mt8173_mmsys_driver_data = {
> > .clk_driver = "clk-mt8173-mm",
> > .routes = mmsys_default_routing_table,
> > @@ -52,6 +88,13 @@ static const struct mtk_mmsys_driver_data
> > mt8173_mmsys_driver_data = {
> > .sw0_rst_offset = MT8183_MMSYS_SW0_RST_B,
> > };
> >
> > +static const struct mtk_mmsys_match_data mt8173_mmsys_match_data =
> > {
> > + .num_drv_data = 1,
> > + .drv_data = {
> > + &mt8173_mmsys_driver_data,
> > + },
> > +};
> > +
> > static const struct mtk_mmsys_driver_data
> > mt8183_mmsys_driver_data = {
> > .clk_driver = "clk-mt8183-mm",
> > .routes = mmsys_mt8183_routing_table,
> > @@ -59,6 +102,13 @@ static const struct mtk_mmsys_driver_data
> > mt8183_mmsys_driver_data = {
> > .sw0_rst_offset = MT8183_MMSYS_SW0_RST_B,
> > };
> >
> > +static const struct mtk_mmsys_match_data mt8183_mmsys_match_data =
> > {
> > + .num_drv_data = 1,
> > + .drv_data = {
> > + &mt8183_mmsys_driver_data,
> > + },
> > +};
> > +
> > static const struct mtk_mmsys_driver_data
> > mt8186_mmsys_driver_data = {
> > .clk_driver = "clk-mt8186-mm",
> > .routes = mmsys_mt8186_routing_table,
> > @@ -66,25 +116,79 @@ static const struct mtk_mmsys_driver_data
> > mt8186_mmsys_driver_data = {
> > .sw0_rst_offset = MT8186_MMSYS_SW0_RST_B,
> > };
> >
> > +static const struct mtk_mmsys_match_data mt8186_mmsys_match_data =
> > {
> > + .num_drv_data = 1,
> > + .drv_data = {
> > + &mt8186_mmsys_driver_data,
> > + },
> > +};
> > +
> > static const struct mtk_mmsys_driver_data
> > mt8192_mmsys_driver_data = {
> > .clk_driver = "clk-mt8192-mm",
> > .routes = mmsys_mt8192_routing_table,
> > .num_routes = ARRAY_SIZE(mmsys_mt8192_routing_table),
> > };
> >
> > +static const struct mtk_mmsys_match_data mt8192_mmsys_match_data =
> > {
> > + .num_drv_data = 1,
> > + .drv_data = {
> > + &mt8192_mmsys_driver_data,
> > + },
> > +};
> > +
> > +static const struct mtk_mmsys_driver_data
> > mt8195_vdosys0_driver_data = {
> > + .io_start = 0x1c01a000,
> > + .clk_driver = "clk-mt8195-vdo0",
> > + .routes = mmsys_mt8195_routing_table,
> > + .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
> > +};
> > +
> > +static const struct mtk_mmsys_driver_data
> > mt8195_vdosys1_driver_data = {
> > + .io_start = 0x1c100000,
> > + .clk_driver = "clk-mt8195-vdo1",
> > +};
> > +
> > +static const struct mtk_mmsys_match_data mt8195_mmsys_match_data =
> > {
> > + .num_drv_data = 2,
> > + .drv_data = {
> > + &mt8195_vdosys0_driver_data,
> > + &mt8195_vdosys1_driver_data,
> > + },
> > +};
> > +
> > static const struct mtk_mmsys_driver_data
> > mt8365_mmsys_driver_data = {
> > .clk_driver = "clk-mt8365-mm",
> > .routes = mt8365_mmsys_routing_table,
> > .num_routes = ARRAY_SIZE(mt8365_mmsys_routing_table),
> > };
> >
> > +static const struct mtk_mmsys_match_data mt8365_mmsys_match_data =
> > {
> > + .num_drv_data = 1,
> > + .drv_data = {
> > + &mt8365_mmsys_driver_data,
> > + },
> > +};
> > +
> > struct mtk_mmsys {
> > void __iomem *regs;
> > const struct mtk_mmsys_driver_data *data;
> > spinlock_t lock; /* protects mmsys_sw_rst_b reg */
> > struct reset_controller_dev rcdev;
> > + phys_addr_t io_start;
> > };
> >
> > +static int mtk_mmsys_find_match_drvdata(struct mtk_mmsys *mmsys,
> > + const struct
> > mtk_mmsys_match_data *match)
> > +{
> > + int i;
> > +
> > + for (i = 0; i < match->num_drv_data; i++)
> > + if (mmsys->io_start == match->drv_data[i]->io_start)
> > + return i;
> > +
> > + return -EINVAL;
> > +}
> > +
> > void mtk_mmsys_ddp_connect(struct device *dev,
> > enum mtk_ddp_comp_id cur,
> > enum mtk_ddp_comp_id next)
> > @@ -179,7 +283,9 @@ static int mtk_mmsys_probe(struct
> > platform_device *pdev)
> > struct device *dev = &pdev->dev;
> > struct platform_device *clks;
> > struct platform_device *drm;
> > + const struct mtk_mmsys_match_data *match_data;
> > struct mtk_mmsys *mmsys;
> > + struct resource *res;
> > int ret;
> >
> > mmsys = devm_kzalloc(dev, sizeof(*mmsys), GFP_KERNEL);
> > @@ -205,7 +311,27 @@ static int mtk_mmsys_probe(struct
> > platform_device *pdev)
> > return ret;
> > }
> >
> > - mmsys->data = of_device_get_match_data(&pdev->dev);
> > + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > + if (!res) {
> > + dev_err(dev, "Couldn't get mmsys resource\n");
> > + return -EINVAL;
> > + }
> > + mmsys->io_start = res->start;
> > +
> > + match_data = of_device_get_match_data(dev);
> > + if (match_data->num_drv_data > 1) {
> > + /* This SoC has multiple mmsys channels */
> > + ret = mtk_mmsys_find_match_drvdata(mmsys, match_data);
> > + if (ret < 0) {
> > + dev_err(dev, "Couldn't get match driver
> > data\n");
> > + return ret;
> > + }
> > + mmsys->data = match_data->drv_data[ret];
> > + } else {
> > + dev_dbg(dev, "Using single mmsys channel\n");
> > + mmsys->data = match_data->drv_data[0];
> > + }
> > +
> > platform_set_drvdata(pdev, mmsys);
> >
> > clks = platform_device_register_data(&pdev->dev, mmsys->data-
> > >clk_driver,
> > @@ -226,43 +352,47 @@ static int mtk_mmsys_probe(struct
> > platform_device *pdev)
> > static const struct of_device_id of_match_mtk_mmsys[] = {
> > {
> > .compatible = "mediatek,mt2701-mmsys",
> > - .data = &mt2701_mmsys_driver_data,
> > + .data = &mt2701_mmsys_match_data,
> > },
> > {
> > .compatible = "mediatek,mt2712-mmsys",
> > - .data = &mt2712_mmsys_driver_data,
> > + .data = &mt2712_mmsys_match_data,
> > },
> > {
> > .compatible = "mediatek,mt6779-mmsys",
> > - .data = &mt6779_mmsys_driver_data,
> > + .data = &mt6779_mmsys_match_data,
> > },
> > {
> > .compatible = "mediatek,mt6797-mmsys",
> > - .data = &mt6797_mmsys_driver_data,
> > + .data = &mt6797_mmsys_match_data,
> > },
> > {
> > .compatible = "mediatek,mt8167-mmsys",
> > - .data = &mt8167_mmsys_driver_data,
> > + .data = &mt8167_mmsys_match_data,
> > },
> > {
> > .compatible = "mediatek,mt8173-mmsys",
> > - .data = &mt8173_mmsys_driver_data,
> > + .data = &mt8173_mmsys_match_data,
> > },
> > {
> > .compatible = "mediatek,mt8183-mmsys",
> > - .data = &mt8183_mmsys_driver_data,
> > + .data = &mt8183_mmsys_match_data,
> > },
> > {
> > .compatible = "mediatek,mt8186-mmsys",
> > - .data = &mt8186_mmsys_driver_data,
> > + .data = &mt8186_mmsys_match_data,
> > },
> > {
> > .compatible = "mediatek,mt8192-mmsys",
> > - .data = &mt8192_mmsys_driver_data,
> > + .data = &mt8192_mmsys_match_data,
> > + },
> > + {
> > + .compatible = "mediatek,mt8195-mmsys",
> > + .data = &mt8195_mmsys_match_data,
> > },
> > {
> > .compatible = "mediatek,mt8365-mmsys",
> > - .data = &mt8365_mmsys_driver_data,
> > + .data = &mt8365_mmsys_match_data,
> > },
> > { }
> > };
> > diff --git a/drivers/soc/mediatek/mtk-mmsys.h
> > b/drivers/soc/mediatek/mtk-mmsys.h
> > index 77f37f8c715b..f01ba206481d 100644
> > --- a/drivers/soc/mediatek/mtk-mmsys.h
> > +++ b/drivers/soc/mediatek/mtk-mmsys.h
> > @@ -87,12 +87,18 @@ struct mtk_mmsys_routes {
> > };
> >
> > struct mtk_mmsys_driver_data {
> > + const resource_size_t io_start;
> > const char *clk_driver;
> > const struct mtk_mmsys_routes *routes;
> > const unsigned int num_routes;
> > const u16 sw0_rst_offset;
> > };
> >
> > +struct mtk_mmsys_match_data {
> > + unsigned short num_drv_data;
> > + const struct mtk_mmsys_driver_data *drv_data[];
> > +};
> > +
> > /*
> > * Routes in mt8173, mt2701, mt2712 are different. That means
> > * in the same register address, it controls different
> > input/output
> > diff --git a/include/linux/soc/mediatek/mtk-mmsys.h
> > b/include/linux/soc/mediatek/mtk-mmsys.h
> > index 4bba275e235a..cff5c9adbf46 100644
> > --- a/include/linux/soc/mediatek/mtk-mmsys.h
> > +++ b/include/linux/soc/mediatek/mtk-mmsys.h
> > @@ -17,13 +17,24 @@ enum mtk_ddp_comp_id {
> > DDP_COMPONENT_COLOR0,
> > DDP_COMPONENT_COLOR1,
> > DDP_COMPONENT_DITHER,
> > + DDP_COMPONENT_DITHER1,
> > + DDP_COMPONENT_DP_INTF0,
> > + DDP_COMPONENT_DP_INTF1,
> > DDP_COMPONENT_DPI0,
> > DDP_COMPONENT_DPI1,
> > + DDP_COMPONENT_DSC0,
> > + DDP_COMPONENT_DSC1,
> > DDP_COMPONENT_DSI0,
> > DDP_COMPONENT_DSI1,
> > DDP_COMPONENT_DSI2,
> > DDP_COMPONENT_DSI3,
> > DDP_COMPONENT_GAMMA,
> > + DDP_COMPONENT_MERGE0,
> > + DDP_COMPONENT_MERGE1,
> > + DDP_COMPONENT_MERGE2,
> > + DDP_COMPONENT_MERGE3,
> > + DDP_COMPONENT_MERGE4,
> > + DDP_COMPONENT_MERGE5,
> > DDP_COMPONENT_OD0,
> > DDP_COMPONENT_OD1,
> > DDP_COMPONENT_OVL0,
c--
Jason-JH Lin <jason-jh.lin@mediatek.com>
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Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [PATCH v20 1/8] soc: mediatek: add mtk-mmsys support for mt8195 vdosys0
@ 2022-04-24 8:47 ` Jason-JH Lin
0 siblings, 0 replies; 110+ messages in thread
From: Jason-JH Lin @ 2022-04-24 8:47 UTC (permalink / raw)
To: Matthias Brugger, Chun-Kuang Hu, AngeloGioacchino Del Regno
Cc: devicetree, Singo Chang, linux-kernel, dri-devel,
Project_Global_Chrome_Upstream_Group, Nancy Lin, linux-mediatek,
linux-arm-kernel
Hi Matthias,
Thanks for the reviews.
On Fri, 2022-04-22 at 14:28 +0200, Matthias Brugger wrote:
>
> On 19/04/2022 11:41, jason-jh.lin wrote:
> > 1. Add mt8195 mmsys compatible for 2 vdosys.
> > 2. Add io_start into each driver data of mt8195 vdosys.
> > 3. Add get match data function to identify mmsys by io_start.
> > 4. Add mt8195 routing table settings of vdosys0.
> >
> > Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> > Reviewed-by: AngeloGioacchino Del Regno <
> > angelogioacchino.delregno@collabora.com>
>
> I'm not very happy with the approach of testing against the reg
> property to
> decide which version of the two mmsys devices we are probing. I think
> a better
> approach would be, if we would have added some mediatek specific ID
> to the
> device tree binding (or use a two compatibles?).
>
We uses two compatibles in previous version(before v16) of this series.
https://patchwork.kernel.org/project/linux-mediatek/patch/20220307032859.3275-5-jason-jh.lin@mediatek.com/
Since we received the comment of VPPSYS from Rob:
https://patchwork.kernel.org/project/linux-mediatek/patch/20220117055254.9777-15-roy-cw.yeh@mediatek.com/#24707362
we're trying to figure out the way to use the same compatible for
different mmsys.
> But as we are at v20 I think it wouldn't be fair to ask for such an
> instrusive
> change. So I'll take this patch now, but maybe we can discuss if we
> can't do
> better in a follow-up patch. Especially I don't think it's a good
> approach to
> check for the io_start in the DRM driver. Couldn't we pass the
> information about
> which of the two mmsys blocks we are calling from through the
> mediatek-drm
> platform device spefic data?
>
But we can't find a suitable property to identify the different mmsys
directly.
In mt8195, 2 pipelines are binding to different mmsys, such as vdosys0
and vdosys1. Each mmsys uses different clock drivers and different
power domain.
Since each mmsys has its own clock, I have tried to differentiate
vdosys0, vdosys1 by the clock names:
https://patchwork.kernel.org/project/linux-mediatek/patch/20220407030409.9664-4-jason-jh.lin@mediatek.com/
But it seems not robust enough.
Then we refer to this io_start solution, the idea from Angelo:
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c?h=next-20220408#n789
I'm not sure if there is another more suitable idea to fit in this
problem.
But I believe, if using different compatibles for each mmsys is
acceptable, then we can keep the original compatible method for
mediatek-drm and mmsys, and also make these works easier.
If you have any ideas to simplify it, please help us :-)
Thanks for your reviews again.
Regards,
Jason-JH.Lin
> I also had a look into the vdosys1 series to better understand why we
> need to do
> things as we do them. But honestly I wasn't able to really understand
> the
> implication of the patch that adds 'multi mmsys support' [1]. For
> this looks
> like a several patches that got squashed into one. But as I don't
> have to
> maintain that it is not my call to complain, the patch has the needed
> reviews.
>
> For this patch, now applied to v5.18-next/soc
>
> Thanks for all people implicated.
>
> Regards,
> Matthias
>
> [1]
>
https://urldefense.com/v3/__https://patchwork.kernel.org/project/linux-mediatek/patch/20220416020749.29010-19-nancy.lin@mediatek.com/__;!!CTRNKA9wMg0ARbw!zwfxXhyNG9gAnlrIB72IpyBFsLEm6pzLdRVgomyZ5tLat_Ddf3e3LenemQDeRVLWEf_p$
>
>
> > ---
> > Based on series [1]
> >
> > [1] MediaTek MT8195 display binding
> > -
> > https://urldefense.com/v3/__https://patchwork.ozlabs.org/project/devicetree-bindings/list/?series=295669__;!!CTRNKA9wMg0ARbw!zwfxXhyNG9gAnlrIB72IpyBFsLEm6pzLdRVgomyZ5tLat_Ddf3e3LenemQDeRXN1cxii$
> >
> > ---
> > drivers/soc/mediatek/mt8195-mmsys.h | 370
> > +++++++++++++++++++++++++
> > drivers/soc/mediatek/mtk-mmsys.c | 152 +++++++++-
> > drivers/soc/mediatek/mtk-mmsys.h | 6 +
> > include/linux/soc/mediatek/mtk-mmsys.h | 11 +
> > 4 files changed, 528 insertions(+), 11 deletions(-)
> > create mode 100644 drivers/soc/mediatek/mt8195-mmsys.h
> >
> > diff --git a/drivers/soc/mediatek/mt8195-mmsys.h
> > b/drivers/soc/mediatek/mt8195-mmsys.h
> > new file mode 100644
> > index 000000000000..13ab0ab64396
> > --- /dev/null
> > +++ b/drivers/soc/mediatek/mt8195-mmsys.h
> > @@ -0,0 +1,370 @@
> > +/* SPDX-License-Identifier: GPL-2.0-only */
> > +
> > +#ifndef __SOC_MEDIATEK_MT8195_MMSYS_H
> > +#define __SOC_MEDIATEK_MT8195_MMSYS_H
> > +
> > +#define MT8195_VDO0_OVL_MOUT_EN
> > 0xf14
> > +#define MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0
> > BIT(0)
> > +#define MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0
> > BIT(1)
> > +#define MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1 BIT(2)
> > +#define MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1
> > BIT(4)
> > +#define MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1
> > BIT(5)
> > +#define MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0 BIT(6)
> > +
> > +#define MT8195_VDO0_SEL_IN 0xf34
> > +#define MT8195_SEL_IN_VPP_MERGE_FROM_MASK GENMASK
> > (1, 0)
> > +#define MT8195_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT (0 <<
> > 0)
> > +#define MT8195_SEL_IN_VPP_MERGE_FROM_DISP_DITHER1 (1 <<
> > 0)
> > +#define MT8195_SEL_IN_VPP_MERGE_FROM_VDO1_VIRTUAL0 (2 <<
> > 0)
> > +#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK
> > GENMASK(4, 4)
> > +#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0
> > (0 << 4)
> > +#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_VPP_MERGE (1 <<
> > 4)
> > +#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_MASK
> > GENMASK(5, 5)
> > +#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_DISP_DITHER1
> > (0 << 5)
> > +#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_VPP_MERGE (1 <<
> > 5)
> > +#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK
> > GENMASK(8, 8)
> > +#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE (0 <<
> > 8)
> > +#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT
> > (1 << 8)
> > +#define MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK
> > GENMASK(9, 9)
> > +#define MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT
> > (0 << 9)
> > +#define MT8195_SEL_IN_DP_INTF0_FROM_MASK GENMASK
> > (13, 12)
> > +#define MT8195_SEL_IN_DP_INTF0_FROM_DSC_WRAP1_OUT (0 <<
> > 0)
> > +#define MT8195_SEL_IN_DP_INTF0_FROM_VPP_MERGE
> > (1 << 12)
> > +#define MT8195_SEL_IN_DP_INTF0_FROM_VDO1_VIRTUAL0 (2 <<
> > 12)
> > +#define MT8195_SEL_IN_DSI0_FROM_MASK
> > GENMASK(16, 16)
> > +#define MT8195_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT
> > (0 << 16)
> > +#define MT8195_SEL_IN_DSI0_FROM_DISP_DITHER0
> > (1 << 16)
> > +#define MT8195_SEL_IN_DSI1_FROM_MASK
> > GENMASK(17, 17)
> > +#define MT8195_SEL_IN_DSI1_FROM_DSC_WRAP1_OUT
> > (0 << 17)
> > +#define MT8195_SEL_IN_DSI1_FROM_VPP_MERGE (1 <<
> > 17)
> > +#define MT8195_SEL_IN_DISP_WDMA1_FROM_MASK GENMASK
> > (20, 20)
> > +#define MT8195_SEL_IN_DISP_WDMA1_FROM_DISP_OVL1
> > (0 << 20)
> > +#define MT8195_SEL_IN_DISP_WDMA1_FROM_VPP_MERGE
> > (1 << 20)
> > +#define MT8195_SEL_IN_DSC_WRAP1_FROM_MASK GENMASK
> > (21, 21)
> > +#define MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
> > (0 << 21)
> > +#define MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1
> > (1 << 21)
> > +#define MT8195_SEL_IN_DISP_WDMA0_FROM_MASK GENMASK
> > (22, 22)
> > +#define MT8195_SEL_IN_DISP_WDMA0_FROM_DISP_OVL0
> > (0 << 22)
> > +
> > +#define MT8195_VDO0_SEL_OUT
> > 0xf38
> > +#define MT8195_SOUT_DISP_DITHER0_TO_MASK BIT(0)
> > +#define MT8195_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN (0 <<
> > 0)
> > +#define MT8195_SOUT_DISP_DITHER0_TO_DSI0 (1 <<
> > 0)
> > +#define MT8195_SOUT_DISP_DITHER1_TO_MASK GENMASK
> > (2, 1)
> > +#define MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_IN (0 <<
> > 1)
> > +#define MT8195_SOUT_DISP_DITHER1_TO_VPP_MERGE
> > (1 << 1)
> > +#define MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT (2 <<
> > 1)
> > +#define MT8195_SOUT_VDO1_VIRTUAL0_TO_MASK GENMASK
> > (4, 4)
> > +#define MT8195_SOUT_VDO1_VIRTUAL0_TO_VPP_MERGE
> > (0 << 4)
> > +#define MT8195_SOUT_VDO1_VIRTUAL0_TO_DP_INTF0
> > (1 << 4)
> > +#define MT8195_SOUT_VPP_MERGE_TO_MASK
> > GENMASK(10, 8)
> > +#define MT8195_SOUT_VPP_MERGE_TO_DSI1
> > (0 << 8)
> > +#define MT8195_SOUT_VPP_MERGE_TO_DP_INTF0 (1 <<
> > 8)
> > +#define MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0
> > (2 << 8)
> > +#define MT8195_SOUT_VPP_MERGE_TO_DISP_WDMA1
> > (3 << 8)
> > +#define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP0_IN
> > (4 << 8)
> > +#define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN_MASK GENMASK
> > (11, 11)
> > +#define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN
> > (0 << 11)
> > +#define MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK GENMASK
> > (13, 12)
> > +#define MT8195_SOUT_DSC_WRAP0_OUT_TO_DSI0 (0 <<
> > 12)
> > +#define MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0 (1 <<
> > 12)
> > +#define MT8195_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE
> > (2 << 12)
> > +#define MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK GENMASK
> > (17, 16)
> > +#define MT8195_SOUT_DSC_WRAP1_OUT_TO_DSI1 (0 <<
> > 16)
> > +#define MT8195_SOUT_DSC_WRAP1_OUT_TO_DP_INTF0
> > (1 << 16)
> > +#define MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0 (2 <<
> > 16)
> > +#define MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE
> > (3 << 16)
> > +
> > +static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[]
> > = {
> > + {
> > + DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
> > + MT8195_VDO0_OVL_MOUT_EN,
> > MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0,
> > + MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0
> > + }, {
> > + DDP_COMPONENT_OVL0, DDP_COMPONENT_WDMA0,
> > + MT8195_VDO0_OVL_MOUT_EN,
> > MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0,
> > + MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0
> > + }, {
> > + DDP_COMPONENT_OVL0, DDP_COMPONENT_OVL1,
> > + MT8195_VDO0_OVL_MOUT_EN,
> > MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1,
> > + MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1
> > + }, {
> > + DDP_COMPONENT_OVL1, DDP_COMPONENT_RDMA1,
> > + MT8195_VDO0_OVL_MOUT_EN,
> > MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1,
> > + MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1
> > + }, {
> > + DDP_COMPONENT_OVL1, DDP_COMPONENT_WDMA1,
> > + MT8195_VDO0_OVL_MOUT_EN,
> > MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1,
> > + MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1
> > + }, {
> > + DDP_COMPONENT_OVL1, DDP_COMPONENT_OVL0,
> > + MT8195_VDO0_OVL_MOUT_EN,
> > MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0,
> > + MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0
> > + }, {
> > + DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0,
> > + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK,
> > + MT8195_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT
> > + }, {
> > + DDP_COMPONENT_DITHER1, DDP_COMPONENT_MERGE0,
> > + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK,
> > + MT8195_SEL_IN_VPP_MERGE_FROM_DISP_DITHER1
> > + }, {
> > + DDP_COMPONENT_MERGE5, DDP_COMPONENT_MERGE0,
> > + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK,
> > + MT8195_SEL_IN_VPP_MERGE_FROM_VDO1_VIRTUAL0
> > + }, {
> > + DDP_COMPONENT_DITHER, DDP_COMPONENT_DSC0,
> > + MT8195_VDO0_SEL_IN,
> > MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK,
> > + MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0
> > + }, {
> > + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC0,
> > + MT8195_VDO0_SEL_IN,
> > MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK,
> > + MT8195_SEL_IN_DSC_WRAP0_IN_FROM_VPP_MERGE
> > + }, {
> > + DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSC1,
> > + MT8195_VDO0_SEL_IN,
> > MT8195_SEL_IN_DSC_WRAP1_IN_FROM_MASK,
> > + MT8195_SEL_IN_DSC_WRAP1_IN_FROM_DISP_DITHER1
> > + }, {
> > + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC1,
> > + MT8195_VDO0_SEL_IN,
> > MT8195_SEL_IN_DSC_WRAP1_IN_FROM_MASK,
> > + MT8195_SEL_IN_DSC_WRAP1_IN_FROM_VPP_MERGE
> > + }, {
> > + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF1,
> > + MT8195_VDO0_SEL_IN,
> > MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
> > + MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE
> > + }, {
> > + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI0,
> > + MT8195_VDO0_SEL_IN,
> > MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
> > + MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE
> > + }, {
> > + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI1,
> > + MT8195_VDO0_SEL_IN,
> > MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
> > + MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE
> > + }, {
> > + DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF1,
> > + MT8195_VDO0_SEL_IN,
> > MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
> > + MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT
> > + }, {
> > + DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI0,
> > + MT8195_VDO0_SEL_IN,
> > MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
> > + MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT
> > + }, {
> > + DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI1,
> > + MT8195_VDO0_SEL_IN,
> > MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
> > + MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT
> > + }, {
> > + DDP_COMPONENT_DSC0, DDP_COMPONENT_DP_INTF1,
> > + MT8195_VDO0_SEL_IN,
> > MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK,
> > + MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT
> > + }, {
> > + DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI0,
> > + MT8195_VDO0_SEL_IN,
> > MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK,
> > + MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT
> > + }, {
> > + DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI1,
> > + MT8195_VDO0_SEL_IN,
> > MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK,
> > + MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT
> > + }, {
> > + DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF0,
> > + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_MASK,
> > + MT8195_SEL_IN_DP_INTF0_FROM_DSC_WRAP1_OUT
> > + }, {
> > + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF0,
> > + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_MASK,
> > + MT8195_SEL_IN_DP_INTF0_FROM_VPP_MERGE
> > + }, {
> > + DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF0,
> > + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_MASK,
> > + MT8195_SEL_IN_DP_INTF0_FROM_VDO1_VIRTUAL0
> > + }, {
> > + DDP_COMPONENT_DSC0, DDP_COMPONENT_DSI0,
> > + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI0_FROM_MASK,
> > + MT8195_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT
> > + }, {
> > + DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
> > + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI0_FROM_MASK,
> > + MT8195_SEL_IN_DSI0_FROM_DISP_DITHER0
> > + }, {
> > + DDP_COMPONENT_DSC1, DDP_COMPONENT_DSI1,
> > + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI1_FROM_MASK,
> > + MT8195_SEL_IN_DSI1_FROM_DSC_WRAP1_OUT
> > + }, {
> > + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSI1,
> > + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI1_FROM_MASK,
> > + MT8195_SEL_IN_DSI1_FROM_VPP_MERGE
> > + }, {
> > + DDP_COMPONENT_OVL1, DDP_COMPONENT_WDMA1,
> > + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA1_FROM_MASK,
> > + MT8195_SEL_IN_DISP_WDMA1_FROM_DISP_OVL1
> > + }, {
> > + DDP_COMPONENT_MERGE0, DDP_COMPONENT_WDMA1,
> > + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA1_FROM_MASK,
> > + MT8195_SEL_IN_DISP_WDMA1_FROM_VPP_MERGE
> > + }, {
> > + DDP_COMPONENT_DSC1, DDP_COMPONENT_DSI1,
> > + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
> > + MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
> > + }, {
> > + DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF0,
> > + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
> > + MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
> > + }, {
> > + DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF1,
> > + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
> > + MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
> > + }, {
> > + DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI0,
> > + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
> > + MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
> > + }, {
> > + DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI1,
> > + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
> > + MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
> > + }, {
> > + DDP_COMPONENT_DSC1, DDP_COMPONENT_MERGE0,
> > + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
> > + MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
> > + }, {
> > + DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSI1,
> > + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
> > + MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1
> > + }, {
> > + DDP_COMPONENT_DITHER1, DDP_COMPONENT_DP_INTF0,
> > + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
> > + MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1
> > + }, {
> > + DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI0,
> > + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
> > + MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1
> > + }, {
> > + DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI1,
> > + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
> > + MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1
> > + }, {
> > + DDP_COMPONENT_OVL0, DDP_COMPONENT_WDMA0,
> > + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA0_FROM_MASK,
> > + MT8195_SEL_IN_DISP_WDMA0_FROM_DISP_OVL0
> > + }, {
> > + DDP_COMPONENT_DITHER, DDP_COMPONENT_DSC0,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER0_TO_MASK,
> > + MT8195_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN
> > + }, {
> > + DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER0_TO_MASK,
> > + MT8195_SOUT_DISP_DITHER0_TO_DSI0
> > + }, {
> > + DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSC1,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
> > + MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_IN
> > + }, {
> > + DDP_COMPONENT_DITHER1, DDP_COMPONENT_MERGE0,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
> > + MT8195_SOUT_DISP_DITHER1_TO_VPP_MERGE
> > + }, {
> > + DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSI1,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
> > + MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT
> > + }, {
> > + DDP_COMPONENT_DITHER1, DDP_COMPONENT_DP_INTF0,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
> > + MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT
> > + }, {
> > + DDP_COMPONENT_DITHER1, DDP_COMPONENT_DP_INTF1,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
> > + MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT
> > + }, {
> > + DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI0,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
> > + MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT
> > + }, {
> > + DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI1,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
> > + MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT
> > + }, {
> > + DDP_COMPONENT_MERGE5, DDP_COMPONENT_MERGE0,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_VDO1_VIRTUAL0_TO_MASK,
> > + MT8195_SOUT_VDO1_VIRTUAL0_TO_VPP_MERGE
> > + }, {
> > + DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF0,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_VDO1_VIRTUAL0_TO_MASK,
> > + MT8195_SOUT_VDO1_VIRTUAL0_TO_DP_INTF0
> > + }, {
> > + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSI1,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
> > + MT8195_SOUT_VPP_MERGE_TO_DSI1
> > + }, {
> > + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF0,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
> > + MT8195_SOUT_VPP_MERGE_TO_DP_INTF0
> > + }, {
> > + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF1,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
> > + MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0
> > + }, {
> > + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI0,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
> > + MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0
> > + }, {
> > + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI1,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
> > + MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0
> > + }, {
> > + DDP_COMPONENT_MERGE0, DDP_COMPONENT_WDMA1,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
> > + MT8195_SOUT_VPP_MERGE_TO_DISP_WDMA1
> > + }, {
> > + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC0,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
> > + MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP0_IN
> > + }, {
> > + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC1,
> > + MT8195_VDO0_SEL_OUT,
> > MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN_MASK,
> > + MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN
> > + }, {
> > + DDP_COMPONENT_DSC0, DDP_COMPONENT_DSI0,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
> > + MT8195_SOUT_DSC_WRAP0_OUT_TO_DSI0
> > + }, {
> > + DDP_COMPONENT_DSC0, DDP_COMPONENT_DP_INTF1,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
> > + MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0
> > + }, {
> > + DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI0,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
> > + MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0
> > + }, {
> > + DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI1,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
> > + MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0
> > + }, {
> > + DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
> > + MT8195_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE
> > + }, {
> > + DDP_COMPONENT_DSC1, DDP_COMPONENT_DSI1,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
> > + MT8195_SOUT_DSC_WRAP1_OUT_TO_DSI1
> > + }, {
> > + DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF0,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
> > + MT8195_SOUT_DSC_WRAP1_OUT_TO_DP_INTF0
> > + }, {
> > + DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF1,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
> > + MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0
> > + }, {
> > + DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI0,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
> > + MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0
> > + }, {
> > + DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI1,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
> > + MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0
> > + }, {
> > + DDP_COMPONENT_DSC1, DDP_COMPONENT_MERGE0,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
> > + MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE
> > + }
> > +};
> > +
> > +#endif /* __SOC_MEDIATEK_MT8195_MMSYS_H */
> > diff --git a/drivers/soc/mediatek/mtk-mmsys.c
> > b/drivers/soc/mediatek/mtk-mmsys.c
> > index 4fc4c2c9ea20..548efed8dc1c 100644
> > --- a/drivers/soc/mediatek/mtk-mmsys.c
> > +++ b/drivers/soc/mediatek/mtk-mmsys.c
> > @@ -17,6 +17,7 @@
> > #include "mt8183-mmsys.h"
> > #include "mt8186-mmsys.h"
> > #include "mt8192-mmsys.h"
> > +#include "mt8195-mmsys.h"
> > #include "mt8365-mmsys.h"
> >
> > static const struct mtk_mmsys_driver_data
> > mt2701_mmsys_driver_data = {
> > @@ -25,26 +26,61 @@ static const struct mtk_mmsys_driver_data
> > mt2701_mmsys_driver_data = {
> > .num_routes = ARRAY_SIZE(mmsys_default_routing_table),
> > };
> >
> > +static const struct mtk_mmsys_match_data mt2701_mmsys_match_data =
> > {
> > + .num_drv_data = 1,
> > + .drv_data = {
> > + &mt2701_mmsys_driver_data,
> > + },
> > +};
> > +
> > static const struct mtk_mmsys_driver_data
> > mt2712_mmsys_driver_data = {
> > .clk_driver = "clk-mt2712-mm",
> > .routes = mmsys_default_routing_table,
> > .num_routes = ARRAY_SIZE(mmsys_default_routing_table),
> > };
> >
> > +static const struct mtk_mmsys_match_data mt2712_mmsys_match_data =
> > {
> > + .num_drv_data = 1,
> > + .drv_data = {
> > + &mt2712_mmsys_driver_data,
> > + },
> > +};
> > +
> > static const struct mtk_mmsys_driver_data
> > mt6779_mmsys_driver_data = {
> > .clk_driver = "clk-mt6779-mm",
> > };
> >
> > +static const struct mtk_mmsys_match_data mt6779_mmsys_match_data =
> > {
> > + .num_drv_data = 1,
> > + .drv_data = {
> > + &mt6779_mmsys_driver_data,
> > + },
> > +};
> > +
> > static const struct mtk_mmsys_driver_data
> > mt6797_mmsys_driver_data = {
> > .clk_driver = "clk-mt6797-mm",
> > };
> >
> > +static const struct mtk_mmsys_match_data mt6797_mmsys_match_data =
> > {
> > + .num_drv_data = 1,
> > + .drv_data = {
> > + &mt6797_mmsys_driver_data,
> > + },
> > +};
> > +
> > static const struct mtk_mmsys_driver_data
> > mt8167_mmsys_driver_data = {
> > .clk_driver = "clk-mt8167-mm",
> > .routes = mt8167_mmsys_routing_table,
> > .num_routes = ARRAY_SIZE(mt8167_mmsys_routing_table),
> > };
> >
> > +static const struct mtk_mmsys_match_data mt8167_mmsys_match_data =
> > {
> > + .num_drv_data = 1,
> > + .drv_data = {
> > + &mt8167_mmsys_driver_data,
> > + },
> > +};
> > +
> > static const struct mtk_mmsys_driver_data
> > mt8173_mmsys_driver_data = {
> > .clk_driver = "clk-mt8173-mm",
> > .routes = mmsys_default_routing_table,
> > @@ -52,6 +88,13 @@ static const struct mtk_mmsys_driver_data
> > mt8173_mmsys_driver_data = {
> > .sw0_rst_offset = MT8183_MMSYS_SW0_RST_B,
> > };
> >
> > +static const struct mtk_mmsys_match_data mt8173_mmsys_match_data =
> > {
> > + .num_drv_data = 1,
> > + .drv_data = {
> > + &mt8173_mmsys_driver_data,
> > + },
> > +};
> > +
> > static const struct mtk_mmsys_driver_data
> > mt8183_mmsys_driver_data = {
> > .clk_driver = "clk-mt8183-mm",
> > .routes = mmsys_mt8183_routing_table,
> > @@ -59,6 +102,13 @@ static const struct mtk_mmsys_driver_data
> > mt8183_mmsys_driver_data = {
> > .sw0_rst_offset = MT8183_MMSYS_SW0_RST_B,
> > };
> >
> > +static const struct mtk_mmsys_match_data mt8183_mmsys_match_data =
> > {
> > + .num_drv_data = 1,
> > + .drv_data = {
> > + &mt8183_mmsys_driver_data,
> > + },
> > +};
> > +
> > static const struct mtk_mmsys_driver_data
> > mt8186_mmsys_driver_data = {
> > .clk_driver = "clk-mt8186-mm",
> > .routes = mmsys_mt8186_routing_table,
> > @@ -66,25 +116,79 @@ static const struct mtk_mmsys_driver_data
> > mt8186_mmsys_driver_data = {
> > .sw0_rst_offset = MT8186_MMSYS_SW0_RST_B,
> > };
> >
> > +static const struct mtk_mmsys_match_data mt8186_mmsys_match_data =
> > {
> > + .num_drv_data = 1,
> > + .drv_data = {
> > + &mt8186_mmsys_driver_data,
> > + },
> > +};
> > +
> > static const struct mtk_mmsys_driver_data
> > mt8192_mmsys_driver_data = {
> > .clk_driver = "clk-mt8192-mm",
> > .routes = mmsys_mt8192_routing_table,
> > .num_routes = ARRAY_SIZE(mmsys_mt8192_routing_table),
> > };
> >
> > +static const struct mtk_mmsys_match_data mt8192_mmsys_match_data =
> > {
> > + .num_drv_data = 1,
> > + .drv_data = {
> > + &mt8192_mmsys_driver_data,
> > + },
> > +};
> > +
> > +static const struct mtk_mmsys_driver_data
> > mt8195_vdosys0_driver_data = {
> > + .io_start = 0x1c01a000,
> > + .clk_driver = "clk-mt8195-vdo0",
> > + .routes = mmsys_mt8195_routing_table,
> > + .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
> > +};
> > +
> > +static const struct mtk_mmsys_driver_data
> > mt8195_vdosys1_driver_data = {
> > + .io_start = 0x1c100000,
> > + .clk_driver = "clk-mt8195-vdo1",
> > +};
> > +
> > +static const struct mtk_mmsys_match_data mt8195_mmsys_match_data =
> > {
> > + .num_drv_data = 2,
> > + .drv_data = {
> > + &mt8195_vdosys0_driver_data,
> > + &mt8195_vdosys1_driver_data,
> > + },
> > +};
> > +
> > static const struct mtk_mmsys_driver_data
> > mt8365_mmsys_driver_data = {
> > .clk_driver = "clk-mt8365-mm",
> > .routes = mt8365_mmsys_routing_table,
> > .num_routes = ARRAY_SIZE(mt8365_mmsys_routing_table),
> > };
> >
> > +static const struct mtk_mmsys_match_data mt8365_mmsys_match_data =
> > {
> > + .num_drv_data = 1,
> > + .drv_data = {
> > + &mt8365_mmsys_driver_data,
> > + },
> > +};
> > +
> > struct mtk_mmsys {
> > void __iomem *regs;
> > const struct mtk_mmsys_driver_data *data;
> > spinlock_t lock; /* protects mmsys_sw_rst_b reg */
> > struct reset_controller_dev rcdev;
> > + phys_addr_t io_start;
> > };
> >
> > +static int mtk_mmsys_find_match_drvdata(struct mtk_mmsys *mmsys,
> > + const struct
> > mtk_mmsys_match_data *match)
> > +{
> > + int i;
> > +
> > + for (i = 0; i < match->num_drv_data; i++)
> > + if (mmsys->io_start == match->drv_data[i]->io_start)
> > + return i;
> > +
> > + return -EINVAL;
> > +}
> > +
> > void mtk_mmsys_ddp_connect(struct device *dev,
> > enum mtk_ddp_comp_id cur,
> > enum mtk_ddp_comp_id next)
> > @@ -179,7 +283,9 @@ static int mtk_mmsys_probe(struct
> > platform_device *pdev)
> > struct device *dev = &pdev->dev;
> > struct platform_device *clks;
> > struct platform_device *drm;
> > + const struct mtk_mmsys_match_data *match_data;
> > struct mtk_mmsys *mmsys;
> > + struct resource *res;
> > int ret;
> >
> > mmsys = devm_kzalloc(dev, sizeof(*mmsys), GFP_KERNEL);
> > @@ -205,7 +311,27 @@ static int mtk_mmsys_probe(struct
> > platform_device *pdev)
> > return ret;
> > }
> >
> > - mmsys->data = of_device_get_match_data(&pdev->dev);
> > + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > + if (!res) {
> > + dev_err(dev, "Couldn't get mmsys resource\n");
> > + return -EINVAL;
> > + }
> > + mmsys->io_start = res->start;
> > +
> > + match_data = of_device_get_match_data(dev);
> > + if (match_data->num_drv_data > 1) {
> > + /* This SoC has multiple mmsys channels */
> > + ret = mtk_mmsys_find_match_drvdata(mmsys, match_data);
> > + if (ret < 0) {
> > + dev_err(dev, "Couldn't get match driver
> > data\n");
> > + return ret;
> > + }
> > + mmsys->data = match_data->drv_data[ret];
> > + } else {
> > + dev_dbg(dev, "Using single mmsys channel\n");
> > + mmsys->data = match_data->drv_data[0];
> > + }
> > +
> > platform_set_drvdata(pdev, mmsys);
> >
> > clks = platform_device_register_data(&pdev->dev, mmsys->data-
> > >clk_driver,
> > @@ -226,43 +352,47 @@ static int mtk_mmsys_probe(struct
> > platform_device *pdev)
> > static const struct of_device_id of_match_mtk_mmsys[] = {
> > {
> > .compatible = "mediatek,mt2701-mmsys",
> > - .data = &mt2701_mmsys_driver_data,
> > + .data = &mt2701_mmsys_match_data,
> > },
> > {
> > .compatible = "mediatek,mt2712-mmsys",
> > - .data = &mt2712_mmsys_driver_data,
> > + .data = &mt2712_mmsys_match_data,
> > },
> > {
> > .compatible = "mediatek,mt6779-mmsys",
> > - .data = &mt6779_mmsys_driver_data,
> > + .data = &mt6779_mmsys_match_data,
> > },
> > {
> > .compatible = "mediatek,mt6797-mmsys",
> > - .data = &mt6797_mmsys_driver_data,
> > + .data = &mt6797_mmsys_match_data,
> > },
> > {
> > .compatible = "mediatek,mt8167-mmsys",
> > - .data = &mt8167_mmsys_driver_data,
> > + .data = &mt8167_mmsys_match_data,
> > },
> > {
> > .compatible = "mediatek,mt8173-mmsys",
> > - .data = &mt8173_mmsys_driver_data,
> > + .data = &mt8173_mmsys_match_data,
> > },
> > {
> > .compatible = "mediatek,mt8183-mmsys",
> > - .data = &mt8183_mmsys_driver_data,
> > + .data = &mt8183_mmsys_match_data,
> > },
> > {
> > .compatible = "mediatek,mt8186-mmsys",
> > - .data = &mt8186_mmsys_driver_data,
> > + .data = &mt8186_mmsys_match_data,
> > },
> > {
> > .compatible = "mediatek,mt8192-mmsys",
> > - .data = &mt8192_mmsys_driver_data,
> > + .data = &mt8192_mmsys_match_data,
> > + },
> > + {
> > + .compatible = "mediatek,mt8195-mmsys",
> > + .data = &mt8195_mmsys_match_data,
> > },
> > {
> > .compatible = "mediatek,mt8365-mmsys",
> > - .data = &mt8365_mmsys_driver_data,
> > + .data = &mt8365_mmsys_match_data,
> > },
> > { }
> > };
> > diff --git a/drivers/soc/mediatek/mtk-mmsys.h
> > b/drivers/soc/mediatek/mtk-mmsys.h
> > index 77f37f8c715b..f01ba206481d 100644
> > --- a/drivers/soc/mediatek/mtk-mmsys.h
> > +++ b/drivers/soc/mediatek/mtk-mmsys.h
> > @@ -87,12 +87,18 @@ struct mtk_mmsys_routes {
> > };
> >
> > struct mtk_mmsys_driver_data {
> > + const resource_size_t io_start;
> > const char *clk_driver;
> > const struct mtk_mmsys_routes *routes;
> > const unsigned int num_routes;
> > const u16 sw0_rst_offset;
> > };
> >
> > +struct mtk_mmsys_match_data {
> > + unsigned short num_drv_data;
> > + const struct mtk_mmsys_driver_data *drv_data[];
> > +};
> > +
> > /*
> > * Routes in mt8173, mt2701, mt2712 are different. That means
> > * in the same register address, it controls different
> > input/output
> > diff --git a/include/linux/soc/mediatek/mtk-mmsys.h
> > b/include/linux/soc/mediatek/mtk-mmsys.h
> > index 4bba275e235a..cff5c9adbf46 100644
> > --- a/include/linux/soc/mediatek/mtk-mmsys.h
> > +++ b/include/linux/soc/mediatek/mtk-mmsys.h
> > @@ -17,13 +17,24 @@ enum mtk_ddp_comp_id {
> > DDP_COMPONENT_COLOR0,
> > DDP_COMPONENT_COLOR1,
> > DDP_COMPONENT_DITHER,
> > + DDP_COMPONENT_DITHER1,
> > + DDP_COMPONENT_DP_INTF0,
> > + DDP_COMPONENT_DP_INTF1,
> > DDP_COMPONENT_DPI0,
> > DDP_COMPONENT_DPI1,
> > + DDP_COMPONENT_DSC0,
> > + DDP_COMPONENT_DSC1,
> > DDP_COMPONENT_DSI0,
> > DDP_COMPONENT_DSI1,
> > DDP_COMPONENT_DSI2,
> > DDP_COMPONENT_DSI3,
> > DDP_COMPONENT_GAMMA,
> > + DDP_COMPONENT_MERGE0,
> > + DDP_COMPONENT_MERGE1,
> > + DDP_COMPONENT_MERGE2,
> > + DDP_COMPONENT_MERGE3,
> > + DDP_COMPONENT_MERGE4,
> > + DDP_COMPONENT_MERGE5,
> > DDP_COMPONENT_OD0,
> > DDP_COMPONENT_OD1,
> > DDP_COMPONENT_OVL0,
c--
Jason-JH Lin <jason-jh.lin@mediatek.com>
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [PATCH v20 1/8] soc: mediatek: add mtk-mmsys support for mt8195 vdosys0
@ 2022-04-24 8:47 ` Jason-JH Lin
0 siblings, 0 replies; 110+ messages in thread
From: Jason-JH Lin @ 2022-04-24 8:47 UTC (permalink / raw)
To: Matthias Brugger, Chun-Kuang Hu, AngeloGioacchino Del Regno
Cc: CK Hu, Nancy Lin, Singo Chang, devicetree, linux-kernel,
dri-devel, linux-mediatek, linux-arm-kernel,
Project_Global_Chrome_Upstream_Group
Hi Matthias,
Thanks for the reviews.
On Fri, 2022-04-22 at 14:28 +0200, Matthias Brugger wrote:
>
> On 19/04/2022 11:41, jason-jh.lin wrote:
> > 1. Add mt8195 mmsys compatible for 2 vdosys.
> > 2. Add io_start into each driver data of mt8195 vdosys.
> > 3. Add get match data function to identify mmsys by io_start.
> > 4. Add mt8195 routing table settings of vdosys0.
> >
> > Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> > Reviewed-by: AngeloGioacchino Del Regno <
> > angelogioacchino.delregno@collabora.com>
>
> I'm not very happy with the approach of testing against the reg
> property to
> decide which version of the two mmsys devices we are probing. I think
> a better
> approach would be, if we would have added some mediatek specific ID
> to the
> device tree binding (or use a two compatibles?).
>
We uses two compatibles in previous version(before v16) of this series.
https://patchwork.kernel.org/project/linux-mediatek/patch/20220307032859.3275-5-jason-jh.lin@mediatek.com/
Since we received the comment of VPPSYS from Rob:
https://patchwork.kernel.org/project/linux-mediatek/patch/20220117055254.9777-15-roy-cw.yeh@mediatek.com/#24707362
we're trying to figure out the way to use the same compatible for
different mmsys.
> But as we are at v20 I think it wouldn't be fair to ask for such an
> instrusive
> change. So I'll take this patch now, but maybe we can discuss if we
> can't do
> better in a follow-up patch. Especially I don't think it's a good
> approach to
> check for the io_start in the DRM driver. Couldn't we pass the
> information about
> which of the two mmsys blocks we are calling from through the
> mediatek-drm
> platform device spefic data?
>
But we can't find a suitable property to identify the different mmsys
directly.
In mt8195, 2 pipelines are binding to different mmsys, such as vdosys0
and vdosys1. Each mmsys uses different clock drivers and different
power domain.
Since each mmsys has its own clock, I have tried to differentiate
vdosys0, vdosys1 by the clock names:
https://patchwork.kernel.org/project/linux-mediatek/patch/20220407030409.9664-4-jason-jh.lin@mediatek.com/
But it seems not robust enough.
Then we refer to this io_start solution, the idea from Angelo:
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c?h=next-20220408#n789
I'm not sure if there is another more suitable idea to fit in this
problem.
But I believe, if using different compatibles for each mmsys is
acceptable, then we can keep the original compatible method for
mediatek-drm and mmsys, and also make these works easier.
If you have any ideas to simplify it, please help us :-)
Thanks for your reviews again.
Regards,
Jason-JH.Lin
> I also had a look into the vdosys1 series to better understand why we
> need to do
> things as we do them. But honestly I wasn't able to really understand
> the
> implication of the patch that adds 'multi mmsys support' [1]. For
> this looks
> like a several patches that got squashed into one. But as I don't
> have to
> maintain that it is not my call to complain, the patch has the needed
> reviews.
>
> For this patch, now applied to v5.18-next/soc
>
> Thanks for all people implicated.
>
> Regards,
> Matthias
>
> [1]
>
https://urldefense.com/v3/__https://patchwork.kernel.org/project/linux-mediatek/patch/20220416020749.29010-19-nancy.lin@mediatek.com/__;!!CTRNKA9wMg0ARbw!zwfxXhyNG9gAnlrIB72IpyBFsLEm6pzLdRVgomyZ5tLat_Ddf3e3LenemQDeRVLWEf_p$
>
>
> > ---
> > Based on series [1]
> >
> > [1] MediaTek MT8195 display binding
> > -
> > https://urldefense.com/v3/__https://patchwork.ozlabs.org/project/devicetree-bindings/list/?series=295669__;!!CTRNKA9wMg0ARbw!zwfxXhyNG9gAnlrIB72IpyBFsLEm6pzLdRVgomyZ5tLat_Ddf3e3LenemQDeRXN1cxii$
> >
> > ---
> > drivers/soc/mediatek/mt8195-mmsys.h | 370
> > +++++++++++++++++++++++++
> > drivers/soc/mediatek/mtk-mmsys.c | 152 +++++++++-
> > drivers/soc/mediatek/mtk-mmsys.h | 6 +
> > include/linux/soc/mediatek/mtk-mmsys.h | 11 +
> > 4 files changed, 528 insertions(+), 11 deletions(-)
> > create mode 100644 drivers/soc/mediatek/mt8195-mmsys.h
> >
> > diff --git a/drivers/soc/mediatek/mt8195-mmsys.h
> > b/drivers/soc/mediatek/mt8195-mmsys.h
> > new file mode 100644
> > index 000000000000..13ab0ab64396
> > --- /dev/null
> > +++ b/drivers/soc/mediatek/mt8195-mmsys.h
> > @@ -0,0 +1,370 @@
> > +/* SPDX-License-Identifier: GPL-2.0-only */
> > +
> > +#ifndef __SOC_MEDIATEK_MT8195_MMSYS_H
> > +#define __SOC_MEDIATEK_MT8195_MMSYS_H
> > +
> > +#define MT8195_VDO0_OVL_MOUT_EN
> > 0xf14
> > +#define MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0
> > BIT(0)
> > +#define MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0
> > BIT(1)
> > +#define MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1 BIT(2)
> > +#define MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1
> > BIT(4)
> > +#define MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1
> > BIT(5)
> > +#define MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0 BIT(6)
> > +
> > +#define MT8195_VDO0_SEL_IN 0xf34
> > +#define MT8195_SEL_IN_VPP_MERGE_FROM_MASK GENMASK
> > (1, 0)
> > +#define MT8195_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT (0 <<
> > 0)
> > +#define MT8195_SEL_IN_VPP_MERGE_FROM_DISP_DITHER1 (1 <<
> > 0)
> > +#define MT8195_SEL_IN_VPP_MERGE_FROM_VDO1_VIRTUAL0 (2 <<
> > 0)
> > +#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK
> > GENMASK(4, 4)
> > +#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0
> > (0 << 4)
> > +#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_VPP_MERGE (1 <<
> > 4)
> > +#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_MASK
> > GENMASK(5, 5)
> > +#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_DISP_DITHER1
> > (0 << 5)
> > +#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_VPP_MERGE (1 <<
> > 5)
> > +#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK
> > GENMASK(8, 8)
> > +#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE (0 <<
> > 8)
> > +#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT
> > (1 << 8)
> > +#define MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK
> > GENMASK(9, 9)
> > +#define MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT
> > (0 << 9)
> > +#define MT8195_SEL_IN_DP_INTF0_FROM_MASK GENMASK
> > (13, 12)
> > +#define MT8195_SEL_IN_DP_INTF0_FROM_DSC_WRAP1_OUT (0 <<
> > 0)
> > +#define MT8195_SEL_IN_DP_INTF0_FROM_VPP_MERGE
> > (1 << 12)
> > +#define MT8195_SEL_IN_DP_INTF0_FROM_VDO1_VIRTUAL0 (2 <<
> > 12)
> > +#define MT8195_SEL_IN_DSI0_FROM_MASK
> > GENMASK(16, 16)
> > +#define MT8195_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT
> > (0 << 16)
> > +#define MT8195_SEL_IN_DSI0_FROM_DISP_DITHER0
> > (1 << 16)
> > +#define MT8195_SEL_IN_DSI1_FROM_MASK
> > GENMASK(17, 17)
> > +#define MT8195_SEL_IN_DSI1_FROM_DSC_WRAP1_OUT
> > (0 << 17)
> > +#define MT8195_SEL_IN_DSI1_FROM_VPP_MERGE (1 <<
> > 17)
> > +#define MT8195_SEL_IN_DISP_WDMA1_FROM_MASK GENMASK
> > (20, 20)
> > +#define MT8195_SEL_IN_DISP_WDMA1_FROM_DISP_OVL1
> > (0 << 20)
> > +#define MT8195_SEL_IN_DISP_WDMA1_FROM_VPP_MERGE
> > (1 << 20)
> > +#define MT8195_SEL_IN_DSC_WRAP1_FROM_MASK GENMASK
> > (21, 21)
> > +#define MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
> > (0 << 21)
> > +#define MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1
> > (1 << 21)
> > +#define MT8195_SEL_IN_DISP_WDMA0_FROM_MASK GENMASK
> > (22, 22)
> > +#define MT8195_SEL_IN_DISP_WDMA0_FROM_DISP_OVL0
> > (0 << 22)
> > +
> > +#define MT8195_VDO0_SEL_OUT
> > 0xf38
> > +#define MT8195_SOUT_DISP_DITHER0_TO_MASK BIT(0)
> > +#define MT8195_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN (0 <<
> > 0)
> > +#define MT8195_SOUT_DISP_DITHER0_TO_DSI0 (1 <<
> > 0)
> > +#define MT8195_SOUT_DISP_DITHER1_TO_MASK GENMASK
> > (2, 1)
> > +#define MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_IN (0 <<
> > 1)
> > +#define MT8195_SOUT_DISP_DITHER1_TO_VPP_MERGE
> > (1 << 1)
> > +#define MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT (2 <<
> > 1)
> > +#define MT8195_SOUT_VDO1_VIRTUAL0_TO_MASK GENMASK
> > (4, 4)
> > +#define MT8195_SOUT_VDO1_VIRTUAL0_TO_VPP_MERGE
> > (0 << 4)
> > +#define MT8195_SOUT_VDO1_VIRTUAL0_TO_DP_INTF0
> > (1 << 4)
> > +#define MT8195_SOUT_VPP_MERGE_TO_MASK
> > GENMASK(10, 8)
> > +#define MT8195_SOUT_VPP_MERGE_TO_DSI1
> > (0 << 8)
> > +#define MT8195_SOUT_VPP_MERGE_TO_DP_INTF0 (1 <<
> > 8)
> > +#define MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0
> > (2 << 8)
> > +#define MT8195_SOUT_VPP_MERGE_TO_DISP_WDMA1
> > (3 << 8)
> > +#define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP0_IN
> > (4 << 8)
> > +#define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN_MASK GENMASK
> > (11, 11)
> > +#define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN
> > (0 << 11)
> > +#define MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK GENMASK
> > (13, 12)
> > +#define MT8195_SOUT_DSC_WRAP0_OUT_TO_DSI0 (0 <<
> > 12)
> > +#define MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0 (1 <<
> > 12)
> > +#define MT8195_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE
> > (2 << 12)
> > +#define MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK GENMASK
> > (17, 16)
> > +#define MT8195_SOUT_DSC_WRAP1_OUT_TO_DSI1 (0 <<
> > 16)
> > +#define MT8195_SOUT_DSC_WRAP1_OUT_TO_DP_INTF0
> > (1 << 16)
> > +#define MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0 (2 <<
> > 16)
> > +#define MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE
> > (3 << 16)
> > +
> > +static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[]
> > = {
> > + {
> > + DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
> > + MT8195_VDO0_OVL_MOUT_EN,
> > MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0,
> > + MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0
> > + }, {
> > + DDP_COMPONENT_OVL0, DDP_COMPONENT_WDMA0,
> > + MT8195_VDO0_OVL_MOUT_EN,
> > MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0,
> > + MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0
> > + }, {
> > + DDP_COMPONENT_OVL0, DDP_COMPONENT_OVL1,
> > + MT8195_VDO0_OVL_MOUT_EN,
> > MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1,
> > + MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1
> > + }, {
> > + DDP_COMPONENT_OVL1, DDP_COMPONENT_RDMA1,
> > + MT8195_VDO0_OVL_MOUT_EN,
> > MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1,
> > + MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1
> > + }, {
> > + DDP_COMPONENT_OVL1, DDP_COMPONENT_WDMA1,
> > + MT8195_VDO0_OVL_MOUT_EN,
> > MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1,
> > + MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1
> > + }, {
> > + DDP_COMPONENT_OVL1, DDP_COMPONENT_OVL0,
> > + MT8195_VDO0_OVL_MOUT_EN,
> > MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0,
> > + MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0
> > + }, {
> > + DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0,
> > + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK,
> > + MT8195_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT
> > + }, {
> > + DDP_COMPONENT_DITHER1, DDP_COMPONENT_MERGE0,
> > + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK,
> > + MT8195_SEL_IN_VPP_MERGE_FROM_DISP_DITHER1
> > + }, {
> > + DDP_COMPONENT_MERGE5, DDP_COMPONENT_MERGE0,
> > + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK,
> > + MT8195_SEL_IN_VPP_MERGE_FROM_VDO1_VIRTUAL0
> > + }, {
> > + DDP_COMPONENT_DITHER, DDP_COMPONENT_DSC0,
> > + MT8195_VDO0_SEL_IN,
> > MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK,
> > + MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0
> > + }, {
> > + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC0,
> > + MT8195_VDO0_SEL_IN,
> > MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK,
> > + MT8195_SEL_IN_DSC_WRAP0_IN_FROM_VPP_MERGE
> > + }, {
> > + DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSC1,
> > + MT8195_VDO0_SEL_IN,
> > MT8195_SEL_IN_DSC_WRAP1_IN_FROM_MASK,
> > + MT8195_SEL_IN_DSC_WRAP1_IN_FROM_DISP_DITHER1
> > + }, {
> > + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC1,
> > + MT8195_VDO0_SEL_IN,
> > MT8195_SEL_IN_DSC_WRAP1_IN_FROM_MASK,
> > + MT8195_SEL_IN_DSC_WRAP1_IN_FROM_VPP_MERGE
> > + }, {
> > + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF1,
> > + MT8195_VDO0_SEL_IN,
> > MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
> > + MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE
> > + }, {
> > + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI0,
> > + MT8195_VDO0_SEL_IN,
> > MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
> > + MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE
> > + }, {
> > + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI1,
> > + MT8195_VDO0_SEL_IN,
> > MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
> > + MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE
> > + }, {
> > + DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF1,
> > + MT8195_VDO0_SEL_IN,
> > MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
> > + MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT
> > + }, {
> > + DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI0,
> > + MT8195_VDO0_SEL_IN,
> > MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
> > + MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT
> > + }, {
> > + DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI1,
> > + MT8195_VDO0_SEL_IN,
> > MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
> > + MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT
> > + }, {
> > + DDP_COMPONENT_DSC0, DDP_COMPONENT_DP_INTF1,
> > + MT8195_VDO0_SEL_IN,
> > MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK,
> > + MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT
> > + }, {
> > + DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI0,
> > + MT8195_VDO0_SEL_IN,
> > MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK,
> > + MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT
> > + }, {
> > + DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI1,
> > + MT8195_VDO0_SEL_IN,
> > MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK,
> > + MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT
> > + }, {
> > + DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF0,
> > + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_MASK,
> > + MT8195_SEL_IN_DP_INTF0_FROM_DSC_WRAP1_OUT
> > + }, {
> > + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF0,
> > + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_MASK,
> > + MT8195_SEL_IN_DP_INTF0_FROM_VPP_MERGE
> > + }, {
> > + DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF0,
> > + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_MASK,
> > + MT8195_SEL_IN_DP_INTF0_FROM_VDO1_VIRTUAL0
> > + }, {
> > + DDP_COMPONENT_DSC0, DDP_COMPONENT_DSI0,
> > + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI0_FROM_MASK,
> > + MT8195_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT
> > + }, {
> > + DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
> > + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI0_FROM_MASK,
> > + MT8195_SEL_IN_DSI0_FROM_DISP_DITHER0
> > + }, {
> > + DDP_COMPONENT_DSC1, DDP_COMPONENT_DSI1,
> > + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI1_FROM_MASK,
> > + MT8195_SEL_IN_DSI1_FROM_DSC_WRAP1_OUT
> > + }, {
> > + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSI1,
> > + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI1_FROM_MASK,
> > + MT8195_SEL_IN_DSI1_FROM_VPP_MERGE
> > + }, {
> > + DDP_COMPONENT_OVL1, DDP_COMPONENT_WDMA1,
> > + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA1_FROM_MASK,
> > + MT8195_SEL_IN_DISP_WDMA1_FROM_DISP_OVL1
> > + }, {
> > + DDP_COMPONENT_MERGE0, DDP_COMPONENT_WDMA1,
> > + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA1_FROM_MASK,
> > + MT8195_SEL_IN_DISP_WDMA1_FROM_VPP_MERGE
> > + }, {
> > + DDP_COMPONENT_DSC1, DDP_COMPONENT_DSI1,
> > + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
> > + MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
> > + }, {
> > + DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF0,
> > + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
> > + MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
> > + }, {
> > + DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF1,
> > + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
> > + MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
> > + }, {
> > + DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI0,
> > + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
> > + MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
> > + }, {
> > + DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI1,
> > + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
> > + MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
> > + }, {
> > + DDP_COMPONENT_DSC1, DDP_COMPONENT_MERGE0,
> > + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
> > + MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
> > + }, {
> > + DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSI1,
> > + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
> > + MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1
> > + }, {
> > + DDP_COMPONENT_DITHER1, DDP_COMPONENT_DP_INTF0,
> > + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
> > + MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1
> > + }, {
> > + DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI0,
> > + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
> > + MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1
> > + }, {
> > + DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI1,
> > + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
> > + MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1
> > + }, {
> > + DDP_COMPONENT_OVL0, DDP_COMPONENT_WDMA0,
> > + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA0_FROM_MASK,
> > + MT8195_SEL_IN_DISP_WDMA0_FROM_DISP_OVL0
> > + }, {
> > + DDP_COMPONENT_DITHER, DDP_COMPONENT_DSC0,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER0_TO_MASK,
> > + MT8195_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN
> > + }, {
> > + DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER0_TO_MASK,
> > + MT8195_SOUT_DISP_DITHER0_TO_DSI0
> > + }, {
> > + DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSC1,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
> > + MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_IN
> > + }, {
> > + DDP_COMPONENT_DITHER1, DDP_COMPONENT_MERGE0,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
> > + MT8195_SOUT_DISP_DITHER1_TO_VPP_MERGE
> > + }, {
> > + DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSI1,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
> > + MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT
> > + }, {
> > + DDP_COMPONENT_DITHER1, DDP_COMPONENT_DP_INTF0,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
> > + MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT
> > + }, {
> > + DDP_COMPONENT_DITHER1, DDP_COMPONENT_DP_INTF1,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
> > + MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT
> > + }, {
> > + DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI0,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
> > + MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT
> > + }, {
> > + DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI1,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
> > + MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT
> > + }, {
> > + DDP_COMPONENT_MERGE5, DDP_COMPONENT_MERGE0,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_VDO1_VIRTUAL0_TO_MASK,
> > + MT8195_SOUT_VDO1_VIRTUAL0_TO_VPP_MERGE
> > + }, {
> > + DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF0,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_VDO1_VIRTUAL0_TO_MASK,
> > + MT8195_SOUT_VDO1_VIRTUAL0_TO_DP_INTF0
> > + }, {
> > + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSI1,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
> > + MT8195_SOUT_VPP_MERGE_TO_DSI1
> > + }, {
> > + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF0,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
> > + MT8195_SOUT_VPP_MERGE_TO_DP_INTF0
> > + }, {
> > + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF1,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
> > + MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0
> > + }, {
> > + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI0,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
> > + MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0
> > + }, {
> > + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI1,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
> > + MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0
> > + }, {
> > + DDP_COMPONENT_MERGE0, DDP_COMPONENT_WDMA1,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
> > + MT8195_SOUT_VPP_MERGE_TO_DISP_WDMA1
> > + }, {
> > + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC0,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
> > + MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP0_IN
> > + }, {
> > + DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC1,
> > + MT8195_VDO0_SEL_OUT,
> > MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN_MASK,
> > + MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN
> > + }, {
> > + DDP_COMPONENT_DSC0, DDP_COMPONENT_DSI0,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
> > + MT8195_SOUT_DSC_WRAP0_OUT_TO_DSI0
> > + }, {
> > + DDP_COMPONENT_DSC0, DDP_COMPONENT_DP_INTF1,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
> > + MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0
> > + }, {
> > + DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI0,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
> > + MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0
> > + }, {
> > + DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI1,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
> > + MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0
> > + }, {
> > + DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
> > + MT8195_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE
> > + }, {
> > + DDP_COMPONENT_DSC1, DDP_COMPONENT_DSI1,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
> > + MT8195_SOUT_DSC_WRAP1_OUT_TO_DSI1
> > + }, {
> > + DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF0,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
> > + MT8195_SOUT_DSC_WRAP1_OUT_TO_DP_INTF0
> > + }, {
> > + DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF1,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
> > + MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0
> > + }, {
> > + DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI0,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
> > + MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0
> > + }, {
> > + DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI1,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
> > + MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0
> > + }, {
> > + DDP_COMPONENT_DSC1, DDP_COMPONENT_MERGE0,
> > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
> > + MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE
> > + }
> > +};
> > +
> > +#endif /* __SOC_MEDIATEK_MT8195_MMSYS_H */
> > diff --git a/drivers/soc/mediatek/mtk-mmsys.c
> > b/drivers/soc/mediatek/mtk-mmsys.c
> > index 4fc4c2c9ea20..548efed8dc1c 100644
> > --- a/drivers/soc/mediatek/mtk-mmsys.c
> > +++ b/drivers/soc/mediatek/mtk-mmsys.c
> > @@ -17,6 +17,7 @@
> > #include "mt8183-mmsys.h"
> > #include "mt8186-mmsys.h"
> > #include "mt8192-mmsys.h"
> > +#include "mt8195-mmsys.h"
> > #include "mt8365-mmsys.h"
> >
> > static const struct mtk_mmsys_driver_data
> > mt2701_mmsys_driver_data = {
> > @@ -25,26 +26,61 @@ static const struct mtk_mmsys_driver_data
> > mt2701_mmsys_driver_data = {
> > .num_routes = ARRAY_SIZE(mmsys_default_routing_table),
> > };
> >
> > +static const struct mtk_mmsys_match_data mt2701_mmsys_match_data =
> > {
> > + .num_drv_data = 1,
> > + .drv_data = {
> > + &mt2701_mmsys_driver_data,
> > + },
> > +};
> > +
> > static const struct mtk_mmsys_driver_data
> > mt2712_mmsys_driver_data = {
> > .clk_driver = "clk-mt2712-mm",
> > .routes = mmsys_default_routing_table,
> > .num_routes = ARRAY_SIZE(mmsys_default_routing_table),
> > };
> >
> > +static const struct mtk_mmsys_match_data mt2712_mmsys_match_data =
> > {
> > + .num_drv_data = 1,
> > + .drv_data = {
> > + &mt2712_mmsys_driver_data,
> > + },
> > +};
> > +
> > static const struct mtk_mmsys_driver_data
> > mt6779_mmsys_driver_data = {
> > .clk_driver = "clk-mt6779-mm",
> > };
> >
> > +static const struct mtk_mmsys_match_data mt6779_mmsys_match_data =
> > {
> > + .num_drv_data = 1,
> > + .drv_data = {
> > + &mt6779_mmsys_driver_data,
> > + },
> > +};
> > +
> > static const struct mtk_mmsys_driver_data
> > mt6797_mmsys_driver_data = {
> > .clk_driver = "clk-mt6797-mm",
> > };
> >
> > +static const struct mtk_mmsys_match_data mt6797_mmsys_match_data =
> > {
> > + .num_drv_data = 1,
> > + .drv_data = {
> > + &mt6797_mmsys_driver_data,
> > + },
> > +};
> > +
> > static const struct mtk_mmsys_driver_data
> > mt8167_mmsys_driver_data = {
> > .clk_driver = "clk-mt8167-mm",
> > .routes = mt8167_mmsys_routing_table,
> > .num_routes = ARRAY_SIZE(mt8167_mmsys_routing_table),
> > };
> >
> > +static const struct mtk_mmsys_match_data mt8167_mmsys_match_data =
> > {
> > + .num_drv_data = 1,
> > + .drv_data = {
> > + &mt8167_mmsys_driver_data,
> > + },
> > +};
> > +
> > static const struct mtk_mmsys_driver_data
> > mt8173_mmsys_driver_data = {
> > .clk_driver = "clk-mt8173-mm",
> > .routes = mmsys_default_routing_table,
> > @@ -52,6 +88,13 @@ static const struct mtk_mmsys_driver_data
> > mt8173_mmsys_driver_data = {
> > .sw0_rst_offset = MT8183_MMSYS_SW0_RST_B,
> > };
> >
> > +static const struct mtk_mmsys_match_data mt8173_mmsys_match_data =
> > {
> > + .num_drv_data = 1,
> > + .drv_data = {
> > + &mt8173_mmsys_driver_data,
> > + },
> > +};
> > +
> > static const struct mtk_mmsys_driver_data
> > mt8183_mmsys_driver_data = {
> > .clk_driver = "clk-mt8183-mm",
> > .routes = mmsys_mt8183_routing_table,
> > @@ -59,6 +102,13 @@ static const struct mtk_mmsys_driver_data
> > mt8183_mmsys_driver_data = {
> > .sw0_rst_offset = MT8183_MMSYS_SW0_RST_B,
> > };
> >
> > +static const struct mtk_mmsys_match_data mt8183_mmsys_match_data =
> > {
> > + .num_drv_data = 1,
> > + .drv_data = {
> > + &mt8183_mmsys_driver_data,
> > + },
> > +};
> > +
> > static const struct mtk_mmsys_driver_data
> > mt8186_mmsys_driver_data = {
> > .clk_driver = "clk-mt8186-mm",
> > .routes = mmsys_mt8186_routing_table,
> > @@ -66,25 +116,79 @@ static const struct mtk_mmsys_driver_data
> > mt8186_mmsys_driver_data = {
> > .sw0_rst_offset = MT8186_MMSYS_SW0_RST_B,
> > };
> >
> > +static const struct mtk_mmsys_match_data mt8186_mmsys_match_data =
> > {
> > + .num_drv_data = 1,
> > + .drv_data = {
> > + &mt8186_mmsys_driver_data,
> > + },
> > +};
> > +
> > static const struct mtk_mmsys_driver_data
> > mt8192_mmsys_driver_data = {
> > .clk_driver = "clk-mt8192-mm",
> > .routes = mmsys_mt8192_routing_table,
> > .num_routes = ARRAY_SIZE(mmsys_mt8192_routing_table),
> > };
> >
> > +static const struct mtk_mmsys_match_data mt8192_mmsys_match_data =
> > {
> > + .num_drv_data = 1,
> > + .drv_data = {
> > + &mt8192_mmsys_driver_data,
> > + },
> > +};
> > +
> > +static const struct mtk_mmsys_driver_data
> > mt8195_vdosys0_driver_data = {
> > + .io_start = 0x1c01a000,
> > + .clk_driver = "clk-mt8195-vdo0",
> > + .routes = mmsys_mt8195_routing_table,
> > + .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
> > +};
> > +
> > +static const struct mtk_mmsys_driver_data
> > mt8195_vdosys1_driver_data = {
> > + .io_start = 0x1c100000,
> > + .clk_driver = "clk-mt8195-vdo1",
> > +};
> > +
> > +static const struct mtk_mmsys_match_data mt8195_mmsys_match_data =
> > {
> > + .num_drv_data = 2,
> > + .drv_data = {
> > + &mt8195_vdosys0_driver_data,
> > + &mt8195_vdosys1_driver_data,
> > + },
> > +};
> > +
> > static const struct mtk_mmsys_driver_data
> > mt8365_mmsys_driver_data = {
> > .clk_driver = "clk-mt8365-mm",
> > .routes = mt8365_mmsys_routing_table,
> > .num_routes = ARRAY_SIZE(mt8365_mmsys_routing_table),
> > };
> >
> > +static const struct mtk_mmsys_match_data mt8365_mmsys_match_data =
> > {
> > + .num_drv_data = 1,
> > + .drv_data = {
> > + &mt8365_mmsys_driver_data,
> > + },
> > +};
> > +
> > struct mtk_mmsys {
> > void __iomem *regs;
> > const struct mtk_mmsys_driver_data *data;
> > spinlock_t lock; /* protects mmsys_sw_rst_b reg */
> > struct reset_controller_dev rcdev;
> > + phys_addr_t io_start;
> > };
> >
> > +static int mtk_mmsys_find_match_drvdata(struct mtk_mmsys *mmsys,
> > + const struct
> > mtk_mmsys_match_data *match)
> > +{
> > + int i;
> > +
> > + for (i = 0; i < match->num_drv_data; i++)
> > + if (mmsys->io_start == match->drv_data[i]->io_start)
> > + return i;
> > +
> > + return -EINVAL;
> > +}
> > +
> > void mtk_mmsys_ddp_connect(struct device *dev,
> > enum mtk_ddp_comp_id cur,
> > enum mtk_ddp_comp_id next)
> > @@ -179,7 +283,9 @@ static int mtk_mmsys_probe(struct
> > platform_device *pdev)
> > struct device *dev = &pdev->dev;
> > struct platform_device *clks;
> > struct platform_device *drm;
> > + const struct mtk_mmsys_match_data *match_data;
> > struct mtk_mmsys *mmsys;
> > + struct resource *res;
> > int ret;
> >
> > mmsys = devm_kzalloc(dev, sizeof(*mmsys), GFP_KERNEL);
> > @@ -205,7 +311,27 @@ static int mtk_mmsys_probe(struct
> > platform_device *pdev)
> > return ret;
> > }
> >
> > - mmsys->data = of_device_get_match_data(&pdev->dev);
> > + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > + if (!res) {
> > + dev_err(dev, "Couldn't get mmsys resource\n");
> > + return -EINVAL;
> > + }
> > + mmsys->io_start = res->start;
> > +
> > + match_data = of_device_get_match_data(dev);
> > + if (match_data->num_drv_data > 1) {
> > + /* This SoC has multiple mmsys channels */
> > + ret = mtk_mmsys_find_match_drvdata(mmsys, match_data);
> > + if (ret < 0) {
> > + dev_err(dev, "Couldn't get match driver
> > data\n");
> > + return ret;
> > + }
> > + mmsys->data = match_data->drv_data[ret];
> > + } else {
> > + dev_dbg(dev, "Using single mmsys channel\n");
> > + mmsys->data = match_data->drv_data[0];
> > + }
> > +
> > platform_set_drvdata(pdev, mmsys);
> >
> > clks = platform_device_register_data(&pdev->dev, mmsys->data-
> > >clk_driver,
> > @@ -226,43 +352,47 @@ static int mtk_mmsys_probe(struct
> > platform_device *pdev)
> > static const struct of_device_id of_match_mtk_mmsys[] = {
> > {
> > .compatible = "mediatek,mt2701-mmsys",
> > - .data = &mt2701_mmsys_driver_data,
> > + .data = &mt2701_mmsys_match_data,
> > },
> > {
> > .compatible = "mediatek,mt2712-mmsys",
> > - .data = &mt2712_mmsys_driver_data,
> > + .data = &mt2712_mmsys_match_data,
> > },
> > {
> > .compatible = "mediatek,mt6779-mmsys",
> > - .data = &mt6779_mmsys_driver_data,
> > + .data = &mt6779_mmsys_match_data,
> > },
> > {
> > .compatible = "mediatek,mt6797-mmsys",
> > - .data = &mt6797_mmsys_driver_data,
> > + .data = &mt6797_mmsys_match_data,
> > },
> > {
> > .compatible = "mediatek,mt8167-mmsys",
> > - .data = &mt8167_mmsys_driver_data,
> > + .data = &mt8167_mmsys_match_data,
> > },
> > {
> > .compatible = "mediatek,mt8173-mmsys",
> > - .data = &mt8173_mmsys_driver_data,
> > + .data = &mt8173_mmsys_match_data,
> > },
> > {
> > .compatible = "mediatek,mt8183-mmsys",
> > - .data = &mt8183_mmsys_driver_data,
> > + .data = &mt8183_mmsys_match_data,
> > },
> > {
> > .compatible = "mediatek,mt8186-mmsys",
> > - .data = &mt8186_mmsys_driver_data,
> > + .data = &mt8186_mmsys_match_data,
> > },
> > {
> > .compatible = "mediatek,mt8192-mmsys",
> > - .data = &mt8192_mmsys_driver_data,
> > + .data = &mt8192_mmsys_match_data,
> > + },
> > + {
> > + .compatible = "mediatek,mt8195-mmsys",
> > + .data = &mt8195_mmsys_match_data,
> > },
> > {
> > .compatible = "mediatek,mt8365-mmsys",
> > - .data = &mt8365_mmsys_driver_data,
> > + .data = &mt8365_mmsys_match_data,
> > },
> > { }
> > };
> > diff --git a/drivers/soc/mediatek/mtk-mmsys.h
> > b/drivers/soc/mediatek/mtk-mmsys.h
> > index 77f37f8c715b..f01ba206481d 100644
> > --- a/drivers/soc/mediatek/mtk-mmsys.h
> > +++ b/drivers/soc/mediatek/mtk-mmsys.h
> > @@ -87,12 +87,18 @@ struct mtk_mmsys_routes {
> > };
> >
> > struct mtk_mmsys_driver_data {
> > + const resource_size_t io_start;
> > const char *clk_driver;
> > const struct mtk_mmsys_routes *routes;
> > const unsigned int num_routes;
> > const u16 sw0_rst_offset;
> > };
> >
> > +struct mtk_mmsys_match_data {
> > + unsigned short num_drv_data;
> > + const struct mtk_mmsys_driver_data *drv_data[];
> > +};
> > +
> > /*
> > * Routes in mt8173, mt2701, mt2712 are different. That means
> > * in the same register address, it controls different
> > input/output
> > diff --git a/include/linux/soc/mediatek/mtk-mmsys.h
> > b/include/linux/soc/mediatek/mtk-mmsys.h
> > index 4bba275e235a..cff5c9adbf46 100644
> > --- a/include/linux/soc/mediatek/mtk-mmsys.h
> > +++ b/include/linux/soc/mediatek/mtk-mmsys.h
> > @@ -17,13 +17,24 @@ enum mtk_ddp_comp_id {
> > DDP_COMPONENT_COLOR0,
> > DDP_COMPONENT_COLOR1,
> > DDP_COMPONENT_DITHER,
> > + DDP_COMPONENT_DITHER1,
> > + DDP_COMPONENT_DP_INTF0,
> > + DDP_COMPONENT_DP_INTF1,
> > DDP_COMPONENT_DPI0,
> > DDP_COMPONENT_DPI1,
> > + DDP_COMPONENT_DSC0,
> > + DDP_COMPONENT_DSC1,
> > DDP_COMPONENT_DSI0,
> > DDP_COMPONENT_DSI1,
> > DDP_COMPONENT_DSI2,
> > DDP_COMPONENT_DSI3,
> > DDP_COMPONENT_GAMMA,
> > + DDP_COMPONENT_MERGE0,
> > + DDP_COMPONENT_MERGE1,
> > + DDP_COMPONENT_MERGE2,
> > + DDP_COMPONENT_MERGE3,
> > + DDP_COMPONENT_MERGE4,
> > + DDP_COMPONENT_MERGE5,
> > DDP_COMPONENT_OD0,
> > DDP_COMPONENT_OD1,
> > DDP_COMPONENT_OVL0,
c--
Jason-JH Lin <jason-jh.lin@mediatek.com>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [PATCH v20 2/8] soc: mediatek: add mtk-mutex support for mt8195 vdosys0
2022-04-22 12:31 ` Matthias Brugger
(?)
(?)
@ 2022-04-24 8:48 ` Jason-JH Lin
-1 siblings, 0 replies; 110+ messages in thread
From: Jason-JH Lin @ 2022-04-24 8:48 UTC (permalink / raw)
To: Matthias Brugger, CK Hu, Chun-Kuang Hu, AngeloGioacchino Del Regno
Cc: Nancy Lin, Singo Chang, devicetree, linux-kernel, dri-devel,
linux-mediatek, linux-arm-kernel,
Project_Global_Chrome_Upstream_Group
Hi Matthias,
Thanks for the reviews.
On Fri, 2022-04-22 at 14:31 +0200, Matthias Brugger wrote:
>
> On 22/04/2022 04:32, Jason-JH Lin wrote:
> > Hi CK,
> >
> > Thanks for the reviews.
> >
> > On Thu, 2022-04-21 at 14:50 +0800, CK Hu wrote:
> > > Hi, Jason:
> > >
> > > On Tue, 2022-04-19 at 17:41 +0800, jason-jh.lin wrote:
> > > > Add mtk-mutex support for mt8195 vdosys0.
> > > >
> > > > Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> > > > Acked-by: AngeloGioacchino Del Regno <
> > > > angelogioacchino.delregno@collabora.com>
> > > > Tested-by: Fei Shao <fshao@chromium.org>
> > > > ---
> > > > drivers/soc/mediatek/mtk-mutex.c | 87
> > > > ++++++++++++++++++++++++++++++--
> > > > 1 file changed, 84 insertions(+), 3 deletions(-)
> > > >
> > > > diff --git a/drivers/soc/mediatek/mtk-mutex.c
> > > > b/drivers/soc/mediatek/mtk-mutex.c
> > > > index aaf8fc1abb43..729ee88035ed 100644
> > > > --- a/drivers/soc/mediatek/mtk-mutex.c
> > > > +++ b/drivers/soc/mediatek/mtk-mutex.c
> > > > @@ -17,6 +17,9 @@
> > > > #define MT8183_MUTEX0_MOD0 0x30
> > > > #define MT8183_MUTEX0_SOF0 0x2c
> > > >
> > > > +#define MT8195_DISP_MUTEX0_MOD0 0x30
> > > > +#define MT8195_DISP_MUTEX0_SOF 0x2c
> > >
> > > This is identical to mt8183, so use mt8183 one instead of
> > > creating
> > > new
> > > one.
> > >
> > > Regards,
> > > CK
> > >
> >
> > I'll fix this in the next version.
>
> Please send this as a follow-up fix on top of:
>
https://urldefense.com/v3/__https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux.git/log/?h=v5.18-next*soc__;Lw!!CTRNKA9wMg0ARbw!0QzNDaejnt54R86SL628fJ9p2BKTOmYBnoz6uPz9X8WsHXeQi3rqPAXmPFRBcw1vEtUu$
>
>
> Regards,
> Matthias
>
OK, I'll send the fix-up patch soon.
Regards,
Jason-JH.Lin
> >
> > Regards,
> > Jason-JH.Lin.
> > > >
> > > >
> > > > +static const struct mtk_mutex_data mt8195_mutex_driver_data =
> > > > {
> > > > + .mutex_mod = mt8195_mutex_mod,
> > > > + .mutex_sof = mt8195_mutex_sof,
> > > > + .mutex_mod_reg = MT8195_DISP_MUTEX0_MOD0,
> > > > + .mutex_sof_reg = MT8195_DISP_MUTEX0_SOF,
> > > > +};
> > > > +
> > > >
> > >
> > >
--
Jason-JH Lin <jason-jh.lin@mediatek.com>
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [PATCH v20 2/8] soc: mediatek: add mtk-mutex support for mt8195 vdosys0
@ 2022-04-24 8:48 ` Jason-JH Lin
0 siblings, 0 replies; 110+ messages in thread
From: Jason-JH Lin @ 2022-04-24 8:48 UTC (permalink / raw)
To: Matthias Brugger, CK Hu, Chun-Kuang Hu, AngeloGioacchino Del Regno
Cc: devicetree, Singo Chang, linux-kernel, dri-devel,
Project_Global_Chrome_Upstream_Group, Nancy Lin, linux-mediatek,
linux-arm-kernel
Hi Matthias,
Thanks for the reviews.
On Fri, 2022-04-22 at 14:31 +0200, Matthias Brugger wrote:
>
> On 22/04/2022 04:32, Jason-JH Lin wrote:
> > Hi CK,
> >
> > Thanks for the reviews.
> >
> > On Thu, 2022-04-21 at 14:50 +0800, CK Hu wrote:
> > > Hi, Jason:
> > >
> > > On Tue, 2022-04-19 at 17:41 +0800, jason-jh.lin wrote:
> > > > Add mtk-mutex support for mt8195 vdosys0.
> > > >
> > > > Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> > > > Acked-by: AngeloGioacchino Del Regno <
> > > > angelogioacchino.delregno@collabora.com>
> > > > Tested-by: Fei Shao <fshao@chromium.org>
> > > > ---
> > > > drivers/soc/mediatek/mtk-mutex.c | 87
> > > > ++++++++++++++++++++++++++++++--
> > > > 1 file changed, 84 insertions(+), 3 deletions(-)
> > > >
> > > > diff --git a/drivers/soc/mediatek/mtk-mutex.c
> > > > b/drivers/soc/mediatek/mtk-mutex.c
> > > > index aaf8fc1abb43..729ee88035ed 100644
> > > > --- a/drivers/soc/mediatek/mtk-mutex.c
> > > > +++ b/drivers/soc/mediatek/mtk-mutex.c
> > > > @@ -17,6 +17,9 @@
> > > > #define MT8183_MUTEX0_MOD0 0x30
> > > > #define MT8183_MUTEX0_SOF0 0x2c
> > > >
> > > > +#define MT8195_DISP_MUTEX0_MOD0 0x30
> > > > +#define MT8195_DISP_MUTEX0_SOF 0x2c
> > >
> > > This is identical to mt8183, so use mt8183 one instead of
> > > creating
> > > new
> > > one.
> > >
> > > Regards,
> > > CK
> > >
> >
> > I'll fix this in the next version.
>
> Please send this as a follow-up fix on top of:
>
https://urldefense.com/v3/__https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux.git/log/?h=v5.18-next*soc__;Lw!!CTRNKA9wMg0ARbw!0QzNDaejnt54R86SL628fJ9p2BKTOmYBnoz6uPz9X8WsHXeQi3rqPAXmPFRBcw1vEtUu$
>
>
> Regards,
> Matthias
>
OK, I'll send the fix-up patch soon.
Regards,
Jason-JH.Lin
> >
> > Regards,
> > Jason-JH.Lin.
> > > >
> > > >
> > > > +static const struct mtk_mutex_data mt8195_mutex_driver_data =
> > > > {
> > > > + .mutex_mod = mt8195_mutex_mod,
> > > > + .mutex_sof = mt8195_mutex_sof,
> > > > + .mutex_mod_reg = MT8195_DISP_MUTEX0_MOD0,
> > > > + .mutex_sof_reg = MT8195_DISP_MUTEX0_SOF,
> > > > +};
> > > > +
> > > >
> > >
> > >
--
Jason-JH Lin <jason-jh.lin@mediatek.com>
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [PATCH v20 2/8] soc: mediatek: add mtk-mutex support for mt8195 vdosys0
@ 2022-04-24 8:48 ` Jason-JH Lin
0 siblings, 0 replies; 110+ messages in thread
From: Jason-JH Lin @ 2022-04-24 8:48 UTC (permalink / raw)
To: Matthias Brugger, CK Hu, Chun-Kuang Hu, AngeloGioacchino Del Regno
Cc: Nancy Lin, Singo Chang, devicetree, linux-kernel, dri-devel,
linux-mediatek, linux-arm-kernel,
Project_Global_Chrome_Upstream_Group
Hi Matthias,
Thanks for the reviews.
On Fri, 2022-04-22 at 14:31 +0200, Matthias Brugger wrote:
>
> On 22/04/2022 04:32, Jason-JH Lin wrote:
> > Hi CK,
> >
> > Thanks for the reviews.
> >
> > On Thu, 2022-04-21 at 14:50 +0800, CK Hu wrote:
> > > Hi, Jason:
> > >
> > > On Tue, 2022-04-19 at 17:41 +0800, jason-jh.lin wrote:
> > > > Add mtk-mutex support for mt8195 vdosys0.
> > > >
> > > > Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> > > > Acked-by: AngeloGioacchino Del Regno <
> > > > angelogioacchino.delregno@collabora.com>
> > > > Tested-by: Fei Shao <fshao@chromium.org>
> > > > ---
> > > > drivers/soc/mediatek/mtk-mutex.c | 87
> > > > ++++++++++++++++++++++++++++++--
> > > > 1 file changed, 84 insertions(+), 3 deletions(-)
> > > >
> > > > diff --git a/drivers/soc/mediatek/mtk-mutex.c
> > > > b/drivers/soc/mediatek/mtk-mutex.c
> > > > index aaf8fc1abb43..729ee88035ed 100644
> > > > --- a/drivers/soc/mediatek/mtk-mutex.c
> > > > +++ b/drivers/soc/mediatek/mtk-mutex.c
> > > > @@ -17,6 +17,9 @@
> > > > #define MT8183_MUTEX0_MOD0 0x30
> > > > #define MT8183_MUTEX0_SOF0 0x2c
> > > >
> > > > +#define MT8195_DISP_MUTEX0_MOD0 0x30
> > > > +#define MT8195_DISP_MUTEX0_SOF 0x2c
> > >
> > > This is identical to mt8183, so use mt8183 one instead of
> > > creating
> > > new
> > > one.
> > >
> > > Regards,
> > > CK
> > >
> >
> > I'll fix this in the next version.
>
> Please send this as a follow-up fix on top of:
>
https://urldefense.com/v3/__https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux.git/log/?h=v5.18-next*soc__;Lw!!CTRNKA9wMg0ARbw!0QzNDaejnt54R86SL628fJ9p2BKTOmYBnoz6uPz9X8WsHXeQi3rqPAXmPFRBcw1vEtUu$
>
>
> Regards,
> Matthias
>
OK, I'll send the fix-up patch soon.
Regards,
Jason-JH.Lin
> >
> > Regards,
> > Jason-JH.Lin.
> > > >
> > > >
> > > > +static const struct mtk_mutex_data mt8195_mutex_driver_data =
> > > > {
> > > > + .mutex_mod = mt8195_mutex_mod,
> > > > + .mutex_sof = mt8195_mutex_sof,
> > > > + .mutex_mod_reg = MT8195_DISP_MUTEX0_MOD0,
> > > > + .mutex_sof_reg = MT8195_DISP_MUTEX0_SOF,
> > > > +};
> > > > +
> > > >
> > >
> > >
--
Jason-JH Lin <jason-jh.lin@mediatek.com>
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [PATCH v20 2/8] soc: mediatek: add mtk-mutex support for mt8195 vdosys0
@ 2022-04-24 8:48 ` Jason-JH Lin
0 siblings, 0 replies; 110+ messages in thread
From: Jason-JH Lin @ 2022-04-24 8:48 UTC (permalink / raw)
To: Matthias Brugger, CK Hu, Chun-Kuang Hu, AngeloGioacchino Del Regno
Cc: Nancy Lin, Singo Chang, devicetree, linux-kernel, dri-devel,
linux-mediatek, linux-arm-kernel,
Project_Global_Chrome_Upstream_Group
Hi Matthias,
Thanks for the reviews.
On Fri, 2022-04-22 at 14:31 +0200, Matthias Brugger wrote:
>
> On 22/04/2022 04:32, Jason-JH Lin wrote:
> > Hi CK,
> >
> > Thanks for the reviews.
> >
> > On Thu, 2022-04-21 at 14:50 +0800, CK Hu wrote:
> > > Hi, Jason:
> > >
> > > On Tue, 2022-04-19 at 17:41 +0800, jason-jh.lin wrote:
> > > > Add mtk-mutex support for mt8195 vdosys0.
> > > >
> > > > Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> > > > Acked-by: AngeloGioacchino Del Regno <
> > > > angelogioacchino.delregno@collabora.com>
> > > > Tested-by: Fei Shao <fshao@chromium.org>
> > > > ---
> > > > drivers/soc/mediatek/mtk-mutex.c | 87
> > > > ++++++++++++++++++++++++++++++--
> > > > 1 file changed, 84 insertions(+), 3 deletions(-)
> > > >
> > > > diff --git a/drivers/soc/mediatek/mtk-mutex.c
> > > > b/drivers/soc/mediatek/mtk-mutex.c
> > > > index aaf8fc1abb43..729ee88035ed 100644
> > > > --- a/drivers/soc/mediatek/mtk-mutex.c
> > > > +++ b/drivers/soc/mediatek/mtk-mutex.c
> > > > @@ -17,6 +17,9 @@
> > > > #define MT8183_MUTEX0_MOD0 0x30
> > > > #define MT8183_MUTEX0_SOF0 0x2c
> > > >
> > > > +#define MT8195_DISP_MUTEX0_MOD0 0x30
> > > > +#define MT8195_DISP_MUTEX0_SOF 0x2c
> > >
> > > This is identical to mt8183, so use mt8183 one instead of
> > > creating
> > > new
> > > one.
> > >
> > > Regards,
> > > CK
> > >
> >
> > I'll fix this in the next version.
>
> Please send this as a follow-up fix on top of:
>
https://urldefense.com/v3/__https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux.git/log/?h=v5.18-next*soc__;Lw!!CTRNKA9wMg0ARbw!0QzNDaejnt54R86SL628fJ9p2BKTOmYBnoz6uPz9X8WsHXeQi3rqPAXmPFRBcw1vEtUu$
>
>
> Regards,
> Matthias
>
OK, I'll send the fix-up patch soon.
Regards,
Jason-JH.Lin
> >
> > Regards,
> > Jason-JH.Lin.
> > > >
> > > >
> > > > +static const struct mtk_mutex_data mt8195_mutex_driver_data =
> > > > {
> > > > + .mutex_mod = mt8195_mutex_mod,
> > > > + .mutex_sof = mt8195_mutex_sof,
> > > > + .mutex_mod_reg = MT8195_DISP_MUTEX0_MOD0,
> > > > + .mutex_sof_reg = MT8195_DISP_MUTEX0_SOF,
> > > > +};
> > > > +
> > > >
> > >
> > >
--
Jason-JH Lin <jason-jh.lin@mediatek.com>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [PATCH v20 8/8] soc: mediatek: remove DDP_DOMPONENT_DITHER from enum
2022-04-22 12:42 ` Matthias Brugger
(?)
(?)
@ 2022-05-01 22:54 ` Chun-Kuang Hu
-1 siblings, 0 replies; 110+ messages in thread
From: Chun-Kuang Hu @ 2022-05-01 22:54 UTC (permalink / raw)
To: Matthias Brugger
Cc: jason-jh.lin, Chun-Kuang Hu, AngeloGioacchino Del Regno, CK Hu,
Nancy Lin, Singo Chang, DTML, linux-kernel, DRI Development,
moderated list:ARM/Mediatek SoC support, Linux ARM,
Project_Global_Chrome_Upstream_Group
Hi, Matthias:
Matthias Brugger <matthias.bgg@gmail.com> 於 2022年4月22日 週五 下午8:42寫道：
>
>
>
> On 19/04/2022 11:41, jason-jh.lin wrote:
> > After mmsys and drm change DITHER enum to DDP_COMPONENT_DITHER0,
> > mmsys header can remove the useless DDP_COMPONENT_DITHER enum.
> >
> > Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> > Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
>
> Acked-by: Matthias Brugger <matthias.bgg@gmail.com>
>
> Chun-Kuang, I think it would make sense to take that through your tree as it
> depends on the previous patches.
>
> I provide you a stable tag so that you can take it:
> v5.18-next-vdso0-stable-tag
After I take this tag, I find one checkpatch warning:
WARNING: DT compatible string "mediatek,mt8195-mmsys" appears
un-documented -- check ./Documentation/devicetree/bindings/
#670: FILE: drivers/soc/mediatek/mtk-mmsys.c:390:
+ .compatible = "mediatek,mt8195-mmsys",
I think this tag lost one binding patch, it's better that this tag has
no this warning.
Regards,
Chun-Kuang.
>
> Regards,
> Matthias
>
> > ---
> > include/linux/soc/mediatek/mtk-mmsys.h | 3 +--
> > 1 file changed, 1 insertion(+), 2 deletions(-)
> >
> > diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
> > index 59117d970daf..fb719fd1281c 100644
> > --- a/include/linux/soc/mediatek/mtk-mmsys.h
> > +++ b/include/linux/soc/mediatek/mtk-mmsys.h
> > @@ -16,8 +16,7 @@ enum mtk_ddp_comp_id {
> > DDP_COMPONENT_CCORR,
> > DDP_COMPONENT_COLOR0,
> > DDP_COMPONENT_COLOR1,
> > - DDP_COMPONENT_DITHER,
> > - DDP_COMPONENT_DITHER0 = DDP_COMPONENT_DITHER,
> > + DDP_COMPONENT_DITHER0,
> > DDP_COMPONENT_DITHER1,
> > DDP_COMPONENT_DP_INTF0,
> > DDP_COMPONENT_DP_INTF1,
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [PATCH v20 8/8] soc: mediatek: remove DDP_DOMPONENT_DITHER from enum
@ 2022-05-01 22:54 ` Chun-Kuang Hu
0 siblings, 0 replies; 110+ messages in thread
From: Chun-Kuang Hu @ 2022-05-01 22:54 UTC (permalink / raw)
To: Matthias Brugger
Cc: jason-jh.lin, Chun-Kuang Hu, AngeloGioacchino Del Regno, CK Hu,
Nancy Lin, Singo Chang, DTML, linux-kernel, DRI Development,
moderated list:ARM/Mediatek SoC support, Linux ARM,
Project_Global_Chrome_Upstream_Group
Hi, Matthias:
Matthias Brugger <matthias.bgg@gmail.com> 於 2022年4月22日 週五 下午8:42寫道：
>
>
>
> On 19/04/2022 11:41, jason-jh.lin wrote:
> > After mmsys and drm change DITHER enum to DDP_COMPONENT_DITHER0,
> > mmsys header can remove the useless DDP_COMPONENT_DITHER enum.
> >
> > Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> > Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
>
> Acked-by: Matthias Brugger <matthias.bgg@gmail.com>
>
> Chun-Kuang, I think it would make sense to take that through your tree as it
> depends on the previous patches.
>
> I provide you a stable tag so that you can take it:
> v5.18-next-vdso0-stable-tag
After I take this tag, I find one checkpatch warning:
WARNING: DT compatible string "mediatek,mt8195-mmsys" appears
un-documented -- check ./Documentation/devicetree/bindings/
#670: FILE: drivers/soc/mediatek/mtk-mmsys.c:390:
+ .compatible = "mediatek,mt8195-mmsys",
I think this tag lost one binding patch, it's better that this tag has
no this warning.
Regards,
Chun-Kuang.
>
> Regards,
> Matthias
>
> > ---
> > include/linux/soc/mediatek/mtk-mmsys.h | 3 +--
> > 1 file changed, 1 insertion(+), 2 deletions(-)
> >
> > diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
> > index 59117d970daf..fb719fd1281c 100644
> > --- a/include/linux/soc/mediatek/mtk-mmsys.h
> > +++ b/include/linux/soc/mediatek/mtk-mmsys.h
> > @@ -16,8 +16,7 @@ enum mtk_ddp_comp_id {
> > DDP_COMPONENT_CCORR,
> > DDP_COMPONENT_COLOR0,
> > DDP_COMPONENT_COLOR1,
> > - DDP_COMPONENT_DITHER,
> > - DDP_COMPONENT_DITHER0 = DDP_COMPONENT_DITHER,
> > + DDP_COMPONENT_DITHER0,
> > DDP_COMPONENT_DITHER1,
> > DDP_COMPONENT_DP_INTF0,
> > DDP_COMPONENT_DP_INTF1,
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [PATCH v20 8/8] soc: mediatek: remove DDP_DOMPONENT_DITHER from enum
@ 2022-05-01 22:54 ` Chun-Kuang Hu
0 siblings, 0 replies; 110+ messages in thread
From: Chun-Kuang Hu @ 2022-05-01 22:54 UTC (permalink / raw)
To: Matthias Brugger
Cc: Chun-Kuang Hu, DTML, jason-jh.lin, Singo Chang, linux-kernel,
DRI Development, Project_Global_Chrome_Upstream_Group, Nancy Lin,
moderated list:ARM/Mediatek SoC support, Linux ARM,
AngeloGioacchino Del Regno
Hi, Matthias:
Matthias Brugger <matthias.bgg@gmail.com> 於 2022年4月22日 週五 下午8:42寫道：
>
>
>
> On 19/04/2022 11:41, jason-jh.lin wrote:
> > After mmsys and drm change DITHER enum to DDP_COMPONENT_DITHER0,
> > mmsys header can remove the useless DDP_COMPONENT_DITHER enum.
> >
> > Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> > Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
>
> Acked-by: Matthias Brugger <matthias.bgg@gmail.com>
>
> Chun-Kuang, I think it would make sense to take that through your tree as it
> depends on the previous patches.
>
> I provide you a stable tag so that you can take it:
> v5.18-next-vdso0-stable-tag
After I take this tag, I find one checkpatch warning:
WARNING: DT compatible string "mediatek,mt8195-mmsys" appears
un-documented -- check ./Documentation/devicetree/bindings/
#670: FILE: drivers/soc/mediatek/mtk-mmsys.c:390:
+ .compatible = "mediatek,mt8195-mmsys",
I think this tag lost one binding patch, it's better that this tag has
no this warning.
Regards,
Chun-Kuang.
>
> Regards,
> Matthias
>
> > ---
> > include/linux/soc/mediatek/mtk-mmsys.h | 3 +--
> > 1 file changed, 1 insertion(+), 2 deletions(-)
> >
> > diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
> > index 59117d970daf..fb719fd1281c 100644
> > --- a/include/linux/soc/mediatek/mtk-mmsys.h
> > +++ b/include/linux/soc/mediatek/mtk-mmsys.h
> > @@ -16,8 +16,7 @@ enum mtk_ddp_comp_id {
> > DDP_COMPONENT_CCORR,
> > DDP_COMPONENT_COLOR0,
> > DDP_COMPONENT_COLOR1,
> > - DDP_COMPONENT_DITHER,
> > - DDP_COMPONENT_DITHER0 = DDP_COMPONENT_DITHER,
> > + DDP_COMPONENT_DITHER0,
> > DDP_COMPONENT_DITHER1,
> > DDP_COMPONENT_DP_INTF0,
> > DDP_COMPONENT_DP_INTF1,
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [PATCH v20 8/8] soc: mediatek: remove DDP_DOMPONENT_DITHER from enum
@ 2022-05-01 22:54 ` Chun-Kuang Hu
0 siblings, 0 replies; 110+ messages in thread
From: Chun-Kuang Hu @ 2022-05-01 22:54 UTC (permalink / raw)
To: Matthias Brugger
Cc: jason-jh.lin, Chun-Kuang Hu, AngeloGioacchino Del Regno, CK Hu,
Nancy Lin, Singo Chang, DTML, linux-kernel, DRI Development,
moderated list:ARM/Mediatek SoC support, Linux ARM,
Project_Global_Chrome_Upstream_Group
Hi, Matthias:
Matthias Brugger <matthias.bgg@gmail.com> 於 2022年4月22日 週五 下午8:42寫道：
>
>
>
> On 19/04/2022 11:41, jason-jh.lin wrote:
> > After mmsys and drm change DITHER enum to DDP_COMPONENT_DITHER0,
> > mmsys header can remove the useless DDP_COMPONENT_DITHER enum.
> >
> > Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> > Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
>
> Acked-by: Matthias Brugger <matthias.bgg@gmail.com>
>
> Chun-Kuang, I think it would make sense to take that through your tree as it
> depends on the previous patches.
>
> I provide you a stable tag so that you can take it:
> v5.18-next-vdso0-stable-tag
After I take this tag, I find one checkpatch warning:
WARNING: DT compatible string "mediatek,mt8195-mmsys" appears
un-documented -- check ./Documentation/devicetree/bindings/
#670: FILE: drivers/soc/mediatek/mtk-mmsys.c:390:
+ .compatible = "mediatek,mt8195-mmsys",
I think this tag lost one binding patch, it's better that this tag has
no this warning.
Regards,
Chun-Kuang.
>
> Regards,
> Matthias
>
> > ---
> > include/linux/soc/mediatek/mtk-mmsys.h | 3 +--
> > 1 file changed, 1 insertion(+), 2 deletions(-)
> >
> > diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
> > index 59117d970daf..fb719fd1281c 100644
> > --- a/include/linux/soc/mediatek/mtk-mmsys.h
> > +++ b/include/linux/soc/mediatek/mtk-mmsys.h
> > @@ -16,8 +16,7 @@ enum mtk_ddp_comp_id {
> > DDP_COMPONENT_CCORR,
> > DDP_COMPONENT_COLOR0,
> > DDP_COMPONENT_COLOR1,
> > - DDP_COMPONENT_DITHER,
> > - DDP_COMPONENT_DITHER0 = DDP_COMPONENT_DITHER,
> > + DDP_COMPONENT_DITHER0,
> > DDP_COMPONENT_DITHER1,
> > DDP_COMPONENT_DP_INTF0,
> > DDP_COMPONENT_DP_INTF1,
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [PATCH v20 8/8] soc: mediatek: remove DDP_DOMPONENT_DITHER from enum
2022-05-01 22:54 ` Chun-Kuang Hu
(?)
(?)
@ 2022-05-13 7:42 ` Matthias Brugger
-1 siblings, 0 replies; 110+ messages in thread
From: Matthias Brugger @ 2022-05-13 7:42 UTC (permalink / raw)
To: Chun-Kuang Hu
Cc: jason-jh.lin, AngeloGioacchino Del Regno, CK Hu, Nancy Lin,
Singo Chang, DTML, linux-kernel, DRI Development,
moderated list:ARM/Mediatek SoC support, Linux ARM,
Project_Global_Chrome_Upstream_Group
Hi Chun-Kuang,
On 02/05/2022 00:54, Chun-Kuang Hu wrote:
> Hi, Matthias:
>
> Matthias Brugger <matthias.bgg@gmail.com> 於 2022年4月22日 週五 下午8:42寫道：
>>
>>
>>
>> On 19/04/2022 11:41, jason-jh.lin wrote:
>>> After mmsys and drm change DITHER enum to DDP_COMPONENT_DITHER0,
>>> mmsys header can remove the useless DDP_COMPONENT_DITHER enum.
>>>
>>> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
>>> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
>>
>> Acked-by: Matthias Brugger <matthias.bgg@gmail.com>
>>
>> Chun-Kuang, I think it would make sense to take that through your tree as it
>> depends on the previous patches.
>>
>> I provide you a stable tag so that you can take it:
>> v5.18-next-vdso0-stable-tag
>
> After I take this tag, I find one checkpatch warning:
>
> WARNING: DT compatible string "mediatek,mt8195-mmsys" appears
> un-documented -- check ./Documentation/devicetree/bindings/
> #670: FILE: drivers/soc/mediatek/mtk-mmsys.c:390:
> + .compatible = "mediatek,mt8195-mmsys",
>
> I think this tag lost one binding patch, it's better that this tag has
> no this warning.
>
Sorry for the late reply I was sick.
The warning is, because the stable branch misses commit:
https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux.git/commit/?h=v5.18-next/soc&id=81c5a41d10b968ea89d5f44fe1e5c2fc70289209
So it's not a real issue and will go away once our branches land in upstream.
Is it OK for you to ignore the issue?
Regards,
Matthias
> Regards,
> Chun-Kuang.
>
>>
>> Regards,
>> Matthias
>>
>>> ---
>>> include/linux/soc/mediatek/mtk-mmsys.h | 3 +--
>>> 1 file changed, 1 insertion(+), 2 deletions(-)
>>>
>>> diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
>>> index 59117d970daf..fb719fd1281c 100644
>>> --- a/include/linux/soc/mediatek/mtk-mmsys.h
>>> +++ b/include/linux/soc/mediatek/mtk-mmsys.h
>>> @@ -16,8 +16,7 @@ enum mtk_ddp_comp_id {
>>> DDP_COMPONENT_CCORR,
>>> DDP_COMPONENT_COLOR0,
>>> DDP_COMPONENT_COLOR1,
>>> - DDP_COMPONENT_DITHER,
>>> - DDP_COMPONENT_DITHER0 = DDP_COMPONENT_DITHER,
>>> + DDP_COMPONENT_DITHER0,
>>> DDP_COMPONENT_DITHER1,
>>> DDP_COMPONENT_DP_INTF0,
>>> DDP_COMPONENT_DP_INTF1,
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [PATCH v20 8/8] soc: mediatek: remove DDP_DOMPONENT_DITHER from enum
@ 2022-05-13 7:42 ` Matthias Brugger
0 siblings, 0 replies; 110+ messages in thread
From: Matthias Brugger @ 2022-05-13 7:42 UTC (permalink / raw)
To: Chun-Kuang Hu
Cc: jason-jh.lin, AngeloGioacchino Del Regno, CK Hu, Nancy Lin,
Singo Chang, DTML, linux-kernel, DRI Development,
moderated list:ARM/Mediatek SoC support, Linux ARM,
Project_Global_Chrome_Upstream_Group
Hi Chun-Kuang,
On 02/05/2022 00:54, Chun-Kuang Hu wrote:
> Hi, Matthias:
>
> Matthias Brugger <matthias.bgg@gmail.com> 於 2022年4月22日 週五 下午8:42寫道：
>>
>>
>>
>> On 19/04/2022 11:41, jason-jh.lin wrote:
>>> After mmsys and drm change DITHER enum to DDP_COMPONENT_DITHER0,
>>> mmsys header can remove the useless DDP_COMPONENT_DITHER enum.
>>>
>>> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
>>> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
>>
>> Acked-by: Matthias Brugger <matthias.bgg@gmail.com>
>>
>> Chun-Kuang, I think it would make sense to take that through your tree as it
>> depends on the previous patches.
>>
>> I provide you a stable tag so that you can take it:
>> v5.18-next-vdso0-stable-tag
>
> After I take this tag, I find one checkpatch warning:
>
> WARNING: DT compatible string "mediatek,mt8195-mmsys" appears
> un-documented -- check ./Documentation/devicetree/bindings/
> #670: FILE: drivers/soc/mediatek/mtk-mmsys.c:390:
> + .compatible = "mediatek,mt8195-mmsys",
>
> I think this tag lost one binding patch, it's better that this tag has
> no this warning.
>
Sorry for the late reply I was sick.
The warning is, because the stable branch misses commit:
https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux.git/commit/?h=v5.18-next/soc&id=81c5a41d10b968ea89d5f44fe1e5c2fc70289209
So it's not a real issue and will go away once our branches land in upstream.
Is it OK for you to ignore the issue?
Regards,
Matthias
> Regards,
> Chun-Kuang.
>
>>
>> Regards,
>> Matthias
>>
>>> ---
>>> include/linux/soc/mediatek/mtk-mmsys.h | 3 +--
>>> 1 file changed, 1 insertion(+), 2 deletions(-)
>>>
>>> diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
>>> index 59117d970daf..fb719fd1281c 100644
>>> --- a/include/linux/soc/mediatek/mtk-mmsys.h
>>> +++ b/include/linux/soc/mediatek/mtk-mmsys.h
>>> @@ -16,8 +16,7 @@ enum mtk_ddp_comp_id {
>>> DDP_COMPONENT_CCORR,
>>> DDP_COMPONENT_COLOR0,
>>> DDP_COMPONENT_COLOR1,
>>> - DDP_COMPONENT_DITHER,
>>> - DDP_COMPONENT_DITHER0 = DDP_COMPONENT_DITHER,
>>> + DDP_COMPONENT_DITHER0,
>>> DDP_COMPONENT_DITHER1,
>>> DDP_COMPONENT_DP_INTF0,
>>> DDP_COMPONENT_DP_INTF1,
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [PATCH v20 8/8] soc: mediatek: remove DDP_DOMPONENT_DITHER from enum
@ 2022-05-13 7:42 ` Matthias Brugger
0 siblings, 0 replies; 110+ messages in thread
From: Matthias Brugger @ 2022-05-13 7:42 UTC (permalink / raw)
To: Chun-Kuang Hu
Cc: DTML, jason-jh.lin, Singo Chang, linux-kernel, DRI Development,
Project_Global_Chrome_Upstream_Group, Nancy Lin,
moderated list:ARM/Mediatek SoC support, Linux ARM,
AngeloGioacchino Del Regno
Hi Chun-Kuang,
On 02/05/2022 00:54, Chun-Kuang Hu wrote:
> Hi, Matthias:
>
> Matthias Brugger <matthias.bgg@gmail.com> 於 2022年4月22日 週五 下午8:42寫道：
>>
>>
>>
>> On 19/04/2022 11:41, jason-jh.lin wrote:
>>> After mmsys and drm change DITHER enum to DDP_COMPONENT_DITHER0,
>>> mmsys header can remove the useless DDP_COMPONENT_DITHER enum.
>>>
>>> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
>>> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
>>
>> Acked-by: Matthias Brugger <matthias.bgg@gmail.com>
>>
>> Chun-Kuang, I think it would make sense to take that through your tree as it
>> depends on the previous patches.
>>
>> I provide you a stable tag so that you can take it:
>> v5.18-next-vdso0-stable-tag
>
> After I take this tag, I find one checkpatch warning:
>
> WARNING: DT compatible string "mediatek,mt8195-mmsys" appears
> un-documented -- check ./Documentation/devicetree/bindings/
> #670: FILE: drivers/soc/mediatek/mtk-mmsys.c:390:
> + .compatible = "mediatek,mt8195-mmsys",
>
> I think this tag lost one binding patch, it's better that this tag has
> no this warning.
>
Sorry for the late reply I was sick.
The warning is, because the stable branch misses commit:
https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux.git/commit/?h=v5.18-next/soc&id=81c5a41d10b968ea89d5f44fe1e5c2fc70289209
So it's not a real issue and will go away once our branches land in upstream.
Is it OK for you to ignore the issue?
Regards,
Matthias
> Regards,
> Chun-Kuang.
>
>>
>> Regards,
>> Matthias
>>
>>> ---
>>> include/linux/soc/mediatek/mtk-mmsys.h | 3 +--
>>> 1 file changed, 1 insertion(+), 2 deletions(-)
>>>
>>> diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
>>> index 59117d970daf..fb719fd1281c 100644
>>> --- a/include/linux/soc/mediatek/mtk-mmsys.h
>>> +++ b/include/linux/soc/mediatek/mtk-mmsys.h
>>> @@ -16,8 +16,7 @@ enum mtk_ddp_comp_id {
>>> DDP_COMPONENT_CCORR,
>>> DDP_COMPONENT_COLOR0,
>>> DDP_COMPONENT_COLOR1,
>>> - DDP_COMPONENT_DITHER,
>>> - DDP_COMPONENT_DITHER0 = DDP_COMPONENT_DITHER,
>>> + DDP_COMPONENT_DITHER0,
>>> DDP_COMPONENT_DITHER1,
>>> DDP_COMPONENT_DP_INTF0,
>>> DDP_COMPONENT_DP_INTF1,
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [PATCH v20 8/8] soc: mediatek: remove DDP_DOMPONENT_DITHER from enum
@ 2022-05-13 7:42 ` Matthias Brugger
0 siblings, 0 replies; 110+ messages in thread
From: Matthias Brugger @ 2022-05-13 7:42 UTC (permalink / raw)
To: Chun-Kuang Hu
Cc: jason-jh.lin, AngeloGioacchino Del Regno, CK Hu, Nancy Lin,
Singo Chang, DTML, linux-kernel, DRI Development,
moderated list:ARM/Mediatek SoC support, Linux ARM,
Project_Global_Chrome_Upstream_Group
Hi Chun-Kuang,
On 02/05/2022 00:54, Chun-Kuang Hu wrote:
> Hi, Matthias:
>
> Matthias Brugger <matthias.bgg@gmail.com> 於 2022年4月22日 週五 下午8:42寫道：
>>
>>
>>
>> On 19/04/2022 11:41, jason-jh.lin wrote:
>>> After mmsys and drm change DITHER enum to DDP_COMPONENT_DITHER0,
>>> mmsys header can remove the useless DDP_COMPONENT_DITHER enum.
>>>
>>> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
>>> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
>>
>> Acked-by: Matthias Brugger <matthias.bgg@gmail.com>
>>
>> Chun-Kuang, I think it would make sense to take that through your tree as it
>> depends on the previous patches.
>>
>> I provide you a stable tag so that you can take it:
>> v5.18-next-vdso0-stable-tag
>
> After I take this tag, I find one checkpatch warning:
>
> WARNING: DT compatible string "mediatek,mt8195-mmsys" appears
> un-documented -- check ./Documentation/devicetree/bindings/
> #670: FILE: drivers/soc/mediatek/mtk-mmsys.c:390:
> + .compatible = "mediatek,mt8195-mmsys",
>
> I think this tag lost one binding patch, it's better that this tag has
> no this warning.
>
Sorry for the late reply I was sick.
The warning is, because the stable branch misses commit:
https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux.git/commit/?h=v5.18-next/soc&id=81c5a41d10b968ea89d5f44fe1e5c2fc70289209
So it's not a real issue and will go away once our branches land in upstream.
Is it OK for you to ignore the issue?
Regards,
Matthias
> Regards,
> Chun-Kuang.
>
>>
>> Regards,
>> Matthias
>>
>>> ---
>>> include/linux/soc/mediatek/mtk-mmsys.h | 3 +--
>>> 1 file changed, 1 insertion(+), 2 deletions(-)
>>>
>>> diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
>>> index 59117d970daf..fb719fd1281c 100644
>>> --- a/include/linux/soc/mediatek/mtk-mmsys.h
>>> +++ b/include/linux/soc/mediatek/mtk-mmsys.h
>>> @@ -16,8 +16,7 @@ enum mtk_ddp_comp_id {
>>> DDP_COMPONENT_CCORR,
>>> DDP_COMPONENT_COLOR0,
>>> DDP_COMPONENT_COLOR1,
>>> - DDP_COMPONENT_DITHER,
>>> - DDP_COMPONENT_DITHER0 = DDP_COMPONENT_DITHER,
>>> + DDP_COMPONENT_DITHER0,
>>> DDP_COMPONENT_DITHER1,
>>> DDP_COMPONENT_DP_INTF0,
>>> DDP_COMPONENT_DP_INTF1,
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [PATCH v20 8/8] soc: mediatek: remove DDP_DOMPONENT_DITHER from enum
2022-05-13 7:42 ` Matthias Brugger
(?)
(?)
@ 2022-05-14 22:45 ` Chun-Kuang Hu
-1 siblings, 0 replies; 110+ messages in thread
From: Chun-Kuang Hu @ 2022-05-14 22:45 UTC (permalink / raw)
To: Matthias Brugger
Cc: Chun-Kuang Hu, jason-jh.lin, AngeloGioacchino Del Regno, CK Hu,
Nancy Lin, Singo Chang, DTML, linux-kernel, DRI Development,
moderated list:ARM/Mediatek SoC support, Linux ARM,
Project_Global_Chrome_Upstream_Group
Hi, Matthias:
Matthias Brugger <matthias.bgg@gmail.com> 於 2022年5月13日 週五 下午3:42寫道：
>
> Hi Chun-Kuang,
>
> On 02/05/2022 00:54, Chun-Kuang Hu wrote:
> > Hi, Matthias:
> >
> > Matthias Brugger <matthias.bgg@gmail.com> 於 2022年4月22日 週五 下午8:42寫道：
> >>
> >>
> >>
> >> On 19/04/2022 11:41, jason-jh.lin wrote:
> >>> After mmsys and drm change DITHER enum to DDP_COMPONENT_DITHER0,
> >>> mmsys header can remove the useless DDP_COMPONENT_DITHER enum.
> >>>
> >>> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> >>> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> >>
> >> Acked-by: Matthias Brugger <matthias.bgg@gmail.com>
> >>
> >> Chun-Kuang, I think it would make sense to take that through your tree as it
> >> depends on the previous patches.
> >>
> >> I provide you a stable tag so that you can take it:
> >> v5.18-next-vdso0-stable-tag
> >
> > After I take this tag, I find one checkpatch warning:
> >
> > WARNING: DT compatible string "mediatek,mt8195-mmsys" appears
> > un-documented -- check ./Documentation/devicetree/bindings/
> > #670: FILE: drivers/soc/mediatek/mtk-mmsys.c:390:
> > + .compatible = "mediatek,mt8195-mmsys",
> >
> > I think this tag lost one binding patch, it's better that this tag has
> > no this warning.
> >
>
> Sorry for the late reply I was sick.
> The warning is, because the stable branch misses commit:
> https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux.git/commit/?h=v5.18-next/soc&id=81c5a41d10b968ea89d5f44fe1e5c2fc70289209
>
> So it's not a real issue and will go away once our branches land in upstream.
> Is it OK for you to ignore the issue?
It's OK for me, but the patch would go through different maintainer's
tree and I'm not sure it's OK for all of them. So I would wait for the
necessary patch land in upstream.
Regards,
Chun-Kuang.
>
> Regards,
> Matthias
>
> > Regards,
> > Chun-Kuang.
> >
> >>
> >> Regards,
> >> Matthias
> >>
> >>> ---
> >>> include/linux/soc/mediatek/mtk-mmsys.h | 3 +--
> >>> 1 file changed, 1 insertion(+), 2 deletions(-)
> >>>
> >>> diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
> >>> index 59117d970daf..fb719fd1281c 100644
> >>> --- a/include/linux/soc/mediatek/mtk-mmsys.h
> >>> +++ b/include/linux/soc/mediatek/mtk-mmsys.h
> >>> @@ -16,8 +16,7 @@ enum mtk_ddp_comp_id {
> >>> DDP_COMPONENT_CCORR,
> >>> DDP_COMPONENT_COLOR0,
> >>> DDP_COMPONENT_COLOR1,
> >>> - DDP_COMPONENT_DITHER,
> >>> - DDP_COMPONENT_DITHER0 = DDP_COMPONENT_DITHER,
> >>> + DDP_COMPONENT_DITHER0,
> >>> DDP_COMPONENT_DITHER1,
> >>> DDP_COMPONENT_DP_INTF0,
> >>> DDP_COMPONENT_DP_INTF1,
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [PATCH v20 8/8] soc: mediatek: remove DDP_DOMPONENT_DITHER from enum
@ 2022-05-14 22:45 ` Chun-Kuang Hu
0 siblings, 0 replies; 110+ messages in thread
From: Chun-Kuang Hu @ 2022-05-14 22:45 UTC (permalink / raw)
To: Matthias Brugger
Cc: Chun-Kuang Hu, jason-jh.lin, AngeloGioacchino Del Regno, CK Hu,
Nancy Lin, Singo Chang, DTML, linux-kernel, DRI Development,
moderated list:ARM/Mediatek SoC support, Linux ARM,
Project_Global_Chrome_Upstream_Group
Hi, Matthias:
Matthias Brugger <matthias.bgg@gmail.com> 於 2022年5月13日 週五 下午3:42寫道：
>
> Hi Chun-Kuang,
>
> On 02/05/2022 00:54, Chun-Kuang Hu wrote:
> > Hi, Matthias:
> >
> > Matthias Brugger <matthias.bgg@gmail.com> 於 2022年4月22日 週五 下午8:42寫道：
> >>
> >>
> >>
> >> On 19/04/2022 11:41, jason-jh.lin wrote:
> >>> After mmsys and drm change DITHER enum to DDP_COMPONENT_DITHER0,
> >>> mmsys header can remove the useless DDP_COMPONENT_DITHER enum.
> >>>
> >>> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> >>> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> >>
> >> Acked-by: Matthias Brugger <matthias.bgg@gmail.com>
> >>
> >> Chun-Kuang, I think it would make sense to take that through your tree as it
> >> depends on the previous patches.
> >>
> >> I provide you a stable tag so that you can take it:
> >> v5.18-next-vdso0-stable-tag
> >
> > After I take this tag, I find one checkpatch warning:
> >
> > WARNING: DT compatible string "mediatek,mt8195-mmsys" appears
> > un-documented -- check ./Documentation/devicetree/bindings/
> > #670: FILE: drivers/soc/mediatek/mtk-mmsys.c:390:
> > + .compatible = "mediatek,mt8195-mmsys",
> >
> > I think this tag lost one binding patch, it's better that this tag has
> > no this warning.
> >
>
> Sorry for the late reply I was sick.
> The warning is, because the stable branch misses commit:
> https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux.git/commit/?h=v5.18-next/soc&id=81c5a41d10b968ea89d5f44fe1e5c2fc70289209
>
> So it's not a real issue and will go away once our branches land in upstream.
> Is it OK for you to ignore the issue?
It's OK for me, but the patch would go through different maintainer's
tree and I'm not sure it's OK for all of them. So I would wait for the
necessary patch land in upstream.
Regards,
Chun-Kuang.
>
> Regards,
> Matthias
>
> > Regards,
> > Chun-Kuang.
> >
> >>
> >> Regards,
> >> Matthias
> >>
> >>> ---
> >>> include/linux/soc/mediatek/mtk-mmsys.h | 3 +--
> >>> 1 file changed, 1 insertion(+), 2 deletions(-)
> >>>
> >>> diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
> >>> index 59117d970daf..fb719fd1281c 100644
> >>> --- a/include/linux/soc/mediatek/mtk-mmsys.h
> >>> +++ b/include/linux/soc/mediatek/mtk-mmsys.h
> >>> @@ -16,8 +16,7 @@ enum mtk_ddp_comp_id {
> >>> DDP_COMPONENT_CCORR,
> >>> DDP_COMPONENT_COLOR0,
> >>> DDP_COMPONENT_COLOR1,
> >>> - DDP_COMPONENT_DITHER,
> >>> - DDP_COMPONENT_DITHER0 = DDP_COMPONENT_DITHER,
> >>> + DDP_COMPONENT_DITHER0,
> >>> DDP_COMPONENT_DITHER1,
> >>> DDP_COMPONENT_DP_INTF0,
> >>> DDP_COMPONENT_DP_INTF1,
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [PATCH v20 8/8] soc: mediatek: remove DDP_DOMPONENT_DITHER from enum
@ 2022-05-14 22:45 ` Chun-Kuang Hu
0 siblings, 0 replies; 110+ messages in thread
From: Chun-Kuang Hu @ 2022-05-14 22:45 UTC (permalink / raw)
To: Matthias Brugger
Cc: Chun-Kuang Hu, DTML, jason-jh.lin, Singo Chang, linux-kernel,
DRI Development, Project_Global_Chrome_Upstream_Group, Nancy Lin,
moderated list:ARM/Mediatek SoC support, Linux ARM,
AngeloGioacchino Del Regno
Hi, Matthias:
Matthias Brugger <matthias.bgg@gmail.com> 於 2022年5月13日 週五 下午3:42寫道：
>
> Hi Chun-Kuang,
>
> On 02/05/2022 00:54, Chun-Kuang Hu wrote:
> > Hi, Matthias:
> >
> > Matthias Brugger <matthias.bgg@gmail.com> 於 2022年4月22日 週五 下午8:42寫道：
> >>
> >>
> >>
> >> On 19/04/2022 11:41, jason-jh.lin wrote:
> >>> After mmsys and drm change DITHER enum to DDP_COMPONENT_DITHER0,
> >>> mmsys header can remove the useless DDP_COMPONENT_DITHER enum.
> >>>
> >>> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> >>> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> >>
> >> Acked-by: Matthias Brugger <matthias.bgg@gmail.com>
> >>
> >> Chun-Kuang, I think it would make sense to take that through your tree as it
> >> depends on the previous patches.
> >>
> >> I provide you a stable tag so that you can take it:
> >> v5.18-next-vdso0-stable-tag
> >
> > After I take this tag, I find one checkpatch warning:
> >
> > WARNING: DT compatible string "mediatek,mt8195-mmsys" appears
> > un-documented -- check ./Documentation/devicetree/bindings/
> > #670: FILE: drivers/soc/mediatek/mtk-mmsys.c:390:
> > + .compatible = "mediatek,mt8195-mmsys",
> >
> > I think this tag lost one binding patch, it's better that this tag has
> > no this warning.
> >
>
> Sorry for the late reply I was sick.
> The warning is, because the stable branch misses commit:
> https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux.git/commit/?h=v5.18-next/soc&id=81c5a41d10b968ea89d5f44fe1e5c2fc70289209
>
> So it's not a real issue and will go away once our branches land in upstream.
> Is it OK for you to ignore the issue?
It's OK for me, but the patch would go through different maintainer's
tree and I'm not sure it's OK for all of them. So I would wait for the
necessary patch land in upstream.
Regards,
Chun-Kuang.
>
> Regards,
> Matthias
>
> > Regards,
> > Chun-Kuang.
> >
> >>
> >> Regards,
> >> Matthias
> >>
> >>> ---
> >>> include/linux/soc/mediatek/mtk-mmsys.h | 3 +--
> >>> 1 file changed, 1 insertion(+), 2 deletions(-)
> >>>
> >>> diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
> >>> index 59117d970daf..fb719fd1281c 100644
> >>> --- a/include/linux/soc/mediatek/mtk-mmsys.h
> >>> +++ b/include/linux/soc/mediatek/mtk-mmsys.h
> >>> @@ -16,8 +16,7 @@ enum mtk_ddp_comp_id {
> >>> DDP_COMPONENT_CCORR,
> >>> DDP_COMPONENT_COLOR0,
> >>> DDP_COMPONENT_COLOR1,
> >>> - DDP_COMPONENT_DITHER,
> >>> - DDP_COMPONENT_DITHER0 = DDP_COMPONENT_DITHER,
> >>> + DDP_COMPONENT_DITHER0,
> >>> DDP_COMPONENT_DITHER1,
> >>> DDP_COMPONENT_DP_INTF0,
> >>> DDP_COMPONENT_DP_INTF1,
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [PATCH v20 8/8] soc: mediatek: remove DDP_DOMPONENT_DITHER from enum
@ 2022-05-14 22:45 ` Chun-Kuang Hu
0 siblings, 0 replies; 110+ messages in thread
From: Chun-Kuang Hu @ 2022-05-14 22:45 UTC (permalink / raw)
To: Matthias Brugger
Cc: Chun-Kuang Hu, jason-jh.lin, AngeloGioacchino Del Regno, CK Hu,
Nancy Lin, Singo Chang, DTML, linux-kernel, DRI Development,
moderated list:ARM/Mediatek SoC support, Linux ARM,
Project_Global_Chrome_Upstream_Group
Hi, Matthias:
Matthias Brugger <matthias.bgg@gmail.com> 於 2022年5月13日 週五 下午3:42寫道：
>
> Hi Chun-Kuang,
>
> On 02/05/2022 00:54, Chun-Kuang Hu wrote:
> > Hi, Matthias:
> >
> > Matthias Brugger <matthias.bgg@gmail.com> 於 2022年4月22日 週五 下午8:42寫道：
> >>
> >>
> >>
> >> On 19/04/2022 11:41, jason-jh.lin wrote:
> >>> After mmsys and drm change DITHER enum to DDP_COMPONENT_DITHER0,
> >>> mmsys header can remove the useless DDP_COMPONENT_DITHER enum.
> >>>
> >>> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> >>> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> >>
> >> Acked-by: Matthias Brugger <matthias.bgg@gmail.com>
> >>
> >> Chun-Kuang, I think it would make sense to take that through your tree as it
> >> depends on the previous patches.
> >>
> >> I provide you a stable tag so that you can take it:
> >> v5.18-next-vdso0-stable-tag
> >
> > After I take this tag, I find one checkpatch warning:
> >
> > WARNING: DT compatible string "mediatek,mt8195-mmsys" appears
> > un-documented -- check ./Documentation/devicetree/bindings/
> > #670: FILE: drivers/soc/mediatek/mtk-mmsys.c:390:
> > + .compatible = "mediatek,mt8195-mmsys",
> >
> > I think this tag lost one binding patch, it's better that this tag has
> > no this warning.
> >
>
> Sorry for the late reply I was sick.
> The warning is, because the stable branch misses commit:
> https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux.git/commit/?h=v5.18-next/soc&id=81c5a41d10b968ea89d5f44fe1e5c2fc70289209
>
> So it's not a real issue and will go away once our branches land in upstream.
> Is it OK for you to ignore the issue?
It's OK for me, but the patch would go through different maintainer's
tree and I'm not sure it's OK for all of them. So I would wait for the
necessary patch land in upstream.
Regards,
Chun-Kuang.
>
> Regards,
> Matthias
>
> > Regards,
> > Chun-Kuang.
> >
> >>
> >> Regards,
> >> Matthias
> >>
> >>> ---
> >>> include/linux/soc/mediatek/mtk-mmsys.h | 3 +--
> >>> 1 file changed, 1 insertion(+), 2 deletions(-)
> >>>
> >>> diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
> >>> index 59117d970daf..fb719fd1281c 100644
> >>> --- a/include/linux/soc/mediatek/mtk-mmsys.h
> >>> +++ b/include/linux/soc/mediatek/mtk-mmsys.h
> >>> @@ -16,8 +16,7 @@ enum mtk_ddp_comp_id {
> >>> DDP_COMPONENT_CCORR,
> >>> DDP_COMPONENT_COLOR0,
> >>> DDP_COMPONENT_COLOR1,
> >>> - DDP_COMPONENT_DITHER,
> >>> - DDP_COMPONENT_DITHER0 = DDP_COMPONENT_DITHER,
> >>> + DDP_COMPONENT_DITHER0,
> >>> DDP_COMPONENT_DITHER1,
> >>> DDP_COMPONENT_DP_INTF0,
> >>> DDP_COMPONENT_DP_INTF1,
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [PATCH v20 8/8] soc: mediatek: remove DDP_DOMPONENT_DITHER from enum
2022-05-14 22:45 ` Chun-Kuang Hu
(?)
(?)
@ 2022-05-17 10:29 ` Matthias Brugger
-1 siblings, 0 replies; 110+ messages in thread
From: Matthias Brugger @ 2022-05-17 10:29 UTC (permalink / raw)
To: Chun-Kuang Hu
Cc: jason-jh.lin, AngeloGioacchino Del Regno, CK Hu, Nancy Lin,
Singo Chang, DTML, linux-kernel, DRI Development,
moderated list:ARM/Mediatek SoC support, Linux ARM,
Project_Global_Chrome_Upstream_Group
On 15/05/2022 00:45, Chun-Kuang Hu wrote:
> Hi, Matthias:
>
> Matthias Brugger <matthias.bgg@gmail.com> 於 2022年5月13日 週五 下午3:42寫道：
>>
>> Hi Chun-Kuang,
>>
>> On 02/05/2022 00:54, Chun-Kuang Hu wrote:
>>> Hi, Matthias:
>>>
>>> Matthias Brugger <matthias.bgg@gmail.com> 於 2022年4月22日 週五 下午8:42寫道：
>>>>
>>>>
>>>>
>>>> On 19/04/2022 11:41, jason-jh.lin wrote:
>>>>> After mmsys and drm change DITHER enum to DDP_COMPONENT_DITHER0,
>>>>> mmsys header can remove the useless DDP_COMPONENT_DITHER enum.
>>>>>
>>>>> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
>>>>> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
>>>>
>>>> Acked-by: Matthias Brugger <matthias.bgg@gmail.com>
>>>>
>>>> Chun-Kuang, I think it would make sense to take that through your tree as it
>>>> depends on the previous patches.
>>>>
>>>> I provide you a stable tag so that you can take it:
>>>> v5.18-next-vdso0-stable-tag
>>>
>>> After I take this tag, I find one checkpatch warning:
>>>
>>> WARNING: DT compatible string "mediatek,mt8195-mmsys" appears
>>> un-documented -- check ./Documentation/devicetree/bindings/
>>> #670: FILE: drivers/soc/mediatek/mtk-mmsys.c:390:
>>> + .compatible = "mediatek,mt8195-mmsys",
>>>
>>> I think this tag lost one binding patch, it's better that this tag has
>>> no this warning.
>>>
>>
>> Sorry for the late reply I was sick.
>> The warning is, because the stable branch misses commit:
>> https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux.git/commit/?h=v5.18-next/soc&id=81c5a41d10b968ea89d5f44fe1e5c2fc70289209
>>
>> So it's not a real issue and will go away once our branches land in upstream.
>> Is it OK for you to ignore the issue?
>
> It's OK for me, but the patch would go through different maintainer's
> tree and I'm not sure it's OK for all of them. So I would wait for the
> necessary patch land in upstream.
>
Ok makes sense. Sorry for the bad coordination from my side on this.
Regards,
Matthias
> Regards,
> Chun-Kuang.
>
>>
>> Regards,
>> Matthias
>>
>>> Regards,
>>> Chun-Kuang.
>>>
>>>>
>>>> Regards,
>>>> Matthias
>>>>
>>>>> ---
>>>>> include/linux/soc/mediatek/mtk-mmsys.h | 3 +--
>>>>> 1 file changed, 1 insertion(+), 2 deletions(-)
>>>>>
>>>>> diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
>>>>> index 59117d970daf..fb719fd1281c 100644
>>>>> --- a/include/linux/soc/mediatek/mtk-mmsys.h
>>>>> +++ b/include/linux/soc/mediatek/mtk-mmsys.h
>>>>> @@ -16,8 +16,7 @@ enum mtk_ddp_comp_id {
>>>>> DDP_COMPONENT_CCORR,
>>>>> DDP_COMPONENT_COLOR0,
>>>>> DDP_COMPONENT_COLOR1,
>>>>> - DDP_COMPONENT_DITHER,
>>>>> - DDP_COMPONENT_DITHER0 = DDP_COMPONENT_DITHER,
>>>>> + DDP_COMPONENT_DITHER0,
>>>>> DDP_COMPONENT_DITHER1,
>>>>> DDP_COMPONENT_DP_INTF0,
>>>>> DDP_COMPONENT_DP_INTF1,
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [PATCH v20 8/8] soc: mediatek: remove DDP_DOMPONENT_DITHER from enum
@ 2022-05-17 10:29 ` Matthias Brugger
0 siblings, 0 replies; 110+ messages in thread
From: Matthias Brugger @ 2022-05-17 10:29 UTC (permalink / raw)
To: Chun-Kuang Hu
Cc: jason-jh.lin, AngeloGioacchino Del Regno, CK Hu, Nancy Lin,
Singo Chang, DTML, linux-kernel, DRI Development,
moderated list:ARM/Mediatek SoC support, Linux ARM,
Project_Global_Chrome_Upstream_Group
On 15/05/2022 00:45, Chun-Kuang Hu wrote:
> Hi, Matthias:
>
> Matthias Brugger <matthias.bgg@gmail.com> 於 2022年5月13日 週五 下午3:42寫道：
>>
>> Hi Chun-Kuang,
>>
>> On 02/05/2022 00:54, Chun-Kuang Hu wrote:
>>> Hi, Matthias:
>>>
>>> Matthias Brugger <matthias.bgg@gmail.com> 於 2022年4月22日 週五 下午8:42寫道：
>>>>
>>>>
>>>>
>>>> On 19/04/2022 11:41, jason-jh.lin wrote:
>>>>> After mmsys and drm change DITHER enum to DDP_COMPONENT_DITHER0,
>>>>> mmsys header can remove the useless DDP_COMPONENT_DITHER enum.
>>>>>
>>>>> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
>>>>> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
>>>>
>>>> Acked-by: Matthias Brugger <matthias.bgg@gmail.com>
>>>>
>>>> Chun-Kuang, I think it would make sense to take that through your tree as it
>>>> depends on the previous patches.
>>>>
>>>> I provide you a stable tag so that you can take it:
>>>> v5.18-next-vdso0-stable-tag
>>>
>>> After I take this tag, I find one checkpatch warning:
>>>
>>> WARNING: DT compatible string "mediatek,mt8195-mmsys" appears
>>> un-documented -- check ./Documentation/devicetree/bindings/
>>> #670: FILE: drivers/soc/mediatek/mtk-mmsys.c:390:
>>> + .compatible = "mediatek,mt8195-mmsys",
>>>
>>> I think this tag lost one binding patch, it's better that this tag has
>>> no this warning.
>>>
>>
>> Sorry for the late reply I was sick.
>> The warning is, because the stable branch misses commit:
>> https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux.git/commit/?h=v5.18-next/soc&id=81c5a41d10b968ea89d5f44fe1e5c2fc70289209
>>
>> So it's not a real issue and will go away once our branches land in upstream.
>> Is it OK for you to ignore the issue?
>
> It's OK for me, but the patch would go through different maintainer's
> tree and I'm not sure it's OK for all of them. So I would wait for the
> necessary patch land in upstream.
>
Ok makes sense. Sorry for the bad coordination from my side on this.
Regards,
Matthias
> Regards,
> Chun-Kuang.
>
>>
>> Regards,
>> Matthias
>>
>>> Regards,
>>> Chun-Kuang.
>>>
>>>>
>>>> Regards,
>>>> Matthias
>>>>
>>>>> ---
>>>>> include/linux/soc/mediatek/mtk-mmsys.h | 3 +--
>>>>> 1 file changed, 1 insertion(+), 2 deletions(-)
>>>>>
>>>>> diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
>>>>> index 59117d970daf..fb719fd1281c 100644
>>>>> --- a/include/linux/soc/mediatek/mtk-mmsys.h
>>>>> +++ b/include/linux/soc/mediatek/mtk-mmsys.h
>>>>> @@ -16,8 +16,7 @@ enum mtk_ddp_comp_id {
>>>>> DDP_COMPONENT_CCORR,
>>>>> DDP_COMPONENT_COLOR0,
>>>>> DDP_COMPONENT_COLOR1,
>>>>> - DDP_COMPONENT_DITHER,
>>>>> - DDP_COMPONENT_DITHER0 = DDP_COMPONENT_DITHER,
>>>>> + DDP_COMPONENT_DITHER0,
>>>>> DDP_COMPONENT_DITHER1,
>>>>> DDP_COMPONENT_DP_INTF0,
>>>>> DDP_COMPONENT_DP_INTF1,
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [PATCH v20 8/8] soc: mediatek: remove DDP_DOMPONENT_DITHER from enum
@ 2022-05-17 10:29 ` Matthias Brugger
0 siblings, 0 replies; 110+ messages in thread
From: Matthias Brugger @ 2022-05-17 10:29 UTC (permalink / raw)
To: Chun-Kuang Hu
Cc: DTML, jason-jh.lin, Singo Chang, linux-kernel, DRI Development,
Project_Global_Chrome_Upstream_Group, Nancy Lin,
moderated list:ARM/Mediatek SoC support, Linux ARM,
AngeloGioacchino Del Regno
On 15/05/2022 00:45, Chun-Kuang Hu wrote:
> Hi, Matthias:
>
> Matthias Brugger <matthias.bgg@gmail.com> 於 2022年5月13日 週五 下午3:42寫道：
>>
>> Hi Chun-Kuang,
>>
>> On 02/05/2022 00:54, Chun-Kuang Hu wrote:
>>> Hi, Matthias:
>>>
>>> Matthias Brugger <matthias.bgg@gmail.com> 於 2022年4月22日 週五 下午8:42寫道：
>>>>
>>>>
>>>>
>>>> On 19/04/2022 11:41, jason-jh.lin wrote:
>>>>> After mmsys and drm change DITHER enum to DDP_COMPONENT_DITHER0,
>>>>> mmsys header can remove the useless DDP_COMPONENT_DITHER enum.
>>>>>
>>>>> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
>>>>> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
>>>>
>>>> Acked-by: Matthias Brugger <matthias.bgg@gmail.com>
>>>>
>>>> Chun-Kuang, I think it would make sense to take that through your tree as it
>>>> depends on the previous patches.
>>>>
>>>> I provide you a stable tag so that you can take it:
>>>> v5.18-next-vdso0-stable-tag
>>>
>>> After I take this tag, I find one checkpatch warning:
>>>
>>> WARNING: DT compatible string "mediatek,mt8195-mmsys" appears
>>> un-documented -- check ./Documentation/devicetree/bindings/
>>> #670: FILE: drivers/soc/mediatek/mtk-mmsys.c:390:
>>> + .compatible = "mediatek,mt8195-mmsys",
>>>
>>> I think this tag lost one binding patch, it's better that this tag has
>>> no this warning.
>>>
>>
>> Sorry for the late reply I was sick.
>> The warning is, because the stable branch misses commit:
>> https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux.git/commit/?h=v5.18-next/soc&id=81c5a41d10b968ea89d5f44fe1e5c2fc70289209
>>
>> So it's not a real issue and will go away once our branches land in upstream.
>> Is it OK for you to ignore the issue?
>
> It's OK for me, but the patch would go through different maintainer's
> tree and I'm not sure it's OK for all of them. So I would wait for the
> necessary patch land in upstream.
>
Ok makes sense. Sorry for the bad coordination from my side on this.
Regards,
Matthias
> Regards,
> Chun-Kuang.
>
>>
>> Regards,
>> Matthias
>>
>>> Regards,
>>> Chun-Kuang.
>>>
>>>>
>>>> Regards,
>>>> Matthias
>>>>
>>>>> ---
>>>>> include/linux/soc/mediatek/mtk-mmsys.h | 3 +--
>>>>> 1 file changed, 1 insertion(+), 2 deletions(-)
>>>>>
>>>>> diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
>>>>> index 59117d970daf..fb719fd1281c 100644
>>>>> --- a/include/linux/soc/mediatek/mtk-mmsys.h
>>>>> +++ b/include/linux/soc/mediatek/mtk-mmsys.h
>>>>> @@ -16,8 +16,7 @@ enum mtk_ddp_comp_id {
>>>>> DDP_COMPONENT_CCORR,
>>>>> DDP_COMPONENT_COLOR0,
>>>>> DDP_COMPONENT_COLOR1,
>>>>> - DDP_COMPONENT_DITHER,
>>>>> - DDP_COMPONENT_DITHER0 = DDP_COMPONENT_DITHER,
>>>>> + DDP_COMPONENT_DITHER0,
>>>>> DDP_COMPONENT_DITHER1,
>>>>> DDP_COMPONENT_DP_INTF0,
>>>>> DDP_COMPONENT_DP_INTF1,
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [PATCH v20 8/8] soc: mediatek: remove DDP_DOMPONENT_DITHER from enum
@ 2022-05-17 10:29 ` Matthias Brugger
0 siblings, 0 replies; 110+ messages in thread
From: Matthias Brugger @ 2022-05-17 10:29 UTC (permalink / raw)
To: Chun-Kuang Hu
Cc: jason-jh.lin, AngeloGioacchino Del Regno, CK Hu, Nancy Lin,
Singo Chang, DTML, linux-kernel, DRI Development,
moderated list:ARM/Mediatek SoC support, Linux ARM,
Project_Global_Chrome_Upstream_Group
On 15/05/2022 00:45, Chun-Kuang Hu wrote:
> Hi, Matthias:
>
> Matthias Brugger <matthias.bgg@gmail.com> 於 2022年5月13日 週五 下午3:42寫道：
>>
>> Hi Chun-Kuang,
>>
>> On 02/05/2022 00:54, Chun-Kuang Hu wrote:
>>> Hi, Matthias:
>>>
>>> Matthias Brugger <matthias.bgg@gmail.com> 於 2022年4月22日 週五 下午8:42寫道：
>>>>
>>>>
>>>>
>>>> On 19/04/2022 11:41, jason-jh.lin wrote:
>>>>> After mmsys and drm change DITHER enum to DDP_COMPONENT_DITHER0,
>>>>> mmsys header can remove the useless DDP_COMPONENT_DITHER enum.
>>>>>
>>>>> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
>>>>> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
>>>>
>>>> Acked-by: Matthias Brugger <matthias.bgg@gmail.com>
>>>>
>>>> Chun-Kuang, I think it would make sense to take that through your tree as it
>>>> depends on the previous patches.
>>>>
>>>> I provide you a stable tag so that you can take it:
>>>> v5.18-next-vdso0-stable-tag
>>>
>>> After I take this tag, I find one checkpatch warning:
>>>
>>> WARNING: DT compatible string "mediatek,mt8195-mmsys" appears
>>> un-documented -- check ./Documentation/devicetree/bindings/
>>> #670: FILE: drivers/soc/mediatek/mtk-mmsys.c:390:
>>> + .compatible = "mediatek,mt8195-mmsys",
>>>
>>> I think this tag lost one binding patch, it's better that this tag has
>>> no this warning.
>>>
>>
>> Sorry for the late reply I was sick.
>> The warning is, because the stable branch misses commit:
>> https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux.git/commit/?h=v5.18-next/soc&id=81c5a41d10b968ea89d5f44fe1e5c2fc70289209
>>
>> So it's not a real issue and will go away once our branches land in upstream.
>> Is it OK for you to ignore the issue?
>
> It's OK for me, but the patch would go through different maintainer's
> tree and I'm not sure it's OK for all of them. So I would wait for the
> necessary patch land in upstream.
>
Ok makes sense. Sorry for the bad coordination from my side on this.
Regards,
Matthias
> Regards,
> Chun-Kuang.
>
>>
>> Regards,
>> Matthias
>>
>>> Regards,
>>> Chun-Kuang.
>>>
>>>>
>>>> Regards,
>>>> Matthias
>>>>
>>>>> ---
>>>>> include/linux/soc/mediatek/mtk-mmsys.h | 3 +--
>>>>> 1 file changed, 1 insertion(+), 2 deletions(-)
>>>>>
>>>>> diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
>>>>> index 59117d970daf..fb719fd1281c 100644
>>>>> --- a/include/linux/soc/mediatek/mtk-mmsys.h
>>>>> +++ b/include/linux/soc/mediatek/mtk-mmsys.h
>>>>> @@ -16,8 +16,7 @@ enum mtk_ddp_comp_id {
>>>>> DDP_COMPONENT_CCORR,
>>>>> DDP_COMPONENT_COLOR0,
>>>>> DDP_COMPONENT_COLOR1,
>>>>> - DDP_COMPONENT_DITHER,
>>>>> - DDP_COMPONENT_DITHER0 = DDP_COMPONENT_DITHER,
>>>>> + DDP_COMPONENT_DITHER0,
>>>>> DDP_COMPONENT_DITHER1,
>>>>> DDP_COMPONENT_DP_INTF0,
>>>>> DDP_COMPONENT_DP_INTF1,
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [PATCH v20 0/8] Add Mediatek Soc DRM (vdosys0) support for mt8195
2022-04-19 9:41 ` jason-jh.lin
(?)
(?)
@ 2022-05-25 9:50 ` AngeloGioacchino Del Regno
-1 siblings, 0 replies; 110+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-05-25 9:50 UTC (permalink / raw)
To: jason-jh.lin, Matthias Brugger, Chun-Kuang Hu
Cc: devicetree, jason-jhlin, Singo Chang, linux-kernel, dri-devel,
Project_Global_Chrome_Upstream_Group, Nancy Lin, linux-mediatek,
linux-arm-kernel
Il 19/04/22 11:41, jason-jh.lin ha scritto:
> From: jason-jhlin <jason-jh.lin@mediatek.corp-partner.google.com>
>
Hello Jason,
this series does not apply cleanly anymore on next-20220525, can you please
rebase and resend?
I hope that with a bit of coordination, we can get the entire display stack
finally upstreamed in v5.19... it's been quite a while... :-)
Cheers,
Angelo
> Change in v20:
> - split binding patch to another series 'MediaTek MT8195 display binding':
> https://patchwork.ozlabs.org/project/devicetree-bindings/list/?series=295669
> - fix io_start type from u32 to resource_size_t
> - fix some commit message for DITHER enum
>
> Change in v19:
> - fix checking condition for the return vaule of platform resource
> - drm/mediatek fix build waning for [-Wunused-const-variable]
>
> Change in v18:
> - change get driver data by io_start and wrap mmsys driver data into
> mmsys match data structure to support identifying multi mmsys driver
> data with the same compatible name
> - change DDP_COMPONENT_DITHER to DDP_CONPONENT_DITHER0
>
> Change in v17:
> - change compatible name from 2 vdosys to 1 mmsys
> - add get driver data by clk name function to get corresponding
> driver data for mt8195 vdosys0
> - add all routing table setting for mt8195 vdosys0
> - remove useless mutex define
>
> Change in v16:
> - rebase on linu-next tag: 'next-20220303'
> - rebase on series: 'Fix MediaTek display dt-bindings issues'
>
> Change in v15:
> - remove mt8195-mmsys.h comment for mux settings
> - define the mask macro to replace using value as mask
> to fix zero mask problem
> - add EOF setting comment for MUTEX sof register
>
> Change in v14:
> - rebase on mediatek-drm-next-5.17
> - rebase on "Add mmsys and mutex support for MDP" series
> - rebase on "media: mediatek: support mdp3 on mt8183 platform" series
>
> Change in v13:
> - remove dts patch
> - rebase on kernel-5.16-rc1
> - rebase on mediatek-drm-next
>
> Change in v12:
> - add clock-names property to merge yaml
> - using BIT(nr) macro to define the settings of mmsys routing table
> - fix clk_get and clk_prepare_enable error handling issue
>
> Change in v11:
> - rebase on kernel-5.15-rc1
> - change mbox label to gce0 for dts node of vdosys0
> - change ovl compatibale to mt8192 to set smi_id_en=true in driver data
> - move common module from display folder to common folder,
> such as AAL, COCLOR, CCORR and MUTEX
>
> Change in v10:
> - rebase on "drm/mediatek: add support for mediatek SOC MT8192" series
> - rebase on "soc: mediatek: mmsys: add mt8192 mmsys support" series
> - fix some typo and "mediatek" start with capital in every dt-bindings
> - move mutex yaml from dfisplay folder to soc folder
> - separate merge additional propoerties to an individual dt-bindings patch
>
> Change in v9:
> - separate power and gce properties of mmsys into another dt-binding patch
> - rebase on "Separate aal module" series
> - keep mtk_ddp_clk_enable/disable in the same place
> - change mtk_dsc_start config register to mtk_drm_ddp_write_mask
> - remove the 0 setting of merge fifo config function
> - add CCORR driver data for mt8195
>
> Change in v8:
> - add DP_INTF0 mux into mmsys routing table
> - add DP_INTF0 mutex mod and enum into add/remove comp function
> - remove bypass DSC enum in mtk_ddp_comp_init
>
> Change in v7:
> - add dt=binding of mmsys and disp path into this series
> - separate th modidfication of alphabetic order, remove unused define and
> rename the define of register offset to individual patch
> - add comment for MERGE ultra and preultra setting
>
> Change in v6:
> - adjust alphabetic order for mediatek-drm
> - move the patch that add mt8195 support for mediatek-drm as
> the lastest patch
> - add MERGE define for const varriable
>
> Change in v5:
> - add power-domain property into vdosys0 and vdosys1 dts node.
> - add MT8195 prifix and remove unused VDO1 define in mt8195-mmsys.h
>
> Change in v4:
> - extract dt-binding patches to another patch series
> - squash DSC module into mtk_drm_ddp_comp.c
> - add coment and simplify MERGE config function
>
> Change in v3:
> - change mmsys and display dt-bindings document from txt to yaml
> - add MERGE additional description in display dt-bindings document
> - fix mboxes-cells number of vdosys0 node in dts
> - drop mutex eof convert define
> - remove pm_runtime apis in DSC and MERGE
> - change DSC and MERGE enum to alphabetic order
>
> Change in v2:
> - add DSC yaml file
> - add mt8195 drm driver porting parts in to one patch
> - remove useless define, variable, structure member and function
> - simplify DSC and MERGE file and switch threre order
>
> jason-jh.lin (8):
> soc: mediatek: add mtk-mmsys support for mt8195 vdosys0
> soc: mediatek: add mtk-mutex support for mt8195 vdosys0
> drm/mediatek: add DSC support for mediatek-drm
> drm/mediatek: add MERGE support for mediatek-drm
> drm/mediatek: add mediatek-drm of vdosys0 support for mt8195
> soc: mediatek: add DDP_DOMPONENT_DITHER0 enum for mt8195 vdosys0
> drm/mediatek: add suffix 0 to DDP_COMPONENT_DITHER for mt8195 vdosys0
> soc: mediatek: remove DDP_DOMPONENT_DITHER from enum
>
> drivers/gpu/drm/mediatek/Makefile | 1 +
> drivers/gpu/drm/mediatek/mtk_disp_drv.h | 8 +
> drivers/gpu/drm/mediatek/mtk_disp_merge.c | 246 +++++++++++++
> drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 6 +
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 65 +++-
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 2 +
> drivers/gpu/drm/mediatek/mtk_drm_drv.c | 151 +++++++-
> drivers/gpu/drm/mediatek/mtk_drm_drv.h | 7 +
> drivers/soc/mediatek/mt8167-mmsys.h | 2 +-
> drivers/soc/mediatek/mt8183-mmsys.h | 2 +-
> drivers/soc/mediatek/mt8186-mmsys.h | 4 +-
> drivers/soc/mediatek/mt8192-mmsys.h | 4 +-
> drivers/soc/mediatek/mt8195-mmsys.h | 370 ++++++++++++++++++++
> drivers/soc/mediatek/mt8365-mmsys.h | 4 +-
> drivers/soc/mediatek/mtk-mmsys.c | 152 +++++++-
> drivers/soc/mediatek/mtk-mmsys.h | 6 +
> drivers/soc/mediatek/mtk-mutex.c | 95 ++++-
> include/linux/soc/mediatek/mtk-mmsys.h | 13 +-
> 18 files changed, 1098 insertions(+), 40 deletions(-)
> create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_merge.c
> create mode 100644 drivers/soc/mediatek/mt8195-mmsys.h
>
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [PATCH v20 0/8] Add Mediatek Soc DRM (vdosys0) support for mt8195
@ 2022-05-25 9:50 ` AngeloGioacchino Del Regno
0 siblings, 0 replies; 110+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-05-25 9:50 UTC (permalink / raw)
To: jason-jh.lin, Matthias Brugger, Chun-Kuang Hu
Cc: CK Hu, Nancy Lin, Singo Chang, devicetree, linux-kernel,
dri-devel, linux-mediatek, linux-arm-kernel,
Project_Global_Chrome_Upstream_Group, jason-jhlin
Il 19/04/22 11:41, jason-jh.lin ha scritto:
> From: jason-jhlin <jason-jh.lin@mediatek.corp-partner.google.com>
>
Hello Jason,
this series does not apply cleanly anymore on next-20220525, can you please
rebase and resend?
I hope that with a bit of coordination, we can get the entire display stack
finally upstreamed in v5.19... it's been quite a while... :-)
Cheers,
Angelo
> Change in v20:
> - split binding patch to another series 'MediaTek MT8195 display binding':
> https://patchwork.ozlabs.org/project/devicetree-bindings/list/?series=295669
> - fix io_start type from u32 to resource_size_t
> - fix some commit message for DITHER enum
>
> Change in v19:
> - fix checking condition for the return vaule of platform resource
> - drm/mediatek fix build waning for [-Wunused-const-variable]
>
> Change in v18:
> - change get driver data by io_start and wrap mmsys driver data into
> mmsys match data structure to support identifying multi mmsys driver
> data with the same compatible name
> - change DDP_COMPONENT_DITHER to DDP_CONPONENT_DITHER0
>
> Change in v17:
> - change compatible name from 2 vdosys to 1 mmsys
> - add get driver data by clk name function to get corresponding
> driver data for mt8195 vdosys0
> - add all routing table setting for mt8195 vdosys0
> - remove useless mutex define
>
> Change in v16:
> - rebase on linu-next tag: 'next-20220303'
> - rebase on series: 'Fix MediaTek display dt-bindings issues'
>
> Change in v15:
> - remove mt8195-mmsys.h comment for mux settings
> - define the mask macro to replace using value as mask
> to fix zero mask problem
> - add EOF setting comment for MUTEX sof register
>
> Change in v14:
> - rebase on mediatek-drm-next-5.17
> - rebase on "Add mmsys and mutex support for MDP" series
> - rebase on "media: mediatek: support mdp3 on mt8183 platform" series
>
> Change in v13:
> - remove dts patch
> - rebase on kernel-5.16-rc1
> - rebase on mediatek-drm-next
>
> Change in v12:
> - add clock-names property to merge yaml
> - using BIT(nr) macro to define the settings of mmsys routing table
> - fix clk_get and clk_prepare_enable error handling issue
>
> Change in v11:
> - rebase on kernel-5.15-rc1
> - change mbox label to gce0 for dts node of vdosys0
> - change ovl compatibale to mt8192 to set smi_id_en=true in driver data
> - move common module from display folder to common folder,
> such as AAL, COCLOR, CCORR and MUTEX
>
> Change in v10:
> - rebase on "drm/mediatek: add support for mediatek SOC MT8192" series
> - rebase on "soc: mediatek: mmsys: add mt8192 mmsys support" series
> - fix some typo and "mediatek" start with capital in every dt-bindings
> - move mutex yaml from dfisplay folder to soc folder
> - separate merge additional propoerties to an individual dt-bindings patch
>
> Change in v9:
> - separate power and gce properties of mmsys into another dt-binding patch
> - rebase on "Separate aal module" series
> - keep mtk_ddp_clk_enable/disable in the same place
> - change mtk_dsc_start config register to mtk_drm_ddp_write_mask
> - remove the 0 setting of merge fifo config function
> - add CCORR driver data for mt8195
>
> Change in v8:
> - add DP_INTF0 mux into mmsys routing table
> - add DP_INTF0 mutex mod and enum into add/remove comp function
> - remove bypass DSC enum in mtk_ddp_comp_init
>
> Change in v7:
> - add dt=binding of mmsys and disp path into this series
> - separate th modidfication of alphabetic order, remove unused define and
> rename the define of register offset to individual patch
> - add comment for MERGE ultra and preultra setting
>
> Change in v6:
> - adjust alphabetic order for mediatek-drm
> - move the patch that add mt8195 support for mediatek-drm as
> the lastest patch
> - add MERGE define for const varriable
>
> Change in v5:
> - add power-domain property into vdosys0 and vdosys1 dts node.
> - add MT8195 prifix and remove unused VDO1 define in mt8195-mmsys.h
>
> Change in v4:
> - extract dt-binding patches to another patch series
> - squash DSC module into mtk_drm_ddp_comp.c
> - add coment and simplify MERGE config function
>
> Change in v3:
> - change mmsys and display dt-bindings document from txt to yaml
> - add MERGE additional description in display dt-bindings document
> - fix mboxes-cells number of vdosys0 node in dts
> - drop mutex eof convert define
> - remove pm_runtime apis in DSC and MERGE
> - change DSC and MERGE enum to alphabetic order
>
> Change in v2:
> - add DSC yaml file
> - add mt8195 drm driver porting parts in to one patch
> - remove useless define, variable, structure member and function
> - simplify DSC and MERGE file and switch threre order
>
> jason-jh.lin (8):
> soc: mediatek: add mtk-mmsys support for mt8195 vdosys0
> soc: mediatek: add mtk-mutex support for mt8195 vdosys0
> drm/mediatek: add DSC support for mediatek-drm
> drm/mediatek: add MERGE support for mediatek-drm
> drm/mediatek: add mediatek-drm of vdosys0 support for mt8195
> soc: mediatek: add DDP_DOMPONENT_DITHER0 enum for mt8195 vdosys0
> drm/mediatek: add suffix 0 to DDP_COMPONENT_DITHER for mt8195 vdosys0
> soc: mediatek: remove DDP_DOMPONENT_DITHER from enum
>
> drivers/gpu/drm/mediatek/Makefile | 1 +
> drivers/gpu/drm/mediatek/mtk_disp_drv.h | 8 +
> drivers/gpu/drm/mediatek/mtk_disp_merge.c | 246 +++++++++++++
> drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 6 +
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 65 +++-
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 2 +
> drivers/gpu/drm/mediatek/mtk_drm_drv.c | 151 +++++++-
> drivers/gpu/drm/mediatek/mtk_drm_drv.h | 7 +
> drivers/soc/mediatek/mt8167-mmsys.h | 2 +-
> drivers/soc/mediatek/mt8183-mmsys.h | 2 +-
> drivers/soc/mediatek/mt8186-mmsys.h | 4 +-
> drivers/soc/mediatek/mt8192-mmsys.h | 4 +-
> drivers/soc/mediatek/mt8195-mmsys.h | 370 ++++++++++++++++++++
> drivers/soc/mediatek/mt8365-mmsys.h | 4 +-
> drivers/soc/mediatek/mtk-mmsys.c | 152 +++++++-
> drivers/soc/mediatek/mtk-mmsys.h | 6 +
> drivers/soc/mediatek/mtk-mutex.c | 95 ++++-
> include/linux/soc/mediatek/mtk-mmsys.h | 13 +-
> 18 files changed, 1098 insertions(+), 40 deletions(-)
> create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_merge.c
> create mode 100644 drivers/soc/mediatek/mt8195-mmsys.h
>
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [PATCH v20 0/8] Add Mediatek Soc DRM (vdosys0) support for mt8195
@ 2022-05-25 9:50 ` AngeloGioacchino Del Regno
0 siblings, 0 replies; 110+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-05-25 9:50 UTC (permalink / raw)
To: jason-jh.lin, Matthias Brugger, Chun-Kuang Hu
Cc: CK Hu, Nancy Lin, Singo Chang, devicetree, linux-kernel,
dri-devel, linux-mediatek, linux-arm-kernel,
Project_Global_Chrome_Upstream_Group, jason-jhlin
Il 19/04/22 11:41, jason-jh.lin ha scritto:
> From: jason-jhlin <jason-jh.lin@mediatek.corp-partner.google.com>
>
Hello Jason,
this series does not apply cleanly anymore on next-20220525, can you please
rebase and resend?
I hope that with a bit of coordination, we can get the entire display stack
finally upstreamed in v5.19... it's been quite a while... :-)
Cheers,
Angelo
> Change in v20:
> - split binding patch to another series 'MediaTek MT8195 display binding':
> https://patchwork.ozlabs.org/project/devicetree-bindings/list/?series=295669
> - fix io_start type from u32 to resource_size_t
> - fix some commit message for DITHER enum
>
> Change in v19:
> - fix checking condition for the return vaule of platform resource
> - drm/mediatek fix build waning for [-Wunused-const-variable]
>
> Change in v18:
> - change get driver data by io_start and wrap mmsys driver data into
> mmsys match data structure to support identifying multi mmsys driver
> data with the same compatible name
> - change DDP_COMPONENT_DITHER to DDP_CONPONENT_DITHER0
>
> Change in v17:
> - change compatible name from 2 vdosys to 1 mmsys
> - add get driver data by clk name function to get corresponding
> driver data for mt8195 vdosys0
> - add all routing table setting for mt8195 vdosys0
> - remove useless mutex define
>
> Change in v16:
> - rebase on linu-next tag: 'next-20220303'
> - rebase on series: 'Fix MediaTek display dt-bindings issues'
>
> Change in v15:
> - remove mt8195-mmsys.h comment for mux settings
> - define the mask macro to replace using value as mask
> to fix zero mask problem
> - add EOF setting comment for MUTEX sof register
>
> Change in v14:
> - rebase on mediatek-drm-next-5.17
> - rebase on "Add mmsys and mutex support for MDP" series
> - rebase on "media: mediatek: support mdp3 on mt8183 platform" series
>
> Change in v13:
> - remove dts patch
> - rebase on kernel-5.16-rc1
> - rebase on mediatek-drm-next
>
> Change in v12:
> - add clock-names property to merge yaml
> - using BIT(nr) macro to define the settings of mmsys routing table
> - fix clk_get and clk_prepare_enable error handling issue
>
> Change in v11:
> - rebase on kernel-5.15-rc1
> - change mbox label to gce0 for dts node of vdosys0
> - change ovl compatibale to mt8192 to set smi_id_en=true in driver data
> - move common module from display folder to common folder,
> such as AAL, COCLOR, CCORR and MUTEX
>
> Change in v10:
> - rebase on "drm/mediatek: add support for mediatek SOC MT8192" series
> - rebase on "soc: mediatek: mmsys: add mt8192 mmsys support" series
> - fix some typo and "mediatek" start with capital in every dt-bindings
> - move mutex yaml from dfisplay folder to soc folder
> - separate merge additional propoerties to an individual dt-bindings patch
>
> Change in v9:
> - separate power and gce properties of mmsys into another dt-binding patch
> - rebase on "Separate aal module" series
> - keep mtk_ddp_clk_enable/disable in the same place
> - change mtk_dsc_start config register to mtk_drm_ddp_write_mask
> - remove the 0 setting of merge fifo config function
> - add CCORR driver data for mt8195
>
> Change in v8:
> - add DP_INTF0 mux into mmsys routing table
> - add DP_INTF0 mutex mod and enum into add/remove comp function
> - remove bypass DSC enum in mtk_ddp_comp_init
>
> Change in v7:
> - add dt=binding of mmsys and disp path into this series
> - separate th modidfication of alphabetic order, remove unused define and
> rename the define of register offset to individual patch
> - add comment for MERGE ultra and preultra setting
>
> Change in v6:
> - adjust alphabetic order for mediatek-drm
> - move the patch that add mt8195 support for mediatek-drm as
> the lastest patch
> - add MERGE define for const varriable
>
> Change in v5:
> - add power-domain property into vdosys0 and vdosys1 dts node.
> - add MT8195 prifix and remove unused VDO1 define in mt8195-mmsys.h
>
> Change in v4:
> - extract dt-binding patches to another patch series
> - squash DSC module into mtk_drm_ddp_comp.c
> - add coment and simplify MERGE config function
>
> Change in v3:
> - change mmsys and display dt-bindings document from txt to yaml
> - add MERGE additional description in display dt-bindings document
> - fix mboxes-cells number of vdosys0 node in dts
> - drop mutex eof convert define
> - remove pm_runtime apis in DSC and MERGE
> - change DSC and MERGE enum to alphabetic order
>
> Change in v2:
> - add DSC yaml file
> - add mt8195 drm driver porting parts in to one patch
> - remove useless define, variable, structure member and function
> - simplify DSC and MERGE file and switch threre order
>
> jason-jh.lin (8):
> soc: mediatek: add mtk-mmsys support for mt8195 vdosys0
> soc: mediatek: add mtk-mutex support for mt8195 vdosys0
> drm/mediatek: add DSC support for mediatek-drm
> drm/mediatek: add MERGE support for mediatek-drm
> drm/mediatek: add mediatek-drm of vdosys0 support for mt8195
> soc: mediatek: add DDP_DOMPONENT_DITHER0 enum for mt8195 vdosys0
> drm/mediatek: add suffix 0 to DDP_COMPONENT_DITHER for mt8195 vdosys0
> soc: mediatek: remove DDP_DOMPONENT_DITHER from enum
>
> drivers/gpu/drm/mediatek/Makefile | 1 +
> drivers/gpu/drm/mediatek/mtk_disp_drv.h | 8 +
> drivers/gpu/drm/mediatek/mtk_disp_merge.c | 246 +++++++++++++
> drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 6 +
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 65 +++-
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 2 +
> drivers/gpu/drm/mediatek/mtk_drm_drv.c | 151 +++++++-
> drivers/gpu/drm/mediatek/mtk_drm_drv.h | 7 +
> drivers/soc/mediatek/mt8167-mmsys.h | 2 +-
> drivers/soc/mediatek/mt8183-mmsys.h | 2 +-
> drivers/soc/mediatek/mt8186-mmsys.h | 4 +-
> drivers/soc/mediatek/mt8192-mmsys.h | 4 +-
> drivers/soc/mediatek/mt8195-mmsys.h | 370 ++++++++++++++++++++
> drivers/soc/mediatek/mt8365-mmsys.h | 4 +-
> drivers/soc/mediatek/mtk-mmsys.c | 152 +++++++-
> drivers/soc/mediatek/mtk-mmsys.h | 6 +
> drivers/soc/mediatek/mtk-mutex.c | 95 ++++-
> include/linux/soc/mediatek/mtk-mmsys.h | 13 +-
> 18 files changed, 1098 insertions(+), 40 deletions(-)
> create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_merge.c
> create mode 100644 drivers/soc/mediatek/mt8195-mmsys.h
>
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [PATCH v20 0/8] Add Mediatek Soc DRM (vdosys0) support for mt8195
@ 2022-05-25 9:50 ` AngeloGioacchino Del Regno
0 siblings, 0 replies; 110+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-05-25 9:50 UTC (permalink / raw)
To: jason-jh.lin, Matthias Brugger, Chun-Kuang Hu
Cc: CK Hu, Nancy Lin, Singo Chang, devicetree, linux-kernel,
dri-devel, linux-mediatek, linux-arm-kernel,
Project_Global_Chrome_Upstream_Group, jason-jhlin
Il 19/04/22 11:41, jason-jh.lin ha scritto:
> From: jason-jhlin <jason-jh.lin@mediatek.corp-partner.google.com>
>
Hello Jason,
this series does not apply cleanly anymore on next-20220525, can you please
rebase and resend?
I hope that with a bit of coordination, we can get the entire display stack
finally upstreamed in v5.19... it's been quite a while... :-)
Cheers,
Angelo
> Change in v20:
> - split binding patch to another series 'MediaTek MT8195 display binding':
> https://patchwork.ozlabs.org/project/devicetree-bindings/list/?series=295669
> - fix io_start type from u32 to resource_size_t
> - fix some commit message for DITHER enum
>
> Change in v19:
> - fix checking condition for the return vaule of platform resource
> - drm/mediatek fix build waning for [-Wunused-const-variable]
>
> Change in v18:
> - change get driver data by io_start and wrap mmsys driver data into
> mmsys match data structure to support identifying multi mmsys driver
> data with the same compatible name
> - change DDP_COMPONENT_DITHER to DDP_CONPONENT_DITHER0
>
> Change in v17:
> - change compatible name from 2 vdosys to 1 mmsys
> - add get driver data by clk name function to get corresponding
> driver data for mt8195 vdosys0
> - add all routing table setting for mt8195 vdosys0
> - remove useless mutex define
>
> Change in v16:
> - rebase on linu-next tag: 'next-20220303'
> - rebase on series: 'Fix MediaTek display dt-bindings issues'
>
> Change in v15:
> - remove mt8195-mmsys.h comment for mux settings
> - define the mask macro to replace using value as mask
> to fix zero mask problem
> - add EOF setting comment for MUTEX sof register
>
> Change in v14:
> - rebase on mediatek-drm-next-5.17
> - rebase on "Add mmsys and mutex support for MDP" series
> - rebase on "media: mediatek: support mdp3 on mt8183 platform" series
>
> Change in v13:
> - remove dts patch
> - rebase on kernel-5.16-rc1
> - rebase on mediatek-drm-next
>
> Change in v12:
> - add clock-names property to merge yaml
> - using BIT(nr) macro to define the settings of mmsys routing table
> - fix clk_get and clk_prepare_enable error handling issue
>
> Change in v11:
> - rebase on kernel-5.15-rc1
> - change mbox label to gce0 for dts node of vdosys0
> - change ovl compatibale to mt8192 to set smi_id_en=true in driver data
> - move common module from display folder to common folder,
> such as AAL, COCLOR, CCORR and MUTEX
>
> Change in v10:
> - rebase on "drm/mediatek: add support for mediatek SOC MT8192" series
> - rebase on "soc: mediatek: mmsys: add mt8192 mmsys support" series
> - fix some typo and "mediatek" start with capital in every dt-bindings
> - move mutex yaml from dfisplay folder to soc folder
> - separate merge additional propoerties to an individual dt-bindings patch
>
> Change in v9:
> - separate power and gce properties of mmsys into another dt-binding patch
> - rebase on "Separate aal module" series
> - keep mtk_ddp_clk_enable/disable in the same place
> - change mtk_dsc_start config register to mtk_drm_ddp_write_mask
> - remove the 0 setting of merge fifo config function
> - add CCORR driver data for mt8195
>
> Change in v8:
> - add DP_INTF0 mux into mmsys routing table
> - add DP_INTF0 mutex mod and enum into add/remove comp function
> - remove bypass DSC enum in mtk_ddp_comp_init
>
> Change in v7:
> - add dt=binding of mmsys and disp path into this series
> - separate th modidfication of alphabetic order, remove unused define and
> rename the define of register offset to individual patch
> - add comment for MERGE ultra and preultra setting
>
> Change in v6:
> - adjust alphabetic order for mediatek-drm
> - move the patch that add mt8195 support for mediatek-drm as
> the lastest patch
> - add MERGE define for const varriable
>
> Change in v5:
> - add power-domain property into vdosys0 and vdosys1 dts node.
> - add MT8195 prifix and remove unused VDO1 define in mt8195-mmsys.h
>
> Change in v4:
> - extract dt-binding patches to another patch series
> - squash DSC module into mtk_drm_ddp_comp.c
> - add coment and simplify MERGE config function
>
> Change in v3:
> - change mmsys and display dt-bindings document from txt to yaml
> - add MERGE additional description in display dt-bindings document
> - fix mboxes-cells number of vdosys0 node in dts
> - drop mutex eof convert define
> - remove pm_runtime apis in DSC and MERGE
> - change DSC and MERGE enum to alphabetic order
>
> Change in v2:
> - add DSC yaml file
> - add mt8195 drm driver porting parts in to one patch
> - remove useless define, variable, structure member and function
> - simplify DSC and MERGE file and switch threre order
>
> jason-jh.lin (8):
> soc: mediatek: add mtk-mmsys support for mt8195 vdosys0
> soc: mediatek: add mtk-mutex support for mt8195 vdosys0
> drm/mediatek: add DSC support for mediatek-drm
> drm/mediatek: add MERGE support for mediatek-drm
> drm/mediatek: add mediatek-drm of vdosys0 support for mt8195
> soc: mediatek: add DDP_DOMPONENT_DITHER0 enum for mt8195 vdosys0
> drm/mediatek: add suffix 0 to DDP_COMPONENT_DITHER for mt8195 vdosys0
> soc: mediatek: remove DDP_DOMPONENT_DITHER from enum
>
> drivers/gpu/drm/mediatek/Makefile | 1 +
> drivers/gpu/drm/mediatek/mtk_disp_drv.h | 8 +
> drivers/gpu/drm/mediatek/mtk_disp_merge.c | 246 +++++++++++++
> drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 6 +
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 65 +++-
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 2 +
> drivers/gpu/drm/mediatek/mtk_drm_drv.c | 151 +++++++-
> drivers/gpu/drm/mediatek/mtk_drm_drv.h | 7 +
> drivers/soc/mediatek/mt8167-mmsys.h | 2 +-
> drivers/soc/mediatek/mt8183-mmsys.h | 2 +-
> drivers/soc/mediatek/mt8186-mmsys.h | 4 +-
> drivers/soc/mediatek/mt8192-mmsys.h | 4 +-
> drivers/soc/mediatek/mt8195-mmsys.h | 370 ++++++++++++++++++++
> drivers/soc/mediatek/mt8365-mmsys.h | 4 +-
> drivers/soc/mediatek/mtk-mmsys.c | 152 +++++++-
> drivers/soc/mediatek/mtk-mmsys.h | 6 +
> drivers/soc/mediatek/mtk-mutex.c | 95 ++++-
> include/linux/soc/mediatek/mtk-mmsys.h | 13 +-
> 18 files changed, 1098 insertions(+), 40 deletions(-)
> create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_merge.c
> create mode 100644 drivers/soc/mediatek/mt8195-mmsys.h
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [PATCH v20 0/8] Add Mediatek Soc DRM (vdosys0) support for mt8195
2022-05-25 9:50 ` AngeloGioacchino Del Regno
(?)
(?)
@ 2022-05-25 13:18 ` Jason-JH Lin
-1 siblings, 0 replies; 110+ messages in thread
From: Jason-JH Lin @ 2022-05-25 13:18 UTC (permalink / raw)
To: AngeloGioacchino Del Regno, Matthias Brugger, Chun-Kuang Hu
Cc: devicetree, jason-jhlin, Singo Chang, linux-kernel, dri-devel,
Project_Global_Chrome_Upstream_Group, Nancy Lin, linux-mediatek,
linux-arm-kernel
Hello Angelo,
OK, I'll rebase on next-20220525 and resend soon.
Regards,
Jason-JH.Lin
On Wed, 2022-05-25 at 11:50 +0200, AngeloGioacchino Del Regno wrote:
> Il 19/04/22 11:41, jason-jh.lin ha scritto:
> > From: jason-jhlin <jason-jh.lin@mediatek.corp-partner.google.com>
> >
>
> Hello Jason,
>
> this series does not apply cleanly anymore on next-20220525, can you
> please
> rebase and resend?
>
> I hope that with a bit of coordination, we can get the entire display
> stack
> finally upstreamed in v5.19... it's been quite a while... :-)
>
> Cheers,
> Angelo
>
> > Change in v20:
> > - split binding patch to another series 'MediaTek MT8195 display
> > binding':
> >
> > https://patchwork.ozlabs.org/project/devicetree-bindings/list/?series=295669
> > - fix io_start type from u32 to resource_size_t
> > - fix some commit message for DITHER enum
snip...
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [PATCH v20 0/8] Add Mediatek Soc DRM (vdosys0) support for mt8195
@ 2022-05-25 13:18 ` Jason-JH Lin
0 siblings, 0 replies; 110+ messages in thread
From: Jason-JH Lin @ 2022-05-25 13:18 UTC (permalink / raw)
To: AngeloGioacchino Del Regno, Matthias Brugger, Chun-Kuang Hu
Cc: CK Hu, Nancy Lin, Singo Chang, devicetree, linux-kernel,
dri-devel, linux-mediatek, linux-arm-kernel,
Project_Global_Chrome_Upstream_Group, jason-jhlin
Hello Angelo,
OK, I'll rebase on next-20220525 and resend soon.
Regards,
Jason-JH.Lin
On Wed, 2022-05-25 at 11:50 +0200, AngeloGioacchino Del Regno wrote:
> Il 19/04/22 11:41, jason-jh.lin ha scritto:
> > From: jason-jhlin <jason-jh.lin@mediatek.corp-partner.google.com>
> >
>
> Hello Jason,
>
> this series does not apply cleanly anymore on next-20220525, can you
> please
> rebase and resend?
>
> I hope that with a bit of coordination, we can get the entire display
> stack
> finally upstreamed in v5.19... it's been quite a while... :-)
>
> Cheers,
> Angelo
>
> > Change in v20:
> > - split binding patch to another series 'MediaTek MT8195 display
> > binding':
> >
> > https://patchwork.ozlabs.org/project/devicetree-bindings/list/?series=295669
> > - fix io_start type from u32 to resource_size_t
> > - fix some commit message for DITHER enum
snip...
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [PATCH v20 0/8] Add Mediatek Soc DRM (vdosys0) support for mt8195
@ 2022-05-25 13:18 ` Jason-JH Lin
0 siblings, 0 replies; 110+ messages in thread
From: Jason-JH Lin @ 2022-05-25 13:18 UTC (permalink / raw)
To: AngeloGioacchino Del Regno, Matthias Brugger, Chun-Kuang Hu
Cc: CK Hu, Nancy Lin, Singo Chang, devicetree, linux-kernel,
dri-devel, linux-mediatek, linux-arm-kernel,
Project_Global_Chrome_Upstream_Group, jason-jhlin
Hello Angelo,
OK, I'll rebase on next-20220525 and resend soon.
Regards,
Jason-JH.Lin
On Wed, 2022-05-25 at 11:50 +0200, AngeloGioacchino Del Regno wrote:
> Il 19/04/22 11:41, jason-jh.lin ha scritto:
> > From: jason-jhlin <jason-jh.lin@mediatek.corp-partner.google.com>
> >
>
> Hello Jason,
>
> this series does not apply cleanly anymore on next-20220525, can you
> please
> rebase and resend?
>
> I hope that with a bit of coordination, we can get the entire display
> stack
> finally upstreamed in v5.19... it's been quite a while... :-)
>
> Cheers,
> Angelo
>
> > Change in v20:
> > - split binding patch to another series 'MediaTek MT8195 display
> > binding':
> >
> > https://patchwork.ozlabs.org/project/devicetree-bindings/list/?series=295669
> > - fix io_start type from u32 to resource_size_t
> > - fix some commit message for DITHER enum
snip...
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [PATCH v20 0/8] Add Mediatek Soc DRM (vdosys0) support for mt8195
@ 2022-05-25 13:18 ` Jason-JH Lin
0 siblings, 0 replies; 110+ messages in thread
From: Jason-JH Lin @ 2022-05-25 13:18 UTC (permalink / raw)
To: AngeloGioacchino Del Regno, Matthias Brugger, Chun-Kuang Hu
Cc: CK Hu, Nancy Lin, Singo Chang, devicetree, linux-kernel,
dri-devel, linux-mediatek, linux-arm-kernel,
Project_Global_Chrome_Upstream_Group, jason-jhlin
Hello Angelo,
OK, I'll rebase on next-20220525 and resend soon.
Regards,
Jason-JH.Lin
On Wed, 2022-05-25 at 11:50 +0200, AngeloGioacchino Del Regno wrote:
> Il 19/04/22 11:41, jason-jh.lin ha scritto:
> > From: jason-jhlin <jason-jh.lin@mediatek.corp-partner.google.com>
> >
>
> Hello Jason,
>
> this series does not apply cleanly anymore on next-20220525, can you
> please
> rebase and resend?
>
> I hope that with a bit of coordination, we can get the entire display
> stack
> finally upstreamed in v5.19... it's been quite a while... :-)
>
> Cheers,
> Angelo
>
> > Change in v20:
> > - split binding patch to another series 'MediaTek MT8195 display
> > binding':
> >
> > https://patchwork.ozlabs.org/project/devicetree-bindings/list/?series=295669
> > - fix io_start type from u32 to resource_size_t
> > - fix some commit message for DITHER enum
snip...
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 110+ messages in thread
end of thread, other threads:[~2022-05-25 13:20 UTC | newest]
Thread overview: 110+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-04-19 9:41 [PATCH v20 0/8] Add Mediatek Soc DRM (vdosys0) support for mt8195 jason-jh.lin
2022-04-19 9:41 ` jason-jh.lin
2022-04-19 9:41 ` jason-jh.lin
2022-04-19 9:41 ` [PATCH v20 1/8] soc: mediatek: add mtk-mmsys support for mt8195 vdosys0 jason-jh.lin
2022-04-19 9:41 ` jason-jh.lin
2022-04-19 9:41 ` jason-jh.lin
2022-04-21 6:06 ` Rex-BC Chen
2022-04-21 6:06 ` Rex-BC Chen
2022-04-21 6:06 ` Rex-BC Chen
2022-04-21 6:32 ` CK Hu
2022-04-21 6:32 ` CK Hu
2022-04-21 6:32 ` CK Hu
2022-04-22 12:28 ` Matthias Brugger
2022-04-22 12:28 ` Matthias Brugger
2022-04-22 12:28 ` Matthias Brugger
2022-04-22 12:28 ` Matthias Brugger
2022-04-24 8:47 ` Jason-JH Lin
2022-04-24 8:47 ` Jason-JH Lin
2022-04-24 8:47 ` Jason-JH Lin
2022-04-24 8:47 ` Jason-JH Lin
2022-04-19 9:41 ` [PATCH v20 2/8] soc: mediatek: add mtk-mutex " jason-jh.lin
2022-04-19 9:41 ` jason-jh.lin
2022-04-19 9:41 ` jason-jh.lin
2022-04-21 6:07 ` Rex-BC Chen
2022-04-21 6:07 ` Rex-BC Chen
2022-04-21 6:07 ` Rex-BC Chen
2022-04-21 6:50 ` CK Hu
2022-04-21 6:50 ` CK Hu
2022-04-21 6:50 ` CK Hu
2022-04-22 2:32 ` Jason-JH Lin
2022-04-22 2:32 ` Jason-JH Lin
2022-04-22 2:32 ` Jason-JH Lin
2022-04-22 2:32 ` Jason-JH Lin
2022-04-22 12:31 ` Matthias Brugger
2022-04-22 12:31 ` Matthias Brugger
2022-04-22 12:31 ` Matthias Brugger
2022-04-22 12:31 ` Matthias Brugger
2022-04-24 8:48 ` Jason-JH Lin
2022-04-24 8:48 ` Jason-JH Lin
2022-04-24 8:48 ` Jason-JH Lin
2022-04-24 8:48 ` Jason-JH Lin
2022-04-22 12:29 ` Matthias Brugger
2022-04-22 12:29 ` Matthias Brugger
2022-04-22 12:29 ` Matthias Brugger
2022-04-22 12:29 ` Matthias Brugger
2022-04-19 9:41 ` [PATCH v20 3/8] drm/mediatek: add DSC support for mediatek-drm jason-jh.lin
2022-04-19 9:41 ` jason-jh.lin
2022-04-19 9:41 ` jason-jh.lin
2022-04-19 9:41 ` [PATCH v20 4/8] drm/mediatek: add MERGE " jason-jh.lin
2022-04-19 9:41 ` jason-jh.lin
2022-04-19 9:41 ` jason-jh.lin
2022-04-19 9:41 ` [PATCH v20 5/8] drm/mediatek: add mediatek-drm of vdosys0 support for mt8195 jason-jh.lin
2022-04-19 9:41 ` jason-jh.lin
2022-04-19 9:41 ` jason-jh.lin
2022-04-21 6:08 ` Rex-BC Chen
2022-04-21 6:08 ` Rex-BC Chen
2022-04-21 6:08 ` Rex-BC Chen
2022-04-22 10:05 ` CK Hu
2022-04-22 10:05 ` CK Hu
2022-04-22 10:05 ` CK Hu
2022-04-19 9:41 ` [PATCH v20 6/8] soc: mediatek: add DDP_DOMPONENT_DITHER0 enum for mt8195 vdosys0 jason-jh.lin
2022-04-19 9:41 ` jason-jh.lin
2022-04-19 9:41 ` jason-jh.lin
2022-04-21 6:10 ` Rex-BC Chen
2022-04-21 6:10 ` Rex-BC Chen
2022-04-21 6:10 ` Rex-BC Chen
2022-04-22 12:32 ` Matthias Brugger
2022-04-22 12:32 ` Matthias Brugger
2022-04-22 12:32 ` Matthias Brugger
2022-04-22 12:32 ` Matthias Brugger
2022-04-19 9:41 ` [PATCH v20 7/8] drm/mediatek: add suffix 0 to DDP_COMPONENT_DITHER " jason-jh.lin
2022-04-19 9:41 ` jason-jh.lin
2022-04-19 9:41 ` jason-jh.lin
2022-04-21 6:11 ` Rex-BC Chen
2022-04-21 6:11 ` Rex-BC Chen
2022-04-21 6:11 ` Rex-BC Chen
2022-04-19 9:41 ` [PATCH v20 8/8] soc: mediatek: remove DDP_DOMPONENT_DITHER from enum jason-jh.lin
2022-04-19 9:41 ` jason-jh.lin
2022-04-19 9:41 ` jason-jh.lin
2022-04-21 6:13 ` Rex-BC Chen
2022-04-21 6:13 ` Rex-BC Chen
2022-04-21 6:13 ` Rex-BC Chen
2022-04-22 12:42 ` Matthias Brugger
2022-04-22 12:42 ` Matthias Brugger
2022-04-22 12:42 ` Matthias Brugger
2022-04-22 12:42 ` Matthias Brugger
2022-05-01 22:54 ` Chun-Kuang Hu
2022-05-01 22:54 ` Chun-Kuang Hu
2022-05-01 22:54 ` Chun-Kuang Hu
2022-05-01 22:54 ` Chun-Kuang Hu
2022-05-13 7:42 ` Matthias Brugger
2022-05-13 7:42 ` Matthias Brugger
2022-05-13 7:42 ` Matthias Brugger
2022-05-13 7:42 ` Matthias Brugger
2022-05-14 22:45 ` Chun-Kuang Hu
2022-05-14 22:45 ` Chun-Kuang Hu
2022-05-14 22:45 ` Chun-Kuang Hu
2022-05-14 22:45 ` Chun-Kuang Hu
2022-05-17 10:29 ` Matthias Brugger
2022-05-17 10:29 ` Matthias Brugger
2022-05-17 10:29 ` Matthias Brugger
2022-05-17 10:29 ` Matthias Brugger
2022-05-25 9:50 ` [PATCH v20 0/8] Add Mediatek Soc DRM (vdosys0) support for mt8195 AngeloGioacchino Del Regno
2022-05-25 9:50 ` AngeloGioacchino Del Regno
2022-05-25 9:50 ` AngeloGioacchino Del Regno
2022-05-25 9:50 ` AngeloGioacchino Del Regno
2022-05-25 13:18 ` Jason-JH Lin
2022-05-25 13:18 ` Jason-JH Lin
2022-05-25 13:18 ` Jason-JH Lin
2022-05-25 13:18 ` Jason-JH Lin
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