From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1573EC433EF for ; Thu, 12 May 2022 11:13:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1353057AbiELLNK convert rfc822-to-8bit (ORCPT ); Thu, 12 May 2022 07:13:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47150 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1353055AbiELLNB (ORCPT ); Thu, 12 May 2022 07:13:01 -0400 Received: from gloria.sntech.de (gloria.sntech.de [185.11.138.130]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 11E9462216 for ; Thu, 12 May 2022 04:12:56 -0700 (PDT) Received: from ip5b412258.dynamic.kabel-deutschland.de ([91.65.34.88] helo=diego.localnet) by gloria.sntech.de with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1np6kZ-0001eb-5Y; Thu, 12 May 2022 13:12:55 +0200 From: Heiko =?ISO-8859-1?Q?St=FCbner?= To: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Cc: Dao Lu , Paul Walmsley , Palmer Dabbelt , Albert Ou , "open list:RISC-V ARCHITECTURE" , Dao Lu Subject: Re: [PATCH] arch/riscv: Add Zihintpause extension support Date: Thu, 12 May 2022 13:12:54 +0200 Message-ID: <4061745.1IzOArtZ34@diego> In-Reply-To: <20220512033045.1101909-1-daolu@rivosinc.com> References: <20220512033045.1101909-1-daolu@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8BIT Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, Am Donnerstag, 12. Mai 2022, 05:30:45 CEST schrieb Dao Lu: > This patch: > 1. Build with _zihintpause if the toolchain has support for it > 2. Detects if the platform supports the extension > 3. Use PAUSE for cpu_relax if both toolchain and the platform support it This simply explains what the patch does, which is also pretty easy to see by just reading the patch, so doesn't provide real additional value. Please use the commit message to provide more background on what you want to achieve. I.e. a short explanation what it is. ----- Implement support for the ZiHintPause extension. The PAUSE instruction is a HINT that indicates the current hart’s rate of instruction retirement should be temporarily reduced or paused. ----- The second sentence obviously comes directly from the riscv-spec pdf ;-) There is one nit below too and with that fixed Reviewed-by: Heiko Stuebner On a Qemu build with your extension patch for it, also Tested-by: Heiko Stuebner > Signed-off-by: Dao Lu > --- > arch/riscv/Makefile | 4 ++++ > arch/riscv/include/asm/hwcap.h | 1 + > arch/riscv/include/asm/vdso/processor.h | 19 ++++++++++++++++--- > arch/riscv/kernel/cpu.c | 1 + > arch/riscv/kernel/cpufeature.c | 7 +++++++ > 5 files changed, 29 insertions(+), 3 deletions(-) > > diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile > index 7d81102cffd4..900a8fda1a2d 100644 > --- a/arch/riscv/Makefile > +++ b/arch/riscv/Makefile > @@ -56,6 +56,10 @@ riscv-march-$(CONFIG_RISCV_ISA_C) := $(riscv-march-y)c > toolchain-need-zicsr-zifencei := $(call cc-option-yn, -march=$(riscv-march-y)_zicsr_zifencei) > riscv-march-$(toolchain-need-zicsr-zifencei) := $(riscv-march-y)_zicsr_zifencei > > +# Check if the toolchain supports Zihintpause extension > +toolchain-supports-zihintpause := $(call cc-option-yn, -march=$(riscv-march-y)_zihintpause) > +riscv-march-$(toolchain-supports-zihintpause) := $(riscv-march-y)_zihintpause > + > KBUILD_CFLAGS += -march=$(subst fd,,$(riscv-march-y)) > KBUILD_AFLAGS += -march=$(riscv-march-y) > > diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h > index 0734e42f74f2..caa9ee5459b4 100644 > --- a/arch/riscv/include/asm/hwcap.h > +++ b/arch/riscv/include/asm/hwcap.h > @@ -52,6 +52,7 @@ extern unsigned long elf_hwcap; > */ > enum riscv_isa_ext_id { > RISCV_ISA_EXT_SSCOFPMF = RISCV_ISA_EXT_BASE, > + RISCV_ISA_EXT_ZIHINTPAUSE, > RISCV_ISA_EXT_ID_MAX = RISCV_ISA_EXT_MAX, > }; > > diff --git a/arch/riscv/include/asm/vdso/processor.h b/arch/riscv/include/asm/vdso/processor.h > index 134388cbaaa1..106b35ba8cac 100644 > --- a/arch/riscv/include/asm/vdso/processor.h > +++ b/arch/riscv/include/asm/vdso/processor.h > @@ -4,15 +4,28 @@ > > #ifndef __ASSEMBLY__ > > +#include > #include > +#include > > +extern struct static_key_false riscv_pause_available; > static inline void cpu_relax(void) > { > + if (!static_branch_likely(&riscv_pause_available)) { > #ifdef __riscv_muldiv > - int dummy; > - /* In lieu of a halt instruction, induce a long-latency stall. */ > - __asm__ __volatile__ ("div %0, %0, zero" : "=r" (dummy)); > + int dummy; > + /* In lieu of a halt instruction, induce a long-latency stall. */ > + __asm__ __volatile__ ("div %0, %0, zero" : "=r" (dummy)); > #endif > + } else { > +#ifdef __riscv_zihintpause > + /* > + * Reduce instruction retirement. > + * This assumes the PC changes. > + */ > + __asm__ __volatile__ ("pause"); > +#endif > + } > barrier(); > } > > diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c > index ccb617791e56..89e563e9c4cc 100644 > --- a/arch/riscv/kernel/cpu.c > +++ b/arch/riscv/kernel/cpu.c > @@ -88,6 +88,7 @@ int riscv_of_parent_hartid(struct device_node *node) > */ > static struct riscv_isa_ext_data isa_ext_arr[] = { > __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF), > + __RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE), > __RISCV_ISA_EXT_DATA("", RISCV_ISA_EXT_MAX), > }; > > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c > index 1b2d42d7f589..327c19507dbb 100644 > --- a/arch/riscv/kernel/cpufeature.c > +++ b/arch/riscv/kernel/cpufeature.c > @@ -24,6 +24,8 @@ static DECLARE_BITMAP(riscv_isa, RISCV_ISA_EXT_MAX) __read_mostly; > #ifdef CONFIG_FPU > __ro_after_init DEFINE_STATIC_KEY_FALSE(cpu_hwcap_fpu); > #endif > +DEFINE_STATIC_KEY_FALSE(riscv_pause_available); > +EXPORT_SYMBOL_GPL(riscv_pause_available); > > /** > * riscv_isa_extension_base() - Get base extension word > @@ -192,6 +194,7 @@ void __init riscv_fill_hwcap(void) > set_bit(*ext - 'a', this_isa); > } else { > SET_ISA_EXT_MAP("sscofpmf", RISCV_ISA_EXT_SSCOFPMF); > + SET_ISA_EXT_MAP("zihintpause", RISCV_ISA_EXT_ZIHINTPAUSE); > } > #undef SET_ISA_EXT_MAP > } > @@ -213,6 +216,10 @@ void __init riscv_fill_hwcap(void) > > } > > + if (__riscv_isa_extension_available(riscv_isa, RISCV_ISA_EXT_ZIHINTPAUSE)) { > + static_branch_enable(&riscv_pause_available); > + } > + You don't really need the braces for the single call to static_branch_enable > /* We don't support systems with F but without D, so mask those out > * here. */ > if ((elf_hwcap & COMPAT_HWCAP_ISA_F) && !(elf_hwcap & COMPAT_HWCAP_ISA_D)) { > Heiko From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 14C31C433FE for ; Thu, 12 May 2022 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c3kgdG8Kc2VlIGJ5IGp1c3QgcmVhZGluZyB0aGUgcGF0Y2gsIHNvIGRvZXNuJ3QgcHJvdmlkZSBy ZWFsIGFkZGl0aW9uYWwgdmFsdWUuCgpQbGVhc2UgdXNlIHRoZSBjb21taXQgbWVzc2FnZSB0byBw cm92aWRlIG1vcmUgYmFja2dyb3VuZCBvbiB3aGF0CnlvdSB3YW50IHRvIGFjaGlldmUuIEkuZS4g YSBzaG9ydCBleHBsYW5hdGlvbiB3aGF0IGl0IGlzLgoKLS0tLS0KSW1wbGVtZW50IHN1cHBvcnQg Zm9yIHRoZSBaaUhpbnRQYXVzZSBleHRlbnNpb24uCgpUaGUgUEFVU0UgaW5zdHJ1Y3Rpb24gaXMg YSBISU5UIHRoYXQgaW5kaWNhdGVzIHRoZSBjdXJyZW50IGhhcnTigJlzIHJhdGUgb2YKaW5zdHJ1 Y3Rpb24gcmV0aXJlbWVudCBzaG91bGQgYmUgdGVtcG9yYXJpbHkgcmVkdWNlZCBvciBwYXVzZWQu Ci0tLS0tCgpUaGUgc2Vjb25kIHNlbnRlbmNlIG9idmlvdXNseSBjb21lcyBkaXJlY3RseSBmcm9t IHRoZSByaXNjdi1zcGVjIHBkZiA7LSkKClRoZXJlIGlzIG9uZSBuaXQgYmVsb3cgdG9vIGFuZCB3 aXRoIHRoYXQgZml4ZWQKClJldmlld2VkLWJ5OiBIZWlrbyBTdHVlYm5lciA8aGVpa29Ac250ZWNo LmRlPgoKT24gYSBRZW11IGJ1aWxkIHdpdGggeW91ciBleHRlbnNpb24gcGF0Y2ggZm9yIGl0LCBh bHNvClRlc3RlZC1ieTogSGVpa28gU3R1ZWJuZXIgPGhlaWtvQHNudGVjaC5kZT4KCgo+IFNpZ25l ZC1vZmYtYnk6IERhbyBMdSA8ZGFvbHVAcml2b3NpbmMuY29tPgo+IC0tLQo+ICBhcmNoL3Jpc2N2 L01ha2VmaWxlICAgICAgICAgICAgICAgICAgICAgfCAgNCArKysrCj4gIGFyY2gvcmlzY3YvaW5j bHVkZS9hc20vaHdjYXAuaCAgICAgICAgICB8ICAxICsKPiAgYXJjaC9yaXNjdi9pbmNsdWRlL2Fz bS92ZHNvL3Byb2Nlc3Nvci5oIHwgMTkgKysrKysrKysrKysrKysrKy0tLQo+ICBhcmNoL3Jpc2N2 L2tlcm5lbC9jcHUuYyAgICAgICAgICAgICAgICAgfCAgMSArCj4gIGFyY2gvcmlzY3Yva2VybmVs L2NwdWZlYXR1cmUuYyAgICAgICAgICB8ICA3ICsrKysrKysKPiAgNSBmaWxlcyBjaGFuZ2VkLCAy OSBpbnNlcnRpb25zKCspLCAzIGRlbGV0aW9ucygtKQo+IAo+IGRpZmYgLS1naXQgYS9hcmNoL3Jp c2N2L01ha2VmaWxlIGIvYXJjaC9yaXNjdi9NYWtlZmlsZQo+IGluZGV4IDdkODExMDJjZmZkNC4u OTAwYThmZGExYTJkIDEwMDY0NAo+IC0tLSBhL2FyY2gvcmlzY3YvTWFrZWZpbGUKPiArKysgYi9h cmNoL3Jpc2N2L01ha2VmaWxlCj4gQEAgLTU2LDYgKzU2LDEwIEBAIHJpc2N2LW1hcmNoLSQoQ09O RklHX1JJU0NWX0lTQV9DKQk6PSAkKHJpc2N2LW1hcmNoLXkpYwo+ICB0b29sY2hhaW4tbmVlZC16 aWNzci16aWZlbmNlaSA6PSAkKGNhbGwgY2Mtb3B0aW9uLXluLCAtbWFyY2g9JChyaXNjdi1tYXJj aC15KV96aWNzcl96aWZlbmNlaSkKPiAgcmlzY3YtbWFyY2gtJCh0b29sY2hhaW4tbmVlZC16aWNz ci16aWZlbmNlaSkgOj0gJChyaXNjdi1tYXJjaC15KV96aWNzcl96aWZlbmNlaQo+ICAKPiArIyBD aGVjayBpZiB0aGUgdG9vbGNoYWluIHN1cHBvcnRzIFppaGludHBhdXNlIGV4dGVuc2lvbgo+ICt0 b29sY2hhaW4tc3VwcG9ydHMtemloaW50cGF1c2UgOj0gJChjYWxsIGNjLW9wdGlvbi15biwgLW1h cmNoPSQocmlzY3YtbWFyY2gteSlfemloaW50cGF1c2UpCj4gK3Jpc2N2LW1hcmNoLSQodG9vbGNo YWluLXN1cHBvcnRzLXppaGludHBhdXNlKSA6PSAkKHJpc2N2LW1hcmNoLXkpX3ppaGludHBhdXNl Cj4gKwo+ICBLQlVJTERfQ0ZMQUdTICs9IC1tYXJjaD0kKHN1YnN0IGZkLCwkKHJpc2N2LW1hcmNo LXkpKQo+ICBLQlVJTERfQUZMQUdTICs9IC1tYXJjaD0kKHJpc2N2LW1hcmNoLXkpCj4gIAo+IGRp ZmYgLS1naXQgYS9hcmNoL3Jpc2N2L2luY2x1ZGUvYXNtL2h3Y2FwLmggYi9hcmNoL3Jpc2N2L2lu Y2x1ZGUvYXNtL2h3Y2FwLmgKPiBpbmRleCAwNzM0ZTQyZjc0ZjIuLmNhYTllZTU0NTliNCAxMDA2 NDQKPiAtLS0gYS9hcmNoL3Jpc2N2L2luY2x1ZGUvYXNtL2h3Y2FwLmgKPiArKysgYi9hcmNoL3Jp c2N2L2luY2x1ZGUvYXNtL2h3Y2FwLmgKPiBAQCAtNTIsNiArNTIsNyBAQCBleHRlcm4gdW5zaWdu ZWQgbG9uZyBlbGZfaHdjYXA7Cj4gICAqLwo+ICBlbnVtIHJpc2N2X2lzYV9leHRfaWQgewo+ICAJ UklTQ1ZfSVNBX0VYVF9TU0NPRlBNRiA9IFJJU0NWX0lTQV9FWFRfQkFTRSwKPiArCVJJU0NWX0lT QV9FWFRfWklISU5UUEFVU0UsCj4gIAlSSVNDVl9JU0FfRVhUX0lEX01BWCA9IFJJU0NWX0lTQV9F WFRfTUFYLAo+ICB9Owo+ICAKPiBkaWZmIC0tZ2l0IGEvYXJjaC9yaXNjdi9pbmNsdWRlL2FzbS92 ZHNvL3Byb2Nlc3Nvci5oIGIvYXJjaC9yaXNjdi9pbmNsdWRlL2FzbS92ZHNvL3Byb2Nlc3Nvci5o Cj4gaW5kZXggMTM0Mzg4Y2JhYWExLi4xMDZiMzViYThjYWMgMTAwNjQ0Cj4gLS0tIGEvYXJjaC9y aXNjdi9pbmNsdWRlL2FzbS92ZHNvL3Byb2Nlc3Nvci5oCj4gKysrIGIvYXJjaC9yaXNjdi9pbmNs dWRlL2FzbS92ZHNvL3Byb2Nlc3Nvci5oCj4gQEAgLTQsMTUgKzQsMjggQEAKPiAgCj4gICNpZm5k ZWYgX19BU1NFTUJMWV9fCj4gIAo+ICsjaW5jbHVkZSA8bGludXgvanVtcF9sYWJlbC5oPgo+ICAj aW5jbHVkZSA8YXNtL2JhcnJpZXIuaD4KPiArI2luY2x1ZGUgPGFzbS9od2NhcC5oPgo+ICAKPiAr ZXh0ZXJuIHN0cnVjdCBzdGF0aWNfa2V5X2ZhbHNlIHJpc2N2X3BhdXNlX2F2YWlsYWJsZTsKPiAg c3RhdGljIGlubGluZSB2b2lkIGNwdV9yZWxheCh2b2lkKQo+ICB7Cj4gKwlpZiAoIXN0YXRpY19i cmFuY2hfbGlrZWx5KCZyaXNjdl9wYXVzZV9hdmFpbGFibGUpKSB7Cj4gICNpZmRlZiBfX3Jpc2N2 X211bGRpdgo+IC0JaW50IGR1bW15Owo+IC0JLyogSW4gbGlldSBvZiBhIGhhbHQgaW5zdHJ1Y3Rp b24sIGluZHVjZSBhIGxvbmctbGF0ZW5jeSBzdGFsbC4gKi8KPiAtCV9fYXNtX18gX192b2xhdGls ZV9fICgiZGl2ICUwLCAlMCwgemVybyIgOiAiPXIiIChkdW1teSkpOwo+ICsJCWludCBkdW1teTsK PiArCQkvKiBJbiBsaWV1IG9mIGEgaGFsdCBpbnN0cnVjdGlvbiwgaW5kdWNlIGEgbG9uZy1sYXRl bmN5IHN0YWxsLiAqLwo+ICsJCV9fYXNtX18gX192b2xhdGlsZV9fICgiZGl2ICUwLCAlMCwgemVy byIgOiAiPXIiIChkdW1teSkpOwo+ICAjZW5kaWYKPiArCX0gZWxzZSB7Cj4gKyNpZmRlZiBfX3Jp c2N2X3ppaGludHBhdXNlCj4gKwkJLyoKPiArCQkgKiBSZWR1Y2UgaW5zdHJ1Y3Rpb24gcmV0aXJl bWVudC4KPiArCQkgKiBUaGlzIGFzc3VtZXMgdGhlIFBDIGNoYW5nZXMuCj4gKwkJICovCj4gKwkJ X19hc21fXyBfX3ZvbGF0aWxlX18gKCJwYXVzZSIpOwo+ICsjZW5kaWYKPiArCX0KPiAgCWJhcnJp ZXIoKTsKPiAgfQo+ICAKPiBkaWZmIC0tZ2l0IGEvYXJjaC9yaXNjdi9rZXJuZWwvY3B1LmMgYi9h cmNoL3Jpc2N2L2tlcm5lbC9jcHUuYwo+IGluZGV4IGNjYjYxNzc5MWU1Ni4uODllNTYzZTljNGNj IDEwMDY0NAo+IC0tLSBhL2FyY2gvcmlzY3Yva2VybmVsL2NwdS5jCj4gKysrIGIvYXJjaC9yaXNj di9rZXJuZWwvY3B1LmMKPiBAQCAtODgsNiArODgsNyBAQCBpbnQgcmlzY3Zfb2ZfcGFyZW50X2hh cnRpZChzdHJ1Y3QgZGV2aWNlX25vZGUgKm5vZGUpCj4gICAqLwo+ICBzdGF0aWMgc3RydWN0IHJp c2N2X2lzYV9leHRfZGF0YSBpc2FfZXh0X2FycltdID0gewo+ICAJX19SSVNDVl9JU0FfRVhUX0RB VEEoc3Njb2ZwbWYsIFJJU0NWX0lTQV9FWFRfU1NDT0ZQTUYpLAo+ICsJX19SSVNDVl9JU0FfRVhU X0RBVEEoemloaW50cGF1c2UsIFJJU0NWX0lTQV9FWFRfWklISU5UUEFVU0UpLAo+ICAJX19SSVND Vl9JU0FfRVhUX0RBVEEoIiIsIFJJU0NWX0lTQV9FWFRfTUFYKSwKPiAgfTsKPiAgCj4gZGlmZiAt LWdpdCBhL2FyY2gvcmlzY3Yva2VybmVsL2NwdWZlYXR1cmUuYyBiL2FyY2gvcmlzY3Yva2VybmVs L2NwdWZlYXR1cmUuYwo+IGluZGV4IDFiMmQ0MmQ3ZjU4OS4uMzI3YzE5NTA3ZGJiIDEwMDY0NAo+ IC0tLSBhL2FyY2gvcmlzY3Yva2VybmVsL2NwdWZlYXR1cmUuYwo+ICsrKyBiL2FyY2gvcmlzY3Yv a2VybmVsL2NwdWZlYXR1cmUuYwo+IEBAIC0yNCw2ICsyNCw4IEBAIHN0YXRpYyBERUNMQVJFX0JJ VE1BUChyaXNjdl9pc2EsIFJJU0NWX0lTQV9FWFRfTUFYKSBfX3JlYWRfbW9zdGx5Owo+ICAjaWZk ZWYgQ09ORklHX0ZQVQo+ICBfX3JvX2FmdGVyX2luaXQgREVGSU5FX1NUQVRJQ19LRVlfRkFMU0Uo Y3B1X2h3Y2FwX2ZwdSk7Cj4gICNlbmRpZgo+ICtERUZJTkVfU1RBVElDX0tFWV9GQUxTRShyaXNj dl9wYXVzZV9hdmFpbGFibGUpOwo+ICtFWFBPUlRfU1lNQk9MX0dQTChyaXNjdl9wYXVzZV9hdmFp bGFibGUpOwo+ICAKPiAgLyoqCj4gICAqIHJpc2N2X2lzYV9leHRlbnNpb25fYmFzZSgpIC0gR2V0 IGJhc2UgZXh0ZW5zaW9uIHdvcmQKPiBAQCAtMTkyLDYgKzE5NCw3IEBAIHZvaWQgX19pbml0IHJp c2N2X2ZpbGxfaHdjYXAodm9pZCkKPiAgCQkJCXNldF9iaXQoKmV4dCAtICdhJywgdGhpc19pc2Ep Owo+ICAJCQl9IGVsc2Ugewo+ICAJCQkJU0VUX0lTQV9FWFRfTUFQKCJzc2NvZnBtZiIsIFJJU0NW X0lTQV9FWFRfU1NDT0ZQTUYpOwo+ICsJCQkJU0VUX0lTQV9FWFRfTUFQKCJ6aWhpbnRwYXVzZSIs IFJJU0NWX0lTQV9FWFRfWklISU5UUEFVU0UpOwo+ICAJCQl9Cj4gICN1bmRlZiBTRVRfSVNBX0VY VF9NQVAKPiAgCQl9Cj4gQEAgLTIxMyw2ICsyMTYsMTAgQEAgdm9pZCBfX2luaXQgcmlzY3ZfZmls bF9od2NhcCh2b2lkKQo+ICAKPiAgCX0KPiAgCj4gKwlpZiAoX19yaXNjdl9pc2FfZXh0ZW5zaW9u X2F2YWlsYWJsZShyaXNjdl9pc2EsIFJJU0NWX0lTQV9FWFRfWklISU5UUEFVU0UpKSB7Cj4gKwkJ c3RhdGljX2JyYW5jaF9lbmFibGUoJnJpc2N2X3BhdXNlX2F2YWlsYWJsZSk7Cj4gKwl9Cj4gKwoK WW91IGRvbid0IHJlYWxseSBuZWVkIHRoZSBicmFjZXMgZm9yIHRoZSBzaW5nbGUgY2FsbCB0byBz dGF0aWNfYnJhbmNoX2VuYWJsZQoKCj4gIAkvKiBXZSBkb24ndCBzdXBwb3J0IHN5c3RlbXMgd2l0 aCBGIGJ1dCB3aXRob3V0IEQsIHNvIG1hc2sgdGhvc2Ugb3V0Cj4gIAkgKiBoZXJlLiAqLwo+ICAJ aWYgKChlbGZfaHdjYXAgJiBDT01QQVRfSFdDQVBfSVNBX0YpICYmICEoZWxmX2h3Y2FwICYgQ09N UEFUX0hXQ0FQX0lTQV9EKSkgewo+IAoKCkhlaWtvCgoKCgpfX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fX19fX19fX19fX19fXwpsaW51eC1yaXNjdiBtYWlsaW5nIGxpc3QKbGludXgt cmlzY3ZAbGlzdHMuaW5mcmFkZWFkLm9yZwpodHRwOi8vbGlzdHMuaW5mcmFkZWFkLm9yZy9tYWls bWFuL2xpc3RpbmZvL2xpbnV4LXJpc2N2Cg==