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X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Dec 2021 11:30:55.5242 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f777f524-aee3-4a90-4084-08d9c0878642 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[63.35.35.123];Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: DB5EUR03FT034.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB7PR08MB3289 Hi Jan > On 24 Sep 2021, at 10:53 am, Jan Beulich wrote: >=20 > Having a separate flush-all hook has always been puzzling me some. We > will want to be able to force a full flush via accumulated flush flags > from the map/unmap functions. Introduce a respective new flag and fold > all flush handling to use the single remaining hook. >=20 > Note that because of the respective comments in SMMU and IPMMU-VMSA > code, I've folded the two prior hook functions into one. For SMMU-v3, > which lacks a comment towards incapable hardware, I've left both > functions in place on the assumption that selective and full flushes > will eventually want separating. For SMMUv3 related Changs: Reviewed-by: Rahul Singh Regards, Rahul >=20 > Signed-off-by: Jan Beulich > --- > TBD: What we really are going to need is for the map/unmap functions to > specify that a wider region needs flushing than just the one > covered by the present set of (un)maps. This may still be less than > a full flush, but at least as a first step it seemed better to me > to keep things simple and go the flush-all route. > --- > v2: New. >=20 > --- a/xen/drivers/passthrough/amd/iommu.h > +++ b/xen/drivers/passthrough/amd/iommu.h > @@ -242,7 +242,6 @@ int amd_iommu_get_reserved_device_memory > int __must_check amd_iommu_flush_iotlb_pages(struct domain *d, dfn_t dfn, > unsigned long page_count, > unsigned int flush_flags); > -int __must_check amd_iommu_flush_iotlb_all(struct domain *d); > void amd_iommu_print_entries(const struct amd_iommu *iommu, unsigned int = dev_id, > dfn_t dfn); >=20 > --- a/xen/drivers/passthrough/amd/iommu_map.c > +++ b/xen/drivers/passthrough/amd/iommu_map.c > @@ -475,15 +475,18 @@ int amd_iommu_flush_iotlb_pages(struct d > { > unsigned long dfn_l =3D dfn_x(dfn); >=20 > - ASSERT(page_count && !dfn_eq(dfn, INVALID_DFN)); > - ASSERT(flush_flags); > + if ( !(flush_flags & IOMMU_FLUSHF_all) ) > + { > + ASSERT(page_count && !dfn_eq(dfn, INVALID_DFN)); > + ASSERT(flush_flags); > + } >=20 > /* Unless a PTE was modified, no flush is required */ > if ( !(flush_flags & IOMMU_FLUSHF_modified) ) > return 0; >=20 > - /* If the range wraps then just flush everything */ > - if ( dfn_l + page_count < dfn_l ) > + /* If so requested or if the range wraps then just flush everything.= */ > + if ( (flush_flags & IOMMU_FLUSHF_all) || dfn_l + page_count < dfn_l = ) > { > amd_iommu_flush_all_pages(d); > return 0; > @@ -508,13 +511,6 @@ int amd_iommu_flush_iotlb_pages(struct d >=20 > return 0; > } > - > -int amd_iommu_flush_iotlb_all(struct domain *d) > -{ > - amd_iommu_flush_all_pages(d); > - > - return 0; > -} >=20 > int amd_iommu_reserve_domain_unity_map(struct domain *d, > const struct ivrs_unity_map *map, > --- a/xen/drivers/passthrough/amd/pci_amd_iommu.c > +++ b/xen/drivers/passthrough/amd/pci_amd_iommu.c > @@ -642,7 +642,6 @@ static const struct iommu_ops __initcons > .map_page =3D amd_iommu_map_page, > .unmap_page =3D amd_iommu_unmap_page, > .iotlb_flush =3D amd_iommu_flush_iotlb_pages, > - .iotlb_flush_all =3D amd_iommu_flush_iotlb_all, > .reassign_device =3D reassign_device, > .get_device_group_id =3D amd_iommu_group_id, > .enable_x2apic =3D iov_enable_xt, > --- a/xen/drivers/passthrough/arm/ipmmu-vmsa.c > +++ b/xen/drivers/passthrough/arm/ipmmu-vmsa.c > @@ -930,13 +930,19 @@ out: > } >=20 > /* Xen IOMMU ops */ > -static int __must_check ipmmu_iotlb_flush_all(struct domain *d) > +static int __must_check ipmmu_iotlb_flush(struct domain *d, dfn_t dfn, > + unsigned long page_count, > + unsigned int flush_flags) > { > struct ipmmu_vmsa_xen_domain *xen_domain =3D dom_iommu(d)->arch.priv; >=20 > + ASSERT(flush_flags); > + > if ( !xen_domain || !xen_domain->root_domain ) > return 0; >=20 > + /* The hardware doesn't support selective TLB flush. */ > + > spin_lock(&xen_domain->lock); > ipmmu_tlb_invalidate(xen_domain->root_domain); > spin_unlock(&xen_domain->lock); > @@ -944,16 +950,6 @@ static int __must_check ipmmu_iotlb_flus > return 0; > } >=20 > -static int __must_check ipmmu_iotlb_flush(struct domain *d, dfn_t dfn, > - unsigned long page_count, > - unsigned int flush_flags) > -{ > - ASSERT(flush_flags); > - > - /* The hardware doesn't support selective TLB flush. */ > - return ipmmu_iotlb_flush_all(d); > -} > - > static struct ipmmu_vmsa_domain *ipmmu_get_cache_domain(struct domain *d, > struct device *de= v) > { > @@ -1303,7 +1299,6 @@ static const struct iommu_ops ipmmu_iomm > .hwdom_init =3D ipmmu_iommu_hwdom_init, > .teardown =3D ipmmu_iommu_domain_teardown, > .iotlb_flush =3D ipmmu_iotlb_flush, > - .iotlb_flush_all =3D ipmmu_iotlb_flush_all, > .assign_device =3D ipmmu_assign_device, > .reassign_device =3D ipmmu_reassign_device, > .map_page =3D arm_iommu_map_page, > --- a/xen/drivers/passthrough/arm/smmu.c > +++ b/xen/drivers/passthrough/arm/smmu.c > @@ -2649,11 +2649,17 @@ static int force_stage =3D 2; > */ > static u32 platform_features =3D ARM_SMMU_FEAT_COHERENT_WALK; >=20 > -static int __must_check arm_smmu_iotlb_flush_all(struct domain *d) > +static int __must_check arm_smmu_iotlb_flush(struct domain *d, dfn_t dfn= , > + unsigned long page_count, > + unsigned int flush_flags) > { > struct arm_smmu_xen_domain *smmu_domain =3D dom_iommu(d)->arch.priv; > struct iommu_domain *cfg; >=20 > + ASSERT(flush_flags); > + > + /* ARM SMMU v1 doesn't have flush by VMA and VMID */ > + > spin_lock(&smmu_domain->lock); > list_for_each_entry(cfg, &smmu_domain->contexts, list) { > /* > @@ -2670,16 +2676,6 @@ static int __must_check arm_smmu_iotlb_f > return 0; > } >=20 > -static int __must_check arm_smmu_iotlb_flush(struct domain *d, dfn_t dfn= , > - unsigned long page_count, > - unsigned int flush_flags) > -{ > - ASSERT(flush_flags); > - > - /* ARM SMMU v1 doesn't have flush by VMA and VMID */ > - return arm_smmu_iotlb_flush_all(d); > -} > - > static struct iommu_domain *arm_smmu_get_domain(struct domain *d, > struct device *dev) > { > @@ -2879,7 +2875,6 @@ static const struct iommu_ops arm_smmu_i > .add_device =3D arm_smmu_dt_add_device_generic, > .teardown =3D arm_smmu_iommu_domain_teardown, > .iotlb_flush =3D arm_smmu_iotlb_flush, > - .iotlb_flush_all =3D arm_smmu_iotlb_flush_all, > .assign_device =3D arm_smmu_assign_dev, > .reassign_device =3D arm_smmu_reassign_dev, > .map_page =3D arm_iommu_map_page, > --- a/xen/drivers/passthrough/arm/smmu-v3.c > +++ b/xen/drivers/passthrough/arm/smmu-v3.c > @@ -3431,7 +3431,6 @@ static const struct iommu_ops arm_smmu_i > .hwdom_init =3D arm_smmu_iommu_hwdom_init, > .teardown =3D arm_smmu_iommu_xen_domain_teardown, > .iotlb_flush =3D arm_smmu_iotlb_flush, > - .iotlb_flush_all =3D arm_smmu_iotlb_flush_all, > .assign_device =3D arm_smmu_assign_dev, > .reassign_device =3D arm_smmu_reassign_dev, > .map_page =3D arm_iommu_map_page, > --- a/xen/drivers/passthrough/iommu.c > +++ b/xen/drivers/passthrough/iommu.c > @@ -463,15 +463,12 @@ int iommu_iotlb_flush_all(struct domain > const struct domain_iommu *hd =3D dom_iommu(d); > int rc; >=20 > - if ( !is_iommu_enabled(d) || !hd->platform_ops->iotlb_flush_all || > + if ( !is_iommu_enabled(d) || !hd->platform_ops->iotlb_flush || > !flush_flags ) > return 0; >=20 > - /* > - * The operation does a full flush so we don't need to pass the > - * flush_flags in. > - */ > - rc =3D iommu_call(hd->platform_ops, iotlb_flush_all, d); > + rc =3D iommu_call(hd->platform_ops, iotlb_flush, d, INVALID_DFN, 0, > + flush_flags | IOMMU_FLUSHF_all); > if ( unlikely(rc) ) > { > if ( !d->is_shutting_down && printk_ratelimit() ) > --- a/xen/drivers/passthrough/vtd/iommu.c > +++ b/xen/drivers/passthrough/vtd/iommu.c > @@ -731,18 +731,21 @@ static int __must_check iommu_flush_iotl > unsigned long page_count, > unsigned int flush_flags) > { > - ASSERT(page_count && !dfn_eq(dfn, INVALID_DFN)); > - ASSERT(flush_flags); > + if ( flush_flags & IOMMU_FLUSHF_all ) > + { > + dfn =3D INVALID_DFN; > + page_count =3D 0; > + } > + else > + { > + ASSERT(page_count && !dfn_eq(dfn, INVALID_DFN)); > + ASSERT(flush_flags); > + } >=20 > return iommu_flush_iotlb(d, dfn, flush_flags & IOMMU_FLUSHF_modified, > page_count); > } >=20 > -static int __must_check iommu_flush_iotlb_all(struct domain *d) > -{ > - return iommu_flush_iotlb(d, INVALID_DFN, 0, 0); > -} > - > static void queue_free_pt(struct domain *d, mfn_t mfn, unsigned int next_= level) > { > if ( next_level > 1 ) > @@ -2841,7 +2844,7 @@ static int __init intel_iommu_quarantine > spin_unlock(&hd->arch.mapping_lock); >=20 > if ( !rc ) > - rc =3D iommu_flush_iotlb_all(d); > + rc =3D iommu_flush_iotlb(d, INVALID_DFN, 0, 0); >=20 > /* Pages may be leaked in failure case */ > return rc; > @@ -2874,7 +2877,6 @@ static struct iommu_ops __initdata vtd_o > .resume =3D vtd_resume, > .crash_shutdown =3D vtd_crash_shutdown, > .iotlb_flush =3D iommu_flush_iotlb_pages, > - .iotlb_flush_all =3D iommu_flush_iotlb_all, > .get_reserved_device_memory =3D intel_iommu_get_reserved_device_memor= y, > .dump_page_tables =3D vtd_dump_page_tables, > }; > --- a/xen/include/xen/iommu.h > +++ b/xen/include/xen/iommu.h > @@ -147,9 +147,11 @@ enum > { > _IOMMU_FLUSHF_added, > _IOMMU_FLUSHF_modified, > + _IOMMU_FLUSHF_all, > }; > #define IOMMU_FLUSHF_added (1u << _IOMMU_FLUSHF_added) > #define IOMMU_FLUSHF_modified (1u << _IOMMU_FLUSHF_modified) > +#define IOMMU_FLUSHF_all (1u << _IOMMU_FLUSHF_all) >=20 > int __must_check iommu_map(struct domain *d, dfn_t dfn, mfn_t mfn, > unsigned long page_count, unsigned int flags, > @@ -282,7 +284,6 @@ struct iommu_ops { > int __must_check (*iotlb_flush)(struct domain *d, dfn_t dfn, > unsigned long page_count, > unsigned int flush_flags); > - int __must_check (*iotlb_flush_all)(struct domain *d); > int (*get_reserved_device_memory)(iommu_grdm_t *, void *); > void (*dump_page_tables)(struct domain *d); >=20 >=20