From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.6 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A8BC7C433DF for ; Thu, 2 Jul 2020 07:50:33 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 859C720899 for ; Thu, 2 Jul 2020 07:50:33 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b="Iy6q1YUM" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728126AbgGBHuc (ORCPT ); Thu, 2 Jul 2020 03:50:32 -0400 Received: from us-smtp-delivery-1.mimecast.com ([207.211.31.120]:59857 "EHLO us-smtp-1.mimecast.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726042AbgGBHuc (ORCPT ); Thu, 2 Jul 2020 03:50:32 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1593676230; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=siZTOIfPD9T2MnCdUtEwr4YB3Ao/TtbkwOBgLqvQBKk=; b=Iy6q1YUMaAawWYkEIDew9xHSJ3TS1n9GcWCn+QLy1Z+xMtEHJGmUMsZi5ncRkgwg8gMpnL ZsZdPPtxCGzJtRyiUTt7BNXImWytLLLdG3yaKb7nuZsle9aZ1mEG8EGJJ9C0DhOvydplUR VS8SxlacVC7lOumjXzOTokUiY0jQKKs= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-287-YfE5AYJQMdOWPk_ilgXALg-1; Thu, 02 Jul 2020 03:50:25 -0400 X-MC-Unique: YfE5AYJQMdOWPk_ilgXALg-1 Received: from smtp.corp.redhat.com (int-mx07.intmail.prod.int.phx2.redhat.com [10.5.11.22]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 5BC7819253C0; Thu, 2 Jul 2020 07:50:23 +0000 (UTC) Received: from [10.36.112.70] (ovpn-112-70.ams2.redhat.com [10.36.112.70]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 691291002397; Thu, 2 Jul 2020 07:50:21 +0000 (UTC) Subject: Re: [PATCH v3 4/7] iommu/vt-d: Handle non-page aligned address To: Jacob Pan , iommu@lists.linux-foundation.org, LKML , Lu Baolu , Joerg Roedel , David Woodhouse Cc: Yi Liu , "Tian, Kevin" , Raj Ashok References: <1593617636-79385-1-git-send-email-jacob.jun.pan@linux.intel.com> <1593617636-79385-5-git-send-email-jacob.jun.pan@linux.intel.com> From: Auger Eric Message-ID: <40a83912-f8ad-9887-38d0-39a70ecc062c@redhat.com> Date: Thu, 2 Jul 2020 09:50:19 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.5.0 MIME-Version: 1.0 In-Reply-To: <1593617636-79385-5-git-send-email-jacob.jun.pan@linux.intel.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-Scanned-By: MIMEDefang 2.84 on 10.5.11.22 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Jacob, On 7/1/20 5:33 PM, Jacob Pan wrote: > From: Liu Yi L > > Address information for device TLB invalidation comes from userspace > when device is directly assigned to a guest with vIOMMU support. > VT-d requires page aligned address. This patch checks and enforce > address to be page aligned, otherwise reserved bits can be set in the > invalidation descriptor. Unrecoverable fault will be reported due to > non-zero value in the reserved bits. on the other hand if user space sends unaligned invalidations, shouldn't it be reported in some way? > > Fixes: 61a06a16e36d8 ("iommu/vt-d: Support flushing more translation > cache types") > Acked-by: Lu Baolu > Signed-off-by: Liu Yi L > Signed-off-by: Jacob Pan > > Signed-off-by: Jacob Pan > --- > drivers/iommu/intel/dmar.c | 20 ++++++++++++++++++-- > 1 file changed, 18 insertions(+), 2 deletions(-) > > diff --git a/drivers/iommu/intel/dmar.c b/drivers/iommu/intel/dmar.c > index d9f973fa1190..3899f3161071 100644 > --- a/drivers/iommu/intel/dmar.c > +++ b/drivers/iommu/intel/dmar.c > @@ -1455,9 +1455,25 @@ void qi_flush_dev_iotlb_pasid(struct intel_iommu *iommu, u16 sid, u16 pfsid, > * Max Invs Pending (MIP) is set to 0 for now until we have DIT in > * ECAP. > */ > - desc.qw1 |= addr & ~mask; > - if (size_order) > + if (addr & ~VTD_PAGE_MASK) > + pr_warn_ratelimited("Invalidate non-page aligned address %llx\n", addr); > + > + /* Take page address */ > + desc.qw1 |= QI_DEV_EIOTLB_ADDR(addr); > + > + if (size_order) { > + /* > + * Existing 0s in address below size_order may be the least > + * significant bit, we must set them to 1s to avoid having > + * smaller size than desired. Shouldn't you test the input addr against the size_order. Aren't they supposed to be consistent? Otherwise one should emit a warning at least? > + */ > + desc.qw1 |= GENMASK_ULL(size_order + VTD_PAGE_SHIFT, > + VTD_PAGE_SHIFT); nit: instead of working directly on .qw1, couldn't you perform all those manipulations directly on addr? and eventually override qw1 at the end? > + /* Clear size_order bit to indicate size */ > + desc.qw1 &= ~mask; > + /* Set the S bit to indicate flushing more than 1 page */ > desc.qw1 |= QI_DEV_EIOTLB_SIZE; > + } > > qi_submit_sync(iommu, &desc, 1, 0); > } > Thanks Eric From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.3 required=3.0 tests=DKIM_INVALID,DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0FEE9C433DF for ; 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Thu, 2 Jul 2020 07:50:23 +0000 (UTC) Received: from [10.36.112.70] (ovpn-112-70.ams2.redhat.com [10.36.112.70]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 691291002397; Thu, 2 Jul 2020 07:50:21 +0000 (UTC) Subject: Re: [PATCH v3 4/7] iommu/vt-d: Handle non-page aligned address To: Jacob Pan , iommu@lists.linux-foundation.org, LKML , Lu Baolu , Joerg Roedel , David Woodhouse References: <1593617636-79385-1-git-send-email-jacob.jun.pan@linux.intel.com> <1593617636-79385-5-git-send-email-jacob.jun.pan@linux.intel.com> From: Auger Eric Message-ID: <40a83912-f8ad-9887-38d0-39a70ecc062c@redhat.com> Date: Thu, 2 Jul 2020 09:50:19 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.5.0 MIME-Version: 1.0 In-Reply-To: <1593617636-79385-5-git-send-email-jacob.jun.pan@linux.intel.com> Content-Language: en-US X-Scanned-By: MIMEDefang 2.84 on 10.5.11.22 Cc: "Tian, Kevin" , Raj Ashok X-BeenThere: iommu@lists.linux-foundation.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Development issues for Linux IOMMU support List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: iommu-bounces@lists.linux-foundation.org Sender: "iommu" Hi Jacob, On 7/1/20 5:33 PM, Jacob Pan wrote: > From: Liu Yi L > > Address information for device TLB invalidation comes from userspace > when device is directly assigned to a guest with vIOMMU support. > VT-d requires page aligned address. This patch checks and enforce > address to be page aligned, otherwise reserved bits can be set in the > invalidation descriptor. Unrecoverable fault will be reported due to > non-zero value in the reserved bits. on the other hand if user space sends unaligned invalidations, shouldn't it be reported in some way? > > Fixes: 61a06a16e36d8 ("iommu/vt-d: Support flushing more translation > cache types") > Acked-by: Lu Baolu > Signed-off-by: Liu Yi L > Signed-off-by: Jacob Pan > > Signed-off-by: Jacob Pan > --- > drivers/iommu/intel/dmar.c | 20 ++++++++++++++++++-- > 1 file changed, 18 insertions(+), 2 deletions(-) > > diff --git a/drivers/iommu/intel/dmar.c b/drivers/iommu/intel/dmar.c > index d9f973fa1190..3899f3161071 100644 > --- a/drivers/iommu/intel/dmar.c > +++ b/drivers/iommu/intel/dmar.c > @@ -1455,9 +1455,25 @@ void qi_flush_dev_iotlb_pasid(struct intel_iommu *iommu, u16 sid, u16 pfsid, > * Max Invs Pending (MIP) is set to 0 for now until we have DIT in > * ECAP. > */ > - desc.qw1 |= addr & ~mask; > - if (size_order) > + if (addr & ~VTD_PAGE_MASK) > + pr_warn_ratelimited("Invalidate non-page aligned address %llx\n", addr); > + > + /* Take page address */ > + desc.qw1 |= QI_DEV_EIOTLB_ADDR(addr); > + > + if (size_order) { > + /* > + * Existing 0s in address below size_order may be the least > + * significant bit, we must set them to 1s to avoid having > + * smaller size than desired. Shouldn't you test the input addr against the size_order. Aren't they supposed to be consistent? Otherwise one should emit a warning at least? > + */ > + desc.qw1 |= GENMASK_ULL(size_order + VTD_PAGE_SHIFT, > + VTD_PAGE_SHIFT); nit: instead of working directly on .qw1, couldn't you perform all those manipulations directly on addr? and eventually override qw1 at the end? > + /* Clear size_order bit to indicate size */ > + desc.qw1 &= ~mask; > + /* Set the S bit to indicate flushing more than 1 page */ > desc.qw1 |= QI_DEV_EIOTLB_SIZE; > + } > > qi_submit_sync(iommu, &desc, 1, 0); > } > Thanks Eric _______________________________________________ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu