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From: "Cédric Le Goater" <clg@kaod.org>
To: David Gibson <david@gibson.dropbear.id.au>
Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org, Greg Kurz <groug@kaod.org>
Subject: Re: [Qemu-devel] [PATCH v2 2/2] spapr: increase the size of the IRQ number space
Date: Thu, 13 Sep 2018 11:30:00 +0200	[thread overview]
Message-ID: <40d86635-fe58-f642-336d-c1df91344073@kaod.org> (raw)
In-Reply-To: <20180913022534.GU7978@umbus.fritz.box>

On 09/13/2018 04:25 AM, David Gibson wrote:
> On Tue, Sep 11, 2018 at 07:55:03AM +0200, Cédric Le Goater wrote:
>> The new layout using static IRQ number does not leave much space to
>> the dynamic MSI range, only 0x100 IRQ numbers. Increase the total
>> number of IRQS for newer machines and introduce a legacy XICS backend
>> for pre-3.1 machines to maintain compatibility.
>>
>> For the old backend, provide a 'nr_msis' value covering the full IRQ
>> number space as it does not use the bitmap allocator to allocate MSI
>> interrupt numbers.
>>
>> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> 
> Applied to ppc-for-3.1, thanks.

I think we are ready for Xive now ?

The patchset is organized as below. The patches tagged v4 have not changed but the others have and a resend will be needed. 

* Device models for Source, Router, EQs, Presenter, Controller :

  ppc/xive: introduce a XIVE interrupt source model (v4)
  ppc/xive: add support for the LSI interrupt sources (v4)
  ppc/xive: introduce the XiveFabric interface (v4)
  ppc/xive: introduce the XiveRouter model (v4)
  ppc/xive: introduce the XIVE Event Queues (v4)
  ppc/xive: add support for the EQ Event State buffers (v4)
  ppc/xive: introduce the XIVE interrupt thread context (v4)
  ppc/xive: introduce a simplified XIVE presenter (v4)
  ppc/xive: notify the CPU when the interrupt priority is more privileged (v4)
  spapr/xive: introduce a XIVE interrupt controller (v4)
  spapr/xive: use the VCPU id as a VP identifier (v5)

* Integration in the sPAPR machine (we can add pnv also)

  spapr: initialize VSMT before initializing the IRQ backend  (v5)
  spapr: introdude a new machine IRQ backend for XIVE  (v5)
  spapr: add hcalls support for the XIVE exploitation interrupt mode  (v5)
  spapr: add device tree support for the XIVE exploitation mode  (v5)
  spapr: allocate the interrupt thread context under the CPU core  (v5)
  spapr: add a 'pseries-3.1-xive' machine type (v5)


* KVM support (KVM XIVE device interfaces)

  spapr: add classes for the XIVE models (v5+)
  target/ppc/kvm: add Linux KVM definitions for XIVE (v5+)
  spapr/xive: add models for KVM support (v5+)
  
* KVM migration (more KVM XIVE device interfaces)

  spapr/xive: add migration support for KVM (v5+)
  spapr: fix XICS migration  (v5+)


Greg is giving it some tests on TCG and now KVM as XIVE is a building 
block for the OpenCAPI passthrough. 

Thanks,

C.

      reply	other threads:[~2018-09-13  9:30 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-09-11  5:55 [Qemu-devel] [PATCH v2 0/2] spapr: introduce a new sPAPRIrq backend Cédric Le Goater
2018-09-11  5:55 ` [Qemu-devel] [PATCH v2 1/2] spapr: introduce a spapr_irq class 'nr_msis' attribute Cédric Le Goater
2018-09-11  7:34   ` Greg Kurz
2018-09-11  7:56     ` Cédric Le Goater
2018-09-13  2:22       ` David Gibson
2018-09-13  2:21   ` David Gibson
2018-09-11  5:55 ` [Qemu-devel] [PATCH v2 2/2] spapr: increase the size of the IRQ number space Cédric Le Goater
2018-09-11  7:50   ` Greg Kurz
2018-09-13  2:25   ` David Gibson
2018-09-13  9:30     ` Cédric Le Goater [this message]

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