From: Michael Ellerman <patch-notifications@ellerman.id.au>
To: Nicholas Piggin <npiggin@gmail.com>, linuxppc-dev@lists.ozlabs.org
Cc: "Aneesh Kumar K . V" <aneesh.kumar@linux.vnet.ibm.com>,
Nicholas Piggin <npiggin@gmail.com>
Subject: Re: powerpc/64s: Fix compiler store ordering to SLB shadow area
Date: Tue, 5 Jun 2018 00:11:22 +1000 (AEST) [thread overview]
Message-ID: <40zxgd3sqlz9s0w@ozlabs.org> (raw)
In-Reply-To: <20180530103122.27674-1-npiggin@gmail.com>
On Wed, 2018-05-30 at 10:31:22 UTC, Nicholas Piggin wrote:
> The stores to update the SLB shadow area must be made as they appear
> in the C code, so that the hypervisor does not see an entry with
> mismatched vsid and esid. Use WRITE_ONCE for this.
>
> GCC has been observed to elide the first store to esid in the update,
> which means that if the hypervisor interrupts the guest after storing
> to vsid, it could see an entry with old esid and new vsid, which may
> possibly result in memory corruption.
>
> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Applied to powerpc next, thanks.
https://git.kernel.org/powerpc/c/926bc2f100c24d4842b3064b5af44a
cheers
prev parent reply other threads:[~2018-06-04 14:11 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-05-30 10:31 [PATCH] powerpc/64s: Fix compiler store ordering to SLB shadow area Nicholas Piggin
2018-05-31 14:22 ` Michael Ellerman
2018-05-31 22:52 ` Nicholas Piggin
2018-06-01 11:13 ` Michael Ellerman
2018-06-01 21:38 ` Segher Boessenkool
2018-06-04 14:11 ` Michael Ellerman [this message]
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