From: Sohil Mehta <sohil.mehta@intel.com>
To: Thomas Gleixner <tglx@linutronix.de>,
Andy Lutomirski <luto@kernel.org>,
the arch/x86 maintainers <x86@kernel.org>
Cc: Tony Luck <tony.luck@intel.com>,
Dave Hansen <dave.hansen@intel.com>,
Ingo Molnar <mingo@redhat.com>, Borislav Petkov <bp@alien8.de>,
"H. Peter Anvin" <hpa@zytor.com>, Jens Axboe <axboe@kernel.dk>,
Christian Brauner <christian@brauner.io>,
"Peter Zijlstra (Intel)" <peterz@infradead.org>,
Shuah Khan <shuah@kernel.org>, Arnd Bergmann <arnd@arndb.de>,
Jonathan Corbet <corbet@lwn.net>, Raj Ashok <ashok.raj@intel.com>,
Jacob Pan <jacob.jun.pan@linux.intel.com>,
Gayatri Kammela <gayatri.kammela@intel.com>,
Zeng Guang <guang.zeng@intel.com>,
"Williams, Dan J" <dan.j.williams@intel.com>,
Randy E Witt <randy.e.witt@intel.com>,
"Shankar, Ravi V" <ravi.v.shankar@intel.com>,
Ramesh Thomas <ramesh.thomas@intel.com>,
Linux API <linux-api@vger.kernel.org>,
<linux-arch@vger.kernel.org>,
"Linux Kernel Mailing List" <linux-kernel@vger.kernel.org>,
<linux-kselftest@vger.kernel.org>
Subject: Re: [RFC PATCH 11/13] x86/uintr: Introduce uintr_wait() syscall
Date: Fri, 1 Oct 2021 16:00:44 -0700 [thread overview]
Message-ID: <410ccb21-49d8-4ec0-3f23-07e37c694bbe@intel.com> (raw)
In-Reply-To: <875yug4eos.ffs@tglx>
On 10/1/2021 2:29 PM, Thomas Gleixner wrote:
> So we'd end up with two XSAVES on context switch. We can simply do:
> XSAVES();
> fpu.state.xtsate.uintr.uinv = 0;
I am a bit confused. Do we need to set UINV to 0 explicitly?
If XSAVES gets called twice during context switch then the UINV in the
XSTATE buffer automatically gets set to 0. Since XSAVES saves the
current UINV value in the MISC_MSR which was already set to 0 by the
previous XSAVES.
Though, this probably happens due to pure luck than intentional design :)
> which allows to do as many XRSTORS in a row as we want. Only the final
> one on the way to user space will have to restore the real vector if the
> register state is not valid:
>
> if (fpu_state_valid()) {
> if (needs_uinv(current)
> wrmsrl(UINV, vector);
> } else {
> if (needs_uinv(current)
> fpu.state.xtsate.uintr.uinv = vector;
> XRSTORS();
> }
I might have missed some subtle difference. Has this logic changed from
what you previously suggested for arch_exit_to_user_mode_prepare()?
if (xrstors_pending)) {
// Update the saved xstate for xrstors
// Unconditionally update the UINV since it could have been
overwritten by calling XSAVES twice.
current->xstate.uintr.uinv = UINTR_NOTIFICATION_VECTOR;
current->xstate.uintr.uirr |= pir;
} else {
// Manually restore UIRR and UINV
rdmsrl(IA32_UINTR_RR, uirr);
wrmsrl(IA32_UINTR_RR, uirr | pir);
misc.val64 = 0;
misc.uittsz = current->uintr->uittsz;
misc.uinv = UINTR_NOTIFICATION_VECTOR;
wrmsrl(IA32_UINTR_MISC, misc.val64);
}
> Hmm?
The one case I can see this failing is if there was another XRSTORS
after the "final" restore in arch_exit_to_user_mode_prepare()? I think
that is not possible but I am not an expert on this. Did I misunderstand
something?
Thanks,
Sohil
next prev parent reply other threads:[~2021-10-01 23:01 UTC|newest]
Thread overview: 89+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-13 20:01 [RFC PATCH 00/13] x86 User Interrupts support Sohil Mehta
2021-09-13 20:01 ` [RFC PATCH 01/13] x86/uintr/man-page: Include man pages draft for reference Sohil Mehta
2021-09-13 20:01 ` [RFC PATCH 02/13] Documentation/x86: Add documentation for User Interrupts Sohil Mehta
2021-09-13 20:01 ` [RFC PATCH 03/13] x86/cpu: Enumerate User Interrupts support Sohil Mehta
2021-09-23 22:24 ` Thomas Gleixner
2021-09-24 19:59 ` Sohil Mehta
2021-09-27 20:42 ` Sohil Mehta
2021-09-13 20:01 ` [RFC PATCH 04/13] x86/fpu/xstate: Enumerate User Interrupts supervisor state Sohil Mehta
2021-09-23 22:34 ` Thomas Gleixner
2021-09-27 22:25 ` Sohil Mehta
2021-09-13 20:01 ` [RFC PATCH 05/13] x86/irq: Reserve a user IPI notification vector Sohil Mehta
2021-09-23 23:07 ` Thomas Gleixner
2021-09-25 13:30 ` Thomas Gleixner
2021-09-26 12:39 ` Thomas Gleixner
2021-09-27 19:07 ` Sohil Mehta
2021-09-28 8:11 ` Thomas Gleixner
2021-09-27 19:26 ` Sohil Mehta
2021-09-13 20:01 ` [RFC PATCH 06/13] x86/uintr: Introduce uintr receiver syscalls Sohil Mehta
2021-09-23 12:26 ` Greg KH
2021-09-24 0:05 ` Thomas Gleixner
2021-09-27 23:20 ` Sohil Mehta
2021-09-28 4:39 ` Greg KH
2021-09-28 16:47 ` Sohil Mehta
2021-09-23 23:52 ` Thomas Gleixner
2021-09-27 23:57 ` Sohil Mehta
2021-09-13 20:01 ` [RFC PATCH 07/13] x86/process/64: Add uintr task context switch support Sohil Mehta
2021-09-24 0:41 ` Thomas Gleixner
2021-09-28 0:30 ` Sohil Mehta
2021-09-13 20:01 ` [RFC PATCH 08/13] x86/process/64: Clean up uintr task fork and exit paths Sohil Mehta
2021-09-24 1:02 ` Thomas Gleixner
2021-09-28 1:23 ` Sohil Mehta
2021-09-13 20:01 ` [RFC PATCH 09/13] x86/uintr: Introduce vector registration and uintr_fd syscall Sohil Mehta
2021-09-24 10:33 ` Thomas Gleixner
2021-09-28 20:40 ` Sohil Mehta
2021-09-13 20:01 ` [RFC PATCH 10/13] x86/uintr: Introduce user IPI sender syscalls Sohil Mehta
2021-09-23 12:28 ` Greg KH
2021-09-28 18:01 ` Sohil Mehta
2021-09-29 7:04 ` Greg KH
2021-09-29 14:27 ` Sohil Mehta
2021-09-24 10:54 ` Thomas Gleixner
2021-09-13 20:01 ` [RFC PATCH 11/13] x86/uintr: Introduce uintr_wait() syscall Sohil Mehta
2021-09-24 11:04 ` Thomas Gleixner
2021-09-25 12:08 ` Thomas Gleixner
2021-09-28 23:13 ` Sohil Mehta
2021-09-28 23:08 ` Sohil Mehta
2021-09-26 14:41 ` Thomas Gleixner
2021-09-29 1:09 ` Sohil Mehta
2021-09-29 3:30 ` Andy Lutomirski
2021-09-29 4:56 ` Sohil Mehta
2021-09-30 18:08 ` Andy Lutomirski
2021-09-30 19:29 ` Thomas Gleixner
2021-09-30 22:01 ` Andy Lutomirski
2021-10-01 0:01 ` Thomas Gleixner
2021-10-01 4:41 ` Andy Lutomirski
2021-10-01 9:56 ` Thomas Gleixner
2021-10-01 15:13 ` Andy Lutomirski
2021-10-01 18:04 ` Sohil Mehta
2021-10-01 21:29 ` Thomas Gleixner
2021-10-01 23:00 ` Sohil Mehta [this message]
2021-10-01 23:04 ` Andy Lutomirski
2021-09-13 20:01 ` [RFC PATCH 12/13] x86/uintr: Wire up the user interrupt syscalls Sohil Mehta
2021-09-13 20:01 ` [RFC PATCH 13/13] selftests/x86: Add basic tests for User IPI Sohil Mehta
2021-09-13 20:27 ` [RFC PATCH 00/13] x86 User Interrupts support Dave Hansen
2021-09-14 19:03 ` Mehta, Sohil
2021-09-23 12:19 ` Greg KH
2021-09-23 14:09 ` Greg KH
2021-09-23 14:46 ` Dave Hansen
2021-09-23 15:07 ` Greg KH
2021-09-23 23:24 ` Sohil Mehta
2021-09-23 23:09 ` Sohil Mehta
2021-09-24 0:17 ` Sohil Mehta
2021-09-23 14:39 ` Jens Axboe
2021-09-29 4:31 ` Andy Lutomirski
2021-09-30 16:30 ` Stefan Hajnoczi
2021-09-30 17:24 ` Sohil Mehta
2021-09-30 17:26 ` Andy Lutomirski
2021-10-01 16:35 ` Stefan Hajnoczi
2021-10-01 16:35 ` Stefan Hajnoczi
2021-10-01 16:41 ` Richard Henderson
2021-10-01 16:41 ` Richard Henderson
2021-09-30 16:26 ` Stefan Hajnoczi
2021-10-01 0:40 ` Sohil Mehta
2021-10-01 8:19 ` Pavel Machek
2021-11-18 22:19 ` Sohil Mehta
2021-11-16 3:49 ` Prakash Sangappa
2021-11-18 21:44 ` Sohil Mehta
2021-12-22 16:17 ` Chrisma Pakha
2022-01-07 2:08 ` Sohil Mehta
2022-01-17 1:14 ` Chrisma Pakha
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