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[88.21.202.78]) by smtp.gmail.com with ESMTPSA id y1sm4091156wrq.16.2020.02.10.23.30.59 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 10 Feb 2020 23:30:59 -0800 (PST) Subject: Re: [RFC PATCH 20/66] Hexagon generator phase 1 - C preprocessor for semantics To: Taylor Simpson , qemu-devel@nongnu.org References: <1581381644-13678-1-git-send-email-tsimpson@quicinc.com> <1581381644-13678-21-git-send-email-tsimpson@quicinc.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <412d6d0b-1541-daf5-454c-97327ddbf51d@redhat.com> Date: Tue, 11 Feb 2020 08:30:59 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.4.1 MIME-Version: 1.0 In-Reply-To: <1581381644-13678-21-git-send-email-tsimpson@quicinc.com> Content-Language: en-US X-MC-Unique: 2Brn0seyPbGyVQG8GdV3Rw-1 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.81 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: riku.voipio@iki.fi, richard.henderson@linaro.org, laurent@vivier.eu, aleksandar.m.mail@gmail.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 2/11/20 1:39 AM, Taylor Simpson wrote: > Run the C preprocessor across the instruction definition files and macro = definitoin file to expand macros and prepare the semantics_generated.pyinc = file. The > resulting file contains one entry with the semantics for each instruction= and > one line with the instruction attributes associated with each macro. >=20 > Signed-off-by: Taylor Simpson > --- > target/hexagon/gen_semantics.c | 92 +++++++++++++++++++++++++++++++++++= +++++++ > 1 file changed, 92 insertions(+) > create mode 100644 target/hexagon/gen_semantics.c >=20 > diff --git a/target/hexagon/gen_semantics.c b/target/hexagon/gen_semantic= s.c > new file mode 100644 > index 0000000..2211ae6 > --- /dev/null > +++ b/target/hexagon/gen_semantics.c > @@ -0,0 +1,92 @@ > +/* > + * Copyright (c) 2019 Qualcomm Innovation Center, Inc. All Rights Reser= ved. > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; either version 2 of the License, or > + * (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, see . > + */ > + > +/* > + * This program generates the semantics file that is processed by > + * the do_qemu.py script. We use the C preporcessor to manipulate the > + * files imported from the Hexagon architecture library. > + */ > + > +#include > +#define STRINGIZE(X) #X > + > +int main(int argc, char *argv[]) > +{ > + FILE *outfile; > + > + if (argc !=3D 2) { > + fprintf(stderr, "Usage: gen_semantics ouptputfile\n"); > + return -1; > + } > + outfile =3D fopen(argv[1], "w"); > + if (outfile =3D=3D NULL) { > + fprintf(stderr, "Cannot open %s for writing\n", argv[1]); > + return -1; > + } > + > +/* > + * Process the instruction definitions > + * Scalar core instructions have the following form > + * Q6INSN(A2_add,"Rd32=3Dadd(Rs32,Rt32)",ATTRIBS(), > + * "Add 32-bit registers", > + * { RdV=3DRsV+RtV;}) > + * HVX instructions have the following form > + * EXTINSN(V6_vinsertwr, "Vx32.w=3Dvinsert(Rt32)", > + * ATTRIBS(A_EXTENSION,A_CVI,A_CVI_VX,A_CVI_LATE,A_NOTE_MPY_RESO= URCE), > + * "Insert Word Scalar into Vector", > + * VxV.uw[0] =3D RtV;) > + */ > +#define Q6INSN(TAG, BEH, ATTRIBS, DESCR, SEM) \ > + do { \ > + fprintf(outfile, "SEMANTICS(\"%s\",%s,\"\"\"%s\"\"\")\n", \ > + #TAG, STRINGIZE(BEH), STRINGIZE(SEM)); \ > + fprintf(outfile, "ATTRIBUTES(\"%s\",\"%s\")\n", \ > + #TAG, STRINGIZE(ATTRIBS)); \ > + } while (0); > +#define EXTINSN(TAG, BEH, ATTRIBS, DESCR, SEM) \ > + do { \ > + fprintf(outfile, "EXT_SEMANTICS(\"%s\",\"%s\",%s,\"\"\"%s\"\"\")= \n", \ > + EXTSTR, #TAG, STRINGIZE(BEH), STRINGIZE(SEM)); \ > + fprintf(outfile, "ATTRIBUTES(\"%s\",\"%s\")\n", \ > + #TAG, STRINGIZE(ATTRIBS)); \ > + } while (0); > +#include "imported/allidefs.def" > +#undef Q6INSN > +#undef EXTINSN > + > +/* > + * Process the macro definitions > + * Macros definitions have the following form > + * DEF_MACRO( > + * fLSBNEW0,, > + * "P0.new[0]", > + * "Least significant bit of new P0", > + * predlog_read(thread,0), > + * (A_DOTNEW,A_IMPLICIT_READS_P0) > + * ) > + * The important part here is the attributes. Whenever an instruction > + * invokes a macro, we add the macro's attributes to the instruction. > + */ > +#define DEF_MACRO(MNAME, PARAMS, SDESC, LDESC, BEH, ATTRS) \ > + fprintf(outfile, "MACROATTRIB(\"%s\",\"\"\"%s\"\"\",\"%s\")\n", \ > + #MNAME, STRINGIZE(BEH), STRINGIZE(ATTRS)); > +#include "imported/macros.def" > +#undef DEF_MACRO > + > + fclose(outfile); > + return 0; > +} >=20 Tested-by: Philippe Mathieu-Daud=C3=A9