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[37.14.164.149]) by smtp.gmail.com with ESMTPSA id p62sm14532096wmp.10.2021.11.29.04.53.41 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 29 Nov 2021 04:53:42 -0800 (PST) Subject: Re: [PULL 0/5] target-arm queue To: Peter Maydell , qemu-devel@nongnu.org References: <20211129103915.1162989-1-peter.maydell@linaro.org> From: Richard Henderson Message-ID: <41da8594-7ef0-4be5-efb0-9f541ebc6fd0@linaro.org> Date: Mon, 29 Nov 2021 13:53:40 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.14.0 MIME-Version: 1.0 In-Reply-To: <20211129103915.1162989-1-peter.maydell@linaro.org> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::336 (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -25 X-Spam_score: -2.6 X-Spam_bar: -- X-Spam_report: (-2.6 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-1.317, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 11/29/21 11:39 AM, Peter Maydell wrote: > Hi; this is a collection of mostly GIC related patches for rc3. > The "Update cached state after LPI state changes" fix is important > and fixes what would otherwise be a regression since we enable the > ITS by default in the virt board now. The others are not regressions > but I think are OK for rc3 as they're fairly self contained (and two > of them are fixes to new-in-6.2 functionality). > > thanks > -- PMM > > The following changes since commit dd4b0de45965538f19bb40c7ddaaba384a8c613a: > > Fix version for v6.2.0-rc2 release (2021-11-26 11:58:54 +0100) > > are available in the Git repository at: > > https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20211129 > > for you to fetch changes up to 90feffad2aafe856ed2af75313b2c1669ba671e9: > > hw/intc/arm_gicv3: fix handling of LPIs in list registers (2021-11-29 10:10:21 +0000) > > ---------------------------------------------------------------- > target-arm queue: > * virt: Diagnose attempts to enable MTE or virt when using HVF accelerator > * GICv3 ITS: Allow clearing of ITS CTLR Enabled bit > * GICv3: Update cached state after LPI state changes > * GICv3: Fix handling of LPIs in list registers > > ---------------------------------------------------------------- > Alexander Graf (1): > hw/arm/virt: Extend nested and mte checks to hvf > > Peter Maydell (3): > hw/intc/arm_gicv3: Update cached state after LPI state changes > hw/intc/arm_gicv3: Add new gicv3_intid_is_special() function > hw/intc/arm_gicv3: fix handling of LPIs in list registers > > Shashi Mallela (1): > hw/intc: cannot clear GICv3 ITS CTLR[Enabled] bit > > hw/intc/gicv3_internal.h | 30 ++++++++++++++++++++++++++++++ > hw/arm/virt.c | 15 +++++++++------ > hw/intc/arm_gicv3.c | 6 ++++-- > hw/intc/arm_gicv3_cpuif.c | 9 ++++----- > hw/intc/arm_gicv3_its.c | 7 ++++--- > hw/intc/arm_gicv3_redist.c | 14 ++++++++++---- > 6 files changed, 61 insertions(+), 20 deletions(-) Applied, thanks. r~