From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.0 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 04880C10F0E for ; Mon, 15 Apr 2019 18:22:12 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id CFA83205F4 for ; Mon, 15 Apr 2019 18:22:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727823AbfDOSWL (ORCPT ); Mon, 15 Apr 2019 14:22:11 -0400 Received: from mga17.intel.com ([192.55.52.151]:13933 "EHLO mga17.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726600AbfDOSWL (ORCPT ); Mon, 15 Apr 2019 14:22:11 -0400 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga107.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 15 Apr 2019 11:22:10 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.60,354,1549958400"; d="scan'208";a="136027987" Received: from spandruv-desk.jf.intel.com ([10.54.75.31]) by orsmga006.jf.intel.com with ESMTP; 15 Apr 2019 11:22:10 -0700 Message-ID: <4205cd7a8b94a6000625b34d51bd6f960af8666f.camel@linux.intel.com> Subject: Re: [PATCH 1/2] x86: intel_pstate: Fix wrong definition of Disable Energy Efficiency Optimization bit From: Srinivas Pandruvada To: Liran Alon Cc: linux-pm@vger.kernel.org, lenb@kernel.org, rjw@rjwysocki.net, viresh.kumar@linaro.org, Boris Ostrovsky Date: Mon, 15 Apr 2019 11:22:10 -0700 In-Reply-To: <40769113-101E-43D0-BC7B-BFF7C72DD1E4@oracle.com> References: <20190414204831.93705-1-liran.alon@oracle.com> <1411b93ccc156d6712b9e9bb7ba3e03049489c02.camel@linux.intel.com> <40769113-101E-43D0-BC7B-BFF7C72DD1E4@oracle.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.28.5 (3.28.5-2.fc28) Mime-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org On Mon, 2019-04-15 at 21:13 +0300, Liran Alon wrote: > > On 15 Apr 2019, at 21:03, Srinivas Pandruvada < > > srinivas.pandruvada@linux.intel.com> wrote: > > > > On Mon, 2019-04-15 at 11:32 +0300, Liran Alon wrote: > > > > On 15 Apr 2019, at 5:00, Srinivas Pandruvada < > > > > srinivas.pandruvada@linux.intel.com> wrote: > > > > > > > > On Sun, 2019-04-14 at 23:48 +0300, Liran Alon wrote: > > > > > Bit definition can be found in Intel SDM Section 2.16 MSRS IN > > > > > THE > > > > > 6TH > > > > > GENERATION, 7TH GENERATION AND 8TH GENERATION > > > > > INTEL® CORE™ PROCESSORS, INTEL® XEON® PROCESSOR SCALABLE > > > > > FAMILY, AND FUTURE INTEL® CORE™ PROCESSORS. > > > > > > > > > > Definition of all Skylake MSR_POWER_CTL bits can also be > > > > > found at > > > > > EDK2 > > > > > source at UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h union > > > > > MSR_SKYLAKE_POWER_CTL_REGISTER. > > > > > > > > > > Fixes: 6e978b22efa1 ("cpufreq: intel_pstate: Disable energy > > > > > efficiency optimization") > > > > > > > > What are you trying to address? This bit 19 has a special > > > > meaning > > > > when > > > > system is in HWP mode. So this is correct. > > > > > > > > Bit 20 has a different meaning depending on legacy or in HWP > > > > mode. > > > > > > > > Thanks, > > > > Srinivas > > > > > > > > > > Maybe I’m misinterpreting Intel SDM, but it seems to me that bit > > > 19 > > > in MSR_POWER_CTL is always "Disable Race to Halt Optimization > > > (R/W)” > > > while bit 20 is the "Disable Energy Efficiency Optimization > > > (R/W)”. > > > > > > I didn’t find a place in Intel SDM where it is discussed that bit > > > 19 > > > have a special meaning when system is in HWP mode. > > > Can you point me to relevant place in Intel SDM? > > > > > > > SDM doesn't describe the algorithms. This is a feature of Intel > > Speed > > Shift Technology aka HWP. Both bits target disabling some energy > > efficiency features of the processor. I wish there are some better > > names of these bits. Ideas is to pick the best for a platform based > > on > > the performance needs. Here based on the experiments, setting bit > > 19 > > gave the required performance on Kaby Lake desktops. > > > > So unless you found some performance/power issue with setting of > > bit 19 > > vs bit 20, on Kaby Lake based platforms, we shouldn't change (may > > be > > rename as per SDM definition). > > > > Thanks, > > Srinivas > > I haven’t found any performance/power issue. > > The name of the bit, the function names, prints and comments just > seems to refer to bit 20 and not bit 19. > If the code intention is to manipulate "Disable Race to Halt > Optimization” bit instead of "Disable Energy Efficiency Optimization” > bit, > code should be renamed appropriately. > Is this code intention? The code change was done before SDM documented this feature, so it is not matching. Thanks, Srinivas