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Hermes SMTP Server) with ESMTPA ID 933f982256ad66195c1bc98306f1939a; Sat, 21 Jan 2023 18:06:42 +0000 (UTC) Message-ID: <420b03de-3b1a-2096-529f-d18bfdf0cf53@aol.com> Date: Sat, 21 Jan 2023 13:06:40 -0500 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.6.1 Subject: Re: [PATCH v6] xen/pt: reserve PCI slot 2 for Intel igd-passthru To: Anthony PERARD Cc: qemu-devel@nongnu.org, xen-devel@lists.xenproject.org, "Michael S. Tsirkin" , Igor Mammedov , Stefano Stabellini References: <830263507e8f1a24a94f81909d5102c4b204e938.1672615492.git.brchuckz.ref@aol.com> <830263507e8f1a24a94f81909d5102c4b204e938.1672615492.git.brchuckz@aol.com> Content-Language: en-US From: Chuck Zmudzinski In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Mailer: WebService/1.1.21096 mail.backend.jedi.jws.acl:role.jedi.acl.token.atz.jws.hermes.aol Received-SPF: pass client-ip=98.137.69.205; envelope-from=brchuckz@aim.com; helo=sonic312-24.consmr.mail.gq1.yahoo.com X-Spam_score_int: -15 X-Spam_score: -1.6 X-Spam_bar: - X-Spam_report: (-1.6 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, NICE_REPLY_A=-0.092, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 1/6/2023 9:03 AM, Anthony PERARD wrote: > On Sun, Jan 01, 2023 at 06:52:03PM -0500, Chuck Zmudzinski wrote: > > Intel specifies that the Intel IGD must occupy slot 2 on the PCI bus, > > as noted in docs/igd-assign.txt in the Qemu source code. > > > > Currently, when the xl toolstack is used to configure a Xen HVM guest with > > Intel IGD passthrough to the guest with the Qemu upstream device model, > > a Qemu emulated PCI device will occupy slot 2 and the Intel IGD will occupy > > a different slot. This problem often prevents the guest from booting. > > > > The only available workaround is not good: Configure Xen HVM guests to use > > the old and no longer maintained Qemu traditional device model available > > from xenbits.xen.org which does reserve slot 2 for the Intel IGD. > > > > To implement this feature in the Qemu upstream device model for Xen HVM > > guests, introduce the following new functions, types, and macros: > > > > * XEN_PT_DEVICE_CLASS declaration, based on the existing TYPE_XEN_PT_DEVICE > > * XEN_PT_DEVICE_GET_CLASS macro helper function for XEN_PT_DEVICE_CLASS > > * typedef XenPTQdevRealize function pointer > > * XEN_PCI_IGD_SLOT_MASK, the value of slot_reserved_mask to reserve slot 2 > > * xen_igd_reserve_slot and xen_igd_clear_slot functions > > > > The new xen_igd_reserve_slot function uses the existing slot_reserved_mask > > member of PCIBus to reserve PCI slot 2 for Xen HVM guests configured using > > the xl toolstack with the gfx_passthru option enabled, which sets the > > igd-passthru=on option to Qemu for the Xen HVM machine type. > > > > The new xen_igd_reserve_slot function also needs to be implemented in > > hw/xen/xen_pt_stub.c to prevent FTBFS during the link stage for the case > > when Qemu is configured with --enable-xen and --disable-xen-pci-passthrough, > > in which case it does nothing. > > > > The new xen_igd_clear_slot function overrides qdev->realize of the parent > > PCI device class to enable the Intel IGD to occupy slot 2 on the PCI bus > > since slot 2 was reserved by xen_igd_reserve_slot when the PCI bus was > > created in hw/i386/pc_piix.c for the case when igd-passthru=on. > > > > Move the call to xen_host_pci_device_get, and the associated error > > handling, from xen_pt_realize to the new xen_igd_clear_slot function to > > initialize the device class and vendor values which enables the checks for > > the Intel IGD to succeed. The verification that the host device is an > > Intel IGD to be passed through is done by checking the domain, bus, slot, > > and function values as well as by checking that gfx_passthru is enabled, > > the device class is VGA, and the device vendor in Intel. > > > > Signed-off-by: Chuck Zmudzinski > > > This patch looks good enough. It only changes the "xenfv" machine so it > doesn't prevent a proper fix to be done in the toolstack libxl. > > The change in xen_pci_passthrough_class_init() to try to run some code > before pci_qdev_realize() could potentially break in the future due to > been uncommon but hopefully that will be ok. > > So if no work to fix libxl appear soon, I'm ok with this patch: > > Reviewed-by: Anthony PERARD > > Thanks, > Hi Anthony, If you have been following this patch it is now at v10. Since there is another approach of patching libxl by using the "pc" machine instead of patching Qemu to fix the "xenfv" machine and there have been other changes, I did not include your Reviewed-by tag in the later versions. I presume you are not interested in dealing with the technical debt of patching libxl as proposed by this patch to libxl: https://lore.kernel.org/xen-devel/20230110073201.mdUvSjy1vKtxPriqMQuWAxIjQzf1eAqIlZgal1u3GBI@z/ because it would be more difficult to maintain and result in reduced startup performance with the Intel IGD than by patching Qemu and fixing the "xenfv" machine type with the Intel IGD directly. So are you OK with v10 of this patch? If so, you can add your Reviewed-by again to v10. The v10 has several changes since v6 as requested by other reviewers (Michael, Stefano, Igor). The v10 of the patch is here: https://lore.kernel.org/qemu-devel/d473914c4d2dc38ae87dca4b898d75b44751c9cb.1674297794.git.brchuckz@aol.com/ Thanks, Chuck