From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B9486C433FE for ; Fri, 10 Dec 2021 15:29:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235623AbhLJPco (ORCPT ); Fri, 10 Dec 2021 10:32:44 -0500 Received: from foss.arm.com ([217.140.110.172]:43280 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231651AbhLJPcn (ORCPT ); Fri, 10 Dec 2021 10:32:43 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 9343D106F; Fri, 10 Dec 2021 07:29:07 -0800 (PST) Received: from [10.57.6.190] (unknown [10.57.6.190]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 88E1A3F5A1; Fri, 10 Dec 2021 07:29:04 -0800 (PST) Subject: Re: [PATCH v1 1/4] perf tools: Prevent out-of-bounds access to registers To: Arnaldo Carvalho de Melo , kajoljain Cc: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, John Garry , Will Deacon , Mathieu Poirier , Leo Yan , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , linux-arm-kernel@lists.infradead.org, linux-csky@vger.kernel.org, linux-riscv@lists.infradead.org References: <20211201123334.679131-1-german.gomez@arm.com> <20211201123334.679131-2-german.gomez@arm.com> <6705021e-5b02-3323-7dbc-4b774f22a435@linux.ibm.com> From: German Gomez Message-ID: <42c6ea29-5904-bb8b-d9c6-a0516c3a564f@arm.com> Date: Fri, 10 Dec 2021 15:28:56 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.14.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit Content-Language: en-US Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 10/12/2021 13:38, Arnaldo Carvalho de Melo wrote: > Em Fri, Dec 10, 2021 at 02:47:49PM +0530, kajoljain escreveu: >> >> On 12/1/21 6:03 PM, German Gomez wrote: >>> The size of the cache of register values is arch-dependant >>> (PERF_REGS_MAX). This has the potential of causing an out-of-bounds >>> access in the function "perf_reg_value" if the local architecture >>> contains less registers than the one the perf.data file was recorded on. >>> >>> Since the maximum number of registers is bound by the bitmask "u64 >>> cache_mask", and the size of the cache when running under x86 systems is >>> 64 already, fix the size to 64 and add a range-check to the function >>> "perf_reg_value" to prevent out-of-bounds access. >>> >> Patch looks good to me. >> >> Reviewed-by: Kajol Jain > Thanks, applied. > > - Arnaldo Thanks Arnaldo, and the rest for the review. I did send a v2 of this patch afterwards. The only difference was to give credit to the reporter in the commit message with: Reported-by: Alexandre Truong Thanks, German > >> Thanks, >> Kajol Jain >> >>> Signed-off-by: German Gomez >>> --- >>> tools/perf/util/event.h | 5 ++++- >>> tools/perf/util/perf_regs.c | 3 +++ >>> 2 files changed, 7 insertions(+), 1 deletion(-) >>> >>> diff --git a/tools/perf/util/event.h b/tools/perf/util/event.h >>> index 95ffed663..c59331eea 100644 >>> --- a/tools/perf/util/event.h >>> +++ b/tools/perf/util/event.h >>> @@ -44,13 +44,16 @@ struct perf_event_attr; >>> /* perf sample has 16 bits size limit */ >>> #define PERF_SAMPLE_MAX_SIZE (1 << 16) >>> >>> +/* number of register is bound by the number of bits in regs_dump::mask (64) */ >>> +#define PERF_SAMPLE_REGS_CACHE_SIZE (8 * sizeof(u64)) >>> + >>> struct regs_dump { >>> u64 abi; >>> u64 mask; >>> u64 *regs; >>> >>> /* Cached values/mask filled by first register access. */ >>> - u64 cache_regs[PERF_REGS_MAX]; >>> + u64 cache_regs[PERF_SAMPLE_REGS_CACHE_SIZE]; >>> u64 cache_mask; >>> }; >>> >>> diff --git a/tools/perf/util/perf_regs.c b/tools/perf/util/perf_regs.c >>> index 5ee47ae15..06a7461ba 100644 >>> --- a/tools/perf/util/perf_regs.c >>> +++ b/tools/perf/util/perf_regs.c >>> @@ -25,6 +25,9 @@ int perf_reg_value(u64 *valp, struct regs_dump *regs, int id) >>> int i, idx = 0; >>> u64 mask = regs->mask; >>> >>> + if ((u64)id >= PERF_SAMPLE_REGS_CACHE_SIZE) >>> + return -EINVAL; >>> + >>> if (regs->cache_mask & (1ULL << id)) >>> goto out; >>> >>> From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3AFC2C433EF for ; Fri, 10 Dec 2021 15:29:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:Date: Message-ID:From:References:Cc:To:Subject:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=4RwTefNyrD3rV0Nxikf/e1OIqJiuBnU+aZY5GxOZAIM=; b=IrIpPBr7FL39jO3jncxodT4NCO c68iAN25eOCJOsUxmC88BH//bHDFucufVNAfbpWTN+4qRyBS7D7Qa5OVK7XJzGwP3ASQ7RR/8mjMM 0TqRcq+dwz58GQeiJH0vrT+TkiqsTHjuQWxvCUL9kMWKw6ejETcJ/TRlzHFOSkjHgBXSrLRmOctgw inrn05ExHXU1P0UDWeAc2jviZQ/AeB8eAXmC7fZ/0Wi1dGnfq/bhsymMMmS/UW2kyxQVmxrNxfPQF BnLl4G2mMpeubzxtiha4b/igTwzvZZuTWV2ONnsIq+rvHcOGAFQxlkBPddpjROs1dCJV6yvlETa6V a0tIN2JQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mvhpp-002R6H-M7; Fri, 10 Dec 2021 15:29:21 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mvhpc-002R3t-Gl; Fri, 10 Dec 2021 15:29:10 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 9343D106F; Fri, 10 Dec 2021 07:29:07 -0800 (PST) Received: from [10.57.6.190] (unknown [10.57.6.190]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 88E1A3F5A1; Fri, 10 Dec 2021 07:29:04 -0800 (PST) Subject: Re: [PATCH v1 1/4] perf tools: Prevent out-of-bounds access to registers To: Arnaldo Carvalho de Melo , kajoljain Cc: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, John Garry , Will Deacon , Mathieu Poirier , Leo Yan , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , linux-arm-kernel@lists.infradead.org, linux-csky@vger.kernel.org, linux-riscv@lists.infradead.org References: <20211201123334.679131-1-german.gomez@arm.com> <20211201123334.679131-2-german.gomez@arm.com> <6705021e-5b02-3323-7dbc-4b774f22a435@linux.ibm.com> From: German Gomez Message-ID: <42c6ea29-5904-bb8b-d9c6-a0516c3a564f@arm.com> Date: Fri, 10 Dec 2021 15:28:56 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.14.0 MIME-Version: 1.0 In-Reply-To: Content-Language: en-US X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211210_072908_687728_1F8D5226 X-CRM114-Status: GOOD ( 18.43 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On 10/12/2021 13:38, Arnaldo Carvalho de Melo wrote: > Em Fri, Dec 10, 2021 at 02:47:49PM +0530, kajoljain escreveu: >> >> On 12/1/21 6:03 PM, German Gomez wrote: >>> The size of the cache of register values is arch-dependant >>> (PERF_REGS_MAX). This has the potential of causing an out-of-bounds >>> access in the function "perf_reg_value" if the local architecture >>> contains less registers than the one the perf.data file was recorded on. >>> >>> Since the maximum number of registers is bound by the bitmask "u64 >>> cache_mask", and the size of the cache when running under x86 systems is >>> 64 already, fix the size to 64 and add a range-check to the function >>> "perf_reg_value" to prevent out-of-bounds access. >>> >> Patch looks good to me. >> >> Reviewed-by: Kajol Jain > Thanks, applied. > > - Arnaldo Thanks Arnaldo, and the rest for the review. I did send a v2 of this patch afterwards. The only difference was to give credit to the reporter in the commit message with: Reported-by: Alexandre Truong Thanks, German > >> Thanks, >> Kajol Jain >> >>> Signed-off-by: German Gomez >>> --- >>> tools/perf/util/event.h | 5 ++++- >>> tools/perf/util/perf_regs.c | 3 +++ >>> 2 files changed, 7 insertions(+), 1 deletion(-) >>> >>> diff --git a/tools/perf/util/event.h b/tools/perf/util/event.h >>> index 95ffed663..c59331eea 100644 >>> --- a/tools/perf/util/event.h >>> +++ b/tools/perf/util/event.h >>> @@ -44,13 +44,16 @@ struct perf_event_attr; >>> /* perf sample has 16 bits size limit */ >>> #define PERF_SAMPLE_MAX_SIZE (1 << 16) >>> >>> +/* number of register is bound by the number of bits in regs_dump::mask (64) */ >>> +#define PERF_SAMPLE_REGS_CACHE_SIZE (8 * sizeof(u64)) >>> + >>> struct regs_dump { >>> u64 abi; >>> u64 mask; >>> u64 *regs; >>> >>> /* Cached values/mask filled by first register access. */ >>> - u64 cache_regs[PERF_REGS_MAX]; >>> + u64 cache_regs[PERF_SAMPLE_REGS_CACHE_SIZE]; >>> u64 cache_mask; >>> }; >>> >>> diff --git a/tools/perf/util/perf_regs.c b/tools/perf/util/perf_regs.c >>> index 5ee47ae15..06a7461ba 100644 >>> --- a/tools/perf/util/perf_regs.c >>> +++ b/tools/perf/util/perf_regs.c >>> @@ -25,6 +25,9 @@ int perf_reg_value(u64 *valp, struct regs_dump *regs, int id) >>> int i, idx = 0; >>> u64 mask = regs->mask; >>> >>> + if ((u64)id >= PERF_SAMPLE_REGS_CACHE_SIZE) >>> + return -EINVAL; >>> + >>> if (regs->cache_mask & (1ULL << id)) >>> goto out; >>> >>> _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D56A2C433F5 for ; Fri, 10 Dec 2021 15:30:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:Date: Message-ID:From:References:Cc:To:Subject:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=2Y2jMfUUZRwxFebrkzyFt3mhFP+Q54U9J1igDTxSw8Q=; b=eFul5Q1uVndKcOilJJ6dP8gUrC T53eApKn2olDf1zlzep+cmyPPnYlqdtvDrvcAMHL07WP87pFgmjFvq7LZ8ONZ6qgP4ie3m42gRdQy T/C6KoeZqB0hgyNJzvwuNbCq7Iz+6ZPxSVGRSvoG0D5lBN5AoTGd827GRNavnn92PhPYKNcMJAgmK LywSjx7Z/PMJ8iYJTKfV0LU93ZK1vVqKD6bAFQLz14uAEsVr8UhE9tqH1Q65guRfJ7eDVLqfqQkjn iSG/nGnmqAEnagaF9/F0mc+ho6GR3TzljqlUYn8b+VcC9WxXHqMTVBtQM3Irh3VBM3Q6UQ+gzLdKh gvIiarkw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mvhpg-002R4t-Bt; Fri, 10 Dec 2021 15:29:12 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mvhpc-002R3t-Gl; Fri, 10 Dec 2021 15:29:10 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 9343D106F; Fri, 10 Dec 2021 07:29:07 -0800 (PST) Received: from [10.57.6.190] (unknown [10.57.6.190]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 88E1A3F5A1; Fri, 10 Dec 2021 07:29:04 -0800 (PST) Subject: Re: [PATCH v1 1/4] perf tools: Prevent out-of-bounds access to registers To: Arnaldo Carvalho de Melo , kajoljain Cc: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, John Garry , Will Deacon , Mathieu Poirier , Leo Yan , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , linux-arm-kernel@lists.infradead.org, linux-csky@vger.kernel.org, linux-riscv@lists.infradead.org References: <20211201123334.679131-1-german.gomez@arm.com> <20211201123334.679131-2-german.gomez@arm.com> <6705021e-5b02-3323-7dbc-4b774f22a435@linux.ibm.com> From: German Gomez Message-ID: <42c6ea29-5904-bb8b-d9c6-a0516c3a564f@arm.com> Date: Fri, 10 Dec 2021 15:28:56 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.14.0 MIME-Version: 1.0 In-Reply-To: Content-Language: en-US X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211210_072908_687728_1F8D5226 X-CRM114-Status: GOOD ( 18.43 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 10/12/2021 13:38, Arnaldo Carvalho de Melo wrote: > Em Fri, Dec 10, 2021 at 02:47:49PM +0530, kajoljain escreveu: >> >> On 12/1/21 6:03 PM, German Gomez wrote: >>> The size of the cache of register values is arch-dependant >>> (PERF_REGS_MAX). This has the potential of causing an out-of-bounds >>> access in the function "perf_reg_value" if the local architecture >>> contains less registers than the one the perf.data file was recorded on. >>> >>> Since the maximum number of registers is bound by the bitmask "u64 >>> cache_mask", and the size of the cache when running under x86 systems is >>> 64 already, fix the size to 64 and add a range-check to the function >>> "perf_reg_value" to prevent out-of-bounds access. >>> >> Patch looks good to me. >> >> Reviewed-by: Kajol Jain > Thanks, applied. > > - Arnaldo Thanks Arnaldo, and the rest for the review. I did send a v2 of this patch afterwards. The only difference was to give credit to the reporter in the commit message with: Reported-by: Alexandre Truong Thanks, German > >> Thanks, >> Kajol Jain >> >>> Signed-off-by: German Gomez >>> --- >>> tools/perf/util/event.h | 5 ++++- >>> tools/perf/util/perf_regs.c | 3 +++ >>> 2 files changed, 7 insertions(+), 1 deletion(-) >>> >>> diff --git a/tools/perf/util/event.h b/tools/perf/util/event.h >>> index 95ffed663..c59331eea 100644 >>> --- a/tools/perf/util/event.h >>> +++ b/tools/perf/util/event.h >>> @@ -44,13 +44,16 @@ struct perf_event_attr; >>> /* perf sample has 16 bits size limit */ >>> #define PERF_SAMPLE_MAX_SIZE (1 << 16) >>> >>> +/* number of register is bound by the number of bits in regs_dump::mask (64) */ >>> +#define PERF_SAMPLE_REGS_CACHE_SIZE (8 * sizeof(u64)) >>> + >>> struct regs_dump { >>> u64 abi; >>> u64 mask; >>> u64 *regs; >>> >>> /* Cached values/mask filled by first register access. */ >>> - u64 cache_regs[PERF_REGS_MAX]; >>> + u64 cache_regs[PERF_SAMPLE_REGS_CACHE_SIZE]; >>> u64 cache_mask; >>> }; >>> >>> diff --git a/tools/perf/util/perf_regs.c b/tools/perf/util/perf_regs.c >>> index 5ee47ae15..06a7461ba 100644 >>> --- a/tools/perf/util/perf_regs.c >>> +++ b/tools/perf/util/perf_regs.c >>> @@ -25,6 +25,9 @@ int perf_reg_value(u64 *valp, struct regs_dump *regs, int id) >>> int i, idx = 0; >>> u64 mask = regs->mask; >>> >>> + if ((u64)id >= PERF_SAMPLE_REGS_CACHE_SIZE) >>> + return -EINVAL; >>> + >>> if (regs->cache_mask & (1ULL << id)) >>> goto out; >>> >>> _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel