From mboxrd@z Thu Jan  1 00:00:00 1970
From: David Wu <david.wu@rock-chips.com>
Date: Sat, 9 May 2020 11:32:33 +0800
Subject: [PATCH 3/8] net: dwc_eth_qos: Add option "snps, reset-gpio"
 phy-rst gpio for stm32
In-Reply-To: <309a8600-1383-7f6f-51c7-1a1d6fb54580@rock-chips.com>
References: <20200430103656.29728-1-david.wu@rock-chips.com>
 <20200430103656.29728-4-david.wu@rock-chips.com>
 <5429ce30-171a-6ec5-846c-fb5fcb5a5a74@wwwdotorg.org>
 <309a8600-1383-7f6f-51c7-1a1d6fb54580@rock-chips.com>
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Hi Stephen,

? 2020/5/9 ??10:41, David Wu ??:
> 
> The kernel's ./Documentation/devicetree/bindings/net/stmmac.txt mentions
> that Required properties:
> 
> - phy-mode: See ethernet.txt file in the same directory.
> - snps,reset-gpio?????? gpio number for phy reset.
> - snps,reset-active-low boolean flag to indicate if phy reset is active 
> low.
> - snps,reset-delays-us? is triplet of delays
>  ??????? The 1st cell is reset pre-delay in micro seconds.
>  ??????? The 2nd cell is reset pulse in micro seconds.
>  ??????? The 3rd cell is reset post-delay in micro seconds.

Sorry, I just saw you replying again before, stmmac.txt was found, this 
reply email please discard.