From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34608) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bDtlC-0001W1-8t for qemu-devel@nongnu.org; Fri, 17 Jun 2016 09:24:38 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bDtl9-0004z8-OG for qemu-devel@nongnu.org; Fri, 17 Jun 2016 09:24:33 -0400 References: <1466169069-29375-1-git-send-email-real@ispras.ru> <1466169069-29375-9-git-send-email-real@ispras.ru> From: Paolo Bonzini Message-ID: <4367d527-50a7-e340-1746-2acd714c2b5c@redhat.com> Date: Fri, 17 Jun 2016 15:24:17 +0200 MIME-Version: 1.0 In-Reply-To: <1466169069-29375-9-git-send-email-real@ispras.ru> Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH 08/13] port92: handle A20 IRQ as GPIO List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Efimov Vasily , qemu-devel@nongnu.org Cc: John Snow , qemu-block@nongnu.org, Gerd Hoffmann , "Michael S. Tsirkin" , Kevin Wolf , Max Reitz , Richard Henderson , Eduardo Habkost , Peter Maydell , Kirill Batuzov On 17/06/2016 15:11, Efimov Vasily wrote: > The port92 device has outgouing IRQ line A20. Currently the IRQ is referenced > by a pointer which normally is set during machine initialization. The > pointer is never changed at runtime. Hence, common GPIO model can be applied > to A20 IRQ line. Note that checking for IRQ to be connected as in > previous version of code is not required qemu_set_irq will do it. > > Signed-off-by: Efimov Vasily > --- > hw/i386/pc.c | 10 +++++----- > 1 file changed, 5 insertions(+), 5 deletions(-) > > diff --git a/hw/i386/pc.c b/hw/i386/pc.c > index 7198ed5..e8b92ea 100644 > --- a/hw/i386/pc.c > +++ b/hw/i386/pc.c > @@ -505,7 +505,7 @@ typedef struct Port92State { > > MemoryRegion io; > uint8_t outport; > - qemu_irq *a20_out; > + qemu_irq a20_out; > } Port92State; > > static void port92_write(void *opaque, hwaddr addr, uint64_t val, > @@ -516,7 +516,7 @@ static void port92_write(void *opaque, hwaddr addr, uint64_t val, > > DPRINTF("port92: write 0x%02" PRIx64 "\n", val); > s->outport = val; > - qemu_set_irq(*s->a20_out, (val >> 1) & 1); > + qemu_set_irq(s->a20_out, (val >> 1) & 1); > if ((val & 1) && !(oldval & 1)) { > qemu_system_reset_request(); > } > @@ -535,9 +535,7 @@ static uint64_t port92_read(void *opaque, hwaddr addr, > > static void port92_init(ISADevice *dev, qemu_irq *a20_out) > { > - Port92State *s = PORT92(dev); > - > - s->a20_out = a20_out; > + qdev_connect_gpio_out(DEVICE(dev), 0, *a20_out); > } > > static const VMStateDescription vmstate_port92_isa = { > @@ -574,6 +572,8 @@ static void port92_initfn(Object *obj) > memory_region_init_io(&s->io, OBJECT(s), &port92_ops, s, "port92", 1); > > s->outport = 0; > + > + qdev_init_gpio_out(DEVICE(obj), &s->a20_out, 1); > } > > static void port92_realizefn(DeviceState *dev, Error **errp) > Same as previous patch---please use named GPIOs. Paolo