From mboxrd@z Thu Jan 1 00:00:00 1970 From: Stefano Babic Date: Sun, 12 Feb 2017 09:45:38 +0100 Subject: [U-Boot] [PATCH V2 03/20] imx: mx7ulp: add iomux driver to support IOMUXC0 and IOMUXC1 In-Reply-To: <1482833066-29291-4-git-send-email-peng.fan@nxp.com> References: <1482833066-29291-1-git-send-email-peng.fan@nxp.com> <1482833066-29291-4-git-send-email-peng.fan@nxp.com> Message-ID: <437194fa-0072-8ef8-ef2c-417a1b8c2e80@denx.de> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Hi Peng, On 27/12/2016 11:04, Peng Fan wrote: > Add a new driver under ULP directory to support its IOMUXC > controllers. The ULP has two IOMUXC, the IOMUXC0 is used > for M4 domain, while IOMUXC1 is for A7. We set IOMUXC1 as > the default IOMUX in this driver. Any pins in IOMUXC0 needs > to configure with IOMUX_CONFIG_MPORTS in its mux_mode field. > > Signed-off-by: Ye Li > Signed-off-by: Peng Fan > Cc: Stefano Babic > --- > > V2: > none > > arch/arm/cpu/armv7/mx7ulp/Makefile | 8 +++ > arch/arm/cpu/armv7/mx7ulp/iomux.c | 70 +++++++++++++++++++++++ > arch/arm/include/asm/arch-mx7ulp/iomux.h | 95 ++++++++++++++++++++++++++++++++ > 3 files changed, 173 insertions(+) > create mode 100644 arch/arm/cpu/armv7/mx7ulp/Makefile > create mode 100644 arch/arm/cpu/armv7/mx7ulp/iomux.c > create mode 100644 arch/arm/include/asm/arch-mx7ulp/iomux.h > > diff --git a/arch/arm/cpu/armv7/mx7ulp/Makefile b/arch/arm/cpu/armv7/mx7ulp/Makefile > new file mode 100644 > index 0000000..be038e7 > --- /dev/null > +++ b/arch/arm/cpu/armv7/mx7ulp/Makefile > @@ -0,0 +1,8 @@ > +# > +# (C) Copyright 2016 Freescale Semiconductor, Inc. > +# > +# SPDX-License-Identifier: GPL-2.0+ > +# > +# > + > +obj-y := iomux.o > diff --git a/arch/arm/cpu/armv7/mx7ulp/iomux.c b/arch/arm/cpu/armv7/mx7ulp/iomux.c > new file mode 100644 > index 0000000..1eba24e > --- /dev/null > +++ b/arch/arm/cpu/armv7/mx7ulp/iomux.c > @@ -0,0 +1,70 @@ > +/* > + * Copyright (C) 2016 Freescale Semiconductor, Inc. > + * > + * SPDX-License-Identifier: GPL-2.0+ > + */ > +#include > +#include > +#include > +#include > + > +static void *base = (void *)IOMUXC_BASE_ADDR; > + > +/* > + * iomuxc0 base address. In imx7ulp-pins.h, > + * the offsets of pins in iomuxc0 are from 0xD000, > + * so we set the base address to (0x4103D000 - 0xD000 = 0x41030000) > + */ > +static void *base_mports = (void *)(AIPS0_BASE + 0x30000); > + > +/* > + * configures a single pad in the iomuxer > + */ > +void mx7ulp_iomux_setup_pad(iomux_cfg_t pad) > +{ > + u32 mux_ctrl_ofs = (pad & MUX_CTRL_OFS_MASK) >> MUX_CTRL_OFS_SHIFT; > + u32 mux_mode = (pad & MUX_MODE_MASK) >> MUX_MODE_SHIFT; > + u32 sel_input_ofs = > + (pad & MUX_SEL_INPUT_OFS_MASK) >> MUX_SEL_INPUT_OFS_SHIFT; > + u32 sel_input = > + (pad & MUX_SEL_INPUT_MASK) >> MUX_SEL_INPUT_SHIFT; > + u32 pad_ctrl_ofs = mux_ctrl_ofs; > + u32 pad_ctrl = (pad & MUX_PAD_CTRL_MASK) >> MUX_PAD_CTRL_SHIFT; > + > + debug("[PAD CFG] = 0x%16llX \r\n\tmux_ctl = 0x%X(0x%X) sel_input = 0x%X(0x%X) pad_ctrl = 0x%X(0x%X)\r\n", > + pad, mux_ctrl_ofs, mux_mode, sel_input_ofs, sel_input, > + pad_ctrl_ofs, pad_ctrl); > + > + if (mux_mode & IOMUX_CONFIG_MPORTS) { > + mux_mode &= ~IOMUX_CONFIG_MPORTS; > + base = base_mports; > + } else { > + base = (void *)IOMUXC_BASE_ADDR; > + } > + > + __raw_writel(((mux_mode << IOMUXC_PCR_MUX_ALT_SHIFT) & > + IOMUXC_PCR_MUX_ALT_MASK), base + mux_ctrl_ofs); > + > + if (sel_input_ofs) > + __raw_writel((sel_input << IOMUXC_PSMI_IMUX_ALT_SHIFT), > + base + sel_input_ofs); > + > + if (!(pad_ctrl & NO_PAD_CTRL)) > + __raw_writel(((mux_mode << IOMUXC_PCR_MUX_ALT_SHIFT) & > + IOMUXC_PCR_MUX_ALT_MASK) | > + (pad_ctrl & (~IOMUXC_PCR_MUX_ALT_MASK)), > + base + pad_ctrl_ofs); > +} > + > +/* configures a list of pads within declared with IOMUX_PADS macro */ > +void mx7ulp_iomux_setup_multiple_pads(iomux_cfg_t const *pad_list, > + unsigned count) > +{ > + iomux_cfg_t const *p = pad_list; > + int i; > + > + for (i = 0; i < count; i++) { > + mx7ulp_iomux_setup_pad(*p); > + p++; > + } > +} > diff --git a/arch/arm/include/asm/arch-mx7ulp/iomux.h b/arch/arm/include/asm/arch-mx7ulp/iomux.h > new file mode 100644 > index 0000000..a2307db > --- /dev/null > +++ b/arch/arm/include/asm/arch-mx7ulp/iomux.h > @@ -0,0 +1,95 @@ > +/* > + * Based on Linux i.MX iomux-v3.h file: > + * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH, > + * > + * > + * Copyright (C) 2016 Freescale Semiconductor, Inc. > + * > + * SPDX-License-Identifier: GPL-2.0+ > + */ > + > +#ifndef __MACH_IOMUX_H__ > +#define __MACH_IOMUX_H__ > + > +/* > + * build IOMUX_PAD structure > + * > + * This iomux scheme is based around pads, which are the physical balls > + * on the processor. > + * > + * - Each pad has a pad control register (IOMUXC_SW_PAD_CTRL_x) which controls > + * things like driving strength and pullup/pulldown. > + * - Each pad can have but not necessarily does have an output routing register > + * (IOMUXC_SW_MUX_CTL_PAD_x). > + * - Each pad can have but not necessarily does have an input routing register > + * (IOMUXC_x_SELECT_INPUT) > + * > + * The three register sets do not have a fixed offset to each other, > + * hence we order this table by pad control registers (which all pads > + * have) and put the optional i/o routing registers into additional > + * fields. > + * > + * The naming convention for the pad modes is SOC_PAD___ > + * If or refers to a GPIO, it is named GPIO__ > + * > + * IOMUX/PAD Bit field definitions > + * > + * MUX_CTRL_OFS: 0..15 (16) > + * SEL_INPUT_OFS: 16..31 (16) > + * MUX_MODE: 32..37 (6) > + * SEL_INP: 38..41 (4) > + * PAD_CTRL + NO_PAD_CTRL: 42..60 (19) > + * reserved: 61-63 (3) > +*/ > + > +typedef u64 iomux_cfg_t; > + > +#define MUX_CTRL_OFS_SHIFT 0 > +#define MUX_CTRL_OFS_MASK ((iomux_cfg_t)0xffff << MUX_CTRL_OFS_SHIFT) > +#define MUX_SEL_INPUT_OFS_SHIFT 16 > +#define MUX_SEL_INPUT_OFS_MASK ((iomux_cfg_t)0xffff << \ > + MUX_SEL_INPUT_OFS_SHIFT) > + > +#define MUX_MODE_SHIFT 32 > +#define MUX_MODE_MASK ((iomux_cfg_t)0x3f << MUX_MODE_SHIFT) > +#define MUX_SEL_INPUT_SHIFT 38 > +#define MUX_SEL_INPUT_MASK ((iomux_cfg_t)0xf << MUX_SEL_INPUT_SHIFT) > +#define MUX_PAD_CTRL_SHIFT 42 > +#define MUX_PAD_CTRL_MASK ((iomux_cfg_t)0x7ffff << MUX_PAD_CTRL_SHIFT) > + > +#define MUX_PAD_CTRL(x) ((iomux_cfg_t)(x) << MUX_PAD_CTRL_SHIFT) > + > +#define IOMUX_PAD(pad_ctrl_ofs, mux_ctrl_ofs, mux_mode, sel_input_ofs, \ > + sel_input, pad_ctrl) \ > + (((iomux_cfg_t)(mux_ctrl_ofs) << MUX_CTRL_OFS_SHIFT) | \ > + ((iomux_cfg_t)(mux_mode) << MUX_MODE_SHIFT) | \ > + ((iomux_cfg_t)(pad_ctrl) << MUX_PAD_CTRL_SHIFT) | \ > + ((iomux_cfg_t)(sel_input_ofs) << MUX_SEL_INPUT_OFS_SHIFT)| \ > + ((iomux_cfg_t)(sel_input) << MUX_SEL_INPUT_SHIFT)) > + > +#define NEW_PAD_CTRL(cfg, pad) (((cfg) & ~MUX_PAD_CTRL_MASK) | \ > + MUX_PAD_CTRL(pad)) > + > + > +#define IOMUX_CONFIG_MPORTS 0x20 > +#define MUX_MODE_MPORTS ((iomux_v3_cfg_t)IOMUX_CONFIG_MPORTS << \ > + MUX_MODE_SHIFT) > + > +/* Bit definition below needs to be fixed acccording to ulp rm */ > + > +#define NO_PAD_CTRL (1 << 18) > +#define PAD_CTL_OBE_ENABLE (1 << 17) > +#define PAD_CTL_IBE_ENABLE (1 << 16) > +#define PAD_CTL_DSE (1 << 6) > +#define PAD_CTL_ODE (1 << 5) > +#define PAD_CTL_SRE_FAST (0 << 2) > +#define PAD_CTL_SRE_SLOW (1 << 2) > +#define PAD_CTL_PUE (1 << 1) > +#define PAD_CTL_PUS_UP ((1 << 0) | PAD_CTL_PUE) > +#define PAD_CTL_PUS_DOWN ((0 << 0) | PAD_CTL_PUE) > + > + > +void mx7ulp_iomux_setup_pad(iomux_cfg_t pad); > +void mx7ulp_iomux_setup_multiple_pads(iomux_cfg_t const *pad_list, > + unsigned count); > +#endif /* __MACH_IOMUX_H__*/ > Thought about if this code can go to iomux_v3.c in imx-common, but functions here are simple and merging together makes the code more difficult to read. So I have not a better idea for it. IMHO it is ok to put it in a separate directory as you did. Reviewed-by : Stefano Babic Best regards, Stefano Babic -- ===================================================================== DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de =====================================================================