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[120.151.179.201]) by smtp.gmail.com with ESMTPSA id u18sm218699pfi.185.2022.01.25.17.17.35 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 25 Jan 2022 17:17:40 -0800 (PST) Subject: Re: [PATCH v2] target/riscv: Enable bitmanip Zicbo[m,z,p] instructions To: Christoph Muellner , Atish Patra , Anup Patel , =?UTF-8?B?RnLDqWTDqXJpYyBQw6l0cm90?= , Palmer Dabbelt , Alistair Francis , Bin Meng , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Philipp Tomsich References: <20220124140023.1165850-1-cmuellner@linux.com> From: Richard Henderson Message-ID: <437cfc65-bf60-2524-387e-cca2f8aff4c6@linaro.org> Date: Wed, 26 Jan 2022 12:17:33 +1100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.14.0 MIME-Version: 1.0 In-Reply-To: <20220124140023.1165850-1-cmuellner@linux.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::1029 (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::1029; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1029.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 1/25/22 1:00 AM, Christoph Muellner wrote: > -ori ............ ..... 110 ..... 0010011 @i > +{ > + [ > + # *** RV32 Zicbop Sandard Extension (hints in the ori-space) *** > + prefetch_i ....... 00000 ..... 110 00000 0010011 @cbo_pref > + prefetch_r ....... 00001 ..... 110 00000 0010011 @cbo_pref > + prefetch_w ....... 00011 ..... 110 00000 0010011 @cbo_pref > + ] > + > + # *** RV32I ori *** > + ori ............ ..... 110 ..... 0010011 @i > +} Hmm. I would simply add a comment about these, without changing any code. They are implemented as nops, so there's no point in the decode distinguishing these from the "normal" nop that ori r0, rx, y will (not) generate. > +static bool trans_cbo_clean(DisasContext *ctx, arg_cbo_clean *a) > +{ > + REQUIRE_ZICBOM(ctx); > + gen_helper_cbo_clean(cpu_env, cpu_gpr[a->rs1]); > + return true; > +} > + > +static bool trans_cbo_flush(DisasContext *ctx, arg_cbo_flush *a) > +{ > + REQUIRE_ZICBOM(ctx); > + gen_helper_cbo_clean(cpu_env, cpu_gpr[a->rs1]); > + return true; > +} Clean and flush are the same thing? > +/* helper_zicbo_envcfg > + * > + * Raise virtual exceptions and illegal instruction exceptions for > + * Zicbo[mz] instructions based on the settings of [mhs]envcfg. > + */ > +static void helper_zicbo_envcfg(CPURISCVState *env, target_ulong envbits) > +{ > +#ifndef CONFIG_USER_ONLY > + target_ulong ra = GETPC(); GETPC may only be called from the outermost helper function (the one directly invoked from tcg generated code). This will not unwind the cpu state correctly. > +static void helper_zicbom_access(CPURISCVState *env, target_ulong address) > +{ > + void* phost; > + int ret = TLB_INVALID_MASK; > + MMUAccessType access_type = MMU_DATA_LOAD; > + target_ulong ra = GETPC(); Likewise. > + address &= ~(RISCV_CPU(env)->cfg.cbolen - 1); RISCV_CPU is to be applied to CPUState, not CPUArchState. You've dereferenced the wrong pointer. You want env_archcpu() instead. Pull that out to a local variable for clarity and do not... > + /* Zeroize the block */ > + memset(mem, 0, RISCV_CPU(env)->cfg.cbolen); ... call it twice. Also, s/zeroize/zero/. r~