Re: [PATCH]: Re: qla1280.c broken on SGI visws, PCI coherency problem

From: Michael Reed <mdr@sgi.com>
To: Jeremy Higdon <jeremy@sgi.com>
Cc: James Bottomley <James.Bottomley@SteelEye.com>,
	pazke@donpac.ru, Michael Joosten <michael.joosten@c-lab.de>,
	linux-scsi@vger.kernel.org
Subject: Re: [PATCH]: Re: qla1280.c broken on SGI visws, PCI coherency	problem
Date: Tue, 13 Dec 2005 21:16:46 -0600	[thread overview]
Message-ID: <439F8E9E.1090608@sgi.com> (raw)
In-Reply-To: <20051214013938.GB185272@sgi.com>

Jeremy and I spoke offline.  We have a REALLY STRONG belief that
the platform is broken with regard to PIO vs. mmio.  We believe
that PIOs on VISWS post, just like mmio.  No SGI designed box
that we're aware of ever implemented PIO semantics.  It had to
be implemented in software.  IT'S NOT A PC!

The best suggestion we can make is find a chip on the bridge
and read a register from that to implement mmiowb() for VISWS.
Just please don't pull the mmiowb() or augment it with a posting read.

Thanks,
 Mike

Jeremy Higdon wrote:
> On Tue, Dec 13, 2005 at 08:50:13AM -0600, James Bottomley wrote:
>> On Tue, 2005-12-13 at 07:22 -0600, Michael Reed wrote:
>>> I believe the biggest issue with VISWS is that it appears to need
>>> mmiowb() and we likely don't know how to implement it.  Hence, for
>>> that platform, it would make sense to replace the mmiowb() with a
>>> posting read.
>> Well, there's an easy way to tell ... the reason for the mmiowb in the
>> qla1280 driver is supposed to be an SMP race, according to the
>> description, so if it fails on UP as well there's something else going
>> on here ...
> 
> The 320 was available with two CPUs, and though the post doesn't say
> what this particular one had, it likely had two.  The original post
> also indicated a problem with a two-cpu motherboard, though I don't
> think that was the 320 (VisWS).
> 
>> I'm still suspicious because the mmiowb() in this driver replaced a
>> posted write flush instruction, which altered the behaviour of the
>> driver.  The qla1280 is just rare enough that it might have taken this
>> long to notice ...
> 
> The 12160 is in most Altix machines and behaves just like a 1280.
> If there were a problem with it in this context, we'd know about it.
> 
> I'm still betting on the old problem (time moves downward):
> 
> 	cpu A	lock
> 		posted pio write X
> 		unlock
> 	cpu B	lock
> 		posted pio write Y
> 		unlock
> 	PCI bus retire pio write Y
> 		retire pio write X
> 
> The Qlogic architecture doesn't like this.
> 
> jeremy
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