[Intel-gfx] [PATCH i-g-t 00/11] Fixes for i915_hangman and gem_exec_capture

[Intel-gfx] [PATCH i-g-t 00/11] Fixes for i915_hangman and gem_exec_capture

[John.C.Harrison]

From: John Harrison <John.C.Harrison@Intel.com>

Fix a bunch of issues with i915_hangman and gem_exec_capture with the
ultimate aim of making them pass on GuC enabled platforms.

Signed-off-by: John Harrison <John.C.Harrison@Intel.com>


John Harrison (11):
  tests/i915/i915_hangman: Add descriptions
  lib/hang: Fix igt_require_hang_ring to work with all engines
  tests/i915/i915_hangman: Update capture test to use engine structure
  tests/i915/i915_hangman: Explicitly test per engine reset vs full GPU
    reset
  tests/i915/i915_hangman: Add uevent test & fix detector
  tests/i915/i915_hangman: Use the correct context in
    hangcheck_unterminated
  tests/i915/i915_hangman: Add alive-ness test after error capture
  lib/store: Refactor common store code into helper function
  tests/i915/i915_hangman: Remove reliance on context persistance
  tests/i915/i915_hangman: Run background task on all engines
  tests/i915/gem_exec_fence: Configure correct context

 lib/igt_aux.c               |   7 ++
 lib/igt_gt.c                |   6 +-
 lib/igt_gt.h                |   2 +-
 lib/igt_store.c             | 114 ++++++++++++++++++
 lib/igt_store.h             |  30 +++++
 lib/meson.build             |   1 +
 tests/i915/gem_exec_fence.c |  79 +------------
 tests/i915/i915_hangman.c   | 223 +++++++++++++++++++++++++++++-------
 8 files changed, 343 insertions(+), 119 deletions(-)
 create mode 100644 lib/igt_store.c
 create mode 100644 lib/igt_store.h

-- 
2.25.1

[Intel-gfx] [PATCH i-g-t 01/11] tests/i915/i915_hangman: Add descriptions

[John.C.Harrison]

From: John Harrison <John.C.Harrison@Intel.com>

Added descriptions of the various sub-tests and the test as a whole.

Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
---
 tests/i915/i915_hangman.c | 11 +++++++++--
 1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/tests/i915/i915_hangman.c b/tests/i915/i915_hangman.c
index 4c18c22db..025bb8713 100644
--- a/tests/i915/i915_hangman.c
+++ b/tests/i915/i915_hangman.c
@@ -46,6 +46,8 @@
 static int device = -1;
 static int sysfs = -1;
 
+IGT_TEST_DESCRIPTION("Tests for hang detection and recovery");
+
 static bool has_error_state(int dir)
 {
 	bool result;
@@ -315,9 +317,9 @@ static void hangcheck_unterminated(void)
 
 	gem_execbuf(device, &execbuf);
 	if (gem_wait(device, handle, &timeout_ns) != 0) {
-		/* need to manually trigger an hang to clean before failing */
+		/* need to manually trigger a hang to clean before failing */
 		igt_force_gpu_reset(device);
-		igt_assert_f(0, "unterminated batch did not trigger an hang!");
+		igt_assert_f(0, "unterminated batch did not trigger a hang!");
 	}
 }
 
@@ -341,9 +343,11 @@ igt_main
 		igt_require(has_error_state(sysfs));
 	}
 
+	igt_describe("Basic error capture");
 	igt_subtest("error-state-basic")
 		test_error_state_basic();
 
+	igt_describe("Per engine error capture");
 	igt_subtest_with_dynamic("error-state-capture") {
 		for_each_ctx_engine(device, ctx, e) {
 			igt_dynamic_f("%s", e->name)
@@ -351,6 +355,7 @@ igt_main
 		}
 	}
 
+	igt_describe("Per engine hang recovery (spin)");
 	igt_subtest_with_dynamic("engine-hang") {
                 int has_gpu_reset = 0;
 		struct drm_i915_getparam gp = {
@@ -369,6 +374,7 @@ igt_main
 		}
 	}
 
+	igt_describe("Per engine hang recovery (invalid CS)");
 	igt_subtest_with_dynamic("engine-error") {
 		int has_gpu_reset = 0;
 		struct drm_i915_getparam gp = {
@@ -386,6 +392,7 @@ igt_main
 		}
 	}
 
+	igt_describe("Check that executing unintialised memory causes a hang");
 	igt_subtest("hangcheck-unterminated")
 		hangcheck_unterminated();
 
-- 
2.25.1

[igt-dev] [PATCH i-g-t 01/11] tests/i915/i915_hangman: Add descriptions

[John.C.Harrison]

From: John Harrison <John.C.Harrison@Intel.com>

Added descriptions of the various sub-tests and the test as a whole.

Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
---
 tests/i915/i915_hangman.c | 11 +++++++++--
 1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/tests/i915/i915_hangman.c b/tests/i915/i915_hangman.c
index 4c18c22db..025bb8713 100644
--- a/tests/i915/i915_hangman.c
+++ b/tests/i915/i915_hangman.c
@@ -46,6 +46,8 @@
 static int device = -1;
 static int sysfs = -1;
 
+IGT_TEST_DESCRIPTION("Tests for hang detection and recovery");
+
 static bool has_error_state(int dir)
 {
 	bool result;
@@ -315,9 +317,9 @@ static void hangcheck_unterminated(void)
 
 	gem_execbuf(device, &execbuf);
 	if (gem_wait(device, handle, &timeout_ns) != 0) {
-		/* need to manually trigger an hang to clean before failing */
+		/* need to manually trigger a hang to clean before failing */
 		igt_force_gpu_reset(device);
-		igt_assert_f(0, "unterminated batch did not trigger an hang!");
+		igt_assert_f(0, "unterminated batch did not trigger a hang!");
 	}
 }
 
@@ -341,9 +343,11 @@ igt_main
 		igt_require(has_error_state(sysfs));
 	}
 
+	igt_describe("Basic error capture");
 	igt_subtest("error-state-basic")
 		test_error_state_basic();
 
+	igt_describe("Per engine error capture");
 	igt_subtest_with_dynamic("error-state-capture") {
 		for_each_ctx_engine(device, ctx, e) {
 			igt_dynamic_f("%s", e->name)
@@ -351,6 +355,7 @@ igt_main
 		}
 	}
 
+	igt_describe("Per engine hang recovery (spin)");
 	igt_subtest_with_dynamic("engine-hang") {
                 int has_gpu_reset = 0;
 		struct drm_i915_getparam gp = {
@@ -369,6 +374,7 @@ igt_main
 		}
 	}
 
+	igt_describe("Per engine hang recovery (invalid CS)");
 	igt_subtest_with_dynamic("engine-error") {
 		int has_gpu_reset = 0;
 		struct drm_i915_getparam gp = {
@@ -386,6 +392,7 @@ igt_main
 		}
 	}
 
+	igt_describe("Check that executing unintialised memory causes a hang");
 	igt_subtest("hangcheck-unterminated")
 		hangcheck_unterminated();
 
-- 
2.25.1

[Intel-gfx] [PATCH i-g-t 02/11] lib/hang: Fix igt_require_hang_ring to work with all engines

[John.C.Harrison]

From: John Harrison <John.C.Harrison@Intel.com>

The above function was checking for valid rings via the old interface.
The new scheme is to check for engines on contexts as there are now
more engines than could be supported.

Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
---
 lib/igt_gt.c              | 6 +++---
 lib/igt_gt.h              | 2 +-
 tests/i915/i915_hangman.c | 6 +++---
 3 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/lib/igt_gt.c b/lib/igt_gt.c
index 7c7df95ee..50da512f2 100644
--- a/lib/igt_gt.c
+++ b/lib/igt_gt.c
@@ -122,12 +122,12 @@ static void eat_error_state(int dev)
  * to be done under hang injection.
  * Default: false
  */
-void igt_require_hang_ring(int fd, int ring)
+void igt_require_hang_ring(int fd, uint32_t ctx, int ring)
 {
 	if (!igt_check_boolean_env_var("IGT_HANG", true))
 		igt_skip("hang injection disabled by user [IGT_HANG=0]\n");
 
-	gem_require_ring(fd, ring);
+        igt_require(gem_context_has_engine(fd, ctx, ring));
 	gem_context_require_bannable(fd);
 	if (!igt_check_boolean_env_var("IGT_HANG_WITHOUT_RESET", false))
 		igt_require(has_gpu_reset(fd));
@@ -290,7 +290,7 @@ static igt_hang_t __igt_hang_ctx(int fd, uint64_t ahnd, uint32_t ctx, int ring,
 	igt_spin_t *spin;
 	unsigned ban;
 
-	igt_require_hang_ring(fd, ring);
+	igt_require_hang_ring(fd, ctx, ring);
 
 	/* check if non-default ctx submission is allowed */
 	igt_require(ctx == 0 || has_ctx_exec(fd, ring, ctx));
diff --git a/lib/igt_gt.h b/lib/igt_gt.h
index c5059817b..3d10349e4 100644
--- a/lib/igt_gt.h
+++ b/lib/igt_gt.h
@@ -31,7 +31,7 @@
 #include "i915/i915_drm_local.h"
 #include "i915_drm.h"
 
-void igt_require_hang_ring(int fd, int ring);
+void igt_require_hang_ring(int fd, uint32_t ctx, int ring);
 
 typedef struct igt_hang {
 	igt_spin_t *spin;
diff --git a/tests/i915/i915_hangman.c b/tests/i915/i915_hangman.c
index 025bb8713..24d3b2739 100644
--- a/tests/i915/i915_hangman.c
+++ b/tests/i915/i915_hangman.c
@@ -295,7 +295,7 @@ test_engine_hang(const intel_ctx_t *ctx,
  * case and it takes a lot more time to wrap, so the acthd can potentially keep
  * increasing for a long time
  */
-static void hangcheck_unterminated(void)
+static void hangcheck_unterminated(const intel_ctx_t *ctx)
 {
 	/* timeout needs to be greater than ~5*hangcheck */
 	int64_t timeout_ns = 100ull * NSEC_PER_SEC; /* 100 seconds */
@@ -304,7 +304,7 @@ static void hangcheck_unterminated(void)
 	uint32_t handle;
 
 	igt_require(gem_uses_full_ppgtt(device));
-	igt_require_hang_ring(device, 0);
+	igt_require_hang_ring(device, ctx->id, 0);
 
 	handle = gem_create(device, 4096);
 
@@ -394,7 +394,7 @@ igt_main
 
 	igt_describe("Check that executing unintialised memory causes a hang");
 	igt_subtest("hangcheck-unterminated")
-		hangcheck_unterminated();
+		hangcheck_unterminated(ctx);
 
 	igt_fixture {
 		igt_disallow_hang(device, hang);
-- 
2.25.1

[Intel-gfx] [PATCH i-g-t 03/11] tests/i915/i915_hangman: Update capture test to use engine structure

[John.C.Harrison]

From: John Harrison <John.C.Harrison@Intel.com>

The capture test was still using old style ring_id and ring_name
(derived from the engine structure at the higher level). Update it to
just take the engine structure directly.

Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
---
 tests/i915/i915_hangman.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/tests/i915/i915_hangman.c b/tests/i915/i915_hangman.c
index 24d3b2739..bd787d7b4 100644
--- a/tests/i915/i915_hangman.c
+++ b/tests/i915/i915_hangman.c
@@ -207,8 +207,8 @@ static void check_error_state(const char *expected_ring_name,
 	igt_assert(found);
 }
 
-static void test_error_state_capture(const intel_ctx_t *ctx, unsigned ring_id,
-				     const char *ring_name)
+static void test_error_state_capture(const intel_ctx_t *ctx,
+				     const struct intel_execution_engine2 *e)
 {
 	uint32_t *batch;
 	igt_hang_t hang;
@@ -217,7 +217,7 @@ static void test_error_state_capture(const intel_ctx_t *ctx, unsigned ring_id,
 
 	clear_error_state();
 
-	hang = igt_hang_ctx_with_ahnd(device, ahnd, ctx->id, ring_id,
+	hang = igt_hang_ctx_with_ahnd(device, ahnd, ctx->id, e->flags,
 				      HANG_ALLOW_CAPTURE);
 	offset = hang.spin->obj[IGT_SPIN_BATCH].offset;
 
@@ -226,7 +226,7 @@ static void test_error_state_capture(const intel_ctx_t *ctx, unsigned ring_id,
 
 	igt_post_hang_ring(device, hang);
 
-	check_error_state(ring_name, offset, batch);
+	check_error_state(e->name, offset, batch);
 	munmap(batch, 4096);
 	put_ahnd(ahnd);
 }
@@ -351,7 +351,7 @@ igt_main
 	igt_subtest_with_dynamic("error-state-capture") {
 		for_each_ctx_engine(device, ctx, e) {
 			igt_dynamic_f("%s", e->name)
-				test_error_state_capture(ctx, e->flags, e->name);
+				test_error_state_capture(ctx, e);
 		}
 	}
 
-- 
2.25.1

[igt-dev] [PATCH i-g-t 03/11] tests/i915/i915_hangman: Update capture test to use engine structure

[John.C.Harrison]

From: John Harrison <John.C.Harrison@Intel.com>

The capture test was still using old style ring_id and ring_name
(derived from the engine structure at the higher level). Update it to
just take the engine structure directly.

Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
---
 tests/i915/i915_hangman.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/tests/i915/i915_hangman.c b/tests/i915/i915_hangman.c
index 24d3b2739..bd787d7b4 100644
--- a/tests/i915/i915_hangman.c
+++ b/tests/i915/i915_hangman.c
@@ -207,8 +207,8 @@ static void check_error_state(const char *expected_ring_name,
 	igt_assert(found);
 }
 
-static void test_error_state_capture(const intel_ctx_t *ctx, unsigned ring_id,
-				     const char *ring_name)
+static void test_error_state_capture(const intel_ctx_t *ctx,
+				     const struct intel_execution_engine2 *e)
 {
 	uint32_t *batch;
 	igt_hang_t hang;
@@ -217,7 +217,7 @@ static void test_error_state_capture(const intel_ctx_t *ctx, unsigned ring_id,
 
 	clear_error_state();
 
-	hang = igt_hang_ctx_with_ahnd(device, ahnd, ctx->id, ring_id,
+	hang = igt_hang_ctx_with_ahnd(device, ahnd, ctx->id, e->flags,
 				      HANG_ALLOW_CAPTURE);
 	offset = hang.spin->obj[IGT_SPIN_BATCH].offset;
 
@@ -226,7 +226,7 @@ static void test_error_state_capture(const intel_ctx_t *ctx, unsigned ring_id,
 
 	igt_post_hang_ring(device, hang);
 
-	check_error_state(ring_name, offset, batch);
+	check_error_state(e->name, offset, batch);
 	munmap(batch, 4096);
 	put_ahnd(ahnd);
 }
@@ -351,7 +351,7 @@ igt_main
 	igt_subtest_with_dynamic("error-state-capture") {
 		for_each_ctx_engine(device, ctx, e) {
 			igt_dynamic_f("%s", e->name)
-				test_error_state_capture(ctx, e->flags, e->name);
+				test_error_state_capture(ctx, e);
 		}
 	}
 
-- 
2.25.1

[Intel-gfx] [PATCH i-g-t 04/11] tests/i915/i915_hangman: Explicitly test per engine reset vs full GPU reset

[John.C.Harrison]

From: John Harrison <John.C.Harrison@Intel.com>

Although the hangman test was ensuring that *some* reset functionality
was enabled, it did not differentiate what kind. The infrastructure
required to choose between per engine reset or full GT reset was
recently added. So update this test to use it as well.

Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
---
 tests/i915/i915_hangman.c | 77 +++++++++++++++++++++++++--------------
 1 file changed, 50 insertions(+), 27 deletions(-)

diff --git a/tests/i915/i915_hangman.c b/tests/i915/i915_hangman.c
index bd787d7b4..f8a48337c 100644
--- a/tests/i915/i915_hangman.c
+++ b/tests/i915/i915_hangman.c
@@ -323,40 +323,26 @@ static void hangcheck_unterminated(const intel_ctx_t *ctx)
 	}
 }
 
-igt_main
+static void do_tests(const char *name, const char *prefix,
+		     const intel_ctx_t *ctx)
 {
 	const struct intel_execution_engine2 *e;
-	const intel_ctx_t *ctx;
-	igt_hang_t hang = {};
-
-	igt_fixture {
-		device = drm_open_driver(DRIVER_INTEL);
-		igt_require_gem(device);
-
-		ctx = intel_ctx_create_all_physical(device);
-
-		hang = igt_allow_hang(device, ctx->id, HANG_ALLOW_CAPTURE);
-
-		sysfs = igt_sysfs_open(device);
-		igt_assert(sysfs != -1);
+	char buff[256];
 
-		igt_require(has_error_state(sysfs));
-	}
-
-	igt_describe("Basic error capture");
-	igt_subtest("error-state-basic")
-		test_error_state_basic();
-
-	igt_describe("Per engine error capture");
-	igt_subtest_with_dynamic("error-state-capture") {
+	snprintf(buff, sizeof(buff), "Per engine error capture (%s reset)", name);
+	igt_describe(buff);
+	snprintf(buff, sizeof(buff), "%s-error-state-capture", prefix);
+	igt_subtest_with_dynamic(buff) {
 		for_each_ctx_engine(device, ctx, e) {
 			igt_dynamic_f("%s", e->name)
 				test_error_state_capture(ctx, e);
 		}
 	}
 
-	igt_describe("Per engine hang recovery (spin)");
-	igt_subtest_with_dynamic("engine-hang") {
+	snprintf(buff, sizeof(buff), "Per engine hang recovery (spin, %s reset)", name);
+	igt_describe(buff);
+	snprintf(buff, sizeof(buff), "%s-engine-hang", prefix);
+	igt_subtest_with_dynamic(buff) {
                 int has_gpu_reset = 0;
 		struct drm_i915_getparam gp = {
 			.param = I915_PARAM_HAS_GPU_RESET,
@@ -374,8 +360,10 @@ igt_main
 		}
 	}
 
-	igt_describe("Per engine hang recovery (invalid CS)");
-	igt_subtest_with_dynamic("engine-error") {
+	snprintf(buff, sizeof(buff), "Per engine hang recovery (invalid CS, %s reset)", name);
+	igt_describe(buff);
+	snprintf(buff, sizeof(buff), "%s-engine-error", prefix);
+	igt_subtest_with_dynamic(buff) {
 		int has_gpu_reset = 0;
 		struct drm_i915_getparam gp = {
 			.param = I915_PARAM_HAS_GPU_RESET,
@@ -391,11 +379,46 @@ igt_main
 				test_engine_hang(ctx, e, IGT_SPIN_INVALID_CS);
 		}
 	}
+}
+
+igt_main
+{
+	const intel_ctx_t *ctx;
+	igt_hang_t hang = {};
+
+	igt_fixture {
+		device = drm_open_driver(DRIVER_INTEL);
+		igt_require_gem(device);
+
+		ctx = intel_ctx_create_all_physical(device);
+
+		hang = igt_allow_hang(device, ctx->id, HANG_ALLOW_CAPTURE);
+
+		sysfs = igt_sysfs_open(device);
+		igt_assert(sysfs != -1);
+
+		igt_require(has_error_state(sysfs));
+	}
+
+	igt_describe("Basic error capture");
+	igt_subtest("error-state-basic")
+		test_error_state_basic();
+
 
 	igt_describe("Check that executing unintialised memory causes a hang");
 	igt_subtest("hangcheck-unterminated")
 		hangcheck_unterminated(ctx);
 
+	do_tests("GT", "gt", ctx);
+
+	igt_fixture {
+		igt_disallow_hang(device, hang);
+
+		hang = igt_allow_hang(device, ctx->id, HANG_ALLOW_CAPTURE | HANG_WANT_ENGINE_RESET);
+	}
+
+	do_tests("engine", "engine", ctx);
+
 	igt_fixture {
 		igt_disallow_hang(device, hang);
 		intel_ctx_destroy(device, ctx);
-- 
2.25.1

[Intel-gfx] [PATCH i-g-t 05/11] tests/i915/i915_hangman: Add uevent test & fix detector

[John.C.Harrison]

From: John Harrison <John.C.Harrison@Intel.com>

Some of the IGT framework relies on receving a uevent when a hang
occurs. So add a test that this actually works.

While testing this, noticed that hangs could sometimes be missed
because the uevent was (presumably) still in flight by the time the
handler was de-registered. So add an extra delay during cleanup to
give the uevent chance to arrive.

Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
---
 lib/igt_aux.c             |  7 +++++++
 tests/i915/i915_hangman.c | 43 +++++++++++++++++++++++++++++++++++++++
 2 files changed, 50 insertions(+)

diff --git a/lib/igt_aux.c b/lib/igt_aux.c
index c247a1aa4..03cc38c93 100644
--- a/lib/igt_aux.c
+++ b/lib/igt_aux.c
@@ -523,6 +523,13 @@ void igt_fork_hang_detector(int fd)
 
 void igt_stop_hang_detector(void)
 {
+	/*
+	 * Give the uevent time to arrive. No sleep at all misses about 20% of
+	 * hangs (at least, in the i915_hangman/detector test). A sleep of 1ms
+	 * seems to miss about 2%, 10ms loses <1%, so 100ms should be safe.
+	 */
+	usleep(100 * 1000);
+
 	igt_stop_helper(&hang_detector);
 }
 
diff --git a/tests/i915/i915_hangman.c b/tests/i915/i915_hangman.c
index f8a48337c..2dd4e1e9f 100644
--- a/tests/i915/i915_hangman.c
+++ b/tests/i915/i915_hangman.c
@@ -31,6 +31,7 @@
 #include <sys/stat.h>
 #include <sys/types.h>
 #include <fcntl.h>
+#include <signal.h>
 
 #include "i915/gem.h"
 #include "i915/gem_create.h"
@@ -289,6 +290,38 @@ test_engine_hang(const intel_ctx_t *ctx,
 	put_ahnd(ahnd);
 }
 
+static int hang_count;
+
+static void sig_io(int sig)
+{
+	hang_count++;
+}
+
+static void test_hang_detector(const intel_ctx_t *ctx,
+			       const struct intel_execution_engine2 *e)
+{
+	igt_hang_t hang;
+	uint64_t ahnd = get_reloc_ahnd(device, ctx->id);
+
+	hang_count = 0;
+
+	igt_fork_hang_detector(device);
+
+	/* Steal the signal handler */
+	signal(SIGIO, sig_io);
+
+	/* Make a hang... */
+	hang = igt_hang_ctx_with_ahnd(device, ahnd, ctx->id, e->flags, 0);
+
+	igt_post_hang_ring(device, hang);
+	put_ahnd(ahnd);
+
+	igt_stop_hang_detector();
+
+	/* Did it work? */
+	igt_assert(hang_count == 1);
+}
+
 /* This test covers the case where we end up in an uninitialised area of the
  * ppgtt and keep executing through it. This is particularly relevant if 48b
  * ppgtt is enabled because the ppgtt is massively bigger compared to the 32b
@@ -409,6 +442,16 @@ igt_main
 	igt_subtest("hangcheck-unterminated")
 		hangcheck_unterminated(ctx);
 
+	igt_describe("Check that hang detector works");
+	igt_subtest_with_dynamic("detector") {
+		const struct intel_execution_engine2 *e;
+
+		for_each_ctx_engine(device, ctx, e) {
+			igt_dynamic_f("%s", e->name)
+				test_hang_detector(ctx, e);
+		}
+	}
+
 	do_tests("GT", "gt", ctx);
 
 	igt_fixture {
-- 
2.25.1

[igt-dev] [PATCH i-g-t 05/11] tests/i915/i915_hangman: Add uevent test & fix detector

[John.C.Harrison]

From: John Harrison <John.C.Harrison@Intel.com>

Some of the IGT framework relies on receving a uevent when a hang
occurs. So add a test that this actually works.

While testing this, noticed that hangs could sometimes be missed
because the uevent was (presumably) still in flight by the time the
handler was de-registered. So add an extra delay during cleanup to
give the uevent chance to arrive.

Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
---
 lib/igt_aux.c             |  7 +++++++
 tests/i915/i915_hangman.c | 43 +++++++++++++++++++++++++++++++++++++++
 2 files changed, 50 insertions(+)

diff --git a/lib/igt_aux.c b/lib/igt_aux.c
index c247a1aa4..03cc38c93 100644
--- a/lib/igt_aux.c
+++ b/lib/igt_aux.c
@@ -523,6 +523,13 @@ void igt_fork_hang_detector(int fd)
 
 void igt_stop_hang_detector(void)
 {
+	/*
+	 * Give the uevent time to arrive. No sleep at all misses about 20% of
+	 * hangs (at least, in the i915_hangman/detector test). A sleep of 1ms
+	 * seems to miss about 2%, 10ms loses <1%, so 100ms should be safe.
+	 */
+	usleep(100 * 1000);
+
 	igt_stop_helper(&hang_detector);
 }
 
diff --git a/tests/i915/i915_hangman.c b/tests/i915/i915_hangman.c
index f8a48337c..2dd4e1e9f 100644
--- a/tests/i915/i915_hangman.c
+++ b/tests/i915/i915_hangman.c
@@ -31,6 +31,7 @@
 #include <sys/stat.h>
 #include <sys/types.h>
 #include <fcntl.h>
+#include <signal.h>
 
 #include "i915/gem.h"
 #include "i915/gem_create.h"
@@ -289,6 +290,38 @@ test_engine_hang(const intel_ctx_t *ctx,
 	put_ahnd(ahnd);
 }
 
+static int hang_count;
+
+static void sig_io(int sig)
+{
+	hang_count++;
+}
+
+static void test_hang_detector(const intel_ctx_t *ctx,
+			       const struct intel_execution_engine2 *e)
+{
+	igt_hang_t hang;
+	uint64_t ahnd = get_reloc_ahnd(device, ctx->id);
+
+	hang_count = 0;
+
+	igt_fork_hang_detector(device);
+
+	/* Steal the signal handler */
+	signal(SIGIO, sig_io);
+
+	/* Make a hang... */
+	hang = igt_hang_ctx_with_ahnd(device, ahnd, ctx->id, e->flags, 0);
+
+	igt_post_hang_ring(device, hang);
+	put_ahnd(ahnd);
+
+	igt_stop_hang_detector();
+
+	/* Did it work? */
+	igt_assert(hang_count == 1);
+}
+
 /* This test covers the case where we end up in an uninitialised area of the
  * ppgtt and keep executing through it. This is particularly relevant if 48b
  * ppgtt is enabled because the ppgtt is massively bigger compared to the 32b
@@ -409,6 +442,16 @@ igt_main
 	igt_subtest("hangcheck-unterminated")
 		hangcheck_unterminated(ctx);
 
+	igt_describe("Check that hang detector works");
+	igt_subtest_with_dynamic("detector") {
+		const struct intel_execution_engine2 *e;
+
+		for_each_ctx_engine(device, ctx, e) {
+			igt_dynamic_f("%s", e->name)
+				test_hang_detector(ctx, e);
+		}
+	}
+
 	do_tests("GT", "gt", ctx);
 
 	igt_fixture {
-- 
2.25.1

[Intel-gfx] [PATCH i-g-t 06/11] tests/i915/i915_hangman: Use the correct context in hangcheck_unterminated

[John.C.Harrison]

From: John Harrison <John.C.Harrison@Intel.com>

The hangman framework sets up a context that is valid for all engines
and has things like banning disabled. The 'unterminated' test then
ignores it and uses the default context. Fix that.

Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
---
 tests/i915/i915_hangman.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/tests/i915/i915_hangman.c b/tests/i915/i915_hangman.c
index 2dd4e1e9f..b77705206 100644
--- a/tests/i915/i915_hangman.c
+++ b/tests/i915/i915_hangman.c
@@ -347,6 +347,7 @@ static void hangcheck_unterminated(const intel_ctx_t *ctx)
 	memset(&execbuf, 0, sizeof(execbuf));
 	execbuf.buffers_ptr = (uintptr_t)&gem_exec;
 	execbuf.buffer_count = 1;
+	execbuf.rsvd1 = ctx->id;
 
 	gem_execbuf(device, &execbuf);
 	if (gem_wait(device, handle, &timeout_ns) != 0) {
-- 
2.25.1

[igt-dev] [PATCH i-g-t 06/11] tests/i915/i915_hangman: Use the correct context in hangcheck_unterminated

[John.C.Harrison]

From: John Harrison <John.C.Harrison@Intel.com>

The hangman framework sets up a context that is valid for all engines
and has things like banning disabled. The 'unterminated' test then
ignores it and uses the default context. Fix that.

Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
---
 tests/i915/i915_hangman.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/tests/i915/i915_hangman.c b/tests/i915/i915_hangman.c
index 2dd4e1e9f..b77705206 100644
--- a/tests/i915/i915_hangman.c
+++ b/tests/i915/i915_hangman.c
@@ -347,6 +347,7 @@ static void hangcheck_unterminated(const intel_ctx_t *ctx)
 	memset(&execbuf, 0, sizeof(execbuf));
 	execbuf.buffers_ptr = (uintptr_t)&gem_exec;
 	execbuf.buffer_count = 1;
+	execbuf.rsvd1 = ctx->id;
 
 	gem_execbuf(device, &execbuf);
 	if (gem_wait(device, handle, &timeout_ns) != 0) {
-- 
2.25.1

[Intel-gfx] [PATCH i-g-t 07/11] tests/i915/i915_hangman: Add alive-ness test after error capture

[John.C.Harrison]

From: John Harrison <John.C.Harrison@Intel.com>

Added a an extra step to the i915_hangman tests to check that the
system is still alive after the hang and recovery. This submits a
simple batch to each engine which does a write to memory and checks
that the write occurred.

Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
---
 tests/i915/i915_hangman.c | 115 ++++++++++++++++++++++++++++++++++++++
 1 file changed, 115 insertions(+)

diff --git a/tests/i915/i915_hangman.c b/tests/i915/i915_hangman.c
index b77705206..20653b479 100644
--- a/tests/i915/i915_hangman.c
+++ b/tests/i915/i915_hangman.c
@@ -47,8 +47,113 @@
 static int device = -1;
 static int sysfs = -1;
 
+#define OFFSET_ALIVE	10
+
 IGT_TEST_DESCRIPTION("Tests for hang detection and recovery");
 
+/* Requires master for STORE_DWORD on gen4/5 */
+static void store(int fd, const struct intel_execution_engine2 *e,
+		  int fence, uint32_t target, unsigned offset_value)
+{
+	const int SCRATCH = 0;
+	const int BATCH = 1;
+	const int gen = intel_gen(intel_get_drm_devid(fd));
+	struct drm_i915_gem_exec_object2 obj[2];
+	struct drm_i915_gem_relocation_entry reloc;
+	struct drm_i915_gem_execbuffer2 execbuf;
+	uint32_t batch[16];
+	int i;
+
+	memset(&execbuf, 0, sizeof(execbuf));
+	execbuf.buffers_ptr = to_user_pointer(obj);
+	execbuf.buffer_count = ARRAY_SIZE(obj);
+	execbuf.flags = e->flags;
+	if (fence != -1) {
+		execbuf.flags |= I915_EXEC_FENCE_IN;
+		execbuf.rsvd2 = fence;
+	}
+	if (gen < 6)
+		execbuf.flags |= I915_EXEC_SECURE;
+
+	memset(obj, 0, sizeof(obj));
+	obj[SCRATCH].handle = target;
+
+	obj[BATCH].handle = gem_create(fd, 4096);
+	obj[BATCH].relocs_ptr = to_user_pointer(&reloc);
+	obj[BATCH].relocation_count = 1;
+	memset(&reloc, 0, sizeof(reloc));
+
+	i = 0;
+	reloc.target_handle = obj[SCRATCH].handle;
+	reloc.presumed_offset = -1;
+	reloc.offset = sizeof(uint32_t) * (i + 1);
+	reloc.delta = sizeof(uint32_t) * offset_value;
+	reloc.read_domains = I915_GEM_DOMAIN_INSTRUCTION;
+	reloc.write_domain = I915_GEM_DOMAIN_INSTRUCTION;
+	batch[i] = MI_STORE_DWORD_IMM | (gen < 6 ? 1 << 22 : 0);
+	if (gen >= 8) {
+		batch[++i] = reloc.delta;
+		batch[++i] = 0;
+	} else if (gen >= 4) {
+		batch[++i] = 0;
+		batch[++i] = reloc.delta;
+		reloc.offset += sizeof(uint32_t);
+	} else {
+		batch[i]--;
+		batch[++i] = reloc.delta;
+	}
+	batch[++i] = offset_value;
+	batch[++i] = MI_BATCH_BUFFER_END;
+	gem_write(fd, obj[BATCH].handle, 0, batch, sizeof(batch));
+	gem_execbuf(fd, &execbuf);
+	gem_close(fd, obj[BATCH].handle);
+}
+
+static void check_alive(void)
+{
+	const struct intel_execution_engine2 *engine;
+	const intel_ctx_t *ctx;
+	uint32_t scratch, *out;
+	int fd, i = 0;
+	uint64_t ahnd;
+
+	fd = drm_open_driver(DRIVER_INTEL);
+	igt_require(gem_class_can_store_dword(fd, 0));
+
+	ctx = intel_ctx_create_all_physical(fd);
+	ahnd = get_reloc_ahnd(fd, ctx->id);
+	scratch = gem_create(fd, 4096);
+	out = gem_mmap__wc(fd, scratch, 0, 4096, PROT_WRITE);
+	gem_set_domain(fd, scratch,
+			I915_GEM_DOMAIN_GTT, I915_GEM_DOMAIN_GTT);
+
+	for_each_physical_engine(fd, engine) {
+		igt_assert_eq_u32(out[i + OFFSET_ALIVE], 0);
+		i++;
+	}
+
+	i = 0;
+	for_each_ctx_engine(fd, ctx, engine) {
+		if (!gem_class_can_store_dword(fd, engine->class))
+			continue;
+
+		/* +OFFSET_ALIVE to ensure engine zero doesn't get a false negative */
+		store(fd, engine, -1, scratch, i + OFFSET_ALIVE);
+		i++;
+	}
+
+	gem_set_domain(fd, scratch, I915_GEM_DOMAIN_GTT, 0);
+
+	while (i--)
+		igt_assert_eq_u32(out[i + OFFSET_ALIVE], i + OFFSET_ALIVE);
+
+	munmap(out, 4096);
+	gem_close(fd, scratch);
+	put_ahnd(ahnd);
+	intel_ctx_destroy(fd, ctx);
+	close(fd);
+}
+
 static bool has_error_state(int dir)
 {
 	bool result;
@@ -230,6 +335,8 @@ static void test_error_state_capture(const intel_ctx_t *ctx,
 	check_error_state(e->name, offset, batch);
 	munmap(batch, 4096);
 	put_ahnd(ahnd);
+
+	check_alive();
 }
 
 static void
@@ -288,6 +395,8 @@ test_engine_hang(const intel_ctx_t *ctx,
 		put_ahnd(ahndN);
 	}
 	put_ahnd(ahnd);
+
+	check_alive();
 }
 
 static int hang_count;
@@ -320,6 +429,8 @@ static void test_hang_detector(const intel_ctx_t *ctx,
 
 	/* Did it work? */
 	igt_assert(hang_count == 1);
+
+	check_alive();
 }
 
 /* This test covers the case where we end up in an uninitialised area of the
@@ -355,6 +466,8 @@ static void hangcheck_unterminated(const intel_ctx_t *ctx)
 		igt_force_gpu_reset(device);
 		igt_assert_f(0, "unterminated batch did not trigger a hang!");
 	}
+
+	check_alive();
 }
 
 static void do_tests(const char *name, const char *prefix,
@@ -432,6 +545,8 @@ igt_main
 		igt_assert(sysfs != -1);
 
 		igt_require(has_error_state(sysfs));
+
+		gem_require_mmap_wc(device);
 	}
 
 	igt_describe("Basic error capture");
-- 
2.25.1

[igt-dev] [PATCH i-g-t 07/11] tests/i915/i915_hangman: Add alive-ness test after error capture

[John.C.Harrison]

From: John Harrison <John.C.Harrison@Intel.com>

Added a an extra step to the i915_hangman tests to check that the
system is still alive after the hang and recovery. This submits a
simple batch to each engine which does a write to memory and checks
that the write occurred.

Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
---
 tests/i915/i915_hangman.c | 115 ++++++++++++++++++++++++++++++++++++++
 1 file changed, 115 insertions(+)

diff --git a/tests/i915/i915_hangman.c b/tests/i915/i915_hangman.c
index b77705206..20653b479 100644
--- a/tests/i915/i915_hangman.c
+++ b/tests/i915/i915_hangman.c
@@ -47,8 +47,113 @@
 static int device = -1;
 static int sysfs = -1;
 
+#define OFFSET_ALIVE	10
+
 IGT_TEST_DESCRIPTION("Tests for hang detection and recovery");
 
+/* Requires master for STORE_DWORD on gen4/5 */
+static void store(int fd, const struct intel_execution_engine2 *e,
+		  int fence, uint32_t target, unsigned offset_value)
+{
+	const int SCRATCH = 0;
+	const int BATCH = 1;
+	const int gen = intel_gen(intel_get_drm_devid(fd));
+	struct drm_i915_gem_exec_object2 obj[2];
+	struct drm_i915_gem_relocation_entry reloc;
+	struct drm_i915_gem_execbuffer2 execbuf;
+	uint32_t batch[16];
+	int i;
+
+	memset(&execbuf, 0, sizeof(execbuf));
+	execbuf.buffers_ptr = to_user_pointer(obj);
+	execbuf.buffer_count = ARRAY_SIZE(obj);
+	execbuf.flags = e->flags;
+	if (fence != -1) {
+		execbuf.flags |= I915_EXEC_FENCE_IN;
+		execbuf.rsvd2 = fence;
+	}
+	if (gen < 6)
+		execbuf.flags |= I915_EXEC_SECURE;
+
+	memset(obj, 0, sizeof(obj));
+	obj[SCRATCH].handle = target;
+
+	obj[BATCH].handle = gem_create(fd, 4096);
+	obj[BATCH].relocs_ptr = to_user_pointer(&reloc);
+	obj[BATCH].relocation_count = 1;
+	memset(&reloc, 0, sizeof(reloc));
+
+	i = 0;
+	reloc.target_handle = obj[SCRATCH].handle;
+	reloc.presumed_offset = -1;
+	reloc.offset = sizeof(uint32_t) * (i + 1);
+	reloc.delta = sizeof(uint32_t) * offset_value;
+	reloc.read_domains = I915_GEM_DOMAIN_INSTRUCTION;
+	reloc.write_domain = I915_GEM_DOMAIN_INSTRUCTION;
+	batch[i] = MI_STORE_DWORD_IMM | (gen < 6 ? 1 << 22 : 0);
+	if (gen >= 8) {
+		batch[++i] = reloc.delta;
+		batch[++i] = 0;
+	} else if (gen >= 4) {
+		batch[++i] = 0;
+		batch[++i] = reloc.delta;
+		reloc.offset += sizeof(uint32_t);
+	} else {
+		batch[i]--;
+		batch[++i] = reloc.delta;
+	}
+	batch[++i] = offset_value;
+	batch[++i] = MI_BATCH_BUFFER_END;
+	gem_write(fd, obj[BATCH].handle, 0, batch, sizeof(batch));
+	gem_execbuf(fd, &execbuf);
+	gem_close(fd, obj[BATCH].handle);
+}
+
+static void check_alive(void)
+{
+	const struct intel_execution_engine2 *engine;
+	const intel_ctx_t *ctx;
+	uint32_t scratch, *out;
+	int fd, i = 0;
+	uint64_t ahnd;
+
+	fd = drm_open_driver(DRIVER_INTEL);
+	igt_require(gem_class_can_store_dword(fd, 0));
+
+	ctx = intel_ctx_create_all_physical(fd);
+	ahnd = get_reloc_ahnd(fd, ctx->id);
+	scratch = gem_create(fd, 4096);
+	out = gem_mmap__wc(fd, scratch, 0, 4096, PROT_WRITE);
+	gem_set_domain(fd, scratch,
+			I915_GEM_DOMAIN_GTT, I915_GEM_DOMAIN_GTT);
+
+	for_each_physical_engine(fd, engine) {
+		igt_assert_eq_u32(out[i + OFFSET_ALIVE], 0);
+		i++;
+	}
+
+	i = 0;
+	for_each_ctx_engine(fd, ctx, engine) {
+		if (!gem_class_can_store_dword(fd, engine->class))
+			continue;
+
+		/* +OFFSET_ALIVE to ensure engine zero doesn't get a false negative */
+		store(fd, engine, -1, scratch, i + OFFSET_ALIVE);
+		i++;
+	}
+
+	gem_set_domain(fd, scratch, I915_GEM_DOMAIN_GTT, 0);
+
+	while (i--)
+		igt_assert_eq_u32(out[i + OFFSET_ALIVE], i + OFFSET_ALIVE);
+
+	munmap(out, 4096);
+	gem_close(fd, scratch);
+	put_ahnd(ahnd);
+	intel_ctx_destroy(fd, ctx);
+	close(fd);
+}
+
 static bool has_error_state(int dir)
 {
 	bool result;
@@ -230,6 +335,8 @@ static void test_error_state_capture(const intel_ctx_t *ctx,
 	check_error_state(e->name, offset, batch);
 	munmap(batch, 4096);
 	put_ahnd(ahnd);
+
+	check_alive();
 }
 
 static void
@@ -288,6 +395,8 @@ test_engine_hang(const intel_ctx_t *ctx,
 		put_ahnd(ahndN);
 	}
 	put_ahnd(ahnd);
+
+	check_alive();
 }
 
 static int hang_count;
@@ -320,6 +429,8 @@ static void test_hang_detector(const intel_ctx_t *ctx,
 
 	/* Did it work? */
 	igt_assert(hang_count == 1);
+
+	check_alive();
 }
 
 /* This test covers the case where we end up in an uninitialised area of the
@@ -355,6 +466,8 @@ static void hangcheck_unterminated(const intel_ctx_t *ctx)
 		igt_force_gpu_reset(device);
 		igt_assert_f(0, "unterminated batch did not trigger a hang!");
 	}
+
+	check_alive();
 }
 
 static void do_tests(const char *name, const char *prefix,
@@ -432,6 +545,8 @@ igt_main
 		igt_assert(sysfs != -1);
 
 		igt_require(has_error_state(sysfs));
+
+		gem_require_mmap_wc(device);
 	}
 
 	igt_describe("Basic error capture");
-- 
2.25.1

[Intel-gfx] [PATCH i-g-t 08/11] lib/store: Refactor common store code into helper function

[John.C.Harrison]

From: John Harrison <John.C.Harrison@Intel.com>

A lot of tests use almost identical code for creating a batch buffer
which does a single write to memory. This patch collects two such
instances into a common helper function. Unfortunately, the other
instances are all subtly different enough to make it not so trivial to
try to use the helper. It could be done but it is unclear if it is
worth the effort at this point. This patch proves the concept, if
people like it enough then it can be extended.

Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
---
 lib/igt_store.c             | 114 ++++++++++++++++++++++++++++++++++++
 lib/igt_store.h             |  30 ++++++++++
 lib/meson.build             |   1 +
 tests/i915/gem_exec_fence.c |  77 ++----------------------
 tests/i915/i915_hangman.c   |  61 +------------------
 5 files changed, 152 insertions(+), 131 deletions(-)
 create mode 100644 lib/igt_store.c
 create mode 100644 lib/igt_store.h

diff --git a/lib/igt_store.c b/lib/igt_store.c
new file mode 100644
index 000000000..6d9869b58
--- /dev/null
+++ b/lib/igt_store.c
@@ -0,0 +1,114 @@
+/*
+ * Copyright © 2020 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#include "i915/gem_create.h"
+#include "igt_core.h"
+#include "drmtest.h"
+#include "igt_store.h"
+#include "intel_chipset.h"
+#include "intel_reg.h"
+#include "ioctl_wrappers.h"
+#include "lib/intel_allocator.h"
+
+/**
+ * SECTION:igt_store_word
+ * @short_description: Library for writing a value to memory
+ * @title: StoreWord
+ * @include: igt.h
+ *
+ * A lot of igt testcases need some mechanism for writing a value to memory
+ * as a test that a batch buffer has executed.
+ *
+ * NB: Requires master for STORE_DWORD on gen4/5.
+ */
+void igt_store_word(int fd, uint64_t ahnd, const intel_ctx_t *ctx,
+		    const struct intel_execution_engine2 *e,
+		    int fence, uint32_t target_handle,
+		    uint64_t target_offset, uint32_t target_value)
+{
+	const int SCRATCH = 0;
+	const int BATCH = 1;
+	const unsigned int gen = intel_gen(intel_get_drm_devid(fd));
+	struct drm_i915_gem_exec_object2 obj[2];
+	struct drm_i915_gem_relocation_entry reloc;
+	struct drm_i915_gem_execbuffer2 execbuf;
+	uint32_t batch[16], delta;
+	uint64_t bb_offset;
+	int i;
+
+	memset(&execbuf, 0, sizeof(execbuf));
+	execbuf.buffers_ptr = to_user_pointer(obj);
+	execbuf.buffer_count = ARRAY_SIZE(obj);
+	execbuf.flags = e->flags;
+	execbuf.rsvd1 = ctx->id;
+	if (fence != -1) {
+		execbuf.flags |= I915_EXEC_FENCE_IN;
+		execbuf.rsvd2 = fence;
+	}
+	if (gen < 6)
+		execbuf.flags |= I915_EXEC_SECURE;
+
+	memset(obj, 0, sizeof(obj));
+	obj[SCRATCH].handle = target_handle;
+
+	obj[BATCH].handle = gem_create(fd, 4096);
+	obj[BATCH].relocs_ptr = to_user_pointer(&reloc);
+	obj[BATCH].relocation_count = !ahnd ? 1 : 0;
+	bb_offset = get_offset(ahnd, obj[BATCH].handle, 4096, 0);
+	memset(&reloc, 0, sizeof(reloc));
+
+	i = 0;
+	delta = sizeof(uint32_t) * target_value;	/* why value not offset??? */
+	if (!ahnd) {
+		reloc.target_handle = obj[SCRATCH].handle;
+		reloc.presumed_offset = -1;
+		reloc.offset = sizeof(uint32_t) * (i + 1);
+		reloc.delta = delta;
+		reloc.read_domains = I915_GEM_DOMAIN_INSTRUCTION;
+		reloc.write_domain = I915_GEM_DOMAIN_INSTRUCTION;
+	} else {
+		obj[SCRATCH].offset = target_offset;
+		obj[SCRATCH].flags |= EXEC_OBJECT_PINNED | EXEC_OBJECT_WRITE;
+		obj[BATCH].offset = bb_offset;
+		obj[BATCH].flags |= EXEC_OBJECT_PINNED;
+	}
+	batch[i] = MI_STORE_DWORD_IMM | (gen < 6 ? 1 << 22 : 0);
+	if (gen >= 8) {
+		batch[++i] = target_offset + delta;
+		batch[++i] = target_offset >> 32;
+	} else if (gen >= 4) {
+		batch[++i] = 0;
+		batch[++i] = delta;
+		reloc.offset += sizeof(uint32_t);
+	} else {
+		batch[i]--;
+		batch[++i] = delta;
+	}
+	batch[++i] = target_value;
+	batch[++i] = MI_BATCH_BUFFER_END;
+	gem_write(fd, obj[BATCH].handle, 0, batch, sizeof(batch));
+	gem_execbuf(fd, &execbuf);
+	gem_close(fd, obj[BATCH].handle);
+	put_offset(ahnd, obj[BATCH].handle);
+}
diff --git a/lib/igt_store.h b/lib/igt_store.h
new file mode 100644
index 000000000..4d5979e07
--- /dev/null
+++ b/lib/igt_store.h
@@ -0,0 +1,30 @@
+/*
+ * Copyright © 2020 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#include "igt_gt.h"
+
+void igt_store_word(int fd, uint64_t ahnd, const intel_ctx_t *ctx,
+		    const struct intel_execution_engine2 *e,
+		    int fence, uint32_t target_handle,
+		    uint64_t target_offset, uint32_t target_value);
diff --git a/lib/meson.build b/lib/meson.build
index b9568a71b..3e43316d1 100644
--- a/lib/meson.build
+++ b/lib/meson.build
@@ -72,6 +72,7 @@ lib_sources = [
 	'igt_map.c',
 	'igt_pm.c',
 	'igt_dummyload.c',
+	'igt_store.c',
 	'uwildmat/uwildmat.c',
 	'igt_kmod.c',
 	'igt_panfrost.c',
diff --git a/tests/i915/gem_exec_fence.c b/tests/i915/gem_exec_fence.c
index 9a6336ce9..c4091a454 100644
--- a/tests/i915/gem_exec_fence.c
+++ b/tests/i915/gem_exec_fence.c
@@ -28,6 +28,7 @@
 #include "i915/gem.h"
 #include "i915/gem_create.h"
 #include "igt.h"
+#include "igt_store.h"
 #include "igt_syncobj.h"
 #include "igt_sysfs.h"
 #include "igt_vgem.h"
@@ -57,74 +58,6 @@ struct sync_merge_data {
 #define   MI_SEMAPHORE_SAD_EQ_SDD       (4 << 12)
 #define   MI_SEMAPHORE_SAD_NEQ_SDD      (5 << 12)
 
-static void store(int fd, uint64_t ahnd, const intel_ctx_t *ctx,
-		  const struct intel_execution_engine2 *e,
-		  int fence, uint32_t target, uint64_t target_offset,
-		  unsigned offset_value)
-{
-	const int SCRATCH = 0;
-	const int BATCH = 1;
-	const unsigned int gen = intel_gen(intel_get_drm_devid(fd));
-	struct drm_i915_gem_exec_object2 obj[2];
-	struct drm_i915_gem_relocation_entry reloc;
-	struct drm_i915_gem_execbuffer2 execbuf;
-	uint32_t batch[16], delta;
-	uint64_t bb_offset;
-	int i;
-
-	memset(&execbuf, 0, sizeof(execbuf));
-	execbuf.buffers_ptr = to_user_pointer(obj);
-	execbuf.buffer_count = 2;
-	execbuf.flags = e->flags | I915_EXEC_FENCE_IN;
-	execbuf.rsvd1 = ctx->id;
-	execbuf.rsvd2 = fence;
-	if (gen < 6)
-		execbuf.flags |= I915_EXEC_SECURE;
-
-	memset(obj, 0, sizeof(obj));
-	obj[SCRATCH].handle = target;
-
-	obj[BATCH].handle = gem_create(fd, 4096);
-	obj[BATCH].relocs_ptr = to_user_pointer(&reloc);
-	obj[BATCH].relocation_count = !ahnd ? 1 : 0;
-	bb_offset = get_offset(ahnd, obj[BATCH].handle, 4096, 0);
-	memset(&reloc, 0, sizeof(reloc));
-
-	i = 0;
-	delta = sizeof(uint32_t) * offset_value;
-	if (!ahnd) {
-		reloc.target_handle = obj[SCRATCH].handle;
-		reloc.presumed_offset = -1;
-		reloc.offset = sizeof(uint32_t) * (i + 1);
-		reloc.delta = delta;
-		reloc.read_domains = I915_GEM_DOMAIN_INSTRUCTION;
-		reloc.write_domain = I915_GEM_DOMAIN_INSTRUCTION;
-	} else {
-		obj[SCRATCH].offset = target_offset;
-		obj[SCRATCH].flags |= EXEC_OBJECT_PINNED | EXEC_OBJECT_WRITE;
-		obj[BATCH].offset = bb_offset;
-		obj[BATCH].flags |= EXEC_OBJECT_PINNED;
-	}
-	batch[i] = MI_STORE_DWORD_IMM | (gen < 6 ? 1 << 22 : 0);
-	if (gen >= 8) {
-		batch[++i] = target_offset + delta;
-		batch[++i] = target_offset >> 32;
-	} else if (gen >= 4) {
-		batch[++i] = 0;
-		batch[++i] = delta;
-		reloc.offset += sizeof(uint32_t);
-	} else {
-		batch[i]--;
-		batch[++i] = delta;
-	}
-	batch[++i] = offset_value;
-	batch[++i] = MI_BATCH_BUFFER_END;
-	gem_write(fd, obj[BATCH].handle, 0, batch, sizeof(batch));
-	gem_execbuf(fd, &execbuf);
-	gem_close(fd, obj[BATCH].handle);
-	put_offset(ahnd, obj[BATCH].handle);
-}
-
 static bool fence_busy(int fence)
 {
 	return poll(&(struct pollfd){fence, POLLIN}, 1, 0) == 0;
@@ -400,13 +333,13 @@ static void test_fence_await(int fd, const intel_ctx_t *ctx,
 			continue;
 
 		if (flags & NONBLOCK) {
-			store(fd, ahnd, ctx, e2, spin->out_fence,
-			      scratch, scratch_offset, i);
+			igt_store_word(fd, ahnd, ctx, e2, spin->out_fence,
+				       scratch, scratch_offset, i);
 		} else {
 			igt_fork(child, 1) {
 				ahnd = get_reloc_ahnd(fd, ctx->id);
-				store(fd, ahnd, ctx, e2, spin->out_fence,
-				      scratch, scratch_offset, i);
+				igt_store_word(fd, ahnd, ctx, e2, spin->out_fence,
+					       scratch, scratch_offset, i);
 				put_ahnd(ahnd);
 			}
 		}
diff --git a/tests/i915/i915_hangman.c b/tests/i915/i915_hangman.c
index 20653b479..4cb9b8b85 100644
--- a/tests/i915/i915_hangman.c
+++ b/tests/i915/i915_hangman.c
@@ -36,6 +36,7 @@
 #include "i915/gem.h"
 #include "i915/gem_create.h"
 #include "igt.h"
+#include "igt_store.h"
 #include "igt_sysfs.h"
 #include "igt_debugfs.h"
 #include "sw_sync.h"
@@ -51,64 +52,6 @@ static int sysfs = -1;
 
 IGT_TEST_DESCRIPTION("Tests for hang detection and recovery");
 
-/* Requires master for STORE_DWORD on gen4/5 */
-static void store(int fd, const struct intel_execution_engine2 *e,
-		  int fence, uint32_t target, unsigned offset_value)
-{
-	const int SCRATCH = 0;
-	const int BATCH = 1;
-	const int gen = intel_gen(intel_get_drm_devid(fd));
-	struct drm_i915_gem_exec_object2 obj[2];
-	struct drm_i915_gem_relocation_entry reloc;
-	struct drm_i915_gem_execbuffer2 execbuf;
-	uint32_t batch[16];
-	int i;
-
-	memset(&execbuf, 0, sizeof(execbuf));
-	execbuf.buffers_ptr = to_user_pointer(obj);
-	execbuf.buffer_count = ARRAY_SIZE(obj);
-	execbuf.flags = e->flags;
-	if (fence != -1) {
-		execbuf.flags |= I915_EXEC_FENCE_IN;
-		execbuf.rsvd2 = fence;
-	}
-	if (gen < 6)
-		execbuf.flags |= I915_EXEC_SECURE;
-
-	memset(obj, 0, sizeof(obj));
-	obj[SCRATCH].handle = target;
-
-	obj[BATCH].handle = gem_create(fd, 4096);
-	obj[BATCH].relocs_ptr = to_user_pointer(&reloc);
-	obj[BATCH].relocation_count = 1;
-	memset(&reloc, 0, sizeof(reloc));
-
-	i = 0;
-	reloc.target_handle = obj[SCRATCH].handle;
-	reloc.presumed_offset = -1;
-	reloc.offset = sizeof(uint32_t) * (i + 1);
-	reloc.delta = sizeof(uint32_t) * offset_value;
-	reloc.read_domains = I915_GEM_DOMAIN_INSTRUCTION;
-	reloc.write_domain = I915_GEM_DOMAIN_INSTRUCTION;
-	batch[i] = MI_STORE_DWORD_IMM | (gen < 6 ? 1 << 22 : 0);
-	if (gen >= 8) {
-		batch[++i] = reloc.delta;
-		batch[++i] = 0;
-	} else if (gen >= 4) {
-		batch[++i] = 0;
-		batch[++i] = reloc.delta;
-		reloc.offset += sizeof(uint32_t);
-	} else {
-		batch[i]--;
-		batch[++i] = reloc.delta;
-	}
-	batch[++i] = offset_value;
-	batch[++i] = MI_BATCH_BUFFER_END;
-	gem_write(fd, obj[BATCH].handle, 0, batch, sizeof(batch));
-	gem_execbuf(fd, &execbuf);
-	gem_close(fd, obj[BATCH].handle);
-}
-
 static void check_alive(void)
 {
 	const struct intel_execution_engine2 *engine;
@@ -138,7 +81,7 @@ static void check_alive(void)
 			continue;
 
 		/* +OFFSET_ALIVE to ensure engine zero doesn't get a false negative */
-		store(fd, engine, -1, scratch, i + OFFSET_ALIVE);
+		igt_store_word(fd, ahnd, ctx, engine, -1, scratch, i + OFFSET_ALIVE, i + OFFSET_ALIVE);
 		i++;
 	}
 
-- 
2.25.1

[igt-dev] [PATCH i-g-t 08/11] lib/store: Refactor common store code into helper function

[John.C.Harrison]

From: John Harrison <John.C.Harrison@Intel.com>

A lot of tests use almost identical code for creating a batch buffer
which does a single write to memory. This patch collects two such
instances into a common helper function. Unfortunately, the other
instances are all subtly different enough to make it not so trivial to
try to use the helper. It could be done but it is unclear if it is
worth the effort at this point. This patch proves the concept, if
people like it enough then it can be extended.

Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
---
 lib/igt_store.c             | 114 ++++++++++++++++++++++++++++++++++++
 lib/igt_store.h             |  30 ++++++++++
 lib/meson.build             |   1 +
 tests/i915/gem_exec_fence.c |  77 ++----------------------
 tests/i915/i915_hangman.c   |  61 +------------------
 5 files changed, 152 insertions(+), 131 deletions(-)
 create mode 100644 lib/igt_store.c
 create mode 100644 lib/igt_store.h

diff --git a/lib/igt_store.c b/lib/igt_store.c
new file mode 100644
index 000000000..6d9869b58
--- /dev/null
+++ b/lib/igt_store.c
@@ -0,0 +1,114 @@
+/*
+ * Copyright © 2020 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#include "i915/gem_create.h"
+#include "igt_core.h"
+#include "drmtest.h"
+#include "igt_store.h"
+#include "intel_chipset.h"
+#include "intel_reg.h"
+#include "ioctl_wrappers.h"
+#include "lib/intel_allocator.h"
+
+/**
+ * SECTION:igt_store_word
+ * @short_description: Library for writing a value to memory
+ * @title: StoreWord
+ * @include: igt.h
+ *
+ * A lot of igt testcases need some mechanism for writing a value to memory
+ * as a test that a batch buffer has executed.
+ *
+ * NB: Requires master for STORE_DWORD on gen4/5.
+ */
+void igt_store_word(int fd, uint64_t ahnd, const intel_ctx_t *ctx,
+		    const struct intel_execution_engine2 *e,
+		    int fence, uint32_t target_handle,
+		    uint64_t target_offset, uint32_t target_value)
+{
+	const int SCRATCH = 0;
+	const int BATCH = 1;
+	const unsigned int gen = intel_gen(intel_get_drm_devid(fd));
+	struct drm_i915_gem_exec_object2 obj[2];
+	struct drm_i915_gem_relocation_entry reloc;
+	struct drm_i915_gem_execbuffer2 execbuf;
+	uint32_t batch[16], delta;
+	uint64_t bb_offset;
+	int i;
+
+	memset(&execbuf, 0, sizeof(execbuf));
+	execbuf.buffers_ptr = to_user_pointer(obj);
+	execbuf.buffer_count = ARRAY_SIZE(obj);
+	execbuf.flags = e->flags;
+	execbuf.rsvd1 = ctx->id;
+	if (fence != -1) {
+		execbuf.flags |= I915_EXEC_FENCE_IN;
+		execbuf.rsvd2 = fence;
+	}
+	if (gen < 6)
+		execbuf.flags |= I915_EXEC_SECURE;
+
+	memset(obj, 0, sizeof(obj));
+	obj[SCRATCH].handle = target_handle;
+
+	obj[BATCH].handle = gem_create(fd, 4096);
+	obj[BATCH].relocs_ptr = to_user_pointer(&reloc);
+	obj[BATCH].relocation_count = !ahnd ? 1 : 0;
+	bb_offset = get_offset(ahnd, obj[BATCH].handle, 4096, 0);
+	memset(&reloc, 0, sizeof(reloc));
+
+	i = 0;
+	delta = sizeof(uint32_t) * target_value;	/* why value not offset??? */
+	if (!ahnd) {
+		reloc.target_handle = obj[SCRATCH].handle;
+		reloc.presumed_offset = -1;
+		reloc.offset = sizeof(uint32_t) * (i + 1);
+		reloc.delta = delta;
+		reloc.read_domains = I915_GEM_DOMAIN_INSTRUCTION;
+		reloc.write_domain = I915_GEM_DOMAIN_INSTRUCTION;
+	} else {
+		obj[SCRATCH].offset = target_offset;
+		obj[SCRATCH].flags |= EXEC_OBJECT_PINNED | EXEC_OBJECT_WRITE;
+		obj[BATCH].offset = bb_offset;
+		obj[BATCH].flags |= EXEC_OBJECT_PINNED;
+	}
+	batch[i] = MI_STORE_DWORD_IMM | (gen < 6 ? 1 << 22 : 0);
+	if (gen >= 8) {
+		batch[++i] = target_offset + delta;
+		batch[++i] = target_offset >> 32;
+	} else if (gen >= 4) {
+		batch[++i] = 0;
+		batch[++i] = delta;
+		reloc.offset += sizeof(uint32_t);
+	} else {
+		batch[i]--;
+		batch[++i] = delta;
+	}
+	batch[++i] = target_value;
+	batch[++i] = MI_BATCH_BUFFER_END;
+	gem_write(fd, obj[BATCH].handle, 0, batch, sizeof(batch));
+	gem_execbuf(fd, &execbuf);
+	gem_close(fd, obj[BATCH].handle);
+	put_offset(ahnd, obj[BATCH].handle);
+}
diff --git a/lib/igt_store.h b/lib/igt_store.h
new file mode 100644
index 000000000..4d5979e07
--- /dev/null
+++ b/lib/igt_store.h
@@ -0,0 +1,30 @@
+/*
+ * Copyright © 2020 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#include "igt_gt.h"
+
+void igt_store_word(int fd, uint64_t ahnd, const intel_ctx_t *ctx,
+		    const struct intel_execution_engine2 *e,
+		    int fence, uint32_t target_handle,
+		    uint64_t target_offset, uint32_t target_value);
diff --git a/lib/meson.build b/lib/meson.build
index b9568a71b..3e43316d1 100644
--- a/lib/meson.build
+++ b/lib/meson.build
@@ -72,6 +72,7 @@ lib_sources = [
 	'igt_map.c',
 	'igt_pm.c',
 	'igt_dummyload.c',
+	'igt_store.c',
 	'uwildmat/uwildmat.c',
 	'igt_kmod.c',
 	'igt_panfrost.c',
diff --git a/tests/i915/gem_exec_fence.c b/tests/i915/gem_exec_fence.c
index 9a6336ce9..c4091a454 100644
--- a/tests/i915/gem_exec_fence.c
+++ b/tests/i915/gem_exec_fence.c
@@ -28,6 +28,7 @@
 #include "i915/gem.h"
 #include "i915/gem_create.h"
 #include "igt.h"
+#include "igt_store.h"
 #include "igt_syncobj.h"
 #include "igt_sysfs.h"
 #include "igt_vgem.h"
@@ -57,74 +58,6 @@ struct sync_merge_data {
 #define   MI_SEMAPHORE_SAD_EQ_SDD       (4 << 12)
 #define   MI_SEMAPHORE_SAD_NEQ_SDD      (5 << 12)
 
-static void store(int fd, uint64_t ahnd, const intel_ctx_t *ctx,
-		  const struct intel_execution_engine2 *e,
-		  int fence, uint32_t target, uint64_t target_offset,
-		  unsigned offset_value)
-{
-	const int SCRATCH = 0;
-	const int BATCH = 1;
-	const unsigned int gen = intel_gen(intel_get_drm_devid(fd));
-	struct drm_i915_gem_exec_object2 obj[2];
-	struct drm_i915_gem_relocation_entry reloc;
-	struct drm_i915_gem_execbuffer2 execbuf;
-	uint32_t batch[16], delta;
-	uint64_t bb_offset;
-	int i;
-
-	memset(&execbuf, 0, sizeof(execbuf));
-	execbuf.buffers_ptr = to_user_pointer(obj);
-	execbuf.buffer_count = 2;
-	execbuf.flags = e->flags | I915_EXEC_FENCE_IN;
-	execbuf.rsvd1 = ctx->id;
-	execbuf.rsvd2 = fence;
-	if (gen < 6)
-		execbuf.flags |= I915_EXEC_SECURE;
-
-	memset(obj, 0, sizeof(obj));
-	obj[SCRATCH].handle = target;
-
-	obj[BATCH].handle = gem_create(fd, 4096);
-	obj[BATCH].relocs_ptr = to_user_pointer(&reloc);
-	obj[BATCH].relocation_count = !ahnd ? 1 : 0;
-	bb_offset = get_offset(ahnd, obj[BATCH].handle, 4096, 0);
-	memset(&reloc, 0, sizeof(reloc));
-
-	i = 0;
-	delta = sizeof(uint32_t) * offset_value;
-	if (!ahnd) {
-		reloc.target_handle = obj[SCRATCH].handle;
-		reloc.presumed_offset = -1;
-		reloc.offset = sizeof(uint32_t) * (i + 1);
-		reloc.delta = delta;
-		reloc.read_domains = I915_GEM_DOMAIN_INSTRUCTION;
-		reloc.write_domain = I915_GEM_DOMAIN_INSTRUCTION;
-	} else {
-		obj[SCRATCH].offset = target_offset;
-		obj[SCRATCH].flags |= EXEC_OBJECT_PINNED | EXEC_OBJECT_WRITE;
-		obj[BATCH].offset = bb_offset;
-		obj[BATCH].flags |= EXEC_OBJECT_PINNED;
-	}
-	batch[i] = MI_STORE_DWORD_IMM | (gen < 6 ? 1 << 22 : 0);
-	if (gen >= 8) {
-		batch[++i] = target_offset + delta;
-		batch[++i] = target_offset >> 32;
-	} else if (gen >= 4) {
-		batch[++i] = 0;
-		batch[++i] = delta;
-		reloc.offset += sizeof(uint32_t);
-	} else {
-		batch[i]--;
-		batch[++i] = delta;
-	}
-	batch[++i] = offset_value;
-	batch[++i] = MI_BATCH_BUFFER_END;
-	gem_write(fd, obj[BATCH].handle, 0, batch, sizeof(batch));
-	gem_execbuf(fd, &execbuf);
-	gem_close(fd, obj[BATCH].handle);
-	put_offset(ahnd, obj[BATCH].handle);
-}
-
 static bool fence_busy(int fence)
 {
 	return poll(&(struct pollfd){fence, POLLIN}, 1, 0) == 0;
@@ -400,13 +333,13 @@ static void test_fence_await(int fd, const intel_ctx_t *ctx,
 			continue;
 
 		if (flags & NONBLOCK) {
-			store(fd, ahnd, ctx, e2, spin->out_fence,
-			      scratch, scratch_offset, i);
+			igt_store_word(fd, ahnd, ctx, e2, spin->out_fence,
+				       scratch, scratch_offset, i);
 		} else {
 			igt_fork(child, 1) {
 				ahnd = get_reloc_ahnd(fd, ctx->id);
-				store(fd, ahnd, ctx, e2, spin->out_fence,
-				      scratch, scratch_offset, i);
+				igt_store_word(fd, ahnd, ctx, e2, spin->out_fence,
+					       scratch, scratch_offset, i);
 				put_ahnd(ahnd);
 			}
 		}
diff --git a/tests/i915/i915_hangman.c b/tests/i915/i915_hangman.c
index 20653b479..4cb9b8b85 100644
--- a/tests/i915/i915_hangman.c
+++ b/tests/i915/i915_hangman.c
@@ -36,6 +36,7 @@
 #include "i915/gem.h"
 #include "i915/gem_create.h"
 #include "igt.h"
+#include "igt_store.h"
 #include "igt_sysfs.h"
 #include "igt_debugfs.h"
 #include "sw_sync.h"
@@ -51,64 +52,6 @@ static int sysfs = -1;
 
 IGT_TEST_DESCRIPTION("Tests for hang detection and recovery");
 
-/* Requires master for STORE_DWORD on gen4/5 */
-static void store(int fd, const struct intel_execution_engine2 *e,
-		  int fence, uint32_t target, unsigned offset_value)
-{
-	const int SCRATCH = 0;
-	const int BATCH = 1;
-	const int gen = intel_gen(intel_get_drm_devid(fd));
-	struct drm_i915_gem_exec_object2 obj[2];
-	struct drm_i915_gem_relocation_entry reloc;
-	struct drm_i915_gem_execbuffer2 execbuf;
-	uint32_t batch[16];
-	int i;
-
-	memset(&execbuf, 0, sizeof(execbuf));
-	execbuf.buffers_ptr = to_user_pointer(obj);
-	execbuf.buffer_count = ARRAY_SIZE(obj);
-	execbuf.flags = e->flags;
-	if (fence != -1) {
-		execbuf.flags |= I915_EXEC_FENCE_IN;
-		execbuf.rsvd2 = fence;
-	}
-	if (gen < 6)
-		execbuf.flags |= I915_EXEC_SECURE;
-
-	memset(obj, 0, sizeof(obj));
-	obj[SCRATCH].handle = target;
-
-	obj[BATCH].handle = gem_create(fd, 4096);
-	obj[BATCH].relocs_ptr = to_user_pointer(&reloc);
-	obj[BATCH].relocation_count = 1;
-	memset(&reloc, 0, sizeof(reloc));
-
-	i = 0;
-	reloc.target_handle = obj[SCRATCH].handle;
-	reloc.presumed_offset = -1;
-	reloc.offset = sizeof(uint32_t) * (i + 1);
-	reloc.delta = sizeof(uint32_t) * offset_value;
-	reloc.read_domains = I915_GEM_DOMAIN_INSTRUCTION;
-	reloc.write_domain = I915_GEM_DOMAIN_INSTRUCTION;
-	batch[i] = MI_STORE_DWORD_IMM | (gen < 6 ? 1 << 22 : 0);
-	if (gen >= 8) {
-		batch[++i] = reloc.delta;
-		batch[++i] = 0;
-	} else if (gen >= 4) {
-		batch[++i] = 0;
-		batch[++i] = reloc.delta;
-		reloc.offset += sizeof(uint32_t);
-	} else {
-		batch[i]--;
-		batch[++i] = reloc.delta;
-	}
-	batch[++i] = offset_value;
-	batch[++i] = MI_BATCH_BUFFER_END;
-	gem_write(fd, obj[BATCH].handle, 0, batch, sizeof(batch));
-	gem_execbuf(fd, &execbuf);
-	gem_close(fd, obj[BATCH].handle);
-}
-
 static void check_alive(void)
 {
 	const struct intel_execution_engine2 *engine;
@@ -138,7 +81,7 @@ static void check_alive(void)
 			continue;
 
 		/* +OFFSET_ALIVE to ensure engine zero doesn't get a false negative */
-		store(fd, engine, -1, scratch, i + OFFSET_ALIVE);
+		igt_store_word(fd, ahnd, ctx, engine, -1, scratch, i + OFFSET_ALIVE, i + OFFSET_ALIVE);
 		i++;
 	}
 
-- 
2.25.1

[Intel-gfx] [PATCH i-g-t 09/11] tests/i915/i915_hangman: Remove reliance on context persistance

[John.C.Harrison]

From: John Harrison <John.C.Harrison@Intel.com>

The hang test was relying on context persitence for no particular
reason. That is, it would set a bunch of background spinners running
then immediately destroy the active contexts but expect the spinners
to keep spinning. With the current implementation of context
persistence in i915, that means that super high priority pings are
sent to each engine at the start of the test. Depending upon the
timing and platform, one of those unexpected pings could cause test
failures.

There is no need to require context persitence in this test. So change
to managing the contexts cleanly and only destroying them when they
are no longer in use.

Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
---
 tests/i915/i915_hangman.c | 15 ++++++++++-----
 1 file changed, 10 insertions(+), 5 deletions(-)

diff --git a/tests/i915/i915_hangman.c b/tests/i915/i915_hangman.c
index 4cb9b8b85..9bcf82dcd 100644
--- a/tests/i915/i915_hangman.c
+++ b/tests/i915/i915_hangman.c
@@ -287,27 +287,29 @@ test_engine_hang(const intel_ctx_t *ctx,
 		 const struct intel_execution_engine2 *e, unsigned int flags)
 {
 	const struct intel_execution_engine2 *other;
-	const intel_ctx_t *tmp_ctx;
+	const intel_ctx_t *local_ctx[GEM_MAX_ENGINES];
 	igt_spin_t *spin, *next;
 	IGT_LIST_HEAD(list);
 	uint64_t ahnd = get_reloc_ahnd(device, ctx->id), ahndN;
+	int num_ctx;
 
 	igt_skip_on(flags & IGT_SPIN_INVALID_CS &&
 		    gem_engine_has_cmdparser(device, &ctx->cfg, e->flags));
 
 	/* Fill all the other engines with background load */
+	num_ctx = 0;
 	for_each_ctx_engine(device, ctx, other) {
 		if (other->flags == e->flags)
 			continue;
 
-		tmp_ctx = intel_ctx_create(device, &ctx->cfg);
-		ahndN = get_reloc_ahnd(device, tmp_ctx->id);
+		local_ctx[num_ctx] = intel_ctx_create(device, &ctx->cfg);
+		ahndN = get_reloc_ahnd(device, local_ctx[num_ctx]->id);
 		spin = __igt_spin_new(device,
 				      .ahnd = ahndN,
-				      .ctx = tmp_ctx,
+				      .ctx = local_ctx[num_ctx],
 				      .engine = other->flags,
 				      .flags = IGT_SPIN_FENCE_OUT);
-		intel_ctx_destroy(device, tmp_ctx);
+		num_ctx++;
 
 		igt_list_move(&spin->link, &list);
 	}
@@ -337,7 +339,10 @@ test_engine_hang(const intel_ctx_t *ctx,
 		igt_spin_free(device, spin);
 		put_ahnd(ahndN);
 	}
+
 	put_ahnd(ahnd);
+	while (num_ctx)
+		intel_ctx_destroy(device, local_ctx[--num_ctx]);
 
 	check_alive();
 }
-- 
2.25.1

[igt-dev] [PATCH i-g-t 09/11] tests/i915/i915_hangman: Remove reliance on context persistance

[John.C.Harrison]

From: John Harrison <John.C.Harrison@Intel.com>

The hang test was relying on context persitence for no particular
reason. That is, it would set a bunch of background spinners running
then immediately destroy the active contexts but expect the spinners
to keep spinning. With the current implementation of context
persistence in i915, that means that super high priority pings are
sent to each engine at the start of the test. Depending upon the
timing and platform, one of those unexpected pings could cause test
failures.

There is no need to require context persitence in this test. So change
to managing the contexts cleanly and only destroying them when they
are no longer in use.

Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
---
 tests/i915/i915_hangman.c | 15 ++++++++++-----
 1 file changed, 10 insertions(+), 5 deletions(-)

diff --git a/tests/i915/i915_hangman.c b/tests/i915/i915_hangman.c
index 4cb9b8b85..9bcf82dcd 100644
--- a/tests/i915/i915_hangman.c
+++ b/tests/i915/i915_hangman.c
@@ -287,27 +287,29 @@ test_engine_hang(const intel_ctx_t *ctx,
 		 const struct intel_execution_engine2 *e, unsigned int flags)
 {
 	const struct intel_execution_engine2 *other;
-	const intel_ctx_t *tmp_ctx;
+	const intel_ctx_t *local_ctx[GEM_MAX_ENGINES];
 	igt_spin_t *spin, *next;
 	IGT_LIST_HEAD(list);
 	uint64_t ahnd = get_reloc_ahnd(device, ctx->id), ahndN;
+	int num_ctx;
 
 	igt_skip_on(flags & IGT_SPIN_INVALID_CS &&
 		    gem_engine_has_cmdparser(device, &ctx->cfg, e->flags));
 
 	/* Fill all the other engines with background load */
+	num_ctx = 0;
 	for_each_ctx_engine(device, ctx, other) {
 		if (other->flags == e->flags)
 			continue;
 
-		tmp_ctx = intel_ctx_create(device, &ctx->cfg);
-		ahndN = get_reloc_ahnd(device, tmp_ctx->id);
+		local_ctx[num_ctx] = intel_ctx_create(device, &ctx->cfg);
+		ahndN = get_reloc_ahnd(device, local_ctx[num_ctx]->id);
 		spin = __igt_spin_new(device,
 				      .ahnd = ahndN,
-				      .ctx = tmp_ctx,
+				      .ctx = local_ctx[num_ctx],
 				      .engine = other->flags,
 				      .flags = IGT_SPIN_FENCE_OUT);
-		intel_ctx_destroy(device, tmp_ctx);
+		num_ctx++;
 
 		igt_list_move(&spin->link, &list);
 	}
@@ -337,7 +339,10 @@ test_engine_hang(const intel_ctx_t *ctx,
 		igt_spin_free(device, spin);
 		put_ahnd(ahndN);
 	}
+
 	put_ahnd(ahnd);
+	while (num_ctx)
+		intel_ctx_destroy(device, local_ctx[--num_ctx]);
 
 	check_alive();
 }
-- 
2.25.1

[Intel-gfx] [PATCH i-g-t 10/11] tests/i915/i915_hangman: Run background task on all engines

[John.C.Harrison]

From: John Harrison <John.C.Harrison@Intel.com>

As opposed to only on the non-target engines. This means that there is
some other workload present for the scheduler to switch between and so
detet the hang immediately.

Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
---
 tests/i915/i915_hangman.c | 10 ++++++----
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/tests/i915/i915_hangman.c b/tests/i915/i915_hangman.c
index 9bcf82dcd..042100355 100644
--- a/tests/i915/i915_hangman.c
+++ b/tests/i915/i915_hangman.c
@@ -296,12 +296,14 @@ test_engine_hang(const intel_ctx_t *ctx,
 	igt_skip_on(flags & IGT_SPIN_INVALID_CS &&
 		    gem_engine_has_cmdparser(device, &ctx->cfg, e->flags));
 
-	/* Fill all the other engines with background load */
+	/*
+	 * Fill all engines with background load.
+	 * This verifies that independent engines are unaffected and gives
+	 * the target engine something to switch between so it notices the
+	 * hang.
+	 */
 	num_ctx = 0;
 	for_each_ctx_engine(device, ctx, other) {
-		if (other->flags == e->flags)
-			continue;
-
 		local_ctx[num_ctx] = intel_ctx_create(device, &ctx->cfg);
 		ahndN = get_reloc_ahnd(device, local_ctx[num_ctx]->id);
 		spin = __igt_spin_new(device,
-- 
2.25.1

[igt-dev] [PATCH i-g-t 10/11] tests/i915/i915_hangman: Run background task on all engines

[John.C.Harrison]

From: John Harrison <John.C.Harrison@Intel.com>

As opposed to only on the non-target engines. This means that there is
some other workload present for the scheduler to switch between and so
detet the hang immediately.

Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
---
 tests/i915/i915_hangman.c | 10 ++++++----
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/tests/i915/i915_hangman.c b/tests/i915/i915_hangman.c
index 9bcf82dcd..042100355 100644
--- a/tests/i915/i915_hangman.c
+++ b/tests/i915/i915_hangman.c
@@ -296,12 +296,14 @@ test_engine_hang(const intel_ctx_t *ctx,
 	igt_skip_on(flags & IGT_SPIN_INVALID_CS &&
 		    gem_engine_has_cmdparser(device, &ctx->cfg, e->flags));
 
-	/* Fill all the other engines with background load */
+	/*
+	 * Fill all engines with background load.
+	 * This verifies that independent engines are unaffected and gives
+	 * the target engine something to switch between so it notices the
+	 * hang.
+	 */
 	num_ctx = 0;
 	for_each_ctx_engine(device, ctx, other) {
-		if (other->flags == e->flags)
-			continue;
-
 		local_ctx[num_ctx] = intel_ctx_create(device, &ctx->cfg);
 		ahndN = get_reloc_ahnd(device, local_ctx[num_ctx]->id);
 		spin = __igt_spin_new(device,
-- 
2.25.1

[Intel-gfx] [PATCH i-g-t 11/11] tests/i915/gem_exec_fence: Configure correct context

[John.C.Harrison]

From: John Harrison <John.C.Harrison@Intel.com>

The update to use intel_ctx_t missed a line that configures the
context to allow hanging. Fix that.

Fixes: 09c36188b23f83ef9a7b5414e2a10100adc4291f

Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
---
 tests/i915/gem_exec_fence.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/tests/i915/gem_exec_fence.c b/tests/i915/gem_exec_fence.c
index c4091a454..328a2f06e 100644
--- a/tests/i915/gem_exec_fence.c
+++ b/tests/i915/gem_exec_fence.c
@@ -3139,7 +3139,7 @@ igt_main
 			igt_hang_t hang;
 
 			igt_fixture {
-				hang = igt_allow_hang(i915, 0, 0);
+				hang = igt_allow_hang(i915, ctx->id, 0);
 				intel_allocator_multiprocess_start();
 			}
 
-- 
2.25.1

[igt-dev] ✓ Fi.CI.BAT: success for Fixes for i915_hangman and gem_exec_capture

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 5857 bytes --]

== Series Details ==

Series: Fixes for i915_hangman and gem_exec_capture
URL   : https://patchwork.freedesktop.org/series/97981/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_10997 -> IGTPW_6492
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6492/index.html

Participating hosts (41 -> 35)
------------------------------

  Additional (1): fi-tgl-u2 
  Missing    (7): bat-dg1-6 fi-bsw-cyan bat-adlp-6 bat-adlp-4 fi-ctg-p8600 bat-jsl-2 fi-bdw-samus 

Known issues
------------

  Here are the changes found in IGTPW_6492 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@amdgpu/amd_cs_nop@sync-fork-gfx0:
    - fi-skl-6600u:       NOTRUN -> [SKIP][1] ([fdo#109271]) +18 similar issues
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6492/fi-skl-6600u/igt@amdgpu/amd_cs_nop@sync-fork-gfx0.html

  * igt@gem_huc_copy@huc-copy:
    - fi-tgl-u2:          NOTRUN -> [SKIP][2] ([i915#2190])
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6492/fi-tgl-u2/igt@gem_huc_copy@huc-copy.html

  * igt@gem_lmem_swapping@verify-random:
    - fi-tgl-u2:          NOTRUN -> [SKIP][3] ([i915#4613]) +3 similar issues
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6492/fi-tgl-u2/igt@gem_lmem_swapping@verify-random.html

  * igt@i915_selftest@live@late_gt_pm:
    - fi-bsw-nick:        [PASS][4] -> [DMESG-FAIL][5] ([i915#2927] / [i915#3428])
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10997/fi-bsw-nick/igt@i915_selftest@live@late_gt_pm.html
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6492/fi-bsw-nick/igt@i915_selftest@live@late_gt_pm.html

  * igt@kms_chamelium@dp-hpd-fast:
    - fi-tgl-u2:          NOTRUN -> [SKIP][6] ([fdo#109284] / [fdo#111827]) +8 similar issues
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6492/fi-tgl-u2/igt@kms_chamelium@dp-hpd-fast.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
    - fi-tgl-u2:          NOTRUN -> [SKIP][7] ([i915#4103]) +1 similar issue
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6492/fi-tgl-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html

  * igt@kms_force_connector_basic@force-load-detect:
    - fi-tgl-u2:          NOTRUN -> [SKIP][8] ([fdo#109285])
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6492/fi-tgl-u2/igt@kms_force_connector_basic@force-load-detect.html

  * igt@kms_frontbuffer_tracking@basic:
    - fi-cml-u2:          [PASS][9] -> [DMESG-WARN][10] ([i915#4269])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10997/fi-cml-u2/igt@kms_frontbuffer_tracking@basic.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6492/fi-cml-u2/igt@kms_frontbuffer_tracking@basic.html

  * igt@prime_vgem@basic-userptr:
    - fi-tgl-u2:          NOTRUN -> [SKIP][11] ([i915#3301])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6492/fi-tgl-u2/igt@prime_vgem@basic-userptr.html

  * igt@runner@aborted:
    - fi-bsw-nick:        NOTRUN -> [FAIL][12] ([fdo#109271] / [i915#1436] / [i915#3428] / [i915#4312])
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6492/fi-bsw-nick/igt@runner@aborted.html

  
#### Possible fixes ####

  * igt@i915_selftest@live@gt_heartbeat:
    - fi-bdw-5557u:       [DMESG-FAIL][13] ([i915#541]) -> [PASS][14]
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10997/fi-bdw-5557u/igt@i915_selftest@live@gt_heartbeat.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6492/fi-bdw-5557u/igt@i915_selftest@live@gt_heartbeat.html

  * igt@kms_psr@primary_page_flip:
    - fi-skl-6600u:       [FAIL][15] ([i915#4547]) -> [PASS][16]
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10997/fi-skl-6600u/igt@kms_psr@primary_page_flip.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6492/fi-skl-6600u/igt@kms_psr@primary_page_flip.html

  
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
  [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
  [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
  [i915#2927]: https://gitlab.freedesktop.org/drm/intel/issues/2927
  [i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
  [i915#3428]: https://gitlab.freedesktop.org/drm/intel/issues/3428
  [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
  [i915#4269]: https://gitlab.freedesktop.org/drm/intel/issues/4269
  [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
  [i915#4547]: https://gitlab.freedesktop.org/drm/intel/issues/4547
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
  [i915#541]: https://gitlab.freedesktop.org/drm/intel/issues/541


Build changes
-------------

  * CI: CI-20190529 -> None
  * IGT: IGT_6307 -> IGTPW_6492

  CI-20190529: 20190529
  CI_DRM_10997: 11fcf5f9147245f403a2d7668c383b2f78258af4 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_6492: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6492/index.html
  IGT_6307: be84fe4f151bc092e068cab5cd0cd19c34948b40 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git



== Testlist changes ==

+igt@i915_hangman@detector
+igt@i915_hangman@engine-engine-error
+igt@i915_hangman@engine-engine-hang
+igt@i915_hangman@engine-error-state-capture
+igt@i915_hangman@gt-engine-error
+igt@i915_hangman@gt-engine-hang
+igt@i915_hangman@gt-error-state-capture
-igt@i915_hangman@engine-error
-igt@i915_hangman@engine-hang
-igt@i915_hangman@error-state-capture

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6492/index.html

[-- Attachment #2: Type: text/html, Size: 6941 bytes --]

[igt-dev] ✓ Fi.CI.IGT: success for Fixes for i915_hangman and gem_exec_capture

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 30261 bytes --]

== Series Details ==

Series: Fixes for i915_hangman and gem_exec_capture
URL   : https://patchwork.freedesktop.org/series/97981/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_10997_full -> IGTPW_6492_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6492/index.html

Participating hosts (10 -> 7)
------------------------------

  Missing    (3): pig-skl-6260u pig-glk-j5005 shard-rkl 

New tests
---------

  New tests have been introduced between CI_DRM_10997_full and IGTPW_6492_full:

### New IGT tests (37) ###

  * igt@i915_hangman@detector:
    - Statuses :
    - Exec time: [None] s

  * igt@i915_hangman@detector@bcs0:
    - Statuses : 6 pass(s)
    - Exec time: [6.02, 15.07] s

  * igt@i915_hangman@detector@rcs0:
    - Statuses : 6 pass(s)
    - Exec time: [5.89, 15.53] s

  * igt@i915_hangman@detector@vcs0:
    - Statuses : 6 pass(s)
    - Exec time: [5.95, 15.07] s

  * igt@i915_hangman@detector@vcs1:
    - Statuses : 2 pass(s)
    - Exec time: [14.97, 15.04] s

  * igt@i915_hangman@detector@vecs0:
    - Statuses : 5 pass(s)
    - Exec time: [14.94, 15.04] s

  * igt@i915_hangman@engine-engine-error:
    - Statuses : 1 skip(s)
    - Exec time: [0.0] s

  * igt@i915_hangman@engine-engine-error@bcs0:
    - Statuses : 2 pass(s) 2 skip(s)
    - Exec time: [0.00, 0.02] s

  * igt@i915_hangman@engine-engine-error@rcs0:
    - Statuses : 4 pass(s)
    - Exec time: [0.02, 0.07] s

  * igt@i915_hangman@engine-engine-error@vcs0:
    - Statuses : 4 pass(s)
    - Exec time: [0.02, 0.07] s

  * igt@i915_hangman@engine-engine-error@vcs1:
    - Statuses : 1 pass(s)
    - Exec time: [0.02] s

  * igt@i915_hangman@engine-engine-error@vecs0:
    - Statuses : 4 pass(s)
    - Exec time: [0.02, 0.07] s

  * igt@i915_hangman@engine-engine-hang:
    - Statuses :
    - Exec time: [None] s

  * igt@i915_hangman@engine-error-state-capture:
    - Statuses :
    - Exec time: [None] s

  * igt@i915_hangman@engine-error-state-capture@bcs0:
    - Statuses : 5 pass(s)
    - Exec time: [6.70, 7.03] s

  * igt@i915_hangman@engine-error-state-capture@rcs0:
    - Statuses : 5 pass(s)
    - Exec time: [6.32, 15.00] s

  * igt@i915_hangman@engine-error-state-capture@vcs0:
    - Statuses : 5 pass(s)
    - Exec time: [6.97, 7.04] s

  * igt@i915_hangman@engine-error-state-capture@vcs1:
    - Statuses : 2 pass(s)
    - Exec time: [6.97, 7.04] s

  * igt@i915_hangman@engine-error-state-capture@vecs0:
    - Statuses : 5 pass(s)
    - Exec time: [6.97, 7.04] s

  * igt@i915_hangman@gt-engine-error:
    - Statuses : 1 skip(s)
    - Exec time: [0.0] s

  * igt@i915_hangman@gt-engine-error@bcs0:
    - Statuses : 2 pass(s) 3 skip(s)
    - Exec time: [0.00, 0.02] s

  * igt@i915_hangman@gt-engine-error@rcs0:
    - Statuses : 5 pass(s)
    - Exec time: [0.02, 0.07] s

  * igt@i915_hangman@gt-engine-error@vcs0:
    - Statuses : 5 pass(s)
    - Exec time: [0.02, 0.07] s

  * igt@i915_hangman@gt-engine-error@vcs1:
    - Statuses : 3 pass(s)
    - Exec time: [0.02, 0.03] s

  * igt@i915_hangman@gt-engine-error@vecs0:
    - Statuses : 5 pass(s)
    - Exec time: [0.02, 0.07] s

  * igt@i915_hangman@gt-engine-hang:
    - Statuses : 1 skip(s)
    - Exec time: [0.0] s

  * igt@i915_hangman@gt-engine-hang@bcs0:
    - Statuses : 5 pass(s)
    - Exec time: [0.70, 0.76] s

  * igt@i915_hangman@gt-engine-hang@rcs0:
    - Statuses : 5 pass(s)
    - Exec time: [0.68, 15.21] s

  * igt@i915_hangman@gt-engine-hang@vcs0:
    - Statuses : 5 pass(s)
    - Exec time: [0.70, 0.76] s

  * igt@i915_hangman@gt-engine-hang@vcs1:
    - Statuses : 3 pass(s)
    - Exec time: [0.70] s

  * igt@i915_hangman@gt-engine-hang@vecs0:
    - Statuses : 5 pass(s)
    - Exec time: [0.70, 0.76] s

  * igt@i915_hangman@gt-error-state-capture:
    - Statuses :
    - Exec time: [None] s

  * igt@i915_hangman@gt-error-state-capture@bcs0:
    - Statuses : 6 pass(s)
    - Exec time: [6.01, 15.04] s

  * igt@i915_hangman@gt-error-state-capture@rcs0:
    - Statuses : 6 pass(s)
    - Exec time: [6.36, 15.45] s

  * igt@i915_hangman@gt-error-state-capture@vcs0:
    - Statuses : 6 pass(s)
    - Exec time: [5.95, 15.06] s

  * igt@i915_hangman@gt-error-state-capture@vcs1:
    - Statuses : 2 pass(s)
    - Exec time: [14.97, 15.04] s

  * igt@i915_hangman@gt-error-state-capture@vecs0:
    - Statuses : 5 pass(s)
    - Exec time: [14.97, 15.04] s

  

Known issues
------------

  Here are the changes found in IGTPW_6492_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@feature_discovery@display-4x:
    - shard-tglb:         NOTRUN -> [SKIP][1] ([i915#1839])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6492/shard-tglb3/igt@feature_discovery@display-4x.html
    - shard-iclb:         NOTRUN -> [SKIP][2] ([i915#1839])
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6492/shard-iclb7/igt@feature_discovery@display-4x.html

  * igt@gem_ctx_persistence@legacy-engines-mixed-process:
    - shard-snb:          NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#1099]) +2 similar issues
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6492/shard-snb7/igt@gem_ctx_persistence@legacy-engines-mixed-process.html

  * igt@gem_eio@in-flight-contexts-immediate:
    - shard-tglb:         [PASS][4] -> [TIMEOUT][5] ([i915#3063])
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10997/shard-tglb6/igt@gem_eio@in-flight-contexts-immediate.html
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6492/shard-tglb1/igt@gem_eio@in-flight-contexts-immediate.html

  * igt@gem_eio@unwedge-stress:
    - shard-iclb:         [PASS][6] -> [TIMEOUT][7] ([i915#2481] / [i915#3070])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10997/shard-iclb7/igt@gem_eio@unwedge-stress.html
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6492/shard-iclb7/igt@gem_eio@unwedge-stress.html

  * igt@gem_exec_balancer@parallel-keep-in-fence:
    - shard-tglb:         NOTRUN -> [SKIP][8] ([i915#4525]) +1 similar issue
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6492/shard-tglb5/igt@gem_exec_balancer@parallel-keep-in-fence.html

  * igt@gem_exec_balancer@parallel-out-fence:
    - shard-iclb:         NOTRUN -> [SKIP][9] ([i915#4525]) +1 similar issue
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6492/shard-iclb1/igt@gem_exec_balancer@parallel-out-fence.html

  * igt@gem_exec_fair@basic-none-share@rcs0:
    - shard-iclb:         [PASS][10] -> [FAIL][11] ([i915#2842])
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10997/shard-iclb3/igt@gem_exec_fair@basic-none-share@rcs0.html
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6492/shard-iclb5/igt@gem_exec_fair@basic-none-share@rcs0.html

  * igt@gem_exec_fair@basic-none-solo@rcs0:
    - shard-kbl:          NOTRUN -> [FAIL][12] ([i915#2842])
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6492/shard-kbl1/igt@gem_exec_fair@basic-none-solo@rcs0.html

  * igt@gem_exec_fair@basic-none-vip@rcs0:
    - shard-tglb:         [PASS][13] -> [FAIL][14] ([i915#2842]) +3 similar issues
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10997/shard-tglb6/igt@gem_exec_fair@basic-none-vip@rcs0.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6492/shard-tglb6/igt@gem_exec_fair@basic-none-vip@rcs0.html

  * igt@gem_exec_fair@basic-throttle@rcs0:
    - shard-iclb:         [PASS][15] -> [FAIL][16] ([i915#2849])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10997/shard-iclb1/igt@gem_exec_fair@basic-throttle@rcs0.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6492/shard-iclb6/igt@gem_exec_fair@basic-throttle@rcs0.html

  * igt@gem_exec_params@no-blt:
    - shard-tglb:         NOTRUN -> [SKIP][17] ([fdo#109283])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6492/shard-tglb1/igt@gem_exec_params@no-blt.html
    - shard-iclb:         NOTRUN -> [SKIP][18] ([fdo#109283])
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6492/shard-iclb3/igt@gem_exec_params@no-blt.html

  * igt@gem_exec_whisper@basic-queues-forked-all:
    - shard-iclb:         [PASS][19] -> [INCOMPLETE][20] ([i915#1895])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10997/shard-iclb4/igt@gem_exec_whisper@basic-queues-forked-all.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6492/shard-iclb2/igt@gem_exec_whisper@basic-queues-forked-all.html

  * igt@gem_lmem_swapping@parallel-multi:
    - shard-tglb:         NOTRUN -> [SKIP][21] ([i915#4613]) +1 similar issue
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6492/shard-tglb1/igt@gem_lmem_swapping@parallel-multi.html

  * igt@gem_lmem_swapping@random:
    - shard-apl:          NOTRUN -> [SKIP][22] ([fdo#109271] / [i915#4613])
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6492/shard-apl4/igt@gem_lmem_swapping@random.html

  * igt@gem_lmem_swapping@smem-oom:
    - shard-kbl:          NOTRUN -> [SKIP][23] ([fdo#109271] / [i915#4613]) +4 similar issues
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6492/shard-kbl7/igt@gem_lmem_swapping@smem-oom.html

  * igt@gem_mmap_gtt@coherency:
    - shard-tglb:         NOTRUN -> [SKIP][24] ([fdo#111656])
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6492/shard-tglb2/igt@gem_mmap_gtt@coherency.html
    - shard-iclb:         NOTRUN -> [SKIP][25] ([fdo#109292])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6492/shard-iclb1/igt@gem_mmap_gtt@coherency.html

  * igt@gem_pwrite@basic-exhaustion:
    - shard-kbl:          NOTRUN -> [WARN][26] ([i915#2658]) +1 similar issue
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6492/shard-kbl7/igt@gem_pwrite@basic-exhaustion.html
    - shard-apl:          NOTRUN -> [WARN][27] ([i915#2658])
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6492/shard-apl6/igt@gem_pwrite@basic-exhaustion.html

  * igt@gem_pxp@fail-invalid-protected-context:
    - shard-tglb:         NOTRUN -> [SKIP][28] ([i915#4270]) +2 similar issues
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6492/shard-tglb2/igt@gem_pxp@fail-invalid-protected-context.html
    - shard-iclb:         NOTRUN -> [SKIP][29] ([i915#4270]) +1 similar issue
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6492/shard-iclb7/igt@gem_pxp@fail-invalid-protected-context.html

  * igt@gem_render_copy@x-tiled-to-vebox-yf-tiled:
    - shard-iclb:         NOTRUN -> [SKIP][30] ([i915#768]) +2 similar issues
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6492/shard-iclb3/igt@gem_render_copy@x-tiled-to-vebox-yf-tiled.html

  * igt@gem_userptr_blits@access-control:
    - shard-tglb:         NOTRUN -> [SKIP][31] ([i915#3297])
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6492/shard-tglb3/igt@gem_userptr_blits@access-control.html
    - shard-iclb:         NOTRUN -> [SKIP][32] ([i915#3297])
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6492/shard-iclb7/igt@gem_userptr_blits@access-control.html

  * igt@gem_userptr_blits@coherency-sync:
    - shard-tglb:         NOTRUN -> [SKIP][33] ([fdo#110542])
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6492/shard-tglb7/igt@gem_userptr_blits@coherency-sync.html
    - shard-iclb:         NOTRUN -> [SKIP][34] ([fdo#109290])
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6492/shard-iclb3/igt@gem_userptr_blits@coherency-sync.html

  * igt@gen7_exec_parse@cmd-crossing-page:
    - shard-tglb:         NOTRUN -> [SKIP][35] ([fdo#109289]) +4 similar issues
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6492/shard-tglb1/igt@gen7_exec_parse@cmd-crossing-page.html

  * igt@gen7_exec_parse@oacontrol-tracking:
    - shard-iclb:         NOTRUN -> [SKIP][36] ([fdo#109289]) +3 similar issues
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6492/shard-iclb4/igt@gen7_exec_parse@oacontrol-tracking.html

  * igt@gen9_exec_parse@allowed-all:
    - shard-iclb:         NOTRUN -> [SKIP][37] ([i915#2856])
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6492/shard-iclb7/igt@gen9_exec_parse@allowed-all.html
    - shard-tglb:         NOTRUN -> [SKIP][38] ([i915#2856]) +2 similar issues
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6492/shard-tglb2/igt@gen9_exec_parse@allowed-all.html

  * igt@i915_pm_backlight@bad-brightness:
    - shard-glk:          NOTRUN -> [SKIP][39] ([fdo#109271]) +96 similar issues
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6492/shard-glk7/igt@i915_pm_backlight@bad-brightness.html

  * igt@i915_pm_dc@dc9-dpms:
    - shard-tglb:         NOTRUN -> [SKIP][40] ([i915#4281])
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6492/shard-tglb8/igt@i915_pm_dc@dc9-dpms.html
    - shard-apl:          [PASS][41] -> [SKIP][42] ([fdo#109271])
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10997/shard-apl6/igt@i915_pm_dc@dc9-dpms.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6492/shard-apl4/igt@i915_pm_dc@dc9-dpms.html

  * igt@i915_pm_lpsp@screens-disabled:
    - shard-tglb:         NOTRUN -> [SKIP][43] ([i915#1902])
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6492/shard-tglb7/igt@i915_pm_lpsp@screens-disabled.html
    - shard-iclb:         NOTRUN -> [SKIP][44] ([i915#1902])
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6492/shard-iclb3/igt@i915_pm_lpsp@screens-disabled.html

  * igt@i915_pm_rpm@dpms-non-lpsp:
    - shard-tglb:         NOTRUN -> [SKIP][45] ([fdo#111644] / [i915#1397] / [i915#2411])
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6492/shard-tglb5/igt@i915_pm_rpm@dpms-non-lpsp.html
    - shard-iclb:         NOTRUN -> [SKIP][46] ([fdo#110892])
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6492/shard-iclb2/igt@i915_pm_rpm@dpms-non-lpsp.html

  * igt@i915_pm_sseu@full-enable:
    - shard-tglb:         NOTRUN -> [SKIP][47] ([i915#4387])
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6492/shard-tglb6/igt@i915_pm_sseu@full-enable.html

  * igt@i915_selftest@live@gt_lrc:
    - shard-tglb:         NOTRUN -> [DMESG-FAIL][48] ([i915#2373])
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6492/shard-tglb7/igt@i915_selftest@live@gt_lrc.html

  * igt@i915_selftest@live@gt_pm:
    - shard-tglb:         NOTRUN -> [DMESG-FAIL][49] ([i915#1759])
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6492/shard-tglb7/igt@i915_selftest@live@gt_pm.html

  * igt@i915_selftest@live@hangcheck:
    - shard-snb:          NOTRUN -> [INCOMPLETE][50] ([i915#3921])
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6492/shard-snb7/igt@i915_selftest@live@hangcheck.html

  * igt@kms_atomic_transition@plane-all-modeset-transition-fencing:
    - shard-iclb:         NOTRUN -> [SKIP][51] ([i915#1769])
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6492/shard-iclb5/igt@kms_atomic_transition@plane-all-modeset-transition-fencing.html
    - shard-tglb:         NOTRUN -> [SKIP][52] ([i915#1769])
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6492/shard-tglb1/igt@kms_atomic_transition@plane-all-modeset-transition-fencing.html

  * igt@kms_big_fb@linear-32bpp-rotate-180:
    - shard-glk:          [PASS][53] -> [DMESG-WARN][54] ([i915#118])
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10997/shard-glk2/igt@kms_big_fb@linear-32bpp-rotate-180.html
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6492/shard-glk4/igt@kms_big_fb@linear-32bpp-rotate-180.html

  * igt@kms_big_fb@linear-8bpp-rotate-270:
    - shard-tglb:         NOTRUN -> [SKIP][55] ([fdo#111614]) +2 similar issues
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6492/shard-tglb1/igt@kms_big_fb@linear-8bpp-rotate-270.html
    - shard-iclb:         NOTRUN -> [SKIP][56] ([fdo#110725] / [fdo#111614])
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6492/shard-iclb2/igt@kms_big_fb@linear-8bpp-rotate-270.html

  * igt@kms_big_fb@x-tiled-32bpp-rotate-180:
    - shard-glk:          NOTRUN -> [DMESG-WARN][57] ([i915#118])
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6492/shard-glk3/igt@kms_big_fb@x-tiled-32bpp-rotate-180.html

  * igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-hflip:
    - shard-kbl:          NOTRUN -> [SKIP][58] ([fdo#109271] / [i915#3777]) +2 similar issues
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6492/shard-kbl6/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-hflip.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip:
    - shard-glk:          NOTRUN -> [SKIP][59] ([fdo#109271] / [i915#3777]) +1 similar issue
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6492/shard-glk5/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip.html
    - shard-apl:          NOTRUN -> [SKIP][60] ([fdo#109271] / [i915#3777]) +2 similar issues
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6492/shard-apl6/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip.html

  * igt@kms_big_fb@yf-tiled-64bpp-rotate-180:
    - shard-iclb:         NOTRUN -> [SKIP][61] ([fdo#110723]) +1 similar issue
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6492/shard-iclb6/igt@kms_big_fb@yf-tiled-64bpp-rotate-180.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-hflip:
    - shard-tglb:         NOTRUN -> [SKIP][62] ([fdo#111615]) +3 similar issues
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6492/shard-tglb7/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-hflip.html

  * igt@kms_ccs@pipe-a-bad-aux-stride-y_tiled_ccs:
    - shard-tglb:         NOTRUN -> [SKIP][63] ([i915#3689]) +6 similar issues
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6492/shard-tglb2/igt@kms_ccs@pipe-a-bad-aux-stride-y_tiled_ccs.html

  * igt@kms_ccs@pipe-a-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc:
    - shard-kbl:          NOTRUN -> [SKIP][64] ([fdo#109271] / [i915#3886]) +21 similar issues
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6492/shard-kbl3/igt@kms_ccs@pipe-a-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc.html

  * igt@kms_ccs@pipe-a-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc:
    - shard-apl:          NOTRUN -> [SKIP][65] ([fdo#109271] / [i915#3886]) +7 similar issues
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6492/shard-apl2/igt@kms_ccs@pipe-a-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc.html
    - shard-iclb:         NOTRUN -> [SKIP][66] ([fdo#109278] / [i915#3886]) +6 similar issues
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6492/shard-iclb8/igt@kms_ccs@pipe-a-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc.html

  * igt@kms_ccs@pipe-a-random-ccs-data-yf_tiled_ccs:
    - shard-tglb:         NOTRUN -> [SKIP][67] ([fdo#111615] / [i915#3689]) +6 similar issues
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6492/shard-tglb6/igt@kms_ccs@pipe-a-random-ccs-data-yf_tiled_ccs.html

  * igt@kms_ccs@pipe-b-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc:
    - shard-glk:          NOTRUN -> [SKIP][68] ([fdo#109271] / [i915#3886]) +7 similar issues
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6492/shard-glk1/igt@kms_ccs@pipe-b-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc.html

  * igt@kms_ccs@pipe-c-bad-aux-stride-y_tiled_gen12_mc_ccs:
    - shard-tglb:         NOTRUN -> [SKIP][69] ([i915#3689] / [i915#3886]) +1 similar issue
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6492/shard-tglb6/igt@kms_ccs@pipe-c-bad-aux-stride-y_tiled_gen12_mc_ccs.html

  * igt@kms_ccs@pipe-d-bad-pixel-format-y_tiled_ccs:
    - shard-snb:          NOTRUN -> [SKIP][70] ([fdo#109271]) +182 similar issues
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6492/shard-snb2/igt@kms_ccs@pipe-d-bad-pixel-format-y_tiled_ccs.html

  * igt@kms_cdclk@mode-transition:
    - shard-apl:          NOTRUN -> [SKIP][71] ([fdo#109271]) +197 similar issues
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6492/shard-apl4/igt@kms_cdclk@mode-transition.html

  * igt@kms_chamelium@hdmi-crc-fast:
    - shard-iclb:         NOTRUN -> [SKIP][72] ([fdo#109284] / [fdo#111827]) +5 similar issues
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6492/shard-iclb5/igt@kms_chamelium@hdmi-crc-fast.html
    - shard-glk:          NOTRUN -> [SKIP][73] ([fdo#109271] / [fdo#111827]) +7 similar issues
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6492/shard-glk1/igt@kms_chamelium@hdmi-crc-fast.html

  * igt@kms_chamelium@hdmi-edid-change-during-suspend:
    - shard-apl:          NOTRUN -> [SKIP][74] ([fdo#109271] / [fdo#111827]) +15 similar issues
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6492/shard-apl3/igt@kms_chamelium@hdmi-edid-change-during-suspend.html

  * igt@kms_chamelium@hdmi-hpd-enable-disable-mode:
    - shard-snb:          NOTRUN -> [SKIP][75] ([fdo#109271] / [fdo#111827]) +7 similar issues
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6492/shard-snb4/igt@kms_chamelium@hdmi-hpd-enable-disable-mode.html

  * igt@kms_chamelium@hdmi-hpd-storm:
    - shard-kbl:          NOTRUN -> [SKIP][76] ([fdo#109271] / [fdo#111827]) +27 similar issues
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6492/shard-kbl6/igt@kms_chamelium@hdmi-hpd-storm.html

  * igt@kms_color@pipe-d-degamma:
    - shard-iclb:         NOTRUN -> [SKIP][77] ([fdo#109278] / [i915#1149])
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6492/shard-iclb3/igt@kms_color@pipe-d-degamma.html

  * igt@kms_color_chamelium@pipe-d-ctm-blue-to-red:
    - shard-tglb:         NOTRUN -> [SKIP][78] ([fdo#109284] / [fdo#111827]) +9 similar issues
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6492/shard-tglb7/igt@kms_color_chamelium@pipe-d-ctm-blue-to-red.html
    - shard-iclb:         NOTRUN -> [SKIP][79] ([fdo#109278] / [fdo#109284] / [fdo#111827])
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6492/shard-iclb3/igt@kms_color_chamelium@pipe-d-ctm-blue-to-red.html

  * igt@kms_content_protection@atomic:
    - shard-kbl:          NOTRUN -> [TIMEOUT][80] ([i915#1319]) +2 similar issues
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6492/shard-kbl1/igt@kms_content_protection@atomic.html
    - shard-apl:          NOTRUN -> [TIMEOUT][81] ([i915#1319])
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6492/shard-apl3/igt@kms_content_protection@atomic.html
    - shard-tglb:         NOTRUN -> [SKIP][82] ([fdo#111828]) +1 similar issue
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6492/shard-tglb2/igt@kms_content_protection@atomic.html

  * igt@kms_content_protection@mei_interface:
    - shard-iclb:         NOTRUN -> [SKIP][83] ([fdo#109300] / [fdo#111066]) +1 similar issue
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6492/shard-iclb4/igt@kms_content_protection@mei_interface.html

  * igt@kms_cursor_crc@pipe-a-cursor-512x512-sliding:
    - shard-iclb:         NOTRUN -> [SKIP][84] ([fdo#109278] / [fdo#109279]) +2 similar issues
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6492/shard-iclb1/igt@kms_cursor_crc@pipe-a-cursor-512x512-sliding.html

  * igt@kms_cursor_crc@pipe-b-cursor-32x32-onscreen:
    - shard-tglb:         NOTRUN -> [SKIP][85] ([i915#3319]) +3 similar issues
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6492/shard-tglb3/igt@kms_cursor_crc@pipe-b-cursor-32x32-onscreen.html

  * igt@kms_cursor_crc@pipe-b-cursor-512x170-onscreen:
    - shard-tglb:         NOTRUN -> [SKIP][86] ([fdo#109279] / [i915#3359]) +2 similar issues
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6492/shard-tglb1/igt@kms_cursor_crc@pipe-b-cursor-512x170-onscreen.html

  * igt@kms_cursor_crc@pipe-c-cursor-suspend:
    - shard-apl:          [PASS][87] -> [DMESG-WARN][88] ([i915#180]) +1 similar issue
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10997/shard-apl3/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6492/shard-apl3/igt@kms_cursor_crc@pipe-c-cursor-suspend.html

  * igt@kms_cursor_crc@pipe-d-cursor-dpms:
    - shard-iclb:         NOTRUN -> [SKIP][89] ([fdo#109278]) +27 similar issues
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6492/shard-iclb7/igt@kms_cursor_crc@pipe-d-cursor-dpms.html

  * igt@kms_cursor_crc@pipe-d-cursor-max-size-rapid-movement:
    - shard-tglb:         NOTRUN -> [SKIP][90] ([i915#3359]) +8 similar issues
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6492/shard-tglb8/igt@kms_cursor_crc@pipe-d-cursor-max-size-rapid-movement.html

  * igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions:
    - shard-iclb:         NOTRUN -> [SKIP][91] ([fdo#109274] / [fdo#109278]) +2 similar issues
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6492/shard-iclb4/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions.html

  * igt@kms_cursor_legacy@cursorb-vs-flipb-atomic:
    - shard-tglb:         NOTRUN -> [SKIP][92] ([fdo#111825]) +43 similar issues
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6492/shard-tglb8/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic.html

  * igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle:
    - shard-tglb:         NOTRUN -> [SKIP][93] ([i915#4103]) +1 similar issue
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6492/shard-tglb2/igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle.html

  * igt@kms_flip@2x-flip-vs-wf_vblank-interruptible:
    - shard-iclb:         NOTRUN -> [SKIP][94] ([fdo#109274])
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6492/shard-iclb8/igt@kms_flip@2x-flip-vs-wf_vblank-interruptible.html

  * igt@kms_flip@flip-vs-suspend-interruptible@a-dp1:
    - shard-apl:          [PASS][95] -> [DMESG-WARN][96] ([i915#180] / [i915#1982])
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10997/shard-apl6/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6492/shard-apl2/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs:
    - shard-kbl:          NOTRUN -> [SKIP][97] ([fdo#109271] / [i915#2672])
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6492/shard-kbl1/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs.html

  * igt@kms_frontbuffer_tracking@fbc-suspend:
    - shard-kbl:          [PASS][98] -> [DMESG-WARN][99] ([i915#180]) +2 similar issues
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10997/shard-kbl3/igt@kms_frontbuffer_tracking@fbc-suspend.html
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6492/shard-kbl1/igt@kms_frontbuffer_tracking@fbc-suspend.html

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-blt:
    - shard-iclb:         NOTRUN -> [SKIP][100] ([fdo#109280]) +21 similar issues
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6492/shard-iclb8/igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-wc:
    - shard-kbl:          NOTRUN -> [SKIP][101] ([fdo#109271]) +330 similar issues
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6492/shard-kbl6/igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-wc.html

  * igt@kms_hdr@static-swap:
    - shard-tglb:         NOTRUN -> [SKIP][102] ([i915#1187])
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6492/shard-tglb3/igt@kms_hdr@static-swap.html

  * igt@kms_pipe_crc_basic@disable-crc-after-crtc-pipe-d:
    - shard-kbl:          NOTRUN -> [SKIP][103] ([fdo#109271] / [i915#533]) +1 similar issue
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6492/shard-kbl6/igt@kms_pipe_crc_basic@disable-crc-after-crtc-pipe-d.html

  * igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb:
    - shard-apl:          NOTRUN -> [FAIL][104] ([fdo#108145] / [i915#265]) +2 similar issues
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6492/shard-apl3/igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb.html

  * igt@kms_plane_alpha_blend@pipe-b-alpha-basic:
    - shard-kbl:          NOTRUN -> [FAIL][105] ([fdo#108145] / [i915#265]) +3 similar issues
   [105]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6492/shard-kbl3/igt@kms_plane_alpha_blend@pipe-b-alpha-basic.html

  * igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb:
    - shard-kbl:          NOTRUN -> [FAIL][106] ([i915#265]) +1 similar issue
   [106]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6492/shard-kbl4/igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb.html

  * igt@kms_plane_lowres@pipe-b-tiling-x:
    - shard-iclb:         NOTRUN -> [SKIP][107] ([i915#3536])
   [107]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6492/shard-iclb5/igt@kms_plane_lowres@pipe-b-tiling-x.html
    - shard-tglb:         NOTRUN -> [SKIP][108] ([i915#3536]) +1 similar issue
   [108]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6492/shard-tglb2/igt@kms_plane_lowres@pipe-b-tiling-x.html

  * igt@kms_plane_lowres@pipe-b-tiling-yf:
    - shard-tglb:         NOTRUN -> [SKIP][109] ([fdo#111615] / [fdo#112054])
   [109]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6492/shard-tglb5/igt@kms_plane_lowres@pipe-b-tiling-yf.html

  * igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-c-scaler-with-clipping-clamping:
    - shard-apl:          NOTRUN -> [SKIP][110] ([fdo#109271] / [i915#2733])
   [110]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6492/shard-apl1/igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-c-scaler-with-clipping-clamping.html
    - shard-kbl:          NOTRUN -> [SKIP][111] ([fdo#109271] / [i915#2733])
   [111]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6492/shard-kbl7/igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-c-scaler-with-clipping-clamping.html
    - shard-glk:          NOTRUN -> [SKIP][112] ([fdo#109271] / [i915#2733])
   [112]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6492/shard-glk1/igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-c-scaler-with-clipping-clamping.html

  * igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area:
    - shard-tglb:         NOTRUN -> [SKIP][113] ([i915#2920])
   [113]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6492/shard-tglb5/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area.html

  * igt@kms_

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6492/index.html

[-- Attachment #2: Type: text/html, Size: 34708 bytes --]

Re: [Intel-gfx] [igt-dev] [PATCH i-g-t 01/11] tests/i915/i915_hangman: Add descriptions

[Petri Latvala]

On Mon, Dec 13, 2021 at 03:29:04PM -0800, John.C.Harrison@Intel.com wrote:
> From: John Harrison <John.C.Harrison@Intel.com>
> 
> Added descriptions of the various sub-tests and the test as a whole.
> 
> Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
> ---
>  tests/i915/i915_hangman.c | 11 +++++++++--
>  1 file changed, 9 insertions(+), 2 deletions(-)
> 
> diff --git a/tests/i915/i915_hangman.c b/tests/i915/i915_hangman.c
> index 4c18c22db..025bb8713 100644
> --- a/tests/i915/i915_hangman.c
> +++ b/tests/i915/i915_hangman.c
> @@ -46,6 +46,8 @@
>  static int device = -1;
>  static int sysfs = -1;
>  
> +IGT_TEST_DESCRIPTION("Tests for hang detection and recovery");
> +
>  static bool has_error_state(int dir)
>  {
>  	bool result;
> @@ -315,9 +317,9 @@ static void hangcheck_unterminated(void)
>  
>  	gem_execbuf(device, &execbuf);
>  	if (gem_wait(device, handle, &timeout_ns) != 0) {
> -		/* need to manually trigger an hang to clean before failing */
> +		/* need to manually trigger a hang to clean before failing */
>  		igt_force_gpu_reset(device);
> -		igt_assert_f(0, "unterminated batch did not trigger an hang!");
> +		igt_assert_f(0, "unterminated batch did not trigger a hang!");

Ouch, this is a bug that could use a drive-by fix in this same commit:
Add a newline after that text.

With that,
Reviewed-by: Petri Latvala <petri.latvala@intel.com>

>  	}
>  }
>  
> @@ -341,9 +343,11 @@ igt_main
>  		igt_require(has_error_state(sysfs));
>  	}
>  
> +	igt_describe("Basic error capture");
>  	igt_subtest("error-state-basic")
>  		test_error_state_basic();
>  
> +	igt_describe("Per engine error capture");
>  	igt_subtest_with_dynamic("error-state-capture") {
>  		for_each_ctx_engine(device, ctx, e) {
>  			igt_dynamic_f("%s", e->name)
> @@ -351,6 +355,7 @@ igt_main
>  		}
>  	}
>  
> +	igt_describe("Per engine hang recovery (spin)");
>  	igt_subtest_with_dynamic("engine-hang") {
>                  int has_gpu_reset = 0;
>  		struct drm_i915_getparam gp = {
> @@ -369,6 +374,7 @@ igt_main
>  		}
>  	}
>  
> +	igt_describe("Per engine hang recovery (invalid CS)");
>  	igt_subtest_with_dynamic("engine-error") {
>  		int has_gpu_reset = 0;
>  		struct drm_i915_getparam gp = {
> @@ -386,6 +392,7 @@ igt_main
>  		}
>  	}
>  
> +	igt_describe("Check that executing unintialised memory causes a hang");
>  	igt_subtest("hangcheck-unterminated")
>  		hangcheck_unterminated();
>  
> -- 
> 2.25.1
> 

Re: [igt-dev] [PATCH i-g-t 01/11] tests/i915/i915_hangman: Add descriptions

[Petri Latvala]

On Mon, Dec 13, 2021 at 03:29:04PM -0800, John.C.Harrison@Intel.com wrote:
> From: John Harrison <John.C.Harrison@Intel.com>
> 
> Added descriptions of the various sub-tests and the test as a whole.
> 
> Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
> ---
>  tests/i915/i915_hangman.c | 11 +++++++++--
>  1 file changed, 9 insertions(+), 2 deletions(-)
> 
> diff --git a/tests/i915/i915_hangman.c b/tests/i915/i915_hangman.c
> index 4c18c22db..025bb8713 100644
> --- a/tests/i915/i915_hangman.c
> +++ b/tests/i915/i915_hangman.c
> @@ -46,6 +46,8 @@
>  static int device = -1;
>  static int sysfs = -1;
>  
> +IGT_TEST_DESCRIPTION("Tests for hang detection and recovery");
> +
>  static bool has_error_state(int dir)
>  {
>  	bool result;
> @@ -315,9 +317,9 @@ static void hangcheck_unterminated(void)
>  
>  	gem_execbuf(device, &execbuf);
>  	if (gem_wait(device, handle, &timeout_ns) != 0) {
> -		/* need to manually trigger an hang to clean before failing */
> +		/* need to manually trigger a hang to clean before failing */
>  		igt_force_gpu_reset(device);
> -		igt_assert_f(0, "unterminated batch did not trigger an hang!");
> +		igt_assert_f(0, "unterminated batch did not trigger a hang!");

Ouch, this is a bug that could use a drive-by fix in this same commit:
Add a newline after that text.

With that,
Reviewed-by: Petri Latvala <petri.latvala@intel.com>

>  	}
>  }
>  
> @@ -341,9 +343,11 @@ igt_main
>  		igt_require(has_error_state(sysfs));
>  	}
>  
> +	igt_describe("Basic error capture");
>  	igt_subtest("error-state-basic")
>  		test_error_state_basic();
>  
> +	igt_describe("Per engine error capture");
>  	igt_subtest_with_dynamic("error-state-capture") {
>  		for_each_ctx_engine(device, ctx, e) {
>  			igt_dynamic_f("%s", e->name)
> @@ -351,6 +355,7 @@ igt_main
>  		}
>  	}
>  
> +	igt_describe("Per engine hang recovery (spin)");
>  	igt_subtest_with_dynamic("engine-hang") {
>                  int has_gpu_reset = 0;
>  		struct drm_i915_getparam gp = {
> @@ -369,6 +374,7 @@ igt_main
>  		}
>  	}
>  
> +	igt_describe("Per engine hang recovery (invalid CS)");
>  	igt_subtest_with_dynamic("engine-error") {
>  		int has_gpu_reset = 0;
>  		struct drm_i915_getparam gp = {
> @@ -386,6 +392,7 @@ igt_main
>  		}
>  	}
>  
> +	igt_describe("Check that executing unintialised memory causes a hang");
>  	igt_subtest("hangcheck-unterminated")
>  		hangcheck_unterminated();
>  
> -- 
> 2.25.1
> 

Re: [Intel-gfx] [igt-dev] [PATCH i-g-t 01/11] tests/i915/i915_hangman: Add descriptions

[John Harrison]

On 12/14/2021 01:47, Petri Latvala wrote:
> On Mon, Dec 13, 2021 at 03:29:04PM -0800, John.C.Harrison@Intel.com wrote:
>> From: John Harrison <John.C.Harrison@Intel.com>
>>
>> Added descriptions of the various sub-tests and the test as a whole.
>>
>> Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
>> ---
>>   tests/i915/i915_hangman.c | 11 +++++++++--
>>   1 file changed, 9 insertions(+), 2 deletions(-)
>>
>> diff --git a/tests/i915/i915_hangman.c b/tests/i915/i915_hangman.c
>> index 4c18c22db..025bb8713 100644
>> --- a/tests/i915/i915_hangman.c
>> +++ b/tests/i915/i915_hangman.c
>> @@ -46,6 +46,8 @@
>>   static int device = -1;
>>   static int sysfs = -1;
>>   
>> +IGT_TEST_DESCRIPTION("Tests for hang detection and recovery");
>> +
>>   static bool has_error_state(int dir)
>>   {
>>   	bool result;
>> @@ -315,9 +317,9 @@ static void hangcheck_unterminated(void)
>>   
>>   	gem_execbuf(device, &execbuf);
>>   	if (gem_wait(device, handle, &timeout_ns) != 0) {
>> -		/* need to manually trigger an hang to clean before failing */
>> +		/* need to manually trigger a hang to clean before failing */
>>   		igt_force_gpu_reset(device);
>> -		igt_assert_f(0, "unterminated batch did not trigger an hang!");
>> +		igt_assert_f(0, "unterminated batch did not trigger a hang!");
> Ouch, this is a bug that could use a drive-by fix in this same commit:
> Add a newline after that text.
>
> With that,
> Reviewed-by: Petri Latvala <petri.latvala@intel.com>
Well spotted. Will add that in.

Thanks,
John.

>
>>   	}
>>   }
>>   
>> @@ -341,9 +343,11 @@ igt_main
>>   		igt_require(has_error_state(sysfs));
>>   	}
>>   
>> +	igt_describe("Basic error capture");
>>   	igt_subtest("error-state-basic")
>>   		test_error_state_basic();
>>   
>> +	igt_describe("Per engine error capture");
>>   	igt_subtest_with_dynamic("error-state-capture") {
>>   		for_each_ctx_engine(device, ctx, e) {
>>   			igt_dynamic_f("%s", e->name)
>> @@ -351,6 +355,7 @@ igt_main
>>   		}
>>   	}
>>   
>> +	igt_describe("Per engine hang recovery (spin)");
>>   	igt_subtest_with_dynamic("engine-hang") {
>>                   int has_gpu_reset = 0;
>>   		struct drm_i915_getparam gp = {
>> @@ -369,6 +374,7 @@ igt_main
>>   		}
>>   	}
>>   
>> +	igt_describe("Per engine hang recovery (invalid CS)");
>>   	igt_subtest_with_dynamic("engine-error") {
>>   		int has_gpu_reset = 0;
>>   		struct drm_i915_getparam gp = {
>> @@ -386,6 +392,7 @@ igt_main
>>   		}
>>   	}
>>   
>> +	igt_describe("Check that executing unintialised memory causes a hang");
>>   	igt_subtest("hangcheck-unterminated")
>>   		hangcheck_unterminated();
>>   
>> -- 
>> 2.25.1
>>

Re: [igt-dev] [PATCH i-g-t 01/11] tests/i915/i915_hangman: Add descriptions

[John Harrison]

On 12/14/2021 01:47, Petri Latvala wrote:
> On Mon, Dec 13, 2021 at 03:29:04PM -0800, John.C.Harrison@Intel.com wrote:
>> From: John Harrison <John.C.Harrison@Intel.com>
>>
>> Added descriptions of the various sub-tests and the test as a whole.
>>
>> Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
>> ---
>>   tests/i915/i915_hangman.c | 11 +++++++++--
>>   1 file changed, 9 insertions(+), 2 deletions(-)
>>
>> diff --git a/tests/i915/i915_hangman.c b/tests/i915/i915_hangman.c
>> index 4c18c22db..025bb8713 100644
>> --- a/tests/i915/i915_hangman.c
>> +++ b/tests/i915/i915_hangman.c
>> @@ -46,6 +46,8 @@
>>   static int device = -1;
>>   static int sysfs = -1;
>>   
>> +IGT_TEST_DESCRIPTION("Tests for hang detection and recovery");
>> +
>>   static bool has_error_state(int dir)
>>   {
>>   	bool result;
>> @@ -315,9 +317,9 @@ static void hangcheck_unterminated(void)
>>   
>>   	gem_execbuf(device, &execbuf);
>>   	if (gem_wait(device, handle, &timeout_ns) != 0) {
>> -		/* need to manually trigger an hang to clean before failing */
>> +		/* need to manually trigger a hang to clean before failing */
>>   		igt_force_gpu_reset(device);
>> -		igt_assert_f(0, "unterminated batch did not trigger an hang!");
>> +		igt_assert_f(0, "unterminated batch did not trigger a hang!");
> Ouch, this is a bug that could use a drive-by fix in this same commit:
> Add a newline after that text.
>
> With that,
> Reviewed-by: Petri Latvala <petri.latvala@intel.com>
Well spotted. Will add that in.

Thanks,
John.

>
>>   	}
>>   }
>>   
>> @@ -341,9 +343,11 @@ igt_main
>>   		igt_require(has_error_state(sysfs));
>>   	}
>>   
>> +	igt_describe("Basic error capture");
>>   	igt_subtest("error-state-basic")
>>   		test_error_state_basic();
>>   
>> +	igt_describe("Per engine error capture");
>>   	igt_subtest_with_dynamic("error-state-capture") {
>>   		for_each_ctx_engine(device, ctx, e) {
>>   			igt_dynamic_f("%s", e->name)
>> @@ -351,6 +355,7 @@ igt_main
>>   		}
>>   	}
>>   
>> +	igt_describe("Per engine hang recovery (spin)");
>>   	igt_subtest_with_dynamic("engine-hang") {
>>                   int has_gpu_reset = 0;
>>   		struct drm_i915_getparam gp = {
>> @@ -369,6 +374,7 @@ igt_main
>>   		}
>>   	}
>>   
>> +	igt_describe("Per engine hang recovery (invalid CS)");
>>   	igt_subtest_with_dynamic("engine-error") {
>>   		int has_gpu_reset = 0;
>>   		struct drm_i915_getparam gp = {
>> @@ -386,6 +392,7 @@ igt_main
>>   		}
>>   	}
>>   
>> +	igt_describe("Check that executing unintialised memory causes a hang");
>>   	igt_subtest("hangcheck-unterminated")
>>   		hangcheck_unterminated();
>>   
>> -- 
>> 2.25.1
>>

Re: [Intel-gfx] [igt-dev] [PATCH i-g-t 07/11] tests/i915/i915_hangman: Add alive-ness test after error capture

[Zbigniew Kempczyński]

On Mon, Dec 13, 2021 at 03:29:10PM -0800, John.C.Harrison@Intel.com wrote:
> From: John Harrison <John.C.Harrison@Intel.com>
> 
> Added a an extra step to the i915_hangman tests to check that the
> system is still alive after the hang and recovery. This submits a
> simple batch to each engine which does a write to memory and checks
> that the write occurred.
> 
> Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
> ---
>  tests/i915/i915_hangman.c | 115 ++++++++++++++++++++++++++++++++++++++
>  1 file changed, 115 insertions(+)
> 
> diff --git a/tests/i915/i915_hangman.c b/tests/i915/i915_hangman.c
> index b77705206..20653b479 100644
> --- a/tests/i915/i915_hangman.c
> +++ b/tests/i915/i915_hangman.c
> @@ -47,8 +47,113 @@
>  static int device = -1;
>  static int sysfs = -1;
>  
> +#define OFFSET_ALIVE	10
> +
>  IGT_TEST_DESCRIPTION("Tests for hang detection and recovery");
>  
> +/* Requires master for STORE_DWORD on gen4/5 */
> +static void store(int fd, const struct intel_execution_engine2 *e,
> +		  int fence, uint32_t target, unsigned offset_value)
> +{
> +	const int SCRATCH = 0;
> +	const int BATCH = 1;
> +	const int gen = intel_gen(intel_get_drm_devid(fd));
> +	struct drm_i915_gem_exec_object2 obj[2];
> +	struct drm_i915_gem_relocation_entry reloc;
> +	struct drm_i915_gem_execbuffer2 execbuf;
> +	uint32_t batch[16];
> +	int i;
> +
> +	memset(&execbuf, 0, sizeof(execbuf));
> +	execbuf.buffers_ptr = to_user_pointer(obj);
> +	execbuf.buffer_count = ARRAY_SIZE(obj);
> +	execbuf.flags = e->flags;
> +	if (fence != -1) {
> +		execbuf.flags |= I915_EXEC_FENCE_IN;
> +		execbuf.rsvd2 = fence;
> +	}
> +	if (gen < 6)
> +		execbuf.flags |= I915_EXEC_SECURE;
> +
> +	memset(obj, 0, sizeof(obj));
> +	obj[SCRATCH].handle = target;
> +
> +	obj[BATCH].handle = gem_create(fd, 4096);
> +	obj[BATCH].relocs_ptr = to_user_pointer(&reloc);
> +	obj[BATCH].relocation_count = 1;
> +	memset(&reloc, 0, sizeof(reloc));
> +
> +	i = 0;
> +	reloc.target_handle = obj[SCRATCH].handle;
> +	reloc.presumed_offset = -1;
> +	reloc.offset = sizeof(uint32_t) * (i + 1);
> +	reloc.delta = sizeof(uint32_t) * offset_value;
> +	reloc.read_domains = I915_GEM_DOMAIN_INSTRUCTION;
> +	reloc.write_domain = I915_GEM_DOMAIN_INSTRUCTION;
> +	batch[i] = MI_STORE_DWORD_IMM | (gen < 6 ? 1 << 22 : 0);
> +	if (gen >= 8) {
> +		batch[++i] = reloc.delta;
> +		batch[++i] = 0;
> +	} else if (gen >= 4) {
> +		batch[++i] = 0;
> +		batch[++i] = reloc.delta;
> +		reloc.offset += sizeof(uint32_t);
> +	} else {
> +		batch[i]--;
> +		batch[++i] = reloc.delta;
> +	}
> +	batch[++i] = offset_value;
> +	batch[++i] = MI_BATCH_BUFFER_END;
> +	gem_write(fd, obj[BATCH].handle, 0, batch, sizeof(batch));
> +	gem_execbuf(fd, &execbuf);
> +	gem_close(fd, obj[BATCH].handle);
> +}
> +
> +static void check_alive(void)
> +{
> +	const struct intel_execution_engine2 *engine;
> +	const intel_ctx_t *ctx;
> +	uint32_t scratch, *out;
> +	int fd, i = 0;
> +	uint64_t ahnd;
> +
> +	fd = drm_open_driver(DRIVER_INTEL);
> +	igt_require(gem_class_can_store_dword(fd, 0));
> +
> +	ctx = intel_ctx_create_all_physical(fd);
> +	ahnd = get_reloc_ahnd(fd, ctx->id);
> +	scratch = gem_create(fd, 4096);
> +	out = gem_mmap__wc(fd, scratch, 0, 4096, PROT_WRITE);
> +	gem_set_domain(fd, scratch,
> +			I915_GEM_DOMAIN_GTT, I915_GEM_DOMAIN_GTT);
> +
> +	for_each_physical_engine(fd, engine) {
> +		igt_assert_eq_u32(out[i + OFFSET_ALIVE], 0);
> +		i++;
> +	}
> +
> +	i = 0;
> +	for_each_ctx_engine(fd, ctx, engine) {
> +		if (!gem_class_can_store_dword(fd, engine->class))
> +			continue;
> +
> +		/* +OFFSET_ALIVE to ensure engine zero doesn't get a false negative */
> +		store(fd, engine, -1, scratch, i + OFFSET_ALIVE);

You need to pass ctx + ahnd to store() to add softpin path. Relocs
won't work above Tigerlake.

--
Zbigniew


> +		i++;
> +	}
> +
> +	gem_set_domain(fd, scratch, I915_GEM_DOMAIN_GTT, 0);
> +
> +	while (i--)
> +		igt_assert_eq_u32(out[i + OFFSET_ALIVE], i + OFFSET_ALIVE);
> +
> +	munmap(out, 4096);
> +	gem_close(fd, scratch);
> +	put_ahnd(ahnd);
> +	intel_ctx_destroy(fd, ctx);
> +	close(fd);
> +}
> +
>  static bool has_error_state(int dir)
>  {
>  	bool result;
> @@ -230,6 +335,8 @@ static void test_error_state_capture(const intel_ctx_t *ctx,
>  	check_error_state(e->name, offset, batch);
>  	munmap(batch, 4096);
>  	put_ahnd(ahnd);
> +
> +	check_alive();
>  }
>  
>  static void
> @@ -288,6 +395,8 @@ test_engine_hang(const intel_ctx_t *ctx,
>  		put_ahnd(ahndN);
>  	}
>  	put_ahnd(ahnd);
> +
> +	check_alive();
>  }
>  
>  static int hang_count;
> @@ -320,6 +429,8 @@ static void test_hang_detector(const intel_ctx_t *ctx,
>  
>  	/* Did it work? */
>  	igt_assert(hang_count == 1);
> +
> +	check_alive();
>  }
>  
>  /* This test covers the case where we end up in an uninitialised area of the
> @@ -355,6 +466,8 @@ static void hangcheck_unterminated(const intel_ctx_t *ctx)
>  		igt_force_gpu_reset(device);
>  		igt_assert_f(0, "unterminated batch did not trigger a hang!");
>  	}
> +
> +	check_alive();
>  }
>  
>  static void do_tests(const char *name, const char *prefix,
> @@ -432,6 +545,8 @@ igt_main
>  		igt_assert(sysfs != -1);
>  
>  		igt_require(has_error_state(sysfs));
> +
> +		gem_require_mmap_wc(device);
>  	}
>  
>  	igt_describe("Basic error capture");
> -- 
> 2.25.1
> 

Re: [Intel-gfx] [igt-dev] [PATCH i-g-t 08/11] lib/store: Refactor common store code into helper function

[Zbigniew Kempczyński]

On Mon, Dec 13, 2021 at 03:29:11PM -0800, John.C.Harrison@Intel.com wrote:
> From: John Harrison <John.C.Harrison@Intel.com>
> 
> A lot of tests use almost identical code for creating a batch buffer
> which does a single write to memory. This patch collects two such
> instances into a common helper function. Unfortunately, the other
> instances are all subtly different enough to make it not so trivial to
> try to use the helper. It could be done but it is unclear if it is
> worth the effort at this point. This patch proves the concept, if
> people like it enough then it can be extended.
> 
> Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
> ---
>  lib/igt_store.c             | 114 ++++++++++++++++++++++++++++++++++++
>  lib/igt_store.h             |  30 ++++++++++
>  lib/meson.build             |   1 +
>  tests/i915/gem_exec_fence.c |  77 ++----------------------
>  tests/i915/i915_hangman.c   |  61 +------------------
>  5 files changed, 152 insertions(+), 131 deletions(-)
>  create mode 100644 lib/igt_store.c
>  create mode 100644 lib/igt_store.h
> 
> diff --git a/lib/igt_store.c b/lib/igt_store.c
> new file mode 100644
> index 000000000..6d9869b58
> --- /dev/null
> +++ b/lib/igt_store.c
> @@ -0,0 +1,114 @@
> +/*
> + * Copyright © 2020 Intel Corporation
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the next
> + * paragraph) shall be included in all copies or substantial portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
> + * IN THE SOFTWARE.
> + *
> + */

Use SPDX. I like idea of extracting this.

> +
> +#include "i915/gem_create.h"
> +#include "igt_core.h"
> +#include "drmtest.h"
> +#include "igt_store.h"
> +#include "intel_chipset.h"
> +#include "intel_reg.h"
> +#include "ioctl_wrappers.h"
> +#include "lib/intel_allocator.h"
> +
> +/**
> + * SECTION:igt_store_word
> + * @short_description: Library for writing a value to memory
> + * @title: StoreWord
> + * @include: igt.h
> + *
> + * A lot of igt testcases need some mechanism for writing a value to memory
> + * as a test that a batch buffer has executed.
> + *
> + * NB: Requires master for STORE_DWORD on gen4/5.
> + */
> +void igt_store_word(int fd, uint64_t ahnd, const intel_ctx_t *ctx,
> +		    const struct intel_execution_engine2 *e,
> +		    int fence, uint32_t target_handle,
> +		    uint64_t target_offset, uint32_t target_value)
> +{
> +	const int SCRATCH = 0;
> +	const int BATCH = 1;
> +	const unsigned int gen = intel_gen(intel_get_drm_devid(fd));
> +	struct drm_i915_gem_exec_object2 obj[2];
> +	struct drm_i915_gem_relocation_entry reloc;
> +	struct drm_i915_gem_execbuffer2 execbuf;
> +	uint32_t batch[16], delta;
> +	uint64_t bb_offset;
> +	int i;
> +
> +	memset(&execbuf, 0, sizeof(execbuf));
> +	execbuf.buffers_ptr = to_user_pointer(obj);
> +	execbuf.buffer_count = ARRAY_SIZE(obj);
> +	execbuf.flags = e->flags;
> +	execbuf.rsvd1 = ctx->id;
> +	if (fence != -1) {
> +		execbuf.flags |= I915_EXEC_FENCE_IN;
> +		execbuf.rsvd2 = fence;
> +	}
> +	if (gen < 6)
> +		execbuf.flags |= I915_EXEC_SECURE;
> +
> +	memset(obj, 0, sizeof(obj));
> +	obj[SCRATCH].handle = target_handle;
> +
> +	obj[BATCH].handle = gem_create(fd, 4096);
> +	obj[BATCH].relocs_ptr = to_user_pointer(&reloc);
> +	obj[BATCH].relocation_count = !ahnd ? 1 : 0;
> +	bb_offset = get_offset(ahnd, obj[BATCH].handle, 4096, 0);
> +	memset(&reloc, 0, sizeof(reloc));
> +
> +	i = 0;
> +	delta = sizeof(uint32_t) * target_value;	/* why value not offset??? */

I guess I know why there's problem here. target_offset is address in vm
passed by the caller. This is regarding to some limitations of allocator
infrastructure - for "reloc" pseudo-allocator you would get new offset 
(internally it returns offset and then add size for new "allocation").
With this we don't need to wait for rebind offset for new execbuf. 
With "simple" allocator put will release offset so new allocation will
reuse same offset. Ashutosh proposed how to join both functionalities
(stepping as with reloc, stateful like in simple) but I got no time to
code this.

Regarding issue here, target_offset passed from the caller is to avoid 
rebind if get_offset() would be called for "reloc" allocator.
So there's not real value offset within bo. I would add separate 
value_offset (shift) to allow caller to put place where it wants to 
write the value.


> +	if (!ahnd) {
> +		reloc.target_handle = obj[SCRATCH].handle;
> +		reloc.presumed_offset = -1;
> +		reloc.offset = sizeof(uint32_t) * (i + 1);
> +		reloc.delta = delta;
> +		reloc.read_domains = I915_GEM_DOMAIN_INSTRUCTION;
> +		reloc.write_domain = I915_GEM_DOMAIN_INSTRUCTION;
> +	} else {
> +		obj[SCRATCH].offset = target_offset;
> +		obj[SCRATCH].flags |= EXEC_OBJECT_PINNED | EXEC_OBJECT_WRITE;
> +		obj[BATCH].offset = bb_offset;
> +		obj[BATCH].flags |= EXEC_OBJECT_PINNED;
> +	}
> +	batch[i] = MI_STORE_DWORD_IMM | (gen < 6 ? 1 << 22 : 0);
> +	if (gen >= 8) {
> +		batch[++i] = target_offset + delta;
> +		batch[++i] = target_offset >> 32;

Probably I've added this in previous code, for being safe I would
add (target_offset + delta) >> 32 for avoid risk passing invalid higher
offset part on 32b boundary.

> +	} else if (gen >= 4) {
> +		batch[++i] = 0;
> +		batch[++i] = delta;
> +		reloc.offset += sizeof(uint32_t);
> +	} else {
> +		batch[i]--;
> +		batch[++i] = delta;
> +	}
> +	batch[++i] = target_value;
> +	batch[++i] = MI_BATCH_BUFFER_END;
> +	gem_write(fd, obj[BATCH].handle, 0, batch, sizeof(batch));
> +	gem_execbuf(fd, &execbuf);
> +	gem_close(fd, obj[BATCH].handle);
> +	put_offset(ahnd, obj[BATCH].handle);
> +}
> diff --git a/lib/igt_store.h b/lib/igt_store.h
> new file mode 100644
> index 000000000..4d5979e07
> --- /dev/null
> +++ b/lib/igt_store.h
> @@ -0,0 +1,30 @@
> +/*
> + * Copyright © 2020 Intel Corporation
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the next
> + * paragraph) shall be included in all copies or substantial portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
> + * IN THE SOFTWARE.
> + *
> + */

Use SPDX and 2021.

--
Zbigniew

> +
> +#include "igt_gt.h"
> +
> +void igt_store_word(int fd, uint64_t ahnd, const intel_ctx_t *ctx,
> +		    const struct intel_execution_engine2 *e,
> +		    int fence, uint32_t target_handle,
> +		    uint64_t target_offset, uint32_t target_value);
> diff --git a/lib/meson.build b/lib/meson.build
> index b9568a71b..3e43316d1 100644
> --- a/lib/meson.build
> +++ b/lib/meson.build
> @@ -72,6 +72,7 @@ lib_sources = [
>  	'igt_map.c',
>  	'igt_pm.c',
>  	'igt_dummyload.c',
> +	'igt_store.c',
>  	'uwildmat/uwildmat.c',
>  	'igt_kmod.c',
>  	'igt_panfrost.c',
> diff --git a/tests/i915/gem_exec_fence.c b/tests/i915/gem_exec_fence.c
> index 9a6336ce9..c4091a454 100644
> --- a/tests/i915/gem_exec_fence.c
> +++ b/tests/i915/gem_exec_fence.c
> @@ -28,6 +28,7 @@
>  #include "i915/gem.h"
>  #include "i915/gem_create.h"
>  #include "igt.h"
> +#include "igt_store.h"
>  #include "igt_syncobj.h"
>  #include "igt_sysfs.h"
>  #include "igt_vgem.h"
> @@ -57,74 +58,6 @@ struct sync_merge_data {
>  #define   MI_SEMAPHORE_SAD_EQ_SDD       (4 << 12)
>  #define   MI_SEMAPHORE_SAD_NEQ_SDD      (5 << 12)
>  
> -static void store(int fd, uint64_t ahnd, const intel_ctx_t *ctx,
> -		  const struct intel_execution_engine2 *e,
> -		  int fence, uint32_t target, uint64_t target_offset,
> -		  unsigned offset_value)
> -{
> -	const int SCRATCH = 0;
> -	const int BATCH = 1;
> -	const unsigned int gen = intel_gen(intel_get_drm_devid(fd));
> -	struct drm_i915_gem_exec_object2 obj[2];
> -	struct drm_i915_gem_relocation_entry reloc;
> -	struct drm_i915_gem_execbuffer2 execbuf;
> -	uint32_t batch[16], delta;
> -	uint64_t bb_offset;
> -	int i;
> -
> -	memset(&execbuf, 0, sizeof(execbuf));
> -	execbuf.buffers_ptr = to_user_pointer(obj);
> -	execbuf.buffer_count = 2;
> -	execbuf.flags = e->flags | I915_EXEC_FENCE_IN;
> -	execbuf.rsvd1 = ctx->id;
> -	execbuf.rsvd2 = fence;
> -	if (gen < 6)
> -		execbuf.flags |= I915_EXEC_SECURE;
> -
> -	memset(obj, 0, sizeof(obj));
> -	obj[SCRATCH].handle = target;
> -
> -	obj[BATCH].handle = gem_create(fd, 4096);
> -	obj[BATCH].relocs_ptr = to_user_pointer(&reloc);
> -	obj[BATCH].relocation_count = !ahnd ? 1 : 0;
> -	bb_offset = get_offset(ahnd, obj[BATCH].handle, 4096, 0);
> -	memset(&reloc, 0, sizeof(reloc));
> -
> -	i = 0;
> -	delta = sizeof(uint32_t) * offset_value;
> -	if (!ahnd) {
> -		reloc.target_handle = obj[SCRATCH].handle;
> -		reloc.presumed_offset = -1;
> -		reloc.offset = sizeof(uint32_t) * (i + 1);
> -		reloc.delta = delta;
> -		reloc.read_domains = I915_GEM_DOMAIN_INSTRUCTION;
> -		reloc.write_domain = I915_GEM_DOMAIN_INSTRUCTION;
> -	} else {
> -		obj[SCRATCH].offset = target_offset;
> -		obj[SCRATCH].flags |= EXEC_OBJECT_PINNED | EXEC_OBJECT_WRITE;
> -		obj[BATCH].offset = bb_offset;
> -		obj[BATCH].flags |= EXEC_OBJECT_PINNED;
> -	}
> -	batch[i] = MI_STORE_DWORD_IMM | (gen < 6 ? 1 << 22 : 0);
> -	if (gen >= 8) {
> -		batch[++i] = target_offset + delta;
> -		batch[++i] = target_offset >> 32;
> -	} else if (gen >= 4) {
> -		batch[++i] = 0;
> -		batch[++i] = delta;
> -		reloc.offset += sizeof(uint32_t);
> -	} else {
> -		batch[i]--;
> -		batch[++i] = delta;
> -	}
> -	batch[++i] = offset_value;
> -	batch[++i] = MI_BATCH_BUFFER_END;
> -	gem_write(fd, obj[BATCH].handle, 0, batch, sizeof(batch));
> -	gem_execbuf(fd, &execbuf);
> -	gem_close(fd, obj[BATCH].handle);
> -	put_offset(ahnd, obj[BATCH].handle);
> -}
> -
>  static bool fence_busy(int fence)
>  {
>  	return poll(&(struct pollfd){fence, POLLIN}, 1, 0) == 0;
> @@ -400,13 +333,13 @@ static void test_fence_await(int fd, const intel_ctx_t *ctx,
>  			continue;
>  
>  		if (flags & NONBLOCK) {
> -			store(fd, ahnd, ctx, e2, spin->out_fence,
> -			      scratch, scratch_offset, i);
> +			igt_store_word(fd, ahnd, ctx, e2, spin->out_fence,
> +				       scratch, scratch_offset, i);
>  		} else {
>  			igt_fork(child, 1) {
>  				ahnd = get_reloc_ahnd(fd, ctx->id);
> -				store(fd, ahnd, ctx, e2, spin->out_fence,
> -				      scratch, scratch_offset, i);
> +				igt_store_word(fd, ahnd, ctx, e2, spin->out_fence,
> +					       scratch, scratch_offset, i);
>  				put_ahnd(ahnd);
>  			}
>  		}
> diff --git a/tests/i915/i915_hangman.c b/tests/i915/i915_hangman.c
> index 20653b479..4cb9b8b85 100644
> --- a/tests/i915/i915_hangman.c
> +++ b/tests/i915/i915_hangman.c
> @@ -36,6 +36,7 @@
>  #include "i915/gem.h"
>  #include "i915/gem_create.h"
>  #include "igt.h"
> +#include "igt_store.h"
>  #include "igt_sysfs.h"
>  #include "igt_debugfs.h"
>  #include "sw_sync.h"
> @@ -51,64 +52,6 @@ static int sysfs = -1;
>  
>  IGT_TEST_DESCRIPTION("Tests for hang detection and recovery");
>  
> -/* Requires master for STORE_DWORD on gen4/5 */
> -static void store(int fd, const struct intel_execution_engine2 *e,
> -		  int fence, uint32_t target, unsigned offset_value)
> -{
> -	const int SCRATCH = 0;
> -	const int BATCH = 1;
> -	const int gen = intel_gen(intel_get_drm_devid(fd));
> -	struct drm_i915_gem_exec_object2 obj[2];
> -	struct drm_i915_gem_relocation_entry reloc;
> -	struct drm_i915_gem_execbuffer2 execbuf;
> -	uint32_t batch[16];
> -	int i;
> -
> -	memset(&execbuf, 0, sizeof(execbuf));
> -	execbuf.buffers_ptr = to_user_pointer(obj);
> -	execbuf.buffer_count = ARRAY_SIZE(obj);
> -	execbuf.flags = e->flags;
> -	if (fence != -1) {
> -		execbuf.flags |= I915_EXEC_FENCE_IN;
> -		execbuf.rsvd2 = fence;
> -	}
> -	if (gen < 6)
> -		execbuf.flags |= I915_EXEC_SECURE;
> -
> -	memset(obj, 0, sizeof(obj));
> -	obj[SCRATCH].handle = target;
> -
> -	obj[BATCH].handle = gem_create(fd, 4096);
> -	obj[BATCH].relocs_ptr = to_user_pointer(&reloc);
> -	obj[BATCH].relocation_count = 1;
> -	memset(&reloc, 0, sizeof(reloc));
> -
> -	i = 0;
> -	reloc.target_handle = obj[SCRATCH].handle;
> -	reloc.presumed_offset = -1;
> -	reloc.offset = sizeof(uint32_t) * (i + 1);
> -	reloc.delta = sizeof(uint32_t) * offset_value;
> -	reloc.read_domains = I915_GEM_DOMAIN_INSTRUCTION;
> -	reloc.write_domain = I915_GEM_DOMAIN_INSTRUCTION;
> -	batch[i] = MI_STORE_DWORD_IMM | (gen < 6 ? 1 << 22 : 0);
> -	if (gen >= 8) {
> -		batch[++i] = reloc.delta;
> -		batch[++i] = 0;
> -	} else if (gen >= 4) {
> -		batch[++i] = 0;
> -		batch[++i] = reloc.delta;
> -		reloc.offset += sizeof(uint32_t);
> -	} else {
> -		batch[i]--;
> -		batch[++i] = reloc.delta;
> -	}
> -	batch[++i] = offset_value;
> -	batch[++i] = MI_BATCH_BUFFER_END;
> -	gem_write(fd, obj[BATCH].handle, 0, batch, sizeof(batch));
> -	gem_execbuf(fd, &execbuf);
> -	gem_close(fd, obj[BATCH].handle);
> -}
> -
>  static void check_alive(void)
>  {
>  	const struct intel_execution_engine2 *engine;
> @@ -138,7 +81,7 @@ static void check_alive(void)
>  			continue;
>  
>  		/* +OFFSET_ALIVE to ensure engine zero doesn't get a false negative */
> -		store(fd, engine, -1, scratch, i + OFFSET_ALIVE);
> +		igt_store_word(fd, ahnd, ctx, engine, -1, scratch, i + OFFSET_ALIVE, i + OFFSET_ALIVE);
>  		i++;
>  	}
>  
> -- 
> 2.25.1
> 

Re: [igt-dev] [PATCH i-g-t 08/11] lib/store: Refactor common store code into helper function

[Zbigniew Kempczyński]

On Mon, Dec 13, 2021 at 03:29:11PM -0800, John.C.Harrison@Intel.com wrote:
> From: John Harrison <John.C.Harrison@Intel.com>
> 
> A lot of tests use almost identical code for creating a batch buffer
> which does a single write to memory. This patch collects two such
> instances into a common helper function. Unfortunately, the other
> instances are all subtly different enough to make it not so trivial to
> try to use the helper. It could be done but it is unclear if it is
> worth the effort at this point. This patch proves the concept, if
> people like it enough then it can be extended.
> 
> Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
> ---
>  lib/igt_store.c             | 114 ++++++++++++++++++++++++++++++++++++
>  lib/igt_store.h             |  30 ++++++++++
>  lib/meson.build             |   1 +
>  tests/i915/gem_exec_fence.c |  77 ++----------------------
>  tests/i915/i915_hangman.c   |  61 +------------------
>  5 files changed, 152 insertions(+), 131 deletions(-)
>  create mode 100644 lib/igt_store.c
>  create mode 100644 lib/igt_store.h
> 
> diff --git a/lib/igt_store.c b/lib/igt_store.c
> new file mode 100644
> index 000000000..6d9869b58
> --- /dev/null
> +++ b/lib/igt_store.c
> @@ -0,0 +1,114 @@
> +/*
> + * Copyright © 2020 Intel Corporation
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the next
> + * paragraph) shall be included in all copies or substantial portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
> + * IN THE SOFTWARE.
> + *
> + */

Use SPDX. I like idea of extracting this.

> +
> +#include "i915/gem_create.h"
> +#include "igt_core.h"
> +#include "drmtest.h"
> +#include "igt_store.h"
> +#include "intel_chipset.h"
> +#include "intel_reg.h"
> +#include "ioctl_wrappers.h"
> +#include "lib/intel_allocator.h"
> +
> +/**
> + * SECTION:igt_store_word
> + * @short_description: Library for writing a value to memory
> + * @title: StoreWord
> + * @include: igt.h
> + *
> + * A lot of igt testcases need some mechanism for writing a value to memory
> + * as a test that a batch buffer has executed.
> + *
> + * NB: Requires master for STORE_DWORD on gen4/5.
> + */
> +void igt_store_word(int fd, uint64_t ahnd, const intel_ctx_t *ctx,
> +		    const struct intel_execution_engine2 *e,
> +		    int fence, uint32_t target_handle,
> +		    uint64_t target_offset, uint32_t target_value)
> +{
> +	const int SCRATCH = 0;
> +	const int BATCH = 1;
> +	const unsigned int gen = intel_gen(intel_get_drm_devid(fd));
> +	struct drm_i915_gem_exec_object2 obj[2];
> +	struct drm_i915_gem_relocation_entry reloc;
> +	struct drm_i915_gem_execbuffer2 execbuf;
> +	uint32_t batch[16], delta;
> +	uint64_t bb_offset;
> +	int i;
> +
> +	memset(&execbuf, 0, sizeof(execbuf));
> +	execbuf.buffers_ptr = to_user_pointer(obj);
> +	execbuf.buffer_count = ARRAY_SIZE(obj);
> +	execbuf.flags = e->flags;
> +	execbuf.rsvd1 = ctx->id;
> +	if (fence != -1) {
> +		execbuf.flags |= I915_EXEC_FENCE_IN;
> +		execbuf.rsvd2 = fence;
> +	}
> +	if (gen < 6)
> +		execbuf.flags |= I915_EXEC_SECURE;
> +
> +	memset(obj, 0, sizeof(obj));
> +	obj[SCRATCH].handle = target_handle;
> +
> +	obj[BATCH].handle = gem_create(fd, 4096);
> +	obj[BATCH].relocs_ptr = to_user_pointer(&reloc);
> +	obj[BATCH].relocation_count = !ahnd ? 1 : 0;
> +	bb_offset = get_offset(ahnd, obj[BATCH].handle, 4096, 0);
> +	memset(&reloc, 0, sizeof(reloc));
> +
> +	i = 0;
> +	delta = sizeof(uint32_t) * target_value;	/* why value not offset??? */

I guess I know why there's problem here. target_offset is address in vm
passed by the caller. This is regarding to some limitations of allocator
infrastructure - for "reloc" pseudo-allocator you would get new offset 
(internally it returns offset and then add size for new "allocation").
With this we don't need to wait for rebind offset for new execbuf. 
With "simple" allocator put will release offset so new allocation will
reuse same offset. Ashutosh proposed how to join both functionalities
(stepping as with reloc, stateful like in simple) but I got no time to
code this.

Regarding issue here, target_offset passed from the caller is to avoid 
rebind if get_offset() would be called for "reloc" allocator.
So there's not real value offset within bo. I would add separate 
value_offset (shift) to allow caller to put place where it wants to 
write the value.


> +	if (!ahnd) {
> +		reloc.target_handle = obj[SCRATCH].handle;
> +		reloc.presumed_offset = -1;
> +		reloc.offset = sizeof(uint32_t) * (i + 1);
> +		reloc.delta = delta;
> +		reloc.read_domains = I915_GEM_DOMAIN_INSTRUCTION;
> +		reloc.write_domain = I915_GEM_DOMAIN_INSTRUCTION;
> +	} else {
> +		obj[SCRATCH].offset = target_offset;
> +		obj[SCRATCH].flags |= EXEC_OBJECT_PINNED | EXEC_OBJECT_WRITE;
> +		obj[BATCH].offset = bb_offset;
> +		obj[BATCH].flags |= EXEC_OBJECT_PINNED;
> +	}
> +	batch[i] = MI_STORE_DWORD_IMM | (gen < 6 ? 1 << 22 : 0);
> +	if (gen >= 8) {
> +		batch[++i] = target_offset + delta;
> +		batch[++i] = target_offset >> 32;

Probably I've added this in previous code, for being safe I would
add (target_offset + delta) >> 32 for avoid risk passing invalid higher
offset part on 32b boundary.

> +	} else if (gen >= 4) {
> +		batch[++i] = 0;
> +		batch[++i] = delta;
> +		reloc.offset += sizeof(uint32_t);
> +	} else {
> +		batch[i]--;
> +		batch[++i] = delta;
> +	}
> +	batch[++i] = target_value;
> +	batch[++i] = MI_BATCH_BUFFER_END;
> +	gem_write(fd, obj[BATCH].handle, 0, batch, sizeof(batch));
> +	gem_execbuf(fd, &execbuf);
> +	gem_close(fd, obj[BATCH].handle);
> +	put_offset(ahnd, obj[BATCH].handle);
> +}
> diff --git a/lib/igt_store.h b/lib/igt_store.h
> new file mode 100644
> index 000000000..4d5979e07
> --- /dev/null
> +++ b/lib/igt_store.h
> @@ -0,0 +1,30 @@
> +/*
> + * Copyright © 2020 Intel Corporation
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the next
> + * paragraph) shall be included in all copies or substantial portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
> + * IN THE SOFTWARE.
> + *
> + */

Use SPDX and 2021.

--
Zbigniew

> +
> +#include "igt_gt.h"
> +
> +void igt_store_word(int fd, uint64_t ahnd, const intel_ctx_t *ctx,
> +		    const struct intel_execution_engine2 *e,
> +		    int fence, uint32_t target_handle,
> +		    uint64_t target_offset, uint32_t target_value);
> diff --git a/lib/meson.build b/lib/meson.build
> index b9568a71b..3e43316d1 100644
> --- a/lib/meson.build
> +++ b/lib/meson.build
> @@ -72,6 +72,7 @@ lib_sources = [
>  	'igt_map.c',
>  	'igt_pm.c',
>  	'igt_dummyload.c',
> +	'igt_store.c',
>  	'uwildmat/uwildmat.c',
>  	'igt_kmod.c',
>  	'igt_panfrost.c',
> diff --git a/tests/i915/gem_exec_fence.c b/tests/i915/gem_exec_fence.c
> index 9a6336ce9..c4091a454 100644
> --- a/tests/i915/gem_exec_fence.c
> +++ b/tests/i915/gem_exec_fence.c
> @@ -28,6 +28,7 @@
>  #include "i915/gem.h"
>  #include "i915/gem_create.h"
>  #include "igt.h"
> +#include "igt_store.h"
>  #include "igt_syncobj.h"
>  #include "igt_sysfs.h"
>  #include "igt_vgem.h"
> @@ -57,74 +58,6 @@ struct sync_merge_data {
>  #define   MI_SEMAPHORE_SAD_EQ_SDD       (4 << 12)
>  #define   MI_SEMAPHORE_SAD_NEQ_SDD      (5 << 12)
>  
> -static void store(int fd, uint64_t ahnd, const intel_ctx_t *ctx,
> -		  const struct intel_execution_engine2 *e,
> -		  int fence, uint32_t target, uint64_t target_offset,
> -		  unsigned offset_value)
> -{
> -	const int SCRATCH = 0;
> -	const int BATCH = 1;
> -	const unsigned int gen = intel_gen(intel_get_drm_devid(fd));
> -	struct drm_i915_gem_exec_object2 obj[2];
> -	struct drm_i915_gem_relocation_entry reloc;
> -	struct drm_i915_gem_execbuffer2 execbuf;
> -	uint32_t batch[16], delta;
> -	uint64_t bb_offset;
> -	int i;
> -
> -	memset(&execbuf, 0, sizeof(execbuf));
> -	execbuf.buffers_ptr = to_user_pointer(obj);
> -	execbuf.buffer_count = 2;
> -	execbuf.flags = e->flags | I915_EXEC_FENCE_IN;
> -	execbuf.rsvd1 = ctx->id;
> -	execbuf.rsvd2 = fence;
> -	if (gen < 6)
> -		execbuf.flags |= I915_EXEC_SECURE;
> -
> -	memset(obj, 0, sizeof(obj));
> -	obj[SCRATCH].handle = target;
> -
> -	obj[BATCH].handle = gem_create(fd, 4096);
> -	obj[BATCH].relocs_ptr = to_user_pointer(&reloc);
> -	obj[BATCH].relocation_count = !ahnd ? 1 : 0;
> -	bb_offset = get_offset(ahnd, obj[BATCH].handle, 4096, 0);
> -	memset(&reloc, 0, sizeof(reloc));
> -
> -	i = 0;
> -	delta = sizeof(uint32_t) * offset_value;
> -	if (!ahnd) {
> -		reloc.target_handle = obj[SCRATCH].handle;
> -		reloc.presumed_offset = -1;
> -		reloc.offset = sizeof(uint32_t) * (i + 1);
> -		reloc.delta = delta;
> -		reloc.read_domains = I915_GEM_DOMAIN_INSTRUCTION;
> -		reloc.write_domain = I915_GEM_DOMAIN_INSTRUCTION;
> -	} else {
> -		obj[SCRATCH].offset = target_offset;
> -		obj[SCRATCH].flags |= EXEC_OBJECT_PINNED | EXEC_OBJECT_WRITE;
> -		obj[BATCH].offset = bb_offset;
> -		obj[BATCH].flags |= EXEC_OBJECT_PINNED;
> -	}
> -	batch[i] = MI_STORE_DWORD_IMM | (gen < 6 ? 1 << 22 : 0);
> -	if (gen >= 8) {
> -		batch[++i] = target_offset + delta;
> -		batch[++i] = target_offset >> 32;
> -	} else if (gen >= 4) {
> -		batch[++i] = 0;
> -		batch[++i] = delta;
> -		reloc.offset += sizeof(uint32_t);
> -	} else {
> -		batch[i]--;
> -		batch[++i] = delta;
> -	}
> -	batch[++i] = offset_value;
> -	batch[++i] = MI_BATCH_BUFFER_END;
> -	gem_write(fd, obj[BATCH].handle, 0, batch, sizeof(batch));
> -	gem_execbuf(fd, &execbuf);
> -	gem_close(fd, obj[BATCH].handle);
> -	put_offset(ahnd, obj[BATCH].handle);
> -}
> -
>  static bool fence_busy(int fence)
>  {
>  	return poll(&(struct pollfd){fence, POLLIN}, 1, 0) == 0;
> @@ -400,13 +333,13 @@ static void test_fence_await(int fd, const intel_ctx_t *ctx,
>  			continue;
>  
>  		if (flags & NONBLOCK) {
> -			store(fd, ahnd, ctx, e2, spin->out_fence,
> -			      scratch, scratch_offset, i);
> +			igt_store_word(fd, ahnd, ctx, e2, spin->out_fence,
> +				       scratch, scratch_offset, i);
>  		} else {
>  			igt_fork(child, 1) {
>  				ahnd = get_reloc_ahnd(fd, ctx->id);
> -				store(fd, ahnd, ctx, e2, spin->out_fence,
> -				      scratch, scratch_offset, i);
> +				igt_store_word(fd, ahnd, ctx, e2, spin->out_fence,
> +					       scratch, scratch_offset, i);
>  				put_ahnd(ahnd);
>  			}
>  		}
> diff --git a/tests/i915/i915_hangman.c b/tests/i915/i915_hangman.c
> index 20653b479..4cb9b8b85 100644
> --- a/tests/i915/i915_hangman.c
> +++ b/tests/i915/i915_hangman.c
> @@ -36,6 +36,7 @@
>  #include "i915/gem.h"
>  #include "i915/gem_create.h"
>  #include "igt.h"
> +#include "igt_store.h"
>  #include "igt_sysfs.h"
>  #include "igt_debugfs.h"
>  #include "sw_sync.h"
> @@ -51,64 +52,6 @@ static int sysfs = -1;
>  
>  IGT_TEST_DESCRIPTION("Tests for hang detection and recovery");
>  
> -/* Requires master for STORE_DWORD on gen4/5 */
> -static void store(int fd, const struct intel_execution_engine2 *e,
> -		  int fence, uint32_t target, unsigned offset_value)
> -{
> -	const int SCRATCH = 0;
> -	const int BATCH = 1;
> -	const int gen = intel_gen(intel_get_drm_devid(fd));
> -	struct drm_i915_gem_exec_object2 obj[2];
> -	struct drm_i915_gem_relocation_entry reloc;
> -	struct drm_i915_gem_execbuffer2 execbuf;
> -	uint32_t batch[16];
> -	int i;
> -
> -	memset(&execbuf, 0, sizeof(execbuf));
> -	execbuf.buffers_ptr = to_user_pointer(obj);
> -	execbuf.buffer_count = ARRAY_SIZE(obj);
> -	execbuf.flags = e->flags;
> -	if (fence != -1) {
> -		execbuf.flags |= I915_EXEC_FENCE_IN;
> -		execbuf.rsvd2 = fence;
> -	}
> -	if (gen < 6)
> -		execbuf.flags |= I915_EXEC_SECURE;
> -
> -	memset(obj, 0, sizeof(obj));
> -	obj[SCRATCH].handle = target;
> -
> -	obj[BATCH].handle = gem_create(fd, 4096);
> -	obj[BATCH].relocs_ptr = to_user_pointer(&reloc);
> -	obj[BATCH].relocation_count = 1;
> -	memset(&reloc, 0, sizeof(reloc));
> -
> -	i = 0;
> -	reloc.target_handle = obj[SCRATCH].handle;
> -	reloc.presumed_offset = -1;
> -	reloc.offset = sizeof(uint32_t) * (i + 1);
> -	reloc.delta = sizeof(uint32_t) * offset_value;
> -	reloc.read_domains = I915_GEM_DOMAIN_INSTRUCTION;
> -	reloc.write_domain = I915_GEM_DOMAIN_INSTRUCTION;
> -	batch[i] = MI_STORE_DWORD_IMM | (gen < 6 ? 1 << 22 : 0);
> -	if (gen >= 8) {
> -		batch[++i] = reloc.delta;
> -		batch[++i] = 0;
> -	} else if (gen >= 4) {
> -		batch[++i] = 0;
> -		batch[++i] = reloc.delta;
> -		reloc.offset += sizeof(uint32_t);
> -	} else {
> -		batch[i]--;
> -		batch[++i] = reloc.delta;
> -	}
> -	batch[++i] = offset_value;
> -	batch[++i] = MI_BATCH_BUFFER_END;
> -	gem_write(fd, obj[BATCH].handle, 0, batch, sizeof(batch));
> -	gem_execbuf(fd, &execbuf);
> -	gem_close(fd, obj[BATCH].handle);
> -}
> -
>  static void check_alive(void)
>  {
>  	const struct intel_execution_engine2 *engine;
> @@ -138,7 +81,7 @@ static void check_alive(void)
>  			continue;
>  
>  		/* +OFFSET_ALIVE to ensure engine zero doesn't get a false negative */
> -		store(fd, engine, -1, scratch, i + OFFSET_ALIVE);
> +		igt_store_word(fd, ahnd, ctx, engine, -1, scratch, i + OFFSET_ALIVE, i + OFFSET_ALIVE);
>  		i++;
>  	}
>  
> -- 
> 2.25.1
> 

Re: [Intel-gfx] [igt-dev] [PATCH i-g-t 07/11] tests/i915/i915_hangman: Add alive-ness test after error capture

[John Harrison]

On 12/15/2021 23:23, Zbigniew Kempczyński wrote:
> On Mon, Dec 13, 2021 at 03:29:10PM -0800, John.C.Harrison@Intel.com wrote:
>> From: John Harrison <John.C.Harrison@Intel.com>
>>
>> Added a an extra step to the i915_hangman tests to check that the
>> system is still alive after the hang and recovery. This submits a
>> simple batch to each engine which does a write to memory and checks
>> that the write occurred.
>>
>> Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
>> ---
>>   tests/i915/i915_hangman.c | 115 ++++++++++++++++++++++++++++++++++++++
>>   1 file changed, 115 insertions(+)
>>
>> diff --git a/tests/i915/i915_hangman.c b/tests/i915/i915_hangman.c
>> index b77705206..20653b479 100644
>> --- a/tests/i915/i915_hangman.c
>> +++ b/tests/i915/i915_hangman.c
>> @@ -47,8 +47,113 @@
>>   static int device = -1;
>>   static int sysfs = -1;
>>   
>> +#define OFFSET_ALIVE	10
>> +
>>   IGT_TEST_DESCRIPTION("Tests for hang detection and recovery");
>>   
>> +/* Requires master for STORE_DWORD on gen4/5 */
>> +static void store(int fd, const struct intel_execution_engine2 *e,
>> +		  int fence, uint32_t target, unsigned offset_value)
>> +{
>> +	const int SCRATCH = 0;
>> +	const int BATCH = 1;
>> +	const int gen = intel_gen(intel_get_drm_devid(fd));
>> +	struct drm_i915_gem_exec_object2 obj[2];
>> +	struct drm_i915_gem_relocation_entry reloc;
>> +	struct drm_i915_gem_execbuffer2 execbuf;
>> +	uint32_t batch[16];
>> +	int i;
>> +
>> +	memset(&execbuf, 0, sizeof(execbuf));
>> +	execbuf.buffers_ptr = to_user_pointer(obj);
>> +	execbuf.buffer_count = ARRAY_SIZE(obj);
>> +	execbuf.flags = e->flags;
>> +	if (fence != -1) {
>> +		execbuf.flags |= I915_EXEC_FENCE_IN;
>> +		execbuf.rsvd2 = fence;
>> +	}
>> +	if (gen < 6)
>> +		execbuf.flags |= I915_EXEC_SECURE;
>> +
>> +	memset(obj, 0, sizeof(obj));
>> +	obj[SCRATCH].handle = target;
>> +
>> +	obj[BATCH].handle = gem_create(fd, 4096);
>> +	obj[BATCH].relocs_ptr = to_user_pointer(&reloc);
>> +	obj[BATCH].relocation_count = 1;
>> +	memset(&reloc, 0, sizeof(reloc));
>> +
>> +	i = 0;
>> +	reloc.target_handle = obj[SCRATCH].handle;
>> +	reloc.presumed_offset = -1;
>> +	reloc.offset = sizeof(uint32_t) * (i + 1);
>> +	reloc.delta = sizeof(uint32_t) * offset_value;
>> +	reloc.read_domains = I915_GEM_DOMAIN_INSTRUCTION;
>> +	reloc.write_domain = I915_GEM_DOMAIN_INSTRUCTION;
>> +	batch[i] = MI_STORE_DWORD_IMM | (gen < 6 ? 1 << 22 : 0);
>> +	if (gen >= 8) {
>> +		batch[++i] = reloc.delta;
>> +		batch[++i] = 0;
>> +	} else if (gen >= 4) {
>> +		batch[++i] = 0;
>> +		batch[++i] = reloc.delta;
>> +		reloc.offset += sizeof(uint32_t);
>> +	} else {
>> +		batch[i]--;
>> +		batch[++i] = reloc.delta;
>> +	}
>> +	batch[++i] = offset_value;
>> +	batch[++i] = MI_BATCH_BUFFER_END;
>> +	gem_write(fd, obj[BATCH].handle, 0, batch, sizeof(batch));
>> +	gem_execbuf(fd, &execbuf);
>> +	gem_close(fd, obj[BATCH].handle);
>> +}
>> +
>> +static void check_alive(void)
>> +{
>> +	const struct intel_execution_engine2 *engine;
>> +	const intel_ctx_t *ctx;
>> +	uint32_t scratch, *out;
>> +	int fd, i = 0;
>> +	uint64_t ahnd;
>> +
>> +	fd = drm_open_driver(DRIVER_INTEL);
>> +	igt_require(gem_class_can_store_dword(fd, 0));
>> +
>> +	ctx = intel_ctx_create_all_physical(fd);
>> +	ahnd = get_reloc_ahnd(fd, ctx->id);
>> +	scratch = gem_create(fd, 4096);
>> +	out = gem_mmap__wc(fd, scratch, 0, 4096, PROT_WRITE);
>> +	gem_set_domain(fd, scratch,
>> +			I915_GEM_DOMAIN_GTT, I915_GEM_DOMAIN_GTT);
>> +
>> +	for_each_physical_engine(fd, engine) {
>> +		igt_assert_eq_u32(out[i + OFFSET_ALIVE], 0);
>> +		i++;
>> +	}
>> +
>> +	i = 0;
>> +	for_each_ctx_engine(fd, ctx, engine) {
>> +		if (!gem_class_can_store_dword(fd, engine->class))
>> +			continue;
>> +
>> +		/* +OFFSET_ALIVE to ensure engine zero doesn't get a false negative */
>> +		store(fd, engine, -1, scratch, i + OFFSET_ALIVE);
> You need to pass ctx + ahnd to store() to add softpin path. Relocs
> won't work above Tigerlake.
There didn't seem much point in reworking the code in this file when it 
is going to be removed in the next patch. I might just re-order the two 
for the next rev. Create the helper first and then never actually add 
the almost-duplicate here at all.

John.

>
> --
> Zbigniew
>
>
>> +		i++;
>> +	}
>> +
>> +	gem_set_domain(fd, scratch, I915_GEM_DOMAIN_GTT, 0);
>> +
>> +	while (i--)
>> +		igt_assert_eq_u32(out[i + OFFSET_ALIVE], i + OFFSET_ALIVE);
>> +
>> +	munmap(out, 4096);
>> +	gem_close(fd, scratch);
>> +	put_ahnd(ahnd);
>> +	intel_ctx_destroy(fd, ctx);
>> +	close(fd);
>> +}
>> +
>>   static bool has_error_state(int dir)
>>   {
>>   	bool result;
>> @@ -230,6 +335,8 @@ static void test_error_state_capture(const intel_ctx_t *ctx,
>>   	check_error_state(e->name, offset, batch);
>>   	munmap(batch, 4096);
>>   	put_ahnd(ahnd);
>> +
>> +	check_alive();
>>   }
>>   
>>   static void
>> @@ -288,6 +395,8 @@ test_engine_hang(const intel_ctx_t *ctx,
>>   		put_ahnd(ahndN);
>>   	}
>>   	put_ahnd(ahnd);
>> +
>> +	check_alive();
>>   }
>>   
>>   static int hang_count;
>> @@ -320,6 +429,8 @@ static void test_hang_detector(const intel_ctx_t *ctx,
>>   
>>   	/* Did it work? */
>>   	igt_assert(hang_count == 1);
>> +
>> +	check_alive();
>>   }
>>   
>>   /* This test covers the case where we end up in an uninitialised area of the
>> @@ -355,6 +466,8 @@ static void hangcheck_unterminated(const intel_ctx_t *ctx)
>>   		igt_force_gpu_reset(device);
>>   		igt_assert_f(0, "unterminated batch did not trigger a hang!");
>>   	}
>> +
>> +	check_alive();
>>   }
>>   
>>   static void do_tests(const char *name, const char *prefix,
>> @@ -432,6 +545,8 @@ igt_main
>>   		igt_assert(sysfs != -1);
>>   
>>   		igt_require(has_error_state(sysfs));
>> +
>> +		gem_require_mmap_wc(device);
>>   	}
>>   
>>   	igt_describe("Basic error capture");
>> -- 
>> 2.25.1
>>

Re: [Intel-gfx] [igt-dev] [PATCH i-g-t 08/11] lib/store: Refactor common store code into helper function

[John Harrison]

On 12/15/2021 23:46, Zbigniew Kempczyński wrote:
> On Mon, Dec 13, 2021 at 03:29:11PM -0800, John.C.Harrison@Intel.com wrote:
>> From: John Harrison <John.C.Harrison@Intel.com>
>>
>> A lot of tests use almost identical code for creating a batch buffer
>> which does a single write to memory. This patch collects two such
>> instances into a common helper function. Unfortunately, the other
>> instances are all subtly different enough to make it not so trivial to
>> try to use the helper. It could be done but it is unclear if it is
>> worth the effort at this point. This patch proves the concept, if
>> people like it enough then it can be extended.
>>
>> Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
>> ---
>>   lib/igt_store.c             | 114 ++++++++++++++++++++++++++++++++++++
>>   lib/igt_store.h             |  30 ++++++++++
>>   lib/meson.build             |   1 +
>>   tests/i915/gem_exec_fence.c |  77 ++----------------------
>>   tests/i915/i915_hangman.c   |  61 +------------------
>>   5 files changed, 152 insertions(+), 131 deletions(-)
>>   create mode 100644 lib/igt_store.c
>>   create mode 100644 lib/igt_store.h
>>
>> diff --git a/lib/igt_store.c b/lib/igt_store.c
>> new file mode 100644
>> index 000000000..6d9869b58
>> --- /dev/null
>> +++ b/lib/igt_store.c
>> @@ -0,0 +1,114 @@
>> +/*
>> + * Copyright © 2020 Intel Corporation
>> + *
>> + * Permission is hereby granted, free of charge, to any person obtaining a
>> + * copy of this software and associated documentation files (the "Software"),
>> + * to deal in the Software without restriction, including without limitation
>> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>> + * and/or sell copies of the Software, and to permit persons to whom the
>> + * Software is furnished to do so, subject to the following conditions:
>> + *
>> + * The above copyright notice and this permission notice (including the next
>> + * paragraph) shall be included in all copies or substantial portions of the
>> + * Software.
>> + *
>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
>> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
>> + * IN THE SOFTWARE.
>> + *
>> + */
> Use SPDX. I like idea of extracting this.
>
>> +
>> +#include "i915/gem_create.h"
>> +#include "igt_core.h"
>> +#include "drmtest.h"
>> +#include "igt_store.h"
>> +#include "intel_chipset.h"
>> +#include "intel_reg.h"
>> +#include "ioctl_wrappers.h"
>> +#include "lib/intel_allocator.h"
>> +
>> +/**
>> + * SECTION:igt_store_word
>> + * @short_description: Library for writing a value to memory
>> + * @title: StoreWord
>> + * @include: igt.h
>> + *
>> + * A lot of igt testcases need some mechanism for writing a value to memory
>> + * as a test that a batch buffer has executed.
>> + *
>> + * NB: Requires master for STORE_DWORD on gen4/5.
>> + */
>> +void igt_store_word(int fd, uint64_t ahnd, const intel_ctx_t *ctx,
>> +		    const struct intel_execution_engine2 *e,
>> +		    int fence, uint32_t target_handle,
>> +		    uint64_t target_offset, uint32_t target_value)
>> +{
>> +	const int SCRATCH = 0;
>> +	const int BATCH = 1;
>> +	const unsigned int gen = intel_gen(intel_get_drm_devid(fd));
>> +	struct drm_i915_gem_exec_object2 obj[2];
>> +	struct drm_i915_gem_relocation_entry reloc;
>> +	struct drm_i915_gem_execbuffer2 execbuf;
>> +	uint32_t batch[16], delta;
>> +	uint64_t bb_offset;
>> +	int i;
>> +
>> +	memset(&execbuf, 0, sizeof(execbuf));
>> +	execbuf.buffers_ptr = to_user_pointer(obj);
>> +	execbuf.buffer_count = ARRAY_SIZE(obj);
>> +	execbuf.flags = e->flags;
>> +	execbuf.rsvd1 = ctx->id;
>> +	if (fence != -1) {
>> +		execbuf.flags |= I915_EXEC_FENCE_IN;
>> +		execbuf.rsvd2 = fence;
>> +	}
>> +	if (gen < 6)
>> +		execbuf.flags |= I915_EXEC_SECURE;
>> +
>> +	memset(obj, 0, sizeof(obj));
>> +	obj[SCRATCH].handle = target_handle;
>> +
>> +	obj[BATCH].handle = gem_create(fd, 4096);
>> +	obj[BATCH].relocs_ptr = to_user_pointer(&reloc);
>> +	obj[BATCH].relocation_count = !ahnd ? 1 : 0;
>> +	bb_offset = get_offset(ahnd, obj[BATCH].handle, 4096, 0);
>> +	memset(&reloc, 0, sizeof(reloc));
>> +
>> +	i = 0;
>> +	delta = sizeof(uint32_t) * target_value;	/* why value not offset??? */
> I guess I know why there's problem here. target_offset is address in vm
> passed by the caller. This is regarding to some limitations of allocator
> infrastructure - for "reloc" pseudo-allocator you would get new offset
> (internally it returns offset and then add size for new "allocation").
> With this we don't need to wait for rebind offset for new execbuf.
> With "simple" allocator put will release offset so new allocation will
> reuse same offset. Ashutosh proposed how to join both functionalities
> (stepping as with reloc, stateful like in simple) but I got no time to
> code this.
>
> Regarding issue here, target_offset passed from the caller is to avoid
> rebind if get_offset() would be called for "reloc" allocator.
> So there's not real value offset within bo. I would add separate
> value_offset (shift) to allow caller to put place where it wants to
> write the value.
If you understand what is going on here and how to improve it then feel 
free to either send me an updated version or post an extra patch after 
this is merged. I don't get how any of the new reloc (or anti-reloc?) 
code is meant to work. These patches were all written as part of the GuC 
support a long time ago - before there was any such thing as an AHND 
(what does that stand for?) or intel_ctx_t. All I'm doing in this patch 
is moving the existing code to a helper and trying to make it generic 
enough to be used by another test. And right now, the two tests are 
passing on both GuC and execlist platforms for me. So the code can't be 
all that broken.


>
>
>> +	if (!ahnd) {
>> +		reloc.target_handle = obj[SCRATCH].handle;
>> +		reloc.presumed_offset = -1;
>> +		reloc.offset = sizeof(uint32_t) * (i + 1);
>> +		reloc.delta = delta;
>> +		reloc.read_domains = I915_GEM_DOMAIN_INSTRUCTION;
>> +		reloc.write_domain = I915_GEM_DOMAIN_INSTRUCTION;
>> +	} else {
>> +		obj[SCRATCH].offset = target_offset;
>> +		obj[SCRATCH].flags |= EXEC_OBJECT_PINNED | EXEC_OBJECT_WRITE;
>> +		obj[BATCH].offset = bb_offset;
>> +		obj[BATCH].flags |= EXEC_OBJECT_PINNED;
>> +	}
>> +	batch[i] = MI_STORE_DWORD_IMM | (gen < 6 ? 1 << 22 : 0);
>> +	if (gen >= 8) {
>> +		batch[++i] = target_offset + delta;
>> +		batch[++i] = target_offset >> 32;
> Probably I've added this in previous code, for being safe I would
> add (target_offset + delta) >> 32 for avoid risk passing invalid higher
> offset part on 32b boundary.
Pretty sure we don't have any addresses larger than 32 bits yet, but 
yes, delta should be added in.

Thanks,
John.

>
>> +	} else if (gen >= 4) {
>> +		batch[++i] = 0;
>> +		batch[++i] = delta;
>> +		reloc.offset += sizeof(uint32_t);
>> +	} else {
>> +		batch[i]--;
>> +		batch[++i] = delta;
>> +	}
>> +	batch[++i] = target_value;
>> +	batch[++i] = MI_BATCH_BUFFER_END;
>> +	gem_write(fd, obj[BATCH].handle, 0, batch, sizeof(batch));
>> +	gem_execbuf(fd, &execbuf);
>> +	gem_close(fd, obj[BATCH].handle);
>> +	put_offset(ahnd, obj[BATCH].handle);
>> +}
>> diff --git a/lib/igt_store.h b/lib/igt_store.h
>> new file mode 100644
>> index 000000000..4d5979e07
>> --- /dev/null
>> +++ b/lib/igt_store.h
>> @@ -0,0 +1,30 @@
>> +/*
>> + * Copyright © 2020 Intel Corporation
>> + *
>> + * Permission is hereby granted, free of charge, to any person obtaining a
>> + * copy of this software and associated documentation files (the "Software"),
>> + * to deal in the Software without restriction, including without limitation
>> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>> + * and/or sell copies of the Software, and to permit persons to whom the
>> + * Software is furnished to do so, subject to the following conditions:
>> + *
>> + * The above copyright notice and this permission notice (including the next
>> + * paragraph) shall be included in all copies or substantial portions of the
>> + * Software.
>> + *
>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
>> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
>> + * IN THE SOFTWARE.
>> + *
>> + */
> Use SPDX and 2021.
>
> --
> Zbigniew
>
>> +
>> +#include "igt_gt.h"
>> +
>> +void igt_store_word(int fd, uint64_t ahnd, const intel_ctx_t *ctx,
>> +		    const struct intel_execution_engine2 *e,
>> +		    int fence, uint32_t target_handle,
>> +		    uint64_t target_offset, uint32_t target_value);
>> diff --git a/lib/meson.build b/lib/meson.build
>> index b9568a71b..3e43316d1 100644
>> --- a/lib/meson.build
>> +++ b/lib/meson.build
>> @@ -72,6 +72,7 @@ lib_sources = [
>>   	'igt_map.c',
>>   	'igt_pm.c',
>>   	'igt_dummyload.c',
>> +	'igt_store.c',
>>   	'uwildmat/uwildmat.c',
>>   	'igt_kmod.c',
>>   	'igt_panfrost.c',
>> diff --git a/tests/i915/gem_exec_fence.c b/tests/i915/gem_exec_fence.c
>> index 9a6336ce9..c4091a454 100644
>> --- a/tests/i915/gem_exec_fence.c
>> +++ b/tests/i915/gem_exec_fence.c
>> @@ -28,6 +28,7 @@
>>   #include "i915/gem.h"
>>   #include "i915/gem_create.h"
>>   #include "igt.h"
>> +#include "igt_store.h"
>>   #include "igt_syncobj.h"
>>   #include "igt_sysfs.h"
>>   #include "igt_vgem.h"
>> @@ -57,74 +58,6 @@ struct sync_merge_data {
>>   #define   MI_SEMAPHORE_SAD_EQ_SDD       (4 << 12)
>>   #define   MI_SEMAPHORE_SAD_NEQ_SDD      (5 << 12)
>>   
>> -static void store(int fd, uint64_t ahnd, const intel_ctx_t *ctx,
>> -		  const struct intel_execution_engine2 *e,
>> -		  int fence, uint32_t target, uint64_t target_offset,
>> -		  unsigned offset_value)
>> -{
>> -	const int SCRATCH = 0;
>> -	const int BATCH = 1;
>> -	const unsigned int gen = intel_gen(intel_get_drm_devid(fd));
>> -	struct drm_i915_gem_exec_object2 obj[2];
>> -	struct drm_i915_gem_relocation_entry reloc;
>> -	struct drm_i915_gem_execbuffer2 execbuf;
>> -	uint32_t batch[16], delta;
>> -	uint64_t bb_offset;
>> -	int i;
>> -
>> -	memset(&execbuf, 0, sizeof(execbuf));
>> -	execbuf.buffers_ptr = to_user_pointer(obj);
>> -	execbuf.buffer_count = 2;
>> -	execbuf.flags = e->flags | I915_EXEC_FENCE_IN;
>> -	execbuf.rsvd1 = ctx->id;
>> -	execbuf.rsvd2 = fence;
>> -	if (gen < 6)
>> -		execbuf.flags |= I915_EXEC_SECURE;
>> -
>> -	memset(obj, 0, sizeof(obj));
>> -	obj[SCRATCH].handle = target;
>> -
>> -	obj[BATCH].handle = gem_create(fd, 4096);
>> -	obj[BATCH].relocs_ptr = to_user_pointer(&reloc);
>> -	obj[BATCH].relocation_count = !ahnd ? 1 : 0;
>> -	bb_offset = get_offset(ahnd, obj[BATCH].handle, 4096, 0);
>> -	memset(&reloc, 0, sizeof(reloc));
>> -
>> -	i = 0;
>> -	delta = sizeof(uint32_t) * offset_value;
>> -	if (!ahnd) {
>> -		reloc.target_handle = obj[SCRATCH].handle;
>> -		reloc.presumed_offset = -1;
>> -		reloc.offset = sizeof(uint32_t) * (i + 1);
>> -		reloc.delta = delta;
>> -		reloc.read_domains = I915_GEM_DOMAIN_INSTRUCTION;
>> -		reloc.write_domain = I915_GEM_DOMAIN_INSTRUCTION;
>> -	} else {
>> -		obj[SCRATCH].offset = target_offset;
>> -		obj[SCRATCH].flags |= EXEC_OBJECT_PINNED | EXEC_OBJECT_WRITE;
>> -		obj[BATCH].offset = bb_offset;
>> -		obj[BATCH].flags |= EXEC_OBJECT_PINNED;
>> -	}
>> -	batch[i] = MI_STORE_DWORD_IMM | (gen < 6 ? 1 << 22 : 0);
>> -	if (gen >= 8) {
>> -		batch[++i] = target_offset + delta;
>> -		batch[++i] = target_offset >> 32;
>> -	} else if (gen >= 4) {
>> -		batch[++i] = 0;
>> -		batch[++i] = delta;
>> -		reloc.offset += sizeof(uint32_t);
>> -	} else {
>> -		batch[i]--;
>> -		batch[++i] = delta;
>> -	}
>> -	batch[++i] = offset_value;
>> -	batch[++i] = MI_BATCH_BUFFER_END;
>> -	gem_write(fd, obj[BATCH].handle, 0, batch, sizeof(batch));
>> -	gem_execbuf(fd, &execbuf);
>> -	gem_close(fd, obj[BATCH].handle);
>> -	put_offset(ahnd, obj[BATCH].handle);
>> -}
>> -
>>   static bool fence_busy(int fence)
>>   {
>>   	return poll(&(struct pollfd){fence, POLLIN}, 1, 0) == 0;
>> @@ -400,13 +333,13 @@ static void test_fence_await(int fd, const intel_ctx_t *ctx,
>>   			continue;
>>   
>>   		if (flags & NONBLOCK) {
>> -			store(fd, ahnd, ctx, e2, spin->out_fence,
>> -			      scratch, scratch_offset, i);
>> +			igt_store_word(fd, ahnd, ctx, e2, spin->out_fence,
>> +				       scratch, scratch_offset, i);
>>   		} else {
>>   			igt_fork(child, 1) {
>>   				ahnd = get_reloc_ahnd(fd, ctx->id);
>> -				store(fd, ahnd, ctx, e2, spin->out_fence,
>> -				      scratch, scratch_offset, i);
>> +				igt_store_word(fd, ahnd, ctx, e2, spin->out_fence,
>> +					       scratch, scratch_offset, i);
>>   				put_ahnd(ahnd);
>>   			}
>>   		}
>> diff --git a/tests/i915/i915_hangman.c b/tests/i915/i915_hangman.c
>> index 20653b479..4cb9b8b85 100644
>> --- a/tests/i915/i915_hangman.c
>> +++ b/tests/i915/i915_hangman.c
>> @@ -36,6 +36,7 @@
>>   #include "i915/gem.h"
>>   #include "i915/gem_create.h"
>>   #include "igt.h"
>> +#include "igt_store.h"
>>   #include "igt_sysfs.h"
>>   #include "igt_debugfs.h"
>>   #include "sw_sync.h"
>> @@ -51,64 +52,6 @@ static int sysfs = -1;
>>   
>>   IGT_TEST_DESCRIPTION("Tests for hang detection and recovery");
>>   
>> -/* Requires master for STORE_DWORD on gen4/5 */
>> -static void store(int fd, const struct intel_execution_engine2 *e,
>> -		  int fence, uint32_t target, unsigned offset_value)
>> -{
>> -	const int SCRATCH = 0;
>> -	const int BATCH = 1;
>> -	const int gen = intel_gen(intel_get_drm_devid(fd));
>> -	struct drm_i915_gem_exec_object2 obj[2];
>> -	struct drm_i915_gem_relocation_entry reloc;
>> -	struct drm_i915_gem_execbuffer2 execbuf;
>> -	uint32_t batch[16];
>> -	int i;
>> -
>> -	memset(&execbuf, 0, sizeof(execbuf));
>> -	execbuf.buffers_ptr = to_user_pointer(obj);
>> -	execbuf.buffer_count = ARRAY_SIZE(obj);
>> -	execbuf.flags = e->flags;
>> -	if (fence != -1) {
>> -		execbuf.flags |= I915_EXEC_FENCE_IN;
>> -		execbuf.rsvd2 = fence;
>> -	}
>> -	if (gen < 6)
>> -		execbuf.flags |= I915_EXEC_SECURE;
>> -
>> -	memset(obj, 0, sizeof(obj));
>> -	obj[SCRATCH].handle = target;
>> -
>> -	obj[BATCH].handle = gem_create(fd, 4096);
>> -	obj[BATCH].relocs_ptr = to_user_pointer(&reloc);
>> -	obj[BATCH].relocation_count = 1;
>> -	memset(&reloc, 0, sizeof(reloc));
>> -
>> -	i = 0;
>> -	reloc.target_handle = obj[SCRATCH].handle;
>> -	reloc.presumed_offset = -1;
>> -	reloc.offset = sizeof(uint32_t) * (i + 1);
>> -	reloc.delta = sizeof(uint32_t) * offset_value;
>> -	reloc.read_domains = I915_GEM_DOMAIN_INSTRUCTION;
>> -	reloc.write_domain = I915_GEM_DOMAIN_INSTRUCTION;
>> -	batch[i] = MI_STORE_DWORD_IMM | (gen < 6 ? 1 << 22 : 0);
>> -	if (gen >= 8) {
>> -		batch[++i] = reloc.delta;
>> -		batch[++i] = 0;
>> -	} else if (gen >= 4) {
>> -		batch[++i] = 0;
>> -		batch[++i] = reloc.delta;
>> -		reloc.offset += sizeof(uint32_t);
>> -	} else {
>> -		batch[i]--;
>> -		batch[++i] = reloc.delta;
>> -	}
>> -	batch[++i] = offset_value;
>> -	batch[++i] = MI_BATCH_BUFFER_END;
>> -	gem_write(fd, obj[BATCH].handle, 0, batch, sizeof(batch));
>> -	gem_execbuf(fd, &execbuf);
>> -	gem_close(fd, obj[BATCH].handle);
>> -}
>> -
>>   static void check_alive(void)
>>   {
>>   	const struct intel_execution_engine2 *engine;
>> @@ -138,7 +81,7 @@ static void check_alive(void)
>>   			continue;
>>   
>>   		/* +OFFSET_ALIVE to ensure engine zero doesn't get a false negative */
>> -		store(fd, engine, -1, scratch, i + OFFSET_ALIVE);
>> +		igt_store_word(fd, ahnd, ctx, engine, -1, scratch, i + OFFSET_ALIVE, i + OFFSET_ALIVE);
>>   		i++;
>>   	}
>>   
>> -- 
>> 2.25.1
>>

Re: [igt-dev] [PATCH i-g-t 08/11] lib/store: Refactor common store code into helper function

[John Harrison]

On 12/15/2021 23:46, Zbigniew Kempczyński wrote:
> On Mon, Dec 13, 2021 at 03:29:11PM -0800, John.C.Harrison@Intel.com wrote:
>> From: John Harrison <John.C.Harrison@Intel.com>
>>
>> A lot of tests use almost identical code for creating a batch buffer
>> which does a single write to memory. This patch collects two such
>> instances into a common helper function. Unfortunately, the other
>> instances are all subtly different enough to make it not so trivial to
>> try to use the helper. It could be done but it is unclear if it is
>> worth the effort at this point. This patch proves the concept, if
>> people like it enough then it can be extended.
>>
>> Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
>> ---
>>   lib/igt_store.c             | 114 ++++++++++++++++++++++++++++++++++++
>>   lib/igt_store.h             |  30 ++++++++++
>>   lib/meson.build             |   1 +
>>   tests/i915/gem_exec_fence.c |  77 ++----------------------
>>   tests/i915/i915_hangman.c   |  61 +------------------
>>   5 files changed, 152 insertions(+), 131 deletions(-)
>>   create mode 100644 lib/igt_store.c
>>   create mode 100644 lib/igt_store.h
>>
>> diff --git a/lib/igt_store.c b/lib/igt_store.c
>> new file mode 100644
>> index 000000000..6d9869b58
>> --- /dev/null
>> +++ b/lib/igt_store.c
>> @@ -0,0 +1,114 @@
>> +/*
>> + * Copyright © 2020 Intel Corporation
>> + *
>> + * Permission is hereby granted, free of charge, to any person obtaining a
>> + * copy of this software and associated documentation files (the "Software"),
>> + * to deal in the Software without restriction, including without limitation
>> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>> + * and/or sell copies of the Software, and to permit persons to whom the
>> + * Software is furnished to do so, subject to the following conditions:
>> + *
>> + * The above copyright notice and this permission notice (including the next
>> + * paragraph) shall be included in all copies or substantial portions of the
>> + * Software.
>> + *
>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
>> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
>> + * IN THE SOFTWARE.
>> + *
>> + */
> Use SPDX. I like idea of extracting this.
>
>> +
>> +#include "i915/gem_create.h"
>> +#include "igt_core.h"
>> +#include "drmtest.h"
>> +#include "igt_store.h"
>> +#include "intel_chipset.h"
>> +#include "intel_reg.h"
>> +#include "ioctl_wrappers.h"
>> +#include "lib/intel_allocator.h"
>> +
>> +/**
>> + * SECTION:igt_store_word
>> + * @short_description: Library for writing a value to memory
>> + * @title: StoreWord
>> + * @include: igt.h
>> + *
>> + * A lot of igt testcases need some mechanism for writing a value to memory
>> + * as a test that a batch buffer has executed.
>> + *
>> + * NB: Requires master for STORE_DWORD on gen4/5.
>> + */
>> +void igt_store_word(int fd, uint64_t ahnd, const intel_ctx_t *ctx,
>> +		    const struct intel_execution_engine2 *e,
>> +		    int fence, uint32_t target_handle,
>> +		    uint64_t target_offset, uint32_t target_value)
>> +{
>> +	const int SCRATCH = 0;
>> +	const int BATCH = 1;
>> +	const unsigned int gen = intel_gen(intel_get_drm_devid(fd));
>> +	struct drm_i915_gem_exec_object2 obj[2];
>> +	struct drm_i915_gem_relocation_entry reloc;
>> +	struct drm_i915_gem_execbuffer2 execbuf;
>> +	uint32_t batch[16], delta;
>> +	uint64_t bb_offset;
>> +	int i;
>> +
>> +	memset(&execbuf, 0, sizeof(execbuf));
>> +	execbuf.buffers_ptr = to_user_pointer(obj);
>> +	execbuf.buffer_count = ARRAY_SIZE(obj);
>> +	execbuf.flags = e->flags;
>> +	execbuf.rsvd1 = ctx->id;
>> +	if (fence != -1) {
>> +		execbuf.flags |= I915_EXEC_FENCE_IN;
>> +		execbuf.rsvd2 = fence;
>> +	}
>> +	if (gen < 6)
>> +		execbuf.flags |= I915_EXEC_SECURE;
>> +
>> +	memset(obj, 0, sizeof(obj));
>> +	obj[SCRATCH].handle = target_handle;
>> +
>> +	obj[BATCH].handle = gem_create(fd, 4096);
>> +	obj[BATCH].relocs_ptr = to_user_pointer(&reloc);
>> +	obj[BATCH].relocation_count = !ahnd ? 1 : 0;
>> +	bb_offset = get_offset(ahnd, obj[BATCH].handle, 4096, 0);
>> +	memset(&reloc, 0, sizeof(reloc));
>> +
>> +	i = 0;
>> +	delta = sizeof(uint32_t) * target_value;	/* why value not offset??? */
> I guess I know why there's problem here. target_offset is address in vm
> passed by the caller. This is regarding to some limitations of allocator
> infrastructure - for "reloc" pseudo-allocator you would get new offset
> (internally it returns offset and then add size for new "allocation").
> With this we don't need to wait for rebind offset for new execbuf.
> With "simple" allocator put will release offset so new allocation will
> reuse same offset. Ashutosh proposed how to join both functionalities
> (stepping as with reloc, stateful like in simple) but I got no time to
> code this.
>
> Regarding issue here, target_offset passed from the caller is to avoid
> rebind if get_offset() would be called for "reloc" allocator.
> So there's not real value offset within bo. I would add separate
> value_offset (shift) to allow caller to put place where it wants to
> write the value.
If you understand what is going on here and how to improve it then feel 
free to either send me an updated version or post an extra patch after 
this is merged. I don't get how any of the new reloc (or anti-reloc?) 
code is meant to work. These patches were all written as part of the GuC 
support a long time ago - before there was any such thing as an AHND 
(what does that stand for?) or intel_ctx_t. All I'm doing in this patch 
is moving the existing code to a helper and trying to make it generic 
enough to be used by another test. And right now, the two tests are 
passing on both GuC and execlist platforms for me. So the code can't be 
all that broken.


>
>
>> +	if (!ahnd) {
>> +		reloc.target_handle = obj[SCRATCH].handle;
>> +		reloc.presumed_offset = -1;
>> +		reloc.offset = sizeof(uint32_t) * (i + 1);
>> +		reloc.delta = delta;
>> +		reloc.read_domains = I915_GEM_DOMAIN_INSTRUCTION;
>> +		reloc.write_domain = I915_GEM_DOMAIN_INSTRUCTION;
>> +	} else {
>> +		obj[SCRATCH].offset = target_offset;
>> +		obj[SCRATCH].flags |= EXEC_OBJECT_PINNED | EXEC_OBJECT_WRITE;
>> +		obj[BATCH].offset = bb_offset;
>> +		obj[BATCH].flags |= EXEC_OBJECT_PINNED;
>> +	}
>> +	batch[i] = MI_STORE_DWORD_IMM | (gen < 6 ? 1 << 22 : 0);
>> +	if (gen >= 8) {
>> +		batch[++i] = target_offset + delta;
>> +		batch[++i] = target_offset >> 32;
> Probably I've added this in previous code, for being safe I would
> add (target_offset + delta) >> 32 for avoid risk passing invalid higher
> offset part on 32b boundary.
Pretty sure we don't have any addresses larger than 32 bits yet, but 
yes, delta should be added in.

Thanks,
John.

>
>> +	} else if (gen >= 4) {
>> +		batch[++i] = 0;
>> +		batch[++i] = delta;
>> +		reloc.offset += sizeof(uint32_t);
>> +	} else {
>> +		batch[i]--;
>> +		batch[++i] = delta;
>> +	}
>> +	batch[++i] = target_value;
>> +	batch[++i] = MI_BATCH_BUFFER_END;
>> +	gem_write(fd, obj[BATCH].handle, 0, batch, sizeof(batch));
>> +	gem_execbuf(fd, &execbuf);
>> +	gem_close(fd, obj[BATCH].handle);
>> +	put_offset(ahnd, obj[BATCH].handle);
>> +}
>> diff --git a/lib/igt_store.h b/lib/igt_store.h
>> new file mode 100644
>> index 000000000..4d5979e07
>> --- /dev/null
>> +++ b/lib/igt_store.h
>> @@ -0,0 +1,30 @@
>> +/*
>> + * Copyright © 2020 Intel Corporation
>> + *
>> + * Permission is hereby granted, free of charge, to any person obtaining a
>> + * copy of this software and associated documentation files (the "Software"),
>> + * to deal in the Software without restriction, including without limitation
>> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>> + * and/or sell copies of the Software, and to permit persons to whom the
>> + * Software is furnished to do so, subject to the following conditions:
>> + *
>> + * The above copyright notice and this permission notice (including the next
>> + * paragraph) shall be included in all copies or substantial portions of the
>> + * Software.
>> + *
>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
>> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
>> + * IN THE SOFTWARE.
>> + *
>> + */
> Use SPDX and 2021.
>
> --
> Zbigniew
>
>> +
>> +#include "igt_gt.h"
>> +
>> +void igt_store_word(int fd, uint64_t ahnd, const intel_ctx_t *ctx,
>> +		    const struct intel_execution_engine2 *e,
>> +		    int fence, uint32_t target_handle,
>> +		    uint64_t target_offset, uint32_t target_value);
>> diff --git a/lib/meson.build b/lib/meson.build
>> index b9568a71b..3e43316d1 100644
>> --- a/lib/meson.build
>> +++ b/lib/meson.build
>> @@ -72,6 +72,7 @@ lib_sources = [
>>   	'igt_map.c',
>>   	'igt_pm.c',
>>   	'igt_dummyload.c',
>> +	'igt_store.c',
>>   	'uwildmat/uwildmat.c',
>>   	'igt_kmod.c',
>>   	'igt_panfrost.c',
>> diff --git a/tests/i915/gem_exec_fence.c b/tests/i915/gem_exec_fence.c
>> index 9a6336ce9..c4091a454 100644
>> --- a/tests/i915/gem_exec_fence.c
>> +++ b/tests/i915/gem_exec_fence.c
>> @@ -28,6 +28,7 @@
>>   #include "i915/gem.h"
>>   #include "i915/gem_create.h"
>>   #include "igt.h"
>> +#include "igt_store.h"
>>   #include "igt_syncobj.h"
>>   #include "igt_sysfs.h"
>>   #include "igt_vgem.h"
>> @@ -57,74 +58,6 @@ struct sync_merge_data {
>>   #define   MI_SEMAPHORE_SAD_EQ_SDD       (4 << 12)
>>   #define   MI_SEMAPHORE_SAD_NEQ_SDD      (5 << 12)
>>   
>> -static void store(int fd, uint64_t ahnd, const intel_ctx_t *ctx,
>> -		  const struct intel_execution_engine2 *e,
>> -		  int fence, uint32_t target, uint64_t target_offset,
>> -		  unsigned offset_value)
>> -{
>> -	const int SCRATCH = 0;
>> -	const int BATCH = 1;
>> -	const unsigned int gen = intel_gen(intel_get_drm_devid(fd));
>> -	struct drm_i915_gem_exec_object2 obj[2];
>> -	struct drm_i915_gem_relocation_entry reloc;
>> -	struct drm_i915_gem_execbuffer2 execbuf;
>> -	uint32_t batch[16], delta;
>> -	uint64_t bb_offset;
>> -	int i;
>> -
>> -	memset(&execbuf, 0, sizeof(execbuf));
>> -	execbuf.buffers_ptr = to_user_pointer(obj);
>> -	execbuf.buffer_count = 2;
>> -	execbuf.flags = e->flags | I915_EXEC_FENCE_IN;
>> -	execbuf.rsvd1 = ctx->id;
>> -	execbuf.rsvd2 = fence;
>> -	if (gen < 6)
>> -		execbuf.flags |= I915_EXEC_SECURE;
>> -
>> -	memset(obj, 0, sizeof(obj));
>> -	obj[SCRATCH].handle = target;
>> -
>> -	obj[BATCH].handle = gem_create(fd, 4096);
>> -	obj[BATCH].relocs_ptr = to_user_pointer(&reloc);
>> -	obj[BATCH].relocation_count = !ahnd ? 1 : 0;
>> -	bb_offset = get_offset(ahnd, obj[BATCH].handle, 4096, 0);
>> -	memset(&reloc, 0, sizeof(reloc));
>> -
>> -	i = 0;
>> -	delta = sizeof(uint32_t) * offset_value;
>> -	if (!ahnd) {
>> -		reloc.target_handle = obj[SCRATCH].handle;
>> -		reloc.presumed_offset = -1;
>> -		reloc.offset = sizeof(uint32_t) * (i + 1);
>> -		reloc.delta = delta;
>> -		reloc.read_domains = I915_GEM_DOMAIN_INSTRUCTION;
>> -		reloc.write_domain = I915_GEM_DOMAIN_INSTRUCTION;
>> -	} else {
>> -		obj[SCRATCH].offset = target_offset;
>> -		obj[SCRATCH].flags |= EXEC_OBJECT_PINNED | EXEC_OBJECT_WRITE;
>> -		obj[BATCH].offset = bb_offset;
>> -		obj[BATCH].flags |= EXEC_OBJECT_PINNED;
>> -	}
>> -	batch[i] = MI_STORE_DWORD_IMM | (gen < 6 ? 1 << 22 : 0);
>> -	if (gen >= 8) {
>> -		batch[++i] = target_offset + delta;
>> -		batch[++i] = target_offset >> 32;
>> -	} else if (gen >= 4) {
>> -		batch[++i] = 0;
>> -		batch[++i] = delta;
>> -		reloc.offset += sizeof(uint32_t);
>> -	} else {
>> -		batch[i]--;
>> -		batch[++i] = delta;
>> -	}
>> -	batch[++i] = offset_value;
>> -	batch[++i] = MI_BATCH_BUFFER_END;
>> -	gem_write(fd, obj[BATCH].handle, 0, batch, sizeof(batch));
>> -	gem_execbuf(fd, &execbuf);
>> -	gem_close(fd, obj[BATCH].handle);
>> -	put_offset(ahnd, obj[BATCH].handle);
>> -}
>> -
>>   static bool fence_busy(int fence)
>>   {
>>   	return poll(&(struct pollfd){fence, POLLIN}, 1, 0) == 0;
>> @@ -400,13 +333,13 @@ static void test_fence_await(int fd, const intel_ctx_t *ctx,
>>   			continue;
>>   
>>   		if (flags & NONBLOCK) {
>> -			store(fd, ahnd, ctx, e2, spin->out_fence,
>> -			      scratch, scratch_offset, i);
>> +			igt_store_word(fd, ahnd, ctx, e2, spin->out_fence,
>> +				       scratch, scratch_offset, i);
>>   		} else {
>>   			igt_fork(child, 1) {
>>   				ahnd = get_reloc_ahnd(fd, ctx->id);
>> -				store(fd, ahnd, ctx, e2, spin->out_fence,
>> -				      scratch, scratch_offset, i);
>> +				igt_store_word(fd, ahnd, ctx, e2, spin->out_fence,
>> +					       scratch, scratch_offset, i);
>>   				put_ahnd(ahnd);
>>   			}
>>   		}
>> diff --git a/tests/i915/i915_hangman.c b/tests/i915/i915_hangman.c
>> index 20653b479..4cb9b8b85 100644
>> --- a/tests/i915/i915_hangman.c
>> +++ b/tests/i915/i915_hangman.c
>> @@ -36,6 +36,7 @@
>>   #include "i915/gem.h"
>>   #include "i915/gem_create.h"
>>   #include "igt.h"
>> +#include "igt_store.h"
>>   #include "igt_sysfs.h"
>>   #include "igt_debugfs.h"
>>   #include "sw_sync.h"
>> @@ -51,64 +52,6 @@ static int sysfs = -1;
>>   
>>   IGT_TEST_DESCRIPTION("Tests for hang detection and recovery");
>>   
>> -/* Requires master for STORE_DWORD on gen4/5 */
>> -static void store(int fd, const struct intel_execution_engine2 *e,
>> -		  int fence, uint32_t target, unsigned offset_value)
>> -{
>> -	const int SCRATCH = 0;
>> -	const int BATCH = 1;
>> -	const int gen = intel_gen(intel_get_drm_devid(fd));
>> -	struct drm_i915_gem_exec_object2 obj[2];
>> -	struct drm_i915_gem_relocation_entry reloc;
>> -	struct drm_i915_gem_execbuffer2 execbuf;
>> -	uint32_t batch[16];
>> -	int i;
>> -
>> -	memset(&execbuf, 0, sizeof(execbuf));
>> -	execbuf.buffers_ptr = to_user_pointer(obj);
>> -	execbuf.buffer_count = ARRAY_SIZE(obj);
>> -	execbuf.flags = e->flags;
>> -	if (fence != -1) {
>> -		execbuf.flags |= I915_EXEC_FENCE_IN;
>> -		execbuf.rsvd2 = fence;
>> -	}
>> -	if (gen < 6)
>> -		execbuf.flags |= I915_EXEC_SECURE;
>> -
>> -	memset(obj, 0, sizeof(obj));
>> -	obj[SCRATCH].handle = target;
>> -
>> -	obj[BATCH].handle = gem_create(fd, 4096);
>> -	obj[BATCH].relocs_ptr = to_user_pointer(&reloc);
>> -	obj[BATCH].relocation_count = 1;
>> -	memset(&reloc, 0, sizeof(reloc));
>> -
>> -	i = 0;
>> -	reloc.target_handle = obj[SCRATCH].handle;
>> -	reloc.presumed_offset = -1;
>> -	reloc.offset = sizeof(uint32_t) * (i + 1);
>> -	reloc.delta = sizeof(uint32_t) * offset_value;
>> -	reloc.read_domains = I915_GEM_DOMAIN_INSTRUCTION;
>> -	reloc.write_domain = I915_GEM_DOMAIN_INSTRUCTION;
>> -	batch[i] = MI_STORE_DWORD_IMM | (gen < 6 ? 1 << 22 : 0);
>> -	if (gen >= 8) {
>> -		batch[++i] = reloc.delta;
>> -		batch[++i] = 0;
>> -	} else if (gen >= 4) {
>> -		batch[++i] = 0;
>> -		batch[++i] = reloc.delta;
>> -		reloc.offset += sizeof(uint32_t);
>> -	} else {
>> -		batch[i]--;
>> -		batch[++i] = reloc.delta;
>> -	}
>> -	batch[++i] = offset_value;
>> -	batch[++i] = MI_BATCH_BUFFER_END;
>> -	gem_write(fd, obj[BATCH].handle, 0, batch, sizeof(batch));
>> -	gem_execbuf(fd, &execbuf);
>> -	gem_close(fd, obj[BATCH].handle);
>> -}
>> -
>>   static void check_alive(void)
>>   {
>>   	const struct intel_execution_engine2 *engine;
>> @@ -138,7 +81,7 @@ static void check_alive(void)
>>   			continue;
>>   
>>   		/* +OFFSET_ALIVE to ensure engine zero doesn't get a false negative */
>> -		store(fd, engine, -1, scratch, i + OFFSET_ALIVE);
>> +		igt_store_word(fd, ahnd, ctx, engine, -1, scratch, i + OFFSET_ALIVE, i + OFFSET_ALIVE);
>>   		i++;
>>   	}
>>   
>> -- 
>> 2.25.1
>>

Re: [Intel-gfx] [igt-dev] [PATCH i-g-t 08/11] lib/store: Refactor common store code into helper function

[Zbigniew Kempczyński]

On Thu, Dec 16, 2021 at 02:40:21PM -0800, John Harrison wrote:
> On 12/15/2021 23:46, Zbigniew Kempczyński wrote:
> > On Mon, Dec 13, 2021 at 03:29:11PM -0800, John.C.Harrison@Intel.com wrote:
> > > From: John Harrison <John.C.Harrison@Intel.com>
> > > 
> > > A lot of tests use almost identical code for creating a batch buffer
> > > which does a single write to memory. This patch collects two such
> > > instances into a common helper function. Unfortunately, the other
> > > instances are all subtly different enough to make it not so trivial to
> > > try to use the helper. It could be done but it is unclear if it is
> > > worth the effort at this point. This patch proves the concept, if
> > > people like it enough then it can be extended.
> > > 
> > > Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
> > > ---
> > >   lib/igt_store.c             | 114 ++++++++++++++++++++++++++++++++++++
> > >   lib/igt_store.h             |  30 ++++++++++
> > >   lib/meson.build             |   1 +
> > >   tests/i915/gem_exec_fence.c |  77 ++----------------------
> > >   tests/i915/i915_hangman.c   |  61 +------------------
> > >   5 files changed, 152 insertions(+), 131 deletions(-)
> > >   create mode 100644 lib/igt_store.c
> > >   create mode 100644 lib/igt_store.h
> > > 
> > > diff --git a/lib/igt_store.c b/lib/igt_store.c
> > > new file mode 100644
> > > index 000000000..6d9869b58
> > > --- /dev/null
> > > +++ b/lib/igt_store.c
> > > @@ -0,0 +1,114 @@
> > > +/*
> > > + * Copyright © 2020 Intel Corporation
> > > + *
> > > + * Permission is hereby granted, free of charge, to any person obtaining a
> > > + * copy of this software and associated documentation files (the "Software"),
> > > + * to deal in the Software without restriction, including without limitation
> > > + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> > > + * and/or sell copies of the Software, and to permit persons to whom the
> > > + * Software is furnished to do so, subject to the following conditions:
> > > + *
> > > + * The above copyright notice and this permission notice (including the next
> > > + * paragraph) shall be included in all copies or substantial portions of the
> > > + * Software.
> > > + *
> > > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> > > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> > > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> > > + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> > > + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> > > + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
> > > + * IN THE SOFTWARE.
> > > + *
> > > + */
> > Use SPDX. I like idea of extracting this.
> > 
> > > +
> > > +#include "i915/gem_create.h"
> > > +#include "igt_core.h"
> > > +#include "drmtest.h"
> > > +#include "igt_store.h"
> > > +#include "intel_chipset.h"
> > > +#include "intel_reg.h"
> > > +#include "ioctl_wrappers.h"
> > > +#include "lib/intel_allocator.h"
> > > +
> > > +/**
> > > + * SECTION:igt_store_word
> > > + * @short_description: Library for writing a value to memory
> > > + * @title: StoreWord
> > > + * @include: igt.h
> > > + *
> > > + * A lot of igt testcases need some mechanism for writing a value to memory
> > > + * as a test that a batch buffer has executed.
> > > + *
> > > + * NB: Requires master for STORE_DWORD on gen4/5.
> > > + */
> > > +void igt_store_word(int fd, uint64_t ahnd, const intel_ctx_t *ctx,
> > > +		    const struct intel_execution_engine2 *e,
> > > +		    int fence, uint32_t target_handle,
> > > +		    uint64_t target_offset, uint32_t target_value)
> > > +{
> > > +	const int SCRATCH = 0;
> > > +	const int BATCH = 1;
> > > +	const unsigned int gen = intel_gen(intel_get_drm_devid(fd));
> > > +	struct drm_i915_gem_exec_object2 obj[2];
> > > +	struct drm_i915_gem_relocation_entry reloc;
> > > +	struct drm_i915_gem_execbuffer2 execbuf;
> > > +	uint32_t batch[16], delta;
> > > +	uint64_t bb_offset;
> > > +	int i;
> > > +
> > > +	memset(&execbuf, 0, sizeof(execbuf));
> > > +	execbuf.buffers_ptr = to_user_pointer(obj);
> > > +	execbuf.buffer_count = ARRAY_SIZE(obj);
> > > +	execbuf.flags = e->flags;
> > > +	execbuf.rsvd1 = ctx->id;
> > > +	if (fence != -1) {
> > > +		execbuf.flags |= I915_EXEC_FENCE_IN;
> > > +		execbuf.rsvd2 = fence;
> > > +	}
> > > +	if (gen < 6)
> > > +		execbuf.flags |= I915_EXEC_SECURE;
> > > +
> > > +	memset(obj, 0, sizeof(obj));
> > > +	obj[SCRATCH].handle = target_handle;
> > > +
> > > +	obj[BATCH].handle = gem_create(fd, 4096);
> > > +	obj[BATCH].relocs_ptr = to_user_pointer(&reloc);
> > > +	obj[BATCH].relocation_count = !ahnd ? 1 : 0;
> > > +	bb_offset = get_offset(ahnd, obj[BATCH].handle, 4096, 0);
> > > +	memset(&reloc, 0, sizeof(reloc));
> > > +
> > > +	i = 0;
> > > +	delta = sizeof(uint32_t) * target_value;	/* why value not offset??? */
> > I guess I know why there's problem here. target_offset is address in vm
> > passed by the caller. This is regarding to some limitations of allocator
> > infrastructure - for "reloc" pseudo-allocator you would get new offset
> > (internally it returns offset and then add size for new "allocation").
> > With this we don't need to wait for rebind offset for new execbuf.
> > With "simple" allocator put will release offset so new allocation will
> > reuse same offset. Ashutosh proposed how to join both functionalities
> > (stepping as with reloc, stateful like in simple) but I got no time to
> > code this.
> > 
> > Regarding issue here, target_offset passed from the caller is to avoid
> > rebind if get_offset() would be called for "reloc" allocator.
> > So there's not real value offset within bo. I would add separate
> > value_offset (shift) to allow caller to put place where it wants to
> > write the value.
> If you understand what is going on here and how to improve it then feel free
> to either send me an updated version or post an extra patch after this is
> merged. I don't get how any of the new reloc (or anti-reloc?) code is meant
> to work. These patches were all written as part of the GuC support a long
> time ago - before there was any such thing as an AHND (what does that stand
> for?) or intel_ctx_t. All I'm doing in this patch is moving the existing
> code to a helper and trying to make it generic enough to be used by another
> test. And right now, the two tests are passing on both GuC and execlist
> platforms for me. So the code can't be all that broken.

I've added some missing parts to your code:

https://patchwork.freedesktop.org/series/98242/

If you think something is missing please add or fix.

Previously value was used both for value and offset within bo 
used for example in gem_exec_fence@basic-await. I think adding
separate arg for offset for value within bo makes this code
more universal.

NB: ahnd is short version of allocator_handle

--
Zbigniew

> 
> 
> > 
> > 
> > > +	if (!ahnd) {
> > > +		reloc.target_handle = obj[SCRATCH].handle;
> > > +		reloc.presumed_offset = -1;
> > > +		reloc.offset = sizeof(uint32_t) * (i + 1);
> > > +		reloc.delta = delta;
> > > +		reloc.read_domains = I915_GEM_DOMAIN_INSTRUCTION;
> > > +		reloc.write_domain = I915_GEM_DOMAIN_INSTRUCTION;
> > > +	} else {
> > > +		obj[SCRATCH].offset = target_offset;
> > > +		obj[SCRATCH].flags |= EXEC_OBJECT_PINNED | EXEC_OBJECT_WRITE;
> > > +		obj[BATCH].offset = bb_offset;
> > > +		obj[BATCH].flags |= EXEC_OBJECT_PINNED;
> > > +	}
> > > +	batch[i] = MI_STORE_DWORD_IMM | (gen < 6 ? 1 << 22 : 0);
> > > +	if (gen >= 8) {
> > > +		batch[++i] = target_offset + delta;
> > > +		batch[++i] = target_offset >> 32;
> > Probably I've added this in previous code, for being safe I would
> > add (target_offset + delta) >> 32 for avoid risk passing invalid higher
> > offset part on 32b boundary.
> Pretty sure we don't have any addresses larger than 32 bits yet, but yes,
> delta should be added in.
> 
> Thanks,
> John.
> 
> > 
> > > +	} else if (gen >= 4) {
> > > +		batch[++i] = 0;
> > > +		batch[++i] = delta;
> > > +		reloc.offset += sizeof(uint32_t);
> > > +	} else {
> > > +		batch[i]--;
> > > +		batch[++i] = delta;
> > > +	}
> > > +	batch[++i] = target_value;
> > > +	batch[++i] = MI_BATCH_BUFFER_END;
> > > +	gem_write(fd, obj[BATCH].handle, 0, batch, sizeof(batch));
> > > +	gem_execbuf(fd, &execbuf);
> > > +	gem_close(fd, obj[BATCH].handle);
> > > +	put_offset(ahnd, obj[BATCH].handle);
> > > +}
> > > diff --git a/lib/igt_store.h b/lib/igt_store.h
> > > new file mode 100644
> > > index 000000000..4d5979e07
> > > --- /dev/null
> > > +++ b/lib/igt_store.h
> > > @@ -0,0 +1,30 @@
> > > +/*
> > > + * Copyright © 2020 Intel Corporation
> > > + *
> > > + * Permission is hereby granted, free of charge, to any person obtaining a
> > > + * copy of this software and associated documentation files (the "Software"),
> > > + * to deal in the Software without restriction, including without limitation
> > > + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> > > + * and/or sell copies of the Software, and to permit persons to whom the
> > > + * Software is furnished to do so, subject to the following conditions:
> > > + *
> > > + * The above copyright notice and this permission notice (including the next
> > > + * paragraph) shall be included in all copies or substantial portions of the
> > > + * Software.
> > > + *
> > > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> > > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> > > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> > > + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> > > + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> > > + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
> > > + * IN THE SOFTWARE.
> > > + *
> > > + */
> > Use SPDX and 2021.
> > 
> > --
> > Zbigniew
> > 
> > > +
> > > +#include "igt_gt.h"
> > > +
> > > +void igt_store_word(int fd, uint64_t ahnd, const intel_ctx_t *ctx,
> > > +		    const struct intel_execution_engine2 *e,
> > > +		    int fence, uint32_t target_handle,
> > > +		    uint64_t target_offset, uint32_t target_value);
> > > diff --git a/lib/meson.build b/lib/meson.build
> > > index b9568a71b..3e43316d1 100644
> > > --- a/lib/meson.build
> > > +++ b/lib/meson.build
> > > @@ -72,6 +72,7 @@ lib_sources = [
> > >   	'igt_map.c',
> > >   	'igt_pm.c',
> > >   	'igt_dummyload.c',
> > > +	'igt_store.c',
> > >   	'uwildmat/uwildmat.c',
> > >   	'igt_kmod.c',
> > >   	'igt_panfrost.c',
> > > diff --git a/tests/i915/gem_exec_fence.c b/tests/i915/gem_exec_fence.c
> > > index 9a6336ce9..c4091a454 100644
> > > --- a/tests/i915/gem_exec_fence.c
> > > +++ b/tests/i915/gem_exec_fence.c
> > > @@ -28,6 +28,7 @@
> > >   #include "i915/gem.h"
> > >   #include "i915/gem_create.h"
> > >   #include "igt.h"
> > > +#include "igt_store.h"
> > >   #include "igt_syncobj.h"
> > >   #include "igt_sysfs.h"
> > >   #include "igt_vgem.h"
> > > @@ -57,74 +58,6 @@ struct sync_merge_data {
> > >   #define   MI_SEMAPHORE_SAD_EQ_SDD       (4 << 12)
> > >   #define   MI_SEMAPHORE_SAD_NEQ_SDD      (5 << 12)
> > > -static void store(int fd, uint64_t ahnd, const intel_ctx_t *ctx,
> > > -		  const struct intel_execution_engine2 *e,
> > > -		  int fence, uint32_t target, uint64_t target_offset,
> > > -		  unsigned offset_value)
> > > -{
> > > -	const int SCRATCH = 0;
> > > -	const int BATCH = 1;
> > > -	const unsigned int gen = intel_gen(intel_get_drm_devid(fd));
> > > -	struct drm_i915_gem_exec_object2 obj[2];
> > > -	struct drm_i915_gem_relocation_entry reloc;
> > > -	struct drm_i915_gem_execbuffer2 execbuf;
> > > -	uint32_t batch[16], delta;
> > > -	uint64_t bb_offset;
> > > -	int i;
> > > -
> > > -	memset(&execbuf, 0, sizeof(execbuf));
> > > -	execbuf.buffers_ptr = to_user_pointer(obj);
> > > -	execbuf.buffer_count = 2;
> > > -	execbuf.flags = e->flags | I915_EXEC_FENCE_IN;
> > > -	execbuf.rsvd1 = ctx->id;
> > > -	execbuf.rsvd2 = fence;
> > > -	if (gen < 6)
> > > -		execbuf.flags |= I915_EXEC_SECURE;
> > > -
> > > -	memset(obj, 0, sizeof(obj));
> > > -	obj[SCRATCH].handle = target;
> > > -
> > > -	obj[BATCH].handle = gem_create(fd, 4096);
> > > -	obj[BATCH].relocs_ptr = to_user_pointer(&reloc);
> > > -	obj[BATCH].relocation_count = !ahnd ? 1 : 0;
> > > -	bb_offset = get_offset(ahnd, obj[BATCH].handle, 4096, 0);
> > > -	memset(&reloc, 0, sizeof(reloc));
> > > -
> > > -	i = 0;
> > > -	delta = sizeof(uint32_t) * offset_value;
> > > -	if (!ahnd) {
> > > -		reloc.target_handle = obj[SCRATCH].handle;
> > > -		reloc.presumed_offset = -1;
> > > -		reloc.offset = sizeof(uint32_t) * (i + 1);
> > > -		reloc.delta = delta;
> > > -		reloc.read_domains = I915_GEM_DOMAIN_INSTRUCTION;
> > > -		reloc.write_domain = I915_GEM_DOMAIN_INSTRUCTION;
> > > -	} else {
> > > -		obj[SCRATCH].offset = target_offset;
> > > -		obj[SCRATCH].flags |= EXEC_OBJECT_PINNED | EXEC_OBJECT_WRITE;
> > > -		obj[BATCH].offset = bb_offset;
> > > -		obj[BATCH].flags |= EXEC_OBJECT_PINNED;
> > > -	}
> > > -	batch[i] = MI_STORE_DWORD_IMM | (gen < 6 ? 1 << 22 : 0);
> > > -	if (gen >= 8) {
> > > -		batch[++i] = target_offset + delta;
> > > -		batch[++i] = target_offset >> 32;
> > > -	} else if (gen >= 4) {
> > > -		batch[++i] = 0;
> > > -		batch[++i] = delta;
> > > -		reloc.offset += sizeof(uint32_t);
> > > -	} else {
> > > -		batch[i]--;
> > > -		batch[++i] = delta;
> > > -	}
> > > -	batch[++i] = offset_value;
> > > -	batch[++i] = MI_BATCH_BUFFER_END;
> > > -	gem_write(fd, obj[BATCH].handle, 0, batch, sizeof(batch));
> > > -	gem_execbuf(fd, &execbuf);
> > > -	gem_close(fd, obj[BATCH].handle);
> > > -	put_offset(ahnd, obj[BATCH].handle);
> > > -}
> > > -
> > >   static bool fence_busy(int fence)
> > >   {
> > >   	return poll(&(struct pollfd){fence, POLLIN}, 1, 0) == 0;
> > > @@ -400,13 +333,13 @@ static void test_fence_await(int fd, const intel_ctx_t *ctx,
> > >   			continue;
> > >   		if (flags & NONBLOCK) {
> > > -			store(fd, ahnd, ctx, e2, spin->out_fence,
> > > -			      scratch, scratch_offset, i);
> > > +			igt_store_word(fd, ahnd, ctx, e2, spin->out_fence,
> > > +				       scratch, scratch_offset, i);
> > >   		} else {
> > >   			igt_fork(child, 1) {
> > >   				ahnd = get_reloc_ahnd(fd, ctx->id);
> > > -				store(fd, ahnd, ctx, e2, spin->out_fence,
> > > -				      scratch, scratch_offset, i);
> > > +				igt_store_word(fd, ahnd, ctx, e2, spin->out_fence,
> > > +					       scratch, scratch_offset, i);
> > >   				put_ahnd(ahnd);
> > >   			}
> > >   		}
> > > diff --git a/tests/i915/i915_hangman.c b/tests/i915/i915_hangman.c
> > > index 20653b479..4cb9b8b85 100644
> > > --- a/tests/i915/i915_hangman.c
> > > +++ b/tests/i915/i915_hangman.c
> > > @@ -36,6 +36,7 @@
> > >   #include "i915/gem.h"
> > >   #include "i915/gem_create.h"
> > >   #include "igt.h"
> > > +#include "igt_store.h"
> > >   #include "igt_sysfs.h"
> > >   #include "igt_debugfs.h"
> > >   #include "sw_sync.h"
> > > @@ -51,64 +52,6 @@ static int sysfs = -1;
> > >   IGT_TEST_DESCRIPTION("Tests for hang detection and recovery");
> > > -/* Requires master for STORE_DWORD on gen4/5 */
> > > -static void store(int fd, const struct intel_execution_engine2 *e,
> > > -		  int fence, uint32_t target, unsigned offset_value)
> > > -{
> > > -	const int SCRATCH = 0;
> > > -	const int BATCH = 1;
> > > -	const int gen = intel_gen(intel_get_drm_devid(fd));
> > > -	struct drm_i915_gem_exec_object2 obj[2];
> > > -	struct drm_i915_gem_relocation_entry reloc;
> > > -	struct drm_i915_gem_execbuffer2 execbuf;
> > > -	uint32_t batch[16];
> > > -	int i;
> > > -
> > > -	memset(&execbuf, 0, sizeof(execbuf));
> > > -	execbuf.buffers_ptr = to_user_pointer(obj);
> > > -	execbuf.buffer_count = ARRAY_SIZE(obj);
> > > -	execbuf.flags = e->flags;
> > > -	if (fence != -1) {
> > > -		execbuf.flags |= I915_EXEC_FENCE_IN;
> > > -		execbuf.rsvd2 = fence;
> > > -	}
> > > -	if (gen < 6)
> > > -		execbuf.flags |= I915_EXEC_SECURE;
> > > -
> > > -	memset(obj, 0, sizeof(obj));
> > > -	obj[SCRATCH].handle = target;
> > > -
> > > -	obj[BATCH].handle = gem_create(fd, 4096);
> > > -	obj[BATCH].relocs_ptr = to_user_pointer(&reloc);
> > > -	obj[BATCH].relocation_count = 1;
> > > -	memset(&reloc, 0, sizeof(reloc));
> > > -
> > > -	i = 0;
> > > -	reloc.target_handle = obj[SCRATCH].handle;
> > > -	reloc.presumed_offset = -1;
> > > -	reloc.offset = sizeof(uint32_t) * (i + 1);
> > > -	reloc.delta = sizeof(uint32_t) * offset_value;
> > > -	reloc.read_domains = I915_GEM_DOMAIN_INSTRUCTION;
> > > -	reloc.write_domain = I915_GEM_DOMAIN_INSTRUCTION;
> > > -	batch[i] = MI_STORE_DWORD_IMM | (gen < 6 ? 1 << 22 : 0);
> > > -	if (gen >= 8) {
> > > -		batch[++i] = reloc.delta;
> > > -		batch[++i] = 0;
> > > -	} else if (gen >= 4) {
> > > -		batch[++i] = 0;
> > > -		batch[++i] = reloc.delta;
> > > -		reloc.offset += sizeof(uint32_t);
> > > -	} else {
> > > -		batch[i]--;
> > > -		batch[++i] = reloc.delta;
> > > -	}
> > > -	batch[++i] = offset_value;
> > > -	batch[++i] = MI_BATCH_BUFFER_END;
> > > -	gem_write(fd, obj[BATCH].handle, 0, batch, sizeof(batch));
> > > -	gem_execbuf(fd, &execbuf);
> > > -	gem_close(fd, obj[BATCH].handle);
> > > -}
> > > -
> > >   static void check_alive(void)
> > >   {
> > >   	const struct intel_execution_engine2 *engine;
> > > @@ -138,7 +81,7 @@ static void check_alive(void)
> > >   			continue;
> > >   		/* +OFFSET_ALIVE to ensure engine zero doesn't get a false negative */
> > > -		store(fd, engine, -1, scratch, i + OFFSET_ALIVE);
> > > +		igt_store_word(fd, ahnd, ctx, engine, -1, scratch, i + OFFSET_ALIVE, i + OFFSET_ALIVE);
> > >   		i++;
> > >   	}
> > > -- 
> > > 2.25.1
> > > 
> 

Re: [Intel-gfx] [igt-dev] [PATCH i-g-t 04/11] tests/i915/i915_hangman: Explicitly test per engine reset vs full GPU reset

[Dandamudi, Priyanka]

Does this test series cover to prove that it can survive killing one without killing all the others except RCS+CCS combination(killing one affects other and shows with the help of reset stats)?


-----Original Message-----
From: igt-dev <igt-dev-bounces@lists.freedesktop.org> On Behalf Of John.C.Harrison@Intel.com
Sent: 14 December 2021 04:59 AM
To: IGT-Dev@Lists.FreeDesktop.Org
Cc: Intel-GFX@Lists.FreeDesktop.Org
Subject: [igt-dev] [PATCH i-g-t 04/11] tests/i915/i915_hangman: Explicitly test per engine reset vs full GPU reset

From: John Harrison <John.C.Harrison@Intel.com>

Although the hangman test was ensuring that *some* reset functionality was enabled, it did not differentiate what kind. The infrastructure required to choose between per engine reset or full GT reset was recently added. So update this test to use it as well.

Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
---
 tests/i915/i915_hangman.c | 77 +++++++++++++++++++++++++--------------
 1 file changed, 50 insertions(+), 27 deletions(-)

diff --git a/tests/i915/i915_hangman.c b/tests/i915/i915_hangman.c index bd787d7b4..f8a48337c 100644
--- a/tests/i915/i915_hangman.c
+++ b/tests/i915/i915_hangman.c
@@ -323,40 +323,26 @@ static void hangcheck_unterminated(const intel_ctx_t *ctx)
 	}
 }
 
-igt_main
+static void do_tests(const char *name, const char *prefix,
+		     const intel_ctx_t *ctx)
 {
 	const struct intel_execution_engine2 *e;
-	const intel_ctx_t *ctx;
-	igt_hang_t hang = {};
-
-	igt_fixture {
-		device = drm_open_driver(DRIVER_INTEL);
-		igt_require_gem(device);
-
-		ctx = intel_ctx_create_all_physical(device);
-
-		hang = igt_allow_hang(device, ctx->id, HANG_ALLOW_CAPTURE);
-
-		sysfs = igt_sysfs_open(device);
-		igt_assert(sysfs != -1);
+	char buff[256];
 
-		igt_require(has_error_state(sysfs));
-	}
-
-	igt_describe("Basic error capture");
-	igt_subtest("error-state-basic")
-		test_error_state_basic();
-
-	igt_describe("Per engine error capture");
-	igt_subtest_with_dynamic("error-state-capture") {
+	snprintf(buff, sizeof(buff), "Per engine error capture (%s reset)", name);
+	igt_describe(buff);
+	snprintf(buff, sizeof(buff), "%s-error-state-capture", prefix);
+	igt_subtest_with_dynamic(buff) {
 		for_each_ctx_engine(device, ctx, e) {
 			igt_dynamic_f("%s", e->name)
 				test_error_state_capture(ctx, e);
 		}
 	}
 
-	igt_describe("Per engine hang recovery (spin)");
-	igt_subtest_with_dynamic("engine-hang") {
+	snprintf(buff, sizeof(buff), "Per engine hang recovery (spin, %s reset)", name);
+	igt_describe(buff);
+	snprintf(buff, sizeof(buff), "%s-engine-hang", prefix);
+	igt_subtest_with_dynamic(buff) {
                 int has_gpu_reset = 0;
 		struct drm_i915_getparam gp = {
 			.param = I915_PARAM_HAS_GPU_RESET,
@@ -374,8 +360,10 @@ igt_main
 		}
 	}
 
-	igt_describe("Per engine hang recovery (invalid CS)");
-	igt_subtest_with_dynamic("engine-error") {
+	snprintf(buff, sizeof(buff), "Per engine hang recovery (invalid CS, %s reset)", name);
+	igt_describe(buff);
+	snprintf(buff, sizeof(buff), "%s-engine-error", prefix);
+	igt_subtest_with_dynamic(buff) {
 		int has_gpu_reset = 0;
 		struct drm_i915_getparam gp = {
 			.param = I915_PARAM_HAS_GPU_RESET,
@@ -391,11 +379,46 @@ igt_main
 				test_engine_hang(ctx, e, IGT_SPIN_INVALID_CS);
 		}
 	}
+}
+
+igt_main
+{
+	const intel_ctx_t *ctx;
+	igt_hang_t hang = {};
+
+	igt_fixture {
+		device = drm_open_driver(DRIVER_INTEL);
+		igt_require_gem(device);
+
+		ctx = intel_ctx_create_all_physical(device);
+
+		hang = igt_allow_hang(device, ctx->id, HANG_ALLOW_CAPTURE);
+
+		sysfs = igt_sysfs_open(device);
+		igt_assert(sysfs != -1);
+
+		igt_require(has_error_state(sysfs));
+	}
+
+	igt_describe("Basic error capture");
+	igt_subtest("error-state-basic")
+		test_error_state_basic();
+
 
 	igt_describe("Check that executing unintialised memory causes a hang");
 	igt_subtest("hangcheck-unterminated")
 		hangcheck_unterminated(ctx);
 
+	do_tests("GT", "gt", ctx);
+
+	igt_fixture {
+		igt_disallow_hang(device, hang);
+
+		hang = igt_allow_hang(device, ctx->id, HANG_ALLOW_CAPTURE | HANG_WANT_ENGINE_RESET);
+	}
+
+	do_tests("engine", "engine", ctx);
+
 	igt_fixture {
 		igt_disallow_hang(device, hang);
 		intel_ctx_destroy(device, ctx);
--
2.25.1

Re: [igt-dev] [PATCH i-g-t 04/11] tests/i915/i915_hangman: Explicitly test per engine reset vs full GPU reset

[Dandamudi, Priyanka]

Does this test series cover to prove that it can survive killing one without killing all the others except RCS+CCS combination(killing one affects other and shows with the help of reset stats)?


-----Original Message-----
From: igt-dev <igt-dev-bounces@lists.freedesktop.org> On Behalf Of John.C.Harrison@Intel.com
Sent: 14 December 2021 04:59 AM
To: IGT-Dev@Lists.FreeDesktop.Org
Cc: Intel-GFX@Lists.FreeDesktop.Org
Subject: [igt-dev] [PATCH i-g-t 04/11] tests/i915/i915_hangman: Explicitly test per engine reset vs full GPU reset

From: John Harrison <John.C.Harrison@Intel.com>

Although the hangman test was ensuring that *some* reset functionality was enabled, it did not differentiate what kind. The infrastructure required to choose between per engine reset or full GT reset was recently added. So update this test to use it as well.

Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
---
 tests/i915/i915_hangman.c | 77 +++++++++++++++++++++++++--------------
 1 file changed, 50 insertions(+), 27 deletions(-)

diff --git a/tests/i915/i915_hangman.c b/tests/i915/i915_hangman.c index bd787d7b4..f8a48337c 100644
--- a/tests/i915/i915_hangman.c
+++ b/tests/i915/i915_hangman.c
@@ -323,40 +323,26 @@ static void hangcheck_unterminated(const intel_ctx_t *ctx)
 	}
 }
 
-igt_main
+static void do_tests(const char *name, const char *prefix,
+		     const intel_ctx_t *ctx)
 {
 	const struct intel_execution_engine2 *e;
-	const intel_ctx_t *ctx;
-	igt_hang_t hang = {};
-
-	igt_fixture {
-		device = drm_open_driver(DRIVER_INTEL);
-		igt_require_gem(device);
-
-		ctx = intel_ctx_create_all_physical(device);
-
-		hang = igt_allow_hang(device, ctx->id, HANG_ALLOW_CAPTURE);
-
-		sysfs = igt_sysfs_open(device);
-		igt_assert(sysfs != -1);
+	char buff[256];
 
-		igt_require(has_error_state(sysfs));
-	}
-
-	igt_describe("Basic error capture");
-	igt_subtest("error-state-basic")
-		test_error_state_basic();
-
-	igt_describe("Per engine error capture");
-	igt_subtest_with_dynamic("error-state-capture") {
+	snprintf(buff, sizeof(buff), "Per engine error capture (%s reset)", name);
+	igt_describe(buff);
+	snprintf(buff, sizeof(buff), "%s-error-state-capture", prefix);
+	igt_subtest_with_dynamic(buff) {
 		for_each_ctx_engine(device, ctx, e) {
 			igt_dynamic_f("%s", e->name)
 				test_error_state_capture(ctx, e);
 		}
 	}
 
-	igt_describe("Per engine hang recovery (spin)");
-	igt_subtest_with_dynamic("engine-hang") {
+	snprintf(buff, sizeof(buff), "Per engine hang recovery (spin, %s reset)", name);
+	igt_describe(buff);
+	snprintf(buff, sizeof(buff), "%s-engine-hang", prefix);
+	igt_subtest_with_dynamic(buff) {
                 int has_gpu_reset = 0;
 		struct drm_i915_getparam gp = {
 			.param = I915_PARAM_HAS_GPU_RESET,
@@ -374,8 +360,10 @@ igt_main
 		}
 	}
 
-	igt_describe("Per engine hang recovery (invalid CS)");
-	igt_subtest_with_dynamic("engine-error") {
+	snprintf(buff, sizeof(buff), "Per engine hang recovery (invalid CS, %s reset)", name);
+	igt_describe(buff);
+	snprintf(buff, sizeof(buff), "%s-engine-error", prefix);
+	igt_subtest_with_dynamic(buff) {
 		int has_gpu_reset = 0;
 		struct drm_i915_getparam gp = {
 			.param = I915_PARAM_HAS_GPU_RESET,
@@ -391,11 +379,46 @@ igt_main
 				test_engine_hang(ctx, e, IGT_SPIN_INVALID_CS);
 		}
 	}
+}
+
+igt_main
+{
+	const intel_ctx_t *ctx;
+	igt_hang_t hang = {};
+
+	igt_fixture {
+		device = drm_open_driver(DRIVER_INTEL);
+		igt_require_gem(device);
+
+		ctx = intel_ctx_create_all_physical(device);
+
+		hang = igt_allow_hang(device, ctx->id, HANG_ALLOW_CAPTURE);
+
+		sysfs = igt_sysfs_open(device);
+		igt_assert(sysfs != -1);
+
+		igt_require(has_error_state(sysfs));
+	}
+
+	igt_describe("Basic error capture");
+	igt_subtest("error-state-basic")
+		test_error_state_basic();
+
 
 	igt_describe("Check that executing unintialised memory causes a hang");
 	igt_subtest("hangcheck-unterminated")
 		hangcheck_unterminated(ctx);
 
+	do_tests("GT", "gt", ctx);
+
+	igt_fixture {
+		igt_disallow_hang(device, hang);
+
+		hang = igt_allow_hang(device, ctx->id, HANG_ALLOW_CAPTURE | HANG_WANT_ENGINE_RESET);
+	}
+
+	do_tests("engine", "engine", ctx);
+
 	igt_fixture {
 		igt_disallow_hang(device, hang);
 		intel_ctx_destroy(device, ctx);
--
2.25.1

[igt-dev] ✓ Fi.CI.BAT: success for Fixes for i915_hangman and gem_exec_capture (rev2)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 4634 bytes --]

== Series Details ==

Series: Fixes for i915_hangman and gem_exec_capture (rev2)
URL   : https://patchwork.freedesktop.org/series/97981/
State : success

== Summary ==

CI Bug Log - changes from IGT_6315 -> IGTPW_6510
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6510/index.html

Participating hosts (41 -> 37)
------------------------------

  Additional (1): fi-kbl-soraka 
  Missing    (5): fi-hsw-4200u fi-bsw-cyan fi-icl-u2 fi-ctg-p8600 fi-bdw-samus 

Known issues
------------

  Here are the changes found in IGTPW_6510 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@amdgpu/amd_basic@cs-gfx:
    - fi-hsw-4770:        NOTRUN -> [SKIP][1] ([fdo#109271] / [fdo#109315]) +17 similar issues
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6510/fi-hsw-4770/igt@amdgpu/amd_basic@cs-gfx.html

  * igt@gem_exec_fence@basic-busy@bcs0:
    - fi-kbl-soraka:      NOTRUN -> [SKIP][2] ([fdo#109271]) +26 similar issues
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6510/fi-kbl-soraka/igt@gem_exec_fence@basic-busy@bcs0.html

  * igt@gem_flink_basic@bad-flink:
    - fi-skl-6600u:       [PASS][3] -> [FAIL][4] ([i915#4547])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6315/fi-skl-6600u/igt@gem_flink_basic@bad-flink.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6510/fi-skl-6600u/igt@gem_flink_basic@bad-flink.html

  * igt@gem_huc_copy@huc-copy:
    - fi-kbl-soraka:      NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#2190])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6510/fi-kbl-soraka/igt@gem_huc_copy@huc-copy.html

  * igt@gem_lmem_swapping@basic:
    - fi-kbl-soraka:      NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#4613]) +3 similar issues
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6510/fi-kbl-soraka/igt@gem_lmem_swapping@basic.html

  * igt@i915_selftest@live@gt_pm:
    - fi-kbl-soraka:      NOTRUN -> [DMESG-FAIL][7] ([i915#1886] / [i915#2291])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6510/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html

  * igt@kms_chamelium@common-hpd-after-suspend:
    - fi-kbl-soraka:      NOTRUN -> [SKIP][8] ([fdo#109271] / [fdo#111827]) +8 similar issues
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6510/fi-kbl-soraka/igt@kms_chamelium@common-hpd-after-suspend.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
    - fi-kbl-soraka:      NOTRUN -> [SKIP][9] ([fdo#109271] / [i915#533])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6510/fi-kbl-soraka/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html

  
#### Possible fixes ####

  * igt@i915_selftest@live@hangcheck:
    - fi-hsw-4770:        [INCOMPLETE][10] ([i915#4785]) -> [PASS][11]
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6315/fi-hsw-4770/igt@i915_selftest@live@hangcheck.html
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6510/fi-hsw-4770/igt@i915_selftest@live@hangcheck.html

  
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886
  [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
  [i915#2291]: https://gitlab.freedesktop.org/drm/intel/issues/2291
  [i915#4547]: https://gitlab.freedesktop.org/drm/intel/issues/4547
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
  [i915#4785]: https://gitlab.freedesktop.org/drm/intel/issues/4785
  [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533


Build changes
-------------

  * CI: CI-20190529 -> None
  * IGT: IGT_6315 -> IGTPW_6510

  CI-20190529: 20190529
  CI_DRM_11016: ae9547869b01c3441cd15dc9521f42ac9dc6d028 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_6510: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6510/index.html
  IGT_6315: 2f59b36a40331e98610dab12baefbe82b6e3cef0 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git



== Testlist changes ==

+igt@i915_hangman@detector
+igt@i915_hangman@engine-engine-error
+igt@i915_hangman@engine-engine-hang
+igt@i915_hangman@engine-error-state-capture
+igt@i915_hangman@gt-engine-error
+igt@i915_hangman@gt-engine-hang
+igt@i915_hangman@gt-error-state-capture
-igt@i915_hangman@engine-error
-igt@i915_hangman@engine-hang
-igt@i915_hangman@error-state-capture

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6510/index.html

[-- Attachment #2: Type: text/html, Size: 5831 bytes --]

[igt-dev] ✓ Fi.CI.IGT: success for Fixes for i915_hangman and gem_exec_capture (rev2)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 30268 bytes --]

== Series Details ==

Series: Fixes for i915_hangman and gem_exec_capture (rev2)
URL   : https://patchwork.freedesktop.org/series/97981/
State : success

== Summary ==

CI Bug Log - changes from IGT_6315_full -> IGTPW_6510_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6510/index.html

Participating hosts (7 -> 7)
------------------------------

  No changes in participating hosts

New tests
---------

  New tests have been introduced between IGT_6315_full and IGTPW_6510_full:

### New IGT tests (36) ###

  * igt@i915_hangman@detector:
    - Statuses :
    - Exec time: [None] s

  * igt@i915_hangman@detector@bcs0:
    - Statuses : 6 pass(s)
    - Exec time: [6.01, 15.07] s

  * igt@i915_hangman@detector@rcs0:
    - Statuses : 6 pass(s)
    - Exec time: [6.32, 15.59] s

  * igt@i915_hangman@detector@vcs0:
    - Statuses : 6 pass(s)
    - Exec time: [6.02, 15.04] s

  * igt@i915_hangman@detector@vcs1:
    - Statuses : 2 pass(s)
    - Exec time: [14.95, 14.98] s

  * igt@i915_hangman@detector@vecs0:
    - Statuses : 5 pass(s)
    - Exec time: [14.88, 15.14] s

  * igt@i915_hangman@engine-engine-error:
    - Statuses : 1 skip(s)
    - Exec time: [0.0] s

  * igt@i915_hangman@engine-engine-error@bcs0:
    - Statuses : 2 pass(s) 3 skip(s)
    - Exec time: [0.00, 0.02] s

  * igt@i915_hangman@engine-engine-error@rcs0:
    - Statuses : 5 pass(s)
    - Exec time: [0.02, 0.09] s

  * igt@i915_hangman@engine-engine-error@vcs0:
    - Statuses : 5 pass(s)
    - Exec time: [0.02, 0.08] s

  * igt@i915_hangman@engine-engine-error@vcs1:
    - Statuses : 2 pass(s)
    - Exec time: [0.02, 0.03] s

  * igt@i915_hangman@engine-engine-error@vecs0:
    - Statuses : 5 pass(s)
    - Exec time: [0.02, 0.07] s

  * igt@i915_hangman@engine-engine-hang:
    - Statuses : 1 skip(s)
    - Exec time: [0.0] s

  * igt@i915_hangman@engine-engine-hang@bcs0:
    - Statuses : 5 pass(s)
    - Exec time: [0.69, 0.76] s

  * igt@i915_hangman@engine-engine-hang@rcs0:
    - Statuses : 5 pass(s)
    - Exec time: [0.72, 14.72] s

  * igt@i915_hangman@engine-engine-hang@vcs0:
    - Statuses : 5 pass(s)
    - Exec time: [0.70, 0.76] s

  * igt@i915_hangman@engine-engine-hang@vcs1:
    - Statuses : 2 pass(s)
    - Exec time: [0.70] s

  * igt@i915_hangman@engine-engine-hang@vecs0:
    - Statuses : 5 pass(s)
    - Exec time: [0.70, 0.77] s

  * igt@i915_hangman@engine-error-state-capture:
    - Statuses : 1 skip(s)
    - Exec time: [0.0] s

  * igt@i915_hangman@engine-error-state-capture@bcs0:
    - Statuses : 3 pass(s)
    - Exec time: [6.72, 7.04] s

  * igt@i915_hangman@engine-error-state-capture@rcs0:
    - Statuses : 3 pass(s)
    - Exec time: [6.34, 14.71] s

  * igt@i915_hangman@engine-error-state-capture@vcs0:
    - Statuses : 3 pass(s)
    - Exec time: [6.97, 7.04] s

  * igt@i915_hangman@engine-error-state-capture@vcs1:
    - Statuses : 2 pass(s)
    - Exec time: [6.97, 6.98] s

  * igt@i915_hangman@engine-error-state-capture@vecs0:
    - Statuses : 3 pass(s)
    - Exec time: [6.97, 7.04] s

  * igt@i915_hangman@gt-engine-error:
    - Statuses : 1 skip(s)
    - Exec time: [0.0] s

  * igt@i915_hangman@gt-engine-error@bcs0:
    - Statuses : 1 pass(s) 2 skip(s)
    - Exec time: [0.00, 0.02] s

  * igt@i915_hangman@gt-engine-error@rcs0:
    - Statuses : 3 pass(s)
    - Exec time: [0.02, 0.07] s

  * igt@i915_hangman@gt-engine-error@vcs0:
    - Statuses : 3 pass(s)
    - Exec time: [0.02, 0.06] s

  * igt@i915_hangman@gt-engine-error@vecs0:
    - Statuses : 3 pass(s)
    - Exec time: [0.02, 0.06] s

  * igt@i915_hangman@gt-engine-hang:
    - Statuses :
    - Exec time: [None] s

  * igt@i915_hangman@gt-error-state-capture:
    - Statuses :
    - Exec time: [None] s

  * igt@i915_hangman@gt-error-state-capture@bcs0:
    - Statuses : 6 pass(s)
    - Exec time: [6.02, 15.04] s

  * igt@i915_hangman@gt-error-state-capture@rcs0:
    - Statuses : 6 pass(s)
    - Exec time: [5.69, 15.57] s

  * igt@i915_hangman@gt-error-state-capture@vcs0:
    - Statuses : 6 pass(s)
    - Exec time: [6.02, 15.05] s

  * igt@i915_hangman@gt-error-state-capture@vcs1:
    - Statuses : 2 pass(s)
    - Exec time: [14.98] s

  * igt@i915_hangman@gt-error-state-capture@vecs0:
    - Statuses : 5 pass(s)
    - Exec time: [14.98, 15.04] s

  

Known issues
------------

  Here are the changes found in IGTPW_6510_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_create@create-massive:
    - shard-apl:          NOTRUN -> [DMESG-WARN][1] ([i915#3002])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6510/shard-apl4/igt@gem_create@create-massive.html

  * igt@gem_eio@unwedge-stress:
    - shard-iclb:         NOTRUN -> [TIMEOUT][2] ([i915#2481] / [i915#3070])
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6510/shard-iclb2/igt@gem_eio@unwedge-stress.html

  * igt@gem_exec_balancer@parallel-bb-first:
    - shard-tglb:         NOTRUN -> [SKIP][3] ([i915#4525]) +1 similar issue
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6510/shard-tglb1/igt@gem_exec_balancer@parallel-bb-first.html

  * igt@gem_exec_balancer@parallel-out-fence:
    - shard-iclb:         NOTRUN -> [SKIP][4] ([i915#4525]) +1 similar issue
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6510/shard-iclb7/igt@gem_exec_balancer@parallel-out-fence.html

  * igt@gem_exec_fair@basic-deadline:
    - shard-glk:          [PASS][5] -> [FAIL][6] ([i915#2846])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6315/shard-glk5/igt@gem_exec_fair@basic-deadline.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6510/shard-glk4/igt@gem_exec_fair@basic-deadline.html

  * igt@gem_exec_fair@basic-none@vecs0:
    - shard-apl:          [PASS][7] -> [FAIL][8] ([i915#2842])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6315/shard-apl2/igt@gem_exec_fair@basic-none@vecs0.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6510/shard-apl1/igt@gem_exec_fair@basic-none@vecs0.html

  * igt@gem_exec_fair@basic-pace-solo@rcs0:
    - shard-iclb:         [PASS][9] -> [FAIL][10] ([i915#2842])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6315/shard-iclb2/igt@gem_exec_fair@basic-pace-solo@rcs0.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6510/shard-iclb6/igt@gem_exec_fair@basic-pace-solo@rcs0.html
    - shard-glk:          [PASS][11] -> [FAIL][12] ([i915#2842])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6315/shard-glk6/igt@gem_exec_fair@basic-pace-solo@rcs0.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6510/shard-glk6/igt@gem_exec_fair@basic-pace-solo@rcs0.html

  * igt@gem_exec_fair@basic-throttle@rcs0:
    - shard-iclb:         [PASS][13] -> [FAIL][14] ([i915#2849])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6315/shard-iclb6/igt@gem_exec_fair@basic-throttle@rcs0.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6510/shard-iclb5/igt@gem_exec_fair@basic-throttle@rcs0.html

  * igt@gem_exec_whisper@basic-queues-all:
    - shard-glk:          [PASS][15] -> [DMESG-WARN][16] ([i915#118]) +1 similar issue
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6315/shard-glk7/igt@gem_exec_whisper@basic-queues-all.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6510/shard-glk8/igt@gem_exec_whisper@basic-queues-all.html

  * igt@gem_lmem_swapping@heavy-verify-random:
    - shard-kbl:          NOTRUN -> [SKIP][17] ([fdo#109271] / [i915#4613]) +2 similar issues
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6510/shard-kbl6/igt@gem_lmem_swapping@heavy-verify-random.html

  * igt@gem_lmem_swapping@random-engines:
    - shard-iclb:         NOTRUN -> [SKIP][18] ([i915#4613])
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6510/shard-iclb7/igt@gem_lmem_swapping@random-engines.html
    - shard-apl:          NOTRUN -> [SKIP][19] ([fdo#109271] / [i915#4613]) +1 similar issue
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6510/shard-apl7/igt@gem_lmem_swapping@random-engines.html
    - shard-glk:          NOTRUN -> [SKIP][20] ([fdo#109271] / [i915#4613])
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6510/shard-glk7/igt@gem_lmem_swapping@random-engines.html
    - shard-tglb:         NOTRUN -> [SKIP][21] ([i915#4613])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6510/shard-tglb2/igt@gem_lmem_swapping@random-engines.html

  * igt@gem_pwrite@basic-exhaustion:
    - shard-kbl:          NOTRUN -> [WARN][22] ([i915#2658])
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6510/shard-kbl1/igt@gem_pwrite@basic-exhaustion.html

  * igt@gem_userptr_blits@dmabuf-sync:
    - shard-kbl:          NOTRUN -> [SKIP][23] ([fdo#109271] / [i915#3323])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6510/shard-kbl3/igt@gem_userptr_blits@dmabuf-sync.html
    - shard-iclb:         NOTRUN -> [SKIP][24] ([i915#3323])
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6510/shard-iclb4/igt@gem_userptr_blits@dmabuf-sync.html
    - shard-apl:          NOTRUN -> [SKIP][25] ([fdo#109271] / [i915#3323])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6510/shard-apl4/igt@gem_userptr_blits@dmabuf-sync.html
    - shard-glk:          NOTRUN -> [SKIP][26] ([fdo#109271] / [i915#3323])
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6510/shard-glk1/igt@gem_userptr_blits@dmabuf-sync.html
    - shard-tglb:         NOTRUN -> [SKIP][27] ([i915#3323])
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6510/shard-tglb3/igt@gem_userptr_blits@dmabuf-sync.html

  * igt@gem_userptr_blits@input-checking:
    - shard-kbl:          NOTRUN -> [DMESG-WARN][28] ([i915#3002])
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6510/shard-kbl6/igt@gem_userptr_blits@input-checking.html

  * igt@gen9_exec_parse@basic-rejected:
    - shard-iclb:         NOTRUN -> [SKIP][29] ([i915#2856]) +1 similar issue
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6510/shard-iclb6/igt@gen9_exec_parse@basic-rejected.html

  * igt@gen9_exec_parse@basic-rejected-ctx-param:
    - shard-tglb:         NOTRUN -> [SKIP][30] ([i915#2856]) +1 similar issue
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6510/shard-tglb3/igt@gen9_exec_parse@basic-rejected-ctx-param.html

  * {igt@i915_hangman@engine-engine-hang} (NEW):
    - shard-snb:          NOTRUN -> [SKIP][31] ([fdo#109271]) +140 similar issues
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6510/shard-snb4/igt@i915_hangman@engine-engine-hang.html

  * igt@i915_pm_dc@dc6-dpms:
    - shard-iclb:         [PASS][32] -> [FAIL][33] ([i915#454])
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6315/shard-iclb8/igt@i915_pm_dc@dc6-dpms.html
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6510/shard-iclb3/igt@i915_pm_dc@dc6-dpms.html

  * igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-dp:
    - shard-apl:          NOTRUN -> [SKIP][34] ([fdo#109271] / [i915#1937])
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6510/shard-apl3/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-dp.html

  * igt@i915_pm_rpm@dpms-non-lpsp:
    - shard-tglb:         NOTRUN -> [SKIP][35] ([fdo#111644] / [i915#1397] / [i915#2411])
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6510/shard-tglb2/igt@i915_pm_rpm@dpms-non-lpsp.html
    - shard-iclb:         NOTRUN -> [SKIP][36] ([fdo#110892])
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6510/shard-iclb4/igt@i915_pm_rpm@dpms-non-lpsp.html

  * igt@i915_pm_rpm@modeset-pc8-residency-stress:
    - shard-apl:          NOTRUN -> [SKIP][37] ([fdo#109271]) +113 similar issues
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6510/shard-apl4/igt@i915_pm_rpm@modeset-pc8-residency-stress.html
    - shard-tglb:         NOTRUN -> [SKIP][38] ([fdo#109506] / [i915#2411])
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6510/shard-tglb3/igt@i915_pm_rpm@modeset-pc8-residency-stress.html
    - shard-iclb:         NOTRUN -> [SKIP][39] ([fdo#109293] / [fdo#109506])
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6510/shard-iclb6/igt@i915_pm_rpm@modeset-pc8-residency-stress.html

  * igt@kms_big_fb@linear-16bpp-rotate-90:
    - shard-iclb:         NOTRUN -> [SKIP][40] ([fdo#110725] / [fdo#111614]) +2 similar issues
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6510/shard-iclb7/igt@kms_big_fb@linear-16bpp-rotate-90.html

  * igt@kms_big_fb@x-tiled-16bpp-rotate-90:
    - shard-glk:          NOTRUN -> [SKIP][41] ([fdo#109271]) +40 similar issues
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6510/shard-glk4/igt@kms_big_fb@x-tiled-16bpp-rotate-90.html
    - shard-tglb:         NOTRUN -> [SKIP][42] ([fdo#111614]) +2 similar issues
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6510/shard-tglb5/igt@kms_big_fb@x-tiled-16bpp-rotate-90.html

  * igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-hflip:
    - shard-kbl:          NOTRUN -> [SKIP][43] ([fdo#109271] / [i915#3777]) +1 similar issue
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6510/shard-kbl4/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-hflip.html

  * igt@kms_big_fb@yf-tiled-64bpp-rotate-0:
    - shard-iclb:         NOTRUN -> [SKIP][44] ([fdo#110723])
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6510/shard-iclb7/igt@kms_big_fb@yf-tiled-64bpp-rotate-0.html

  * igt@kms_big_fb@yf-tiled-addfb-size-overflow:
    - shard-tglb:         NOTRUN -> [SKIP][45] ([fdo#111615]) +2 similar issues
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6510/shard-tglb5/igt@kms_big_fb@yf-tiled-addfb-size-overflow.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip:
    - shard-apl:          NOTRUN -> [SKIP][46] ([fdo#109271] / [i915#3777])
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6510/shard-apl1/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip.html

  * igt@kms_ccs@pipe-a-crc-primary-basic-y_tiled_gen12_rc_ccs_cc:
    - shard-iclb:         NOTRUN -> [SKIP][47] ([fdo#109278] / [i915#3886]) +1 similar issue
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6510/shard-iclb6/igt@kms_ccs@pipe-a-crc-primary-basic-y_tiled_gen12_rc_ccs_cc.html

  * igt@kms_ccs@pipe-a-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc:
    - shard-kbl:          NOTRUN -> [SKIP][48] ([fdo#109271] / [i915#3886]) +4 similar issues
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6510/shard-kbl6/igt@kms_ccs@pipe-a-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc.html

  * igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs:
    - shard-apl:          NOTRUN -> [SKIP][49] ([fdo#109271] / [i915#3886]) +2 similar issues
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6510/shard-apl1/igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs.html

  * igt@kms_ccs@pipe-b-bad-aux-stride-y_tiled_gen12_mc_ccs:
    - shard-tglb:         NOTRUN -> [SKIP][50] ([i915#3689] / [i915#3886]) +1 similar issue
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6510/shard-tglb6/igt@kms_ccs@pipe-b-bad-aux-stride-y_tiled_gen12_mc_ccs.html

  * igt@kms_ccs@pipe-b-crc-primary-basic-y_tiled_gen12_rc_ccs_cc:
    - shard-glk:          NOTRUN -> [SKIP][51] ([fdo#109271] / [i915#3886])
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6510/shard-glk7/igt@kms_ccs@pipe-b-crc-primary-basic-y_tiled_gen12_rc_ccs_cc.html

  * igt@kms_ccs@pipe-c-random-ccs-data-yf_tiled_ccs:
    - shard-tglb:         NOTRUN -> [SKIP][52] ([fdo#111615] / [i915#3689])
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6510/shard-tglb3/igt@kms_ccs@pipe-c-random-ccs-data-yf_tiled_ccs.html

  * igt@kms_ccs@pipe-d-ccs-on-another-bo-y_tiled_ccs:
    - shard-tglb:         NOTRUN -> [SKIP][53] ([i915#3689]) +4 similar issues
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6510/shard-tglb2/igt@kms_ccs@pipe-d-ccs-on-another-bo-y_tiled_ccs.html

  * igt@kms_chamelium@dp-frame-dump:
    - shard-iclb:         NOTRUN -> [SKIP][54] ([fdo#109284] / [fdo#111827]) +4 similar issues
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6510/shard-iclb4/igt@kms_chamelium@dp-frame-dump.html
    - shard-glk:          NOTRUN -> [SKIP][55] ([fdo#109271] / [fdo#111827]) +3 similar issues
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6510/shard-glk8/igt@kms_chamelium@dp-frame-dump.html

  * igt@kms_chamelium@dp-mode-timings:
    - shard-apl:          NOTRUN -> [SKIP][56] ([fdo#109271] / [fdo#111827]) +13 similar issues
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6510/shard-apl1/igt@kms_chamelium@dp-mode-timings.html

  * igt@kms_chamelium@hdmi-hpd-with-enabled-mode:
    - shard-kbl:          NOTRUN -> [SKIP][57] ([fdo#109271] / [fdo#111827]) +11 similar issues
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6510/shard-kbl1/igt@kms_chamelium@hdmi-hpd-with-enabled-mode.html

  * igt@kms_chamelium@hdmi-mode-timings:
    - shard-snb:          NOTRUN -> [SKIP][58] ([fdo#109271] / [fdo#111827]) +6 similar issues
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6510/shard-snb5/igt@kms_chamelium@hdmi-mode-timings.html

  * igt@kms_chamelium@vga-hpd:
    - shard-tglb:         NOTRUN -> [SKIP][59] ([fdo#109284] / [fdo#111827]) +8 similar issues
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6510/shard-tglb5/igt@kms_chamelium@vga-hpd.html

  * igt@kms_color@pipe-d-degamma:
    - shard-iclb:         NOTRUN -> [SKIP][60] ([fdo#109278] / [i915#1149]) +1 similar issue
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6510/shard-iclb8/igt@kms_color@pipe-d-degamma.html

  * igt@kms_color_chamelium@pipe-d-ctm-0-5:
    - shard-iclb:         NOTRUN -> [SKIP][61] ([fdo#109278] / [fdo#109284] / [fdo#111827])
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6510/shard-iclb2/igt@kms_color_chamelium@pipe-d-ctm-0-5.html

  * igt@kms_content_protection@atomic-dpms:
    - shard-apl:          NOTRUN -> [TIMEOUT][62] ([i915#1319]) +1 similar issue
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6510/shard-apl7/igt@kms_content_protection@atomic-dpms.html
    - shard-kbl:          NOTRUN -> [TIMEOUT][63] ([i915#1319])
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6510/shard-kbl7/igt@kms_content_protection@atomic-dpms.html

  * igt@kms_content_protection@uevent:
    - shard-kbl:          NOTRUN -> [FAIL][64] ([i915#2105])
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6510/shard-kbl1/igt@kms_content_protection@uevent.html

  * igt@kms_cursor_crc@pipe-a-cursor-32x32-rapid-movement:
    - shard-tglb:         NOTRUN -> [SKIP][65] ([i915#3319]) +1 similar issue
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6510/shard-tglb8/igt@kms_cursor_crc@pipe-a-cursor-32x32-rapid-movement.html

  * igt@kms_cursor_crc@pipe-a-cursor-512x512-sliding:
    - shard-iclb:         NOTRUN -> [SKIP][66] ([fdo#109278] / [fdo#109279]) +3 similar issues
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6510/shard-iclb1/igt@kms_cursor_crc@pipe-a-cursor-512x512-sliding.html

  * igt@kms_cursor_crc@pipe-a-cursor-max-size-onscreen:
    - shard-tglb:         NOTRUN -> [SKIP][67] ([i915#3359]) +3 similar issues
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6510/shard-tglb6/igt@kms_cursor_crc@pipe-a-cursor-max-size-onscreen.html

  * igt@kms_cursor_crc@pipe-b-cursor-512x170-random:
    - shard-tglb:         NOTRUN -> [SKIP][68] ([fdo#109279] / [i915#3359]) +3 similar issues
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6510/shard-tglb2/igt@kms_cursor_crc@pipe-b-cursor-512x170-random.html

  * igt@kms_cursor_crc@pipe-d-cursor-256x85-random:
    - shard-iclb:         NOTRUN -> [SKIP][69] ([fdo#109278]) +13 similar issues
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6510/shard-iclb3/igt@kms_cursor_crc@pipe-d-cursor-256x85-random.html

  * igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions:
    - shard-iclb:         NOTRUN -> [SKIP][70] ([fdo#109274] / [fdo#109278]) +1 similar issue
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6510/shard-iclb1/igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions.html

  * igt@kms_cursor_legacy@pipe-d-single-bo:
    - shard-glk:          NOTRUN -> [SKIP][71] ([fdo#109271] / [i915#533])
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6510/shard-glk9/igt@kms_cursor_legacy@pipe-d-single-bo.html
    - shard-kbl:          NOTRUN -> [SKIP][72] ([fdo#109271] / [i915#533]) +1 similar issue
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6510/shard-kbl4/igt@kms_cursor_legacy@pipe-d-single-bo.html

  * igt@kms_flip@2x-flip-vs-fences-interruptible:
    - shard-tglb:         NOTRUN -> [SKIP][73] ([fdo#111825]) +19 similar issues
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6510/shard-tglb1/igt@kms_flip@2x-flip-vs-fences-interruptible.html
    - shard-iclb:         NOTRUN -> [SKIP][74] ([fdo#109274]) +1 similar issue
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6510/shard-iclb3/igt@kms_flip@2x-flip-vs-fences-interruptible.html

  * igt@kms_flip@flip-vs-suspend-interruptible@c-dp1:
    - shard-apl:          [PASS][75] -> [DMESG-WARN][76] ([i915#180]) +3 similar issues
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6315/shard-apl8/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6510/shard-apl8/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html

  * igt@kms_flip@flip-vs-suspend@c-dp1:
    - shard-kbl:          [PASS][77] -> [DMESG-WARN][78] ([i915#180]) +4 similar issues
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6315/shard-kbl7/igt@kms_flip@flip-vs-suspend@c-dp1.html
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6510/shard-kbl4/igt@kms_flip@flip-vs-suspend@c-dp1.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs:
    - shard-kbl:          NOTRUN -> [SKIP][79] ([fdo#109271] / [i915#2672])
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6510/shard-kbl6/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs.html
    - shard-apl:          NOTRUN -> [SKIP][80] ([fdo#109271] / [i915#2672])
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6510/shard-apl8/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs.html
    - shard-glk:          NOTRUN -> [SKIP][81] ([fdo#109271] / [i915#2672])
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6510/shard-glk5/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs.html
    - shard-iclb:         NOTRUN -> [SKIP][82] ([i915#2587])
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6510/shard-iclb1/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile:
    - shard-iclb:         [PASS][83] -> [SKIP][84] ([i915#3701])
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6315/shard-iclb1/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile.html
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6510/shard-iclb2/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile.html

  * igt@kms_force_connector_basic@force-load-detect:
    - shard-iclb:         NOTRUN -> [SKIP][85] ([fdo#109285])
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6510/shard-iclb5/igt@kms_force_connector_basic@force-load-detect.html
    - shard-tglb:         NOTRUN -> [SKIP][86] ([fdo#109285])
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6510/shard-tglb1/igt@kms_force_connector_basic@force-load-detect.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-blt:
    - shard-kbl:          NOTRUN -> [SKIP][87] ([fdo#109271]) +160 similar issues
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6510/shard-kbl6/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-render:
    - shard-iclb:         NOTRUN -> [SKIP][88] ([fdo#109280]) +12 similar issues
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6510/shard-iclb1/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-render.html

  * igt@kms_hdr@static-toggle-suspend:
    - shard-tglb:         NOTRUN -> [SKIP][89] ([i915#1187])
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6510/shard-tglb8/igt@kms_hdr@static-toggle-suspend.html
    - shard-iclb:         NOTRUN -> [SKIP][90] ([i915#1187])
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6510/shard-iclb7/igt@kms_hdr@static-toggle-suspend.html

  * igt@kms_pipe_b_c_ivb@disable-pipe-b-enable-pipe-c:
    - shard-iclb:         NOTRUN -> [SKIP][91] ([fdo#109289]) +1 similar issue
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6510/shard-iclb4/igt@kms_pipe_b_c_ivb@disable-pipe-b-enable-pipe-c.html

  * igt@kms_pipe_b_c_ivb@enable-pipe-c-while-b-has-3-lanes:
    - shard-tglb:         NOTRUN -> [SKIP][92] ([fdo#109289]) +2 similar issues
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6510/shard-tglb3/igt@kms_pipe_b_c_ivb@enable-pipe-c-while-b-has-3-lanes.html

  * igt@kms_pipe_crc_basic@hang-read-crc-pipe-b:
    - shard-kbl:          [PASS][93] -> [SKIP][94] ([fdo#109271])
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6315/shard-kbl3/igt@kms_pipe_crc_basic@hang-read-crc-pipe-b.html
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6510/shard-kbl1/igt@kms_pipe_crc_basic@hang-read-crc-pipe-b.html
    - shard-apl:          [PASS][95] -> [SKIP][96] ([fdo#109271])
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6315/shard-apl2/igt@kms_pipe_crc_basic@hang-read-crc-pipe-b.html
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6510/shard-apl7/igt@kms_pipe_crc_basic@hang-read-crc-pipe-b.html
    - shard-glk:          [PASS][97] -> [SKIP][98] ([fdo#109271])
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6315/shard-glk6/igt@kms_pipe_crc_basic@hang-read-crc-pipe-b.html
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6510/shard-glk8/igt@kms_pipe_crc_basic@hang-read-crc-pipe-b.html

  * igt@kms_pipe_crc_basic@read-crc-pipe-d-frame-sequence:
    - shard-apl:          NOTRUN -> [SKIP][99] ([fdo#109271] / [i915#533]) +1 similar issue
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6510/shard-apl2/igt@kms_pipe_crc_basic@read-crc-pipe-d-frame-sequence.html

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
    - shard-kbl:          NOTRUN -> [DMESG-WARN][100] ([i915#180]) +1 similar issue
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6510/shard-kbl1/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c.html

  * igt@kms_plane_alpha_blend@pipe-a-alpha-basic:
    - shard-apl:          NOTRUN -> [FAIL][101] ([fdo#108145] / [i915#265]) +2 similar issues
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6510/shard-apl1/igt@kms_plane_alpha_blend@pipe-a-alpha-basic.html

  * igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb:
    - shard-kbl:          NOTRUN -> [FAIL][102] ([i915#265])
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6510/shard-kbl6/igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb.html

  * igt@kms_plane_alpha_blend@pipe-c-constant-alpha-max:
    - shard-glk:          NOTRUN -> [FAIL][103] ([fdo#108145] / [i915#265])
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6510/shard-glk1/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-max.html
    - shard-kbl:          NOTRUN -> [FAIL][104] ([fdo#108145] / [i915#265]) +1 similar issue
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6510/shard-kbl4/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-max.html

  * igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-c-scaler-with-clipping-clamping:
    - shard-apl:          NOTRUN -> [SKIP][105] ([fdo#109271] / [i915#2733])
   [105]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6510/shard-apl7/igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-c-scaler-with-clipping-clamping.html

  * igt@kms_psr2_sf@cursor-plane-update-sf:
    - shard-kbl:          NOTRUN -> [SKIP][106] ([fdo#109271] / [i915#658])
   [106]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6510/shard-kbl4/igt@kms_psr2_sf@cursor-plane-update-sf.html

  * igt@kms_psr2_sf@plane-move-sf-dmg-area:
    - shard-apl:          NOTRUN -> [SKIP][107] ([fdo#109271] / [i915#658])
   [107]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6510/shard-apl2/igt@kms_psr2_sf@plane-move-sf-dmg-area.html

  * igt@kms_psr@psr2_dpms:
    - shard-tglb:         NOTRUN -> [FAIL][108] ([i915#132] / [i915#3467]) +1 similar issue
   [108]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6510/shard-tglb8/igt@kms_psr@psr2_dpms.html
    - shard-iclb:         NOTRUN -> [SKIP][109] ([fdo#109441]) +1 similar issue
   [109]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6510/shard-iclb7/igt@kms_psr@psr2_dpms.html

  * igt@kms_psr@psr2_sprite_plane_move:
    - shard-iclb:         [PASS][110] -> [SKIP][111] ([fdo#109441]) +1 similar issue
   [110]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6315/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html
   [111]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6510/shard-iclb4/igt@kms_psr@psr2_sprite_plane_move.html

  * igt@kms_setmode@basic:
    - shard-snb:          NOTRUN -> [FAIL][112] ([i915#31])
   [112]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6510/shard-snb4/igt@kms_setmode@basic.html

  * igt@kms_vblank@pipe-a-ts-continuation-suspend:
    - shard-kbl:          NOTRUN -> [DMESG-WARN][113] ([i915#180] / [i915#295])
   [113]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6510/shard-kbl1/igt@kms_vblank@pipe-a-ts-continuation-suspend.html

  * igt@kms_vrr@flip-basic:
    - shard-tglb:         NOTRUN -> [SKIP][114] ([fdo#109502])
   [114]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6510/shard-tglb7/igt@kms_vrr@flip-basic.html
    - shard-iclb:         NOTRUN -> [SKIP][115] ([fdo#109502])
   [115]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6510/shard-iclb2/igt@kms_vrr@flip-basic.html

  * igt@kms_writeback@writeback-fb-id:
    - shard-kbl:          NOTRUN -> [SKIP][116] ([fdo#109271] / [i915#2437])
   [116]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6510/shard-kbl1/igt@kms_writeback@writeback-fb-id.html
    - shard-t

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6510/index.html

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Re: [Intel-gfx] [igt-dev] [PATCH i-g-t 04/11] tests/i915/i915_hangman: Explicitly test per engine reset vs full GPU reset

[John Harrison]

On 12/21/2021 03:28, Dandamudi, Priyanka wrote:
> Does this test series cover to prove that it can survive killing one without killing all the others except RCS+CCS combination(killing one affects other and shows with the help of reset stats)?
That is part of the purpose of i915_hangman - to test that a hang on one 
engine does not affect work on other engines. Note that there is no CCS 
support in IGT yet. Patches are still in progress. At least, they 
certainly hadn't been merged when this patch set was posted.

John.

Re: [igt-dev] [PATCH i-g-t 04/11] tests/i915/i915_hangman: Explicitly test per engine reset vs full GPU reset

[John Harrison]

On 12/21/2021 03:28, Dandamudi, Priyanka wrote:
> Does this test series cover to prove that it can survive killing one without killing all the others except RCS+CCS combination(killing one affects other and shows with the help of reset stats)?
That is part of the purpose of i915_hangman - to test that a hang on one 
engine does not affect work on other engines. Note that there is no CCS 
support in IGT yet. Patches are still in progress. At least, they 
certainly hadn't been merged when this patch set was posted.

John.

Re: [Intel-gfx] [igt-dev] [PATCH i-g-t 08/11] lib/store: Refactor common store code into helper function

[John Harrison]

On 12/20/2021 10:13, Zbigniew Kempczyński wrote:
> On Thu, Dec 16, 2021 at 02:40:21PM -0800, John Harrison wrote:
>> On 12/15/2021 23:46, Zbigniew Kempczyński wrote:
>>> On Mon, Dec 13, 2021 at 03:29:11PM -0800, John.C.Harrison@Intel.com wrote:
>>>> From: John Harrison <John.C.Harrison@Intel.com>
>>>>
>>>> A lot of tests use almost identical code for creating a batch buffer
>>>> which does a single write to memory. This patch collects two such
>>>> instances into a common helper function. Unfortunately, the other
>>>> instances are all subtly different enough to make it not so trivial to
>>>> try to use the helper. It could be done but it is unclear if it is
>>>> worth the effort at this point. This patch proves the concept, if
>>>> people like it enough then it can be extended.
>>>>
>>>> Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
>>>> ---
>>>>    lib/igt_store.c             | 114 ++++++++++++++++++++++++++++++++++++
>>>>    lib/igt_store.h             |  30 ++++++++++
>>>>    lib/meson.build             |   1 +
>>>>    tests/i915/gem_exec_fence.c |  77 ++----------------------
>>>>    tests/i915/i915_hangman.c   |  61 +------------------
>>>>    5 files changed, 152 insertions(+), 131 deletions(-)
>>>>    create mode 100644 lib/igt_store.c
>>>>    create mode 100644 lib/igt_store.h
>>>>
>>>> diff --git a/lib/igt_store.c b/lib/igt_store.c
>>>> new file mode 100644
>>>> index 000000000..6d9869b58
>>>> --- /dev/null
>>>> +++ b/lib/igt_store.c
>>>> @@ -0,0 +1,114 @@
>>>> +/*
>>>> + * Copyright © 2020 Intel Corporation
>>>> + *
>>>> + * Permission is hereby granted, free of charge, to any person obtaining a
>>>> + * copy of this software and associated documentation files (the "Software"),
>>>> + * to deal in the Software without restriction, including without limitation
>>>> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>>>> + * and/or sell copies of the Software, and to permit persons to whom the
>>>> + * Software is furnished to do so, subject to the following conditions:
>>>> + *
>>>> + * The above copyright notice and this permission notice (including the next
>>>> + * paragraph) shall be included in all copies or substantial portions of the
>>>> + * Software.
>>>> + *
>>>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>>>> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>>>> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>>>> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
>>>> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>>>> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
>>>> + * IN THE SOFTWARE.
>>>> + *
>>>> + */
>>> Use SPDX. I like idea of extracting this.
>>>
>>>> +
>>>> +#include "i915/gem_create.h"
>>>> +#include "igt_core.h"
>>>> +#include "drmtest.h"
>>>> +#include "igt_store.h"
>>>> +#include "intel_chipset.h"
>>>> +#include "intel_reg.h"
>>>> +#include "ioctl_wrappers.h"
>>>> +#include "lib/intel_allocator.h"
>>>> +
>>>> +/**
>>>> + * SECTION:igt_store_word
>>>> + * @short_description: Library for writing a value to memory
>>>> + * @title: StoreWord
>>>> + * @include: igt.h
>>>> + *
>>>> + * A lot of igt testcases need some mechanism for writing a value to memory
>>>> + * as a test that a batch buffer has executed.
>>>> + *
>>>> + * NB: Requires master for STORE_DWORD on gen4/5.
>>>> + */
>>>> +void igt_store_word(int fd, uint64_t ahnd, const intel_ctx_t *ctx,
>>>> +		    const struct intel_execution_engine2 *e,
>>>> +		    int fence, uint32_t target_handle,
>>>> +		    uint64_t target_offset, uint32_t target_value)
>>>> +{
>>>> +	const int SCRATCH = 0;
>>>> +	const int BATCH = 1;
>>>> +	const unsigned int gen = intel_gen(intel_get_drm_devid(fd));
>>>> +	struct drm_i915_gem_exec_object2 obj[2];
>>>> +	struct drm_i915_gem_relocation_entry reloc;
>>>> +	struct drm_i915_gem_execbuffer2 execbuf;
>>>> +	uint32_t batch[16], delta;
>>>> +	uint64_t bb_offset;
>>>> +	int i;
>>>> +
>>>> +	memset(&execbuf, 0, sizeof(execbuf));
>>>> +	execbuf.buffers_ptr = to_user_pointer(obj);
>>>> +	execbuf.buffer_count = ARRAY_SIZE(obj);
>>>> +	execbuf.flags = e->flags;
>>>> +	execbuf.rsvd1 = ctx->id;
>>>> +	if (fence != -1) {
>>>> +		execbuf.flags |= I915_EXEC_FENCE_IN;
>>>> +		execbuf.rsvd2 = fence;
>>>> +	}
>>>> +	if (gen < 6)
>>>> +		execbuf.flags |= I915_EXEC_SECURE;
>>>> +
>>>> +	memset(obj, 0, sizeof(obj));
>>>> +	obj[SCRATCH].handle = target_handle;
>>>> +
>>>> +	obj[BATCH].handle = gem_create(fd, 4096);
>>>> +	obj[BATCH].relocs_ptr = to_user_pointer(&reloc);
>>>> +	obj[BATCH].relocation_count = !ahnd ? 1 : 0;
>>>> +	bb_offset = get_offset(ahnd, obj[BATCH].handle, 4096, 0);
>>>> +	memset(&reloc, 0, sizeof(reloc));
>>>> +
>>>> +	i = 0;
>>>> +	delta = sizeof(uint32_t) * target_value;	/* why value not offset??? */
>>> I guess I know why there's problem here. target_offset is address in vm
>>> passed by the caller. This is regarding to some limitations of allocator
>>> infrastructure - for "reloc" pseudo-allocator you would get new offset
>>> (internally it returns offset and then add size for new "allocation").
>>> With this we don't need to wait for rebind offset for new execbuf.
>>> With "simple" allocator put will release offset so new allocation will
>>> reuse same offset. Ashutosh proposed how to join both functionalities
>>> (stepping as with reloc, stateful like in simple) but I got no time to
>>> code this.
>>>
>>> Regarding issue here, target_offset passed from the caller is to avoid
>>> rebind if get_offset() would be called for "reloc" allocator.
>>> So there's not real value offset within bo. I would add separate
>>> value_offset (shift) to allow caller to put place where it wants to
>>> write the value.
>> If you understand what is going on here and how to improve it then feel free
>> to either send me an updated version or post an extra patch after this is
>> merged. I don't get how any of the new reloc (or anti-reloc?) code is meant
>> to work. These patches were all written as part of the GuC support a long
>> time ago - before there was any such thing as an AHND (what does that stand
>> for?) or intel_ctx_t. All I'm doing in this patch is moving the existing
>> code to a helper and trying to make it generic enough to be used by another
>> test. And right now, the two tests are passing on both GuC and execlist
>> platforms for me. So the code can't be all that broken.
> I've added some missing parts to your code:
>
> https://patchwork.freedesktop.org/series/98242/
>
> If you think something is missing please add or fix.
>
> Previously value was used both for value and offset within bo
> used for example in gem_exec_fence@basic-await. I think adding
> separate arg for offset for value within bo makes this code
> more universal.
I don't follow. The purpose of the offset is the to say where the value 
is written within the buffer. As in 'target_offset' is 'offset into 
target buffer to write value'. You have added a 'value_offset' which 
surely would be defined as 'the offset at which to write the value in 
the target buffer'. I.e. exactly the same thing. What is the intention 
behind having two separate offset variables?

John.


>
> NB: ahnd is short version of allocator_handle
>
> --
> Zbigniew
>
>>
>>>
>>>> +	if (!ahnd) {
>>>> +		reloc.target_handle = obj[SCRATCH].handle;
>>>> +		reloc.presumed_offset = -1;
>>>> +		reloc.offset = sizeof(uint32_t) * (i + 1);
>>>> +		reloc.delta = delta;
>>>> +		reloc.read_domains = I915_GEM_DOMAIN_INSTRUCTION;
>>>> +		reloc.write_domain = I915_GEM_DOMAIN_INSTRUCTION;
>>>> +	} else {
>>>> +		obj[SCRATCH].offset = target_offset;
>>>> +		obj[SCRATCH].flags |= EXEC_OBJECT_PINNED | EXEC_OBJECT_WRITE;
>>>> +		obj[BATCH].offset = bb_offset;
>>>> +		obj[BATCH].flags |= EXEC_OBJECT_PINNED;
>>>> +	}
>>>> +	batch[i] = MI_STORE_DWORD_IMM | (gen < 6 ? 1 << 22 : 0);
>>>> +	if (gen >= 8) {
>>>> +		batch[++i] = target_offset + delta;
>>>> +		batch[++i] = target_offset >> 32;
>>> Probably I've added this in previous code, for being safe I would
>>> add (target_offset + delta) >> 32 for avoid risk passing invalid higher
>>> offset part on 32b boundary.
>> Pretty sure we don't have any addresses larger than 32 bits yet, but yes,
>> delta should be added in.
>>
>> Thanks,
>> John.
>>
>>>> +	} else if (gen >= 4) {
>>>> +		batch[++i] = 0;
>>>> +		batch[++i] = delta;
>>>> +		reloc.offset += sizeof(uint32_t);
>>>> +	} else {
>>>> +		batch[i]--;
>>>> +		batch[++i] = delta;
>>>> +	}
>>>> +	batch[++i] = target_value;
>>>> +	batch[++i] = MI_BATCH_BUFFER_END;
>>>> +	gem_write(fd, obj[BATCH].handle, 0, batch, sizeof(batch));
>>>> +	gem_execbuf(fd, &execbuf);
>>>> +	gem_close(fd, obj[BATCH].handle);
>>>> +	put_offset(ahnd, obj[BATCH].handle);
>>>> +}
>>>> diff --git a/lib/igt_store.h b/lib/igt_store.h
>>>> new file mode 100644
>>>> index 000000000..4d5979e07
>>>> --- /dev/null
>>>> +++ b/lib/igt_store.h
>>>> @@ -0,0 +1,30 @@
>>>> +/*
>>>> + * Copyright © 2020 Intel Corporation
>>>> + *
>>>> + * Permission is hereby granted, free of charge, to any person obtaining a
>>>> + * copy of this software and associated documentation files (the "Software"),
>>>> + * to deal in the Software without restriction, including without limitation
>>>> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>>>> + * and/or sell copies of the Software, and to permit persons to whom the
>>>> + * Software is furnished to do so, subject to the following conditions:
>>>> + *
>>>> + * The above copyright notice and this permission notice (including the next
>>>> + * paragraph) shall be included in all copies or substantial portions of the
>>>> + * Software.
>>>> + *
>>>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>>>> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>>>> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>>>> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
>>>> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>>>> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
>>>> + * IN THE SOFTWARE.
>>>> + *
>>>> + */
>>> Use SPDX and 2021.
>>>
>>> --
>>> Zbigniew
>>>
>>>> +
>>>> +#include "igt_gt.h"
>>>> +
>>>> +void igt_store_word(int fd, uint64_t ahnd, const intel_ctx_t *ctx,
>>>> +		    const struct intel_execution_engine2 *e,
>>>> +		    int fence, uint32_t target_handle,
>>>> +		    uint64_t target_offset, uint32_t target_value);
>>>> diff --git a/lib/meson.build b/lib/meson.build
>>>> index b9568a71b..3e43316d1 100644
>>>> --- a/lib/meson.build
>>>> +++ b/lib/meson.build
>>>> @@ -72,6 +72,7 @@ lib_sources = [
>>>>    	'igt_map.c',
>>>>    	'igt_pm.c',
>>>>    	'igt_dummyload.c',
>>>> +	'igt_store.c',
>>>>    	'uwildmat/uwildmat.c',
>>>>    	'igt_kmod.c',
>>>>    	'igt_panfrost.c',
>>>> diff --git a/tests/i915/gem_exec_fence.c b/tests/i915/gem_exec_fence.c
>>>> index 9a6336ce9..c4091a454 100644
>>>> --- a/tests/i915/gem_exec_fence.c
>>>> +++ b/tests/i915/gem_exec_fence.c
>>>> @@ -28,6 +28,7 @@
>>>>    #include "i915/gem.h"
>>>>    #include "i915/gem_create.h"
>>>>    #include "igt.h"
>>>> +#include "igt_store.h"
>>>>    #include "igt_syncobj.h"
>>>>    #include "igt_sysfs.h"
>>>>    #include "igt_vgem.h"
>>>> @@ -57,74 +58,6 @@ struct sync_merge_data {
>>>>    #define   MI_SEMAPHORE_SAD_EQ_SDD       (4 << 12)
>>>>    #define   MI_SEMAPHORE_SAD_NEQ_SDD      (5 << 12)
>>>> -static void store(int fd, uint64_t ahnd, const intel_ctx_t *ctx,
>>>> -		  const struct intel_execution_engine2 *e,
>>>> -		  int fence, uint32_t target, uint64_t target_offset,
>>>> -		  unsigned offset_value)
>>>> -{
>>>> -	const int SCRATCH = 0;
>>>> -	const int BATCH = 1;
>>>> -	const unsigned int gen = intel_gen(intel_get_drm_devid(fd));
>>>> -	struct drm_i915_gem_exec_object2 obj[2];
>>>> -	struct drm_i915_gem_relocation_entry reloc;
>>>> -	struct drm_i915_gem_execbuffer2 execbuf;
>>>> -	uint32_t batch[16], delta;
>>>> -	uint64_t bb_offset;
>>>> -	int i;
>>>> -
>>>> -	memset(&execbuf, 0, sizeof(execbuf));
>>>> -	execbuf.buffers_ptr = to_user_pointer(obj);
>>>> -	execbuf.buffer_count = 2;
>>>> -	execbuf.flags = e->flags | I915_EXEC_FENCE_IN;
>>>> -	execbuf.rsvd1 = ctx->id;
>>>> -	execbuf.rsvd2 = fence;
>>>> -	if (gen < 6)
>>>> -		execbuf.flags |= I915_EXEC_SECURE;
>>>> -
>>>> -	memset(obj, 0, sizeof(obj));
>>>> -	obj[SCRATCH].handle = target;
>>>> -
>>>> -	obj[BATCH].handle = gem_create(fd, 4096);
>>>> -	obj[BATCH].relocs_ptr = to_user_pointer(&reloc);
>>>> -	obj[BATCH].relocation_count = !ahnd ? 1 : 0;
>>>> -	bb_offset = get_offset(ahnd, obj[BATCH].handle, 4096, 0);
>>>> -	memset(&reloc, 0, sizeof(reloc));
>>>> -
>>>> -	i = 0;
>>>> -	delta = sizeof(uint32_t) * offset_value;
>>>> -	if (!ahnd) {
>>>> -		reloc.target_handle = obj[SCRATCH].handle;
>>>> -		reloc.presumed_offset = -1;
>>>> -		reloc.offset = sizeof(uint32_t) * (i + 1);
>>>> -		reloc.delta = delta;
>>>> -		reloc.read_domains = I915_GEM_DOMAIN_INSTRUCTION;
>>>> -		reloc.write_domain = I915_GEM_DOMAIN_INSTRUCTION;
>>>> -	} else {
>>>> -		obj[SCRATCH].offset = target_offset;
>>>> -		obj[SCRATCH].flags |= EXEC_OBJECT_PINNED | EXEC_OBJECT_WRITE;
>>>> -		obj[BATCH].offset = bb_offset;
>>>> -		obj[BATCH].flags |= EXEC_OBJECT_PINNED;
>>>> -	}
>>>> -	batch[i] = MI_STORE_DWORD_IMM | (gen < 6 ? 1 << 22 : 0);
>>>> -	if (gen >= 8) {
>>>> -		batch[++i] = target_offset + delta;
>>>> -		batch[++i] = target_offset >> 32;
>>>> -	} else if (gen >= 4) {
>>>> -		batch[++i] = 0;
>>>> -		batch[++i] = delta;
>>>> -		reloc.offset += sizeof(uint32_t);
>>>> -	} else {
>>>> -		batch[i]--;
>>>> -		batch[++i] = delta;
>>>> -	}
>>>> -	batch[++i] = offset_value;
>>>> -	batch[++i] = MI_BATCH_BUFFER_END;
>>>> -	gem_write(fd, obj[BATCH].handle, 0, batch, sizeof(batch));
>>>> -	gem_execbuf(fd, &execbuf);
>>>> -	gem_close(fd, obj[BATCH].handle);
>>>> -	put_offset(ahnd, obj[BATCH].handle);
>>>> -}
>>>> -
>>>>    static bool fence_busy(int fence)
>>>>    {
>>>>    	return poll(&(struct pollfd){fence, POLLIN}, 1, 0) == 0;
>>>> @@ -400,13 +333,13 @@ static void test_fence_await(int fd, const intel_ctx_t *ctx,
>>>>    			continue;
>>>>    		if (flags & NONBLOCK) {
>>>> -			store(fd, ahnd, ctx, e2, spin->out_fence,
>>>> -			      scratch, scratch_offset, i);
>>>> +			igt_store_word(fd, ahnd, ctx, e2, spin->out_fence,
>>>> +				       scratch, scratch_offset, i);
>>>>    		} else {
>>>>    			igt_fork(child, 1) {
>>>>    				ahnd = get_reloc_ahnd(fd, ctx->id);
>>>> -				store(fd, ahnd, ctx, e2, spin->out_fence,
>>>> -				      scratch, scratch_offset, i);
>>>> +				igt_store_word(fd, ahnd, ctx, e2, spin->out_fence,
>>>> +					       scratch, scratch_offset, i);
>>>>    				put_ahnd(ahnd);
>>>>    			}
>>>>    		}
>>>> diff --git a/tests/i915/i915_hangman.c b/tests/i915/i915_hangman.c
>>>> index 20653b479..4cb9b8b85 100644
>>>> --- a/tests/i915/i915_hangman.c
>>>> +++ b/tests/i915/i915_hangman.c
>>>> @@ -36,6 +36,7 @@
>>>>    #include "i915/gem.h"
>>>>    #include "i915/gem_create.h"
>>>>    #include "igt.h"
>>>> +#include "igt_store.h"
>>>>    #include "igt_sysfs.h"
>>>>    #include "igt_debugfs.h"
>>>>    #include "sw_sync.h"
>>>> @@ -51,64 +52,6 @@ static int sysfs = -1;
>>>>    IGT_TEST_DESCRIPTION("Tests for hang detection and recovery");
>>>> -/* Requires master for STORE_DWORD on gen4/5 */
>>>> -static void store(int fd, const struct intel_execution_engine2 *e,
>>>> -		  int fence, uint32_t target, unsigned offset_value)
>>>> -{
>>>> -	const int SCRATCH = 0;
>>>> -	const int BATCH = 1;
>>>> -	const int gen = intel_gen(intel_get_drm_devid(fd));
>>>> -	struct drm_i915_gem_exec_object2 obj[2];
>>>> -	struct drm_i915_gem_relocation_entry reloc;
>>>> -	struct drm_i915_gem_execbuffer2 execbuf;
>>>> -	uint32_t batch[16];
>>>> -	int i;
>>>> -
>>>> -	memset(&execbuf, 0, sizeof(execbuf));
>>>> -	execbuf.buffers_ptr = to_user_pointer(obj);
>>>> -	execbuf.buffer_count = ARRAY_SIZE(obj);
>>>> -	execbuf.flags = e->flags;
>>>> -	if (fence != -1) {
>>>> -		execbuf.flags |= I915_EXEC_FENCE_IN;
>>>> -		execbuf.rsvd2 = fence;
>>>> -	}
>>>> -	if (gen < 6)
>>>> -		execbuf.flags |= I915_EXEC_SECURE;
>>>> -
>>>> -	memset(obj, 0, sizeof(obj));
>>>> -	obj[SCRATCH].handle = target;
>>>> -
>>>> -	obj[BATCH].handle = gem_create(fd, 4096);
>>>> -	obj[BATCH].relocs_ptr = to_user_pointer(&reloc);
>>>> -	obj[BATCH].relocation_count = 1;
>>>> -	memset(&reloc, 0, sizeof(reloc));
>>>> -
>>>> -	i = 0;
>>>> -	reloc.target_handle = obj[SCRATCH].handle;
>>>> -	reloc.presumed_offset = -1;
>>>> -	reloc.offset = sizeof(uint32_t) * (i + 1);
>>>> -	reloc.delta = sizeof(uint32_t) * offset_value;
>>>> -	reloc.read_domains = I915_GEM_DOMAIN_INSTRUCTION;
>>>> -	reloc.write_domain = I915_GEM_DOMAIN_INSTRUCTION;
>>>> -	batch[i] = MI_STORE_DWORD_IMM | (gen < 6 ? 1 << 22 : 0);
>>>> -	if (gen >= 8) {
>>>> -		batch[++i] = reloc.delta;
>>>> -		batch[++i] = 0;
>>>> -	} else if (gen >= 4) {
>>>> -		batch[++i] = 0;
>>>> -		batch[++i] = reloc.delta;
>>>> -		reloc.offset += sizeof(uint32_t);
>>>> -	} else {
>>>> -		batch[i]--;
>>>> -		batch[++i] = reloc.delta;
>>>> -	}
>>>> -	batch[++i] = offset_value;
>>>> -	batch[++i] = MI_BATCH_BUFFER_END;
>>>> -	gem_write(fd, obj[BATCH].handle, 0, batch, sizeof(batch));
>>>> -	gem_execbuf(fd, &execbuf);
>>>> -	gem_close(fd, obj[BATCH].handle);
>>>> -}
>>>> -
>>>>    static void check_alive(void)
>>>>    {
>>>>    	const struct intel_execution_engine2 *engine;
>>>> @@ -138,7 +81,7 @@ static void check_alive(void)
>>>>    			continue;
>>>>    		/* +OFFSET_ALIVE to ensure engine zero doesn't get a false negative */
>>>> -		store(fd, engine, -1, scratch, i + OFFSET_ALIVE);
>>>> +		igt_store_word(fd, ahnd, ctx, engine, -1, scratch, i + OFFSET_ALIVE, i + OFFSET_ALIVE);
>>>>    		i++;
>>>>    	}
>>>> -- 
>>>> 2.25.1
>>>>

Re: [igt-dev] [PATCH i-g-t 08/11] lib/store: Refactor common store code into helper function

[John Harrison]

On 12/20/2021 10:13, Zbigniew Kempczyński wrote:
> On Thu, Dec 16, 2021 at 02:40:21PM -0800, John Harrison wrote:
>> On 12/15/2021 23:46, Zbigniew Kempczyński wrote:
>>> On Mon, Dec 13, 2021 at 03:29:11PM -0800, John.C.Harrison@Intel.com wrote:
>>>> From: John Harrison <John.C.Harrison@Intel.com>
>>>>
>>>> A lot of tests use almost identical code for creating a batch buffer
>>>> which does a single write to memory. This patch collects two such
>>>> instances into a common helper function. Unfortunately, the other
>>>> instances are all subtly different enough to make it not so trivial to
>>>> try to use the helper. It could be done but it is unclear if it is
>>>> worth the effort at this point. This patch proves the concept, if
>>>> people like it enough then it can be extended.
>>>>
>>>> Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
>>>> ---
>>>>    lib/igt_store.c             | 114 ++++++++++++++++++++++++++++++++++++
>>>>    lib/igt_store.h             |  30 ++++++++++
>>>>    lib/meson.build             |   1 +
>>>>    tests/i915/gem_exec_fence.c |  77 ++----------------------
>>>>    tests/i915/i915_hangman.c   |  61 +------------------
>>>>    5 files changed, 152 insertions(+), 131 deletions(-)
>>>>    create mode 100644 lib/igt_store.c
>>>>    create mode 100644 lib/igt_store.h
>>>>
>>>> diff --git a/lib/igt_store.c b/lib/igt_store.c
>>>> new file mode 100644
>>>> index 000000000..6d9869b58
>>>> --- /dev/null
>>>> +++ b/lib/igt_store.c
>>>> @@ -0,0 +1,114 @@
>>>> +/*
>>>> + * Copyright © 2020 Intel Corporation
>>>> + *
>>>> + * Permission is hereby granted, free of charge, to any person obtaining a
>>>> + * copy of this software and associated documentation files (the "Software"),
>>>> + * to deal in the Software without restriction, including without limitation
>>>> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>>>> + * and/or sell copies of the Software, and to permit persons to whom the
>>>> + * Software is furnished to do so, subject to the following conditions:
>>>> + *
>>>> + * The above copyright notice and this permission notice (including the next
>>>> + * paragraph) shall be included in all copies or substantial portions of the
>>>> + * Software.
>>>> + *
>>>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>>>> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>>>> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>>>> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
>>>> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>>>> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
>>>> + * IN THE SOFTWARE.
>>>> + *
>>>> + */
>>> Use SPDX. I like idea of extracting this.
>>>
>>>> +
>>>> +#include "i915/gem_create.h"
>>>> +#include "igt_core.h"
>>>> +#include "drmtest.h"
>>>> +#include "igt_store.h"
>>>> +#include "intel_chipset.h"
>>>> +#include "intel_reg.h"
>>>> +#include "ioctl_wrappers.h"
>>>> +#include "lib/intel_allocator.h"
>>>> +
>>>> +/**
>>>> + * SECTION:igt_store_word
>>>> + * @short_description: Library for writing a value to memory
>>>> + * @title: StoreWord
>>>> + * @include: igt.h
>>>> + *
>>>> + * A lot of igt testcases need some mechanism for writing a value to memory
>>>> + * as a test that a batch buffer has executed.
>>>> + *
>>>> + * NB: Requires master for STORE_DWORD on gen4/5.
>>>> + */
>>>> +void igt_store_word(int fd, uint64_t ahnd, const intel_ctx_t *ctx,
>>>> +		    const struct intel_execution_engine2 *e,
>>>> +		    int fence, uint32_t target_handle,
>>>> +		    uint64_t target_offset, uint32_t target_value)
>>>> +{
>>>> +	const int SCRATCH = 0;
>>>> +	const int BATCH = 1;
>>>> +	const unsigned int gen = intel_gen(intel_get_drm_devid(fd));
>>>> +	struct drm_i915_gem_exec_object2 obj[2];
>>>> +	struct drm_i915_gem_relocation_entry reloc;
>>>> +	struct drm_i915_gem_execbuffer2 execbuf;
>>>> +	uint32_t batch[16], delta;
>>>> +	uint64_t bb_offset;
>>>> +	int i;
>>>> +
>>>> +	memset(&execbuf, 0, sizeof(execbuf));
>>>> +	execbuf.buffers_ptr = to_user_pointer(obj);
>>>> +	execbuf.buffer_count = ARRAY_SIZE(obj);
>>>> +	execbuf.flags = e->flags;
>>>> +	execbuf.rsvd1 = ctx->id;
>>>> +	if (fence != -1) {
>>>> +		execbuf.flags |= I915_EXEC_FENCE_IN;
>>>> +		execbuf.rsvd2 = fence;
>>>> +	}
>>>> +	if (gen < 6)
>>>> +		execbuf.flags |= I915_EXEC_SECURE;
>>>> +
>>>> +	memset(obj, 0, sizeof(obj));
>>>> +	obj[SCRATCH].handle = target_handle;
>>>> +
>>>> +	obj[BATCH].handle = gem_create(fd, 4096);
>>>> +	obj[BATCH].relocs_ptr = to_user_pointer(&reloc);
>>>> +	obj[BATCH].relocation_count = !ahnd ? 1 : 0;
>>>> +	bb_offset = get_offset(ahnd, obj[BATCH].handle, 4096, 0);
>>>> +	memset(&reloc, 0, sizeof(reloc));
>>>> +
>>>> +	i = 0;
>>>> +	delta = sizeof(uint32_t) * target_value;	/* why value not offset??? */
>>> I guess I know why there's problem here. target_offset is address in vm
>>> passed by the caller. This is regarding to some limitations of allocator
>>> infrastructure - for "reloc" pseudo-allocator you would get new offset
>>> (internally it returns offset and then add size for new "allocation").
>>> With this we don't need to wait for rebind offset for new execbuf.
>>> With "simple" allocator put will release offset so new allocation will
>>> reuse same offset. Ashutosh proposed how to join both functionalities
>>> (stepping as with reloc, stateful like in simple) but I got no time to
>>> code this.
>>>
>>> Regarding issue here, target_offset passed from the caller is to avoid
>>> rebind if get_offset() would be called for "reloc" allocator.
>>> So there's not real value offset within bo. I would add separate
>>> value_offset (shift) to allow caller to put place where it wants to
>>> write the value.
>> If you understand what is going on here and how to improve it then feel free
>> to either send me an updated version or post an extra patch after this is
>> merged. I don't get how any of the new reloc (or anti-reloc?) code is meant
>> to work. These patches were all written as part of the GuC support a long
>> time ago - before there was any such thing as an AHND (what does that stand
>> for?) or intel_ctx_t. All I'm doing in this patch is moving the existing
>> code to a helper and trying to make it generic enough to be used by another
>> test. And right now, the two tests are passing on both GuC and execlist
>> platforms for me. So the code can't be all that broken.
> I've added some missing parts to your code:
>
> https://patchwork.freedesktop.org/series/98242/
>
> If you think something is missing please add or fix.
>
> Previously value was used both for value and offset within bo
> used for example in gem_exec_fence@basic-await. I think adding
> separate arg for offset for value within bo makes this code
> more universal.
I don't follow. The purpose of the offset is the to say where the value 
is written within the buffer. As in 'target_offset' is 'offset into 
target buffer to write value'. You have added a 'value_offset' which 
surely would be defined as 'the offset at which to write the value in 
the target buffer'. I.e. exactly the same thing. What is the intention 
behind having two separate offset variables?

John.


>
> NB: ahnd is short version of allocator_handle
>
> --
> Zbigniew
>
>>
>>>
>>>> +	if (!ahnd) {
>>>> +		reloc.target_handle = obj[SCRATCH].handle;
>>>> +		reloc.presumed_offset = -1;
>>>> +		reloc.offset = sizeof(uint32_t) * (i + 1);
>>>> +		reloc.delta = delta;
>>>> +		reloc.read_domains = I915_GEM_DOMAIN_INSTRUCTION;
>>>> +		reloc.write_domain = I915_GEM_DOMAIN_INSTRUCTION;
>>>> +	} else {
>>>> +		obj[SCRATCH].offset = target_offset;
>>>> +		obj[SCRATCH].flags |= EXEC_OBJECT_PINNED | EXEC_OBJECT_WRITE;
>>>> +		obj[BATCH].offset = bb_offset;
>>>> +		obj[BATCH].flags |= EXEC_OBJECT_PINNED;
>>>> +	}
>>>> +	batch[i] = MI_STORE_DWORD_IMM | (gen < 6 ? 1 << 22 : 0);
>>>> +	if (gen >= 8) {
>>>> +		batch[++i] = target_offset + delta;
>>>> +		batch[++i] = target_offset >> 32;
>>> Probably I've added this in previous code, for being safe I would
>>> add (target_offset + delta) >> 32 for avoid risk passing invalid higher
>>> offset part on 32b boundary.
>> Pretty sure we don't have any addresses larger than 32 bits yet, but yes,
>> delta should be added in.
>>
>> Thanks,
>> John.
>>
>>>> +	} else if (gen >= 4) {
>>>> +		batch[++i] = 0;
>>>> +		batch[++i] = delta;
>>>> +		reloc.offset += sizeof(uint32_t);
>>>> +	} else {
>>>> +		batch[i]--;
>>>> +		batch[++i] = delta;
>>>> +	}
>>>> +	batch[++i] = target_value;
>>>> +	batch[++i] = MI_BATCH_BUFFER_END;
>>>> +	gem_write(fd, obj[BATCH].handle, 0, batch, sizeof(batch));
>>>> +	gem_execbuf(fd, &execbuf);
>>>> +	gem_close(fd, obj[BATCH].handle);
>>>> +	put_offset(ahnd, obj[BATCH].handle);
>>>> +}
>>>> diff --git a/lib/igt_store.h b/lib/igt_store.h
>>>> new file mode 100644
>>>> index 000000000..4d5979e07
>>>> --- /dev/null
>>>> +++ b/lib/igt_store.h
>>>> @@ -0,0 +1,30 @@
>>>> +/*
>>>> + * Copyright © 2020 Intel Corporation
>>>> + *
>>>> + * Permission is hereby granted, free of charge, to any person obtaining a
>>>> + * copy of this software and associated documentation files (the "Software"),
>>>> + * to deal in the Software without restriction, including without limitation
>>>> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>>>> + * and/or sell copies of the Software, and to permit persons to whom the
>>>> + * Software is furnished to do so, subject to the following conditions:
>>>> + *
>>>> + * The above copyright notice and this permission notice (including the next
>>>> + * paragraph) shall be included in all copies or substantial portions of the
>>>> + * Software.
>>>> + *
>>>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>>>> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>>>> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>>>> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
>>>> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>>>> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
>>>> + * IN THE SOFTWARE.
>>>> + *
>>>> + */
>>> Use SPDX and 2021.
>>>
>>> --
>>> Zbigniew
>>>
>>>> +
>>>> +#include "igt_gt.h"
>>>> +
>>>> +void igt_store_word(int fd, uint64_t ahnd, const intel_ctx_t *ctx,
>>>> +		    const struct intel_execution_engine2 *e,
>>>> +		    int fence, uint32_t target_handle,
>>>> +		    uint64_t target_offset, uint32_t target_value);
>>>> diff --git a/lib/meson.build b/lib/meson.build
>>>> index b9568a71b..3e43316d1 100644
>>>> --- a/lib/meson.build
>>>> +++ b/lib/meson.build
>>>> @@ -72,6 +72,7 @@ lib_sources = [
>>>>    	'igt_map.c',
>>>>    	'igt_pm.c',
>>>>    	'igt_dummyload.c',
>>>> +	'igt_store.c',
>>>>    	'uwildmat/uwildmat.c',
>>>>    	'igt_kmod.c',
>>>>    	'igt_panfrost.c',
>>>> diff --git a/tests/i915/gem_exec_fence.c b/tests/i915/gem_exec_fence.c
>>>> index 9a6336ce9..c4091a454 100644
>>>> --- a/tests/i915/gem_exec_fence.c
>>>> +++ b/tests/i915/gem_exec_fence.c
>>>> @@ -28,6 +28,7 @@
>>>>    #include "i915/gem.h"
>>>>    #include "i915/gem_create.h"
>>>>    #include "igt.h"
>>>> +#include "igt_store.h"
>>>>    #include "igt_syncobj.h"
>>>>    #include "igt_sysfs.h"
>>>>    #include "igt_vgem.h"
>>>> @@ -57,74 +58,6 @@ struct sync_merge_data {
>>>>    #define   MI_SEMAPHORE_SAD_EQ_SDD       (4 << 12)
>>>>    #define   MI_SEMAPHORE_SAD_NEQ_SDD      (5 << 12)
>>>> -static void store(int fd, uint64_t ahnd, const intel_ctx_t *ctx,
>>>> -		  const struct intel_execution_engine2 *e,
>>>> -		  int fence, uint32_t target, uint64_t target_offset,
>>>> -		  unsigned offset_value)
>>>> -{
>>>> -	const int SCRATCH = 0;
>>>> -	const int BATCH = 1;
>>>> -	const unsigned int gen = intel_gen(intel_get_drm_devid(fd));
>>>> -	struct drm_i915_gem_exec_object2 obj[2];
>>>> -	struct drm_i915_gem_relocation_entry reloc;
>>>> -	struct drm_i915_gem_execbuffer2 execbuf;
>>>> -	uint32_t batch[16], delta;
>>>> -	uint64_t bb_offset;
>>>> -	int i;
>>>> -
>>>> -	memset(&execbuf, 0, sizeof(execbuf));
>>>> -	execbuf.buffers_ptr = to_user_pointer(obj);
>>>> -	execbuf.buffer_count = 2;
>>>> -	execbuf.flags = e->flags | I915_EXEC_FENCE_IN;
>>>> -	execbuf.rsvd1 = ctx->id;
>>>> -	execbuf.rsvd2 = fence;
>>>> -	if (gen < 6)
>>>> -		execbuf.flags |= I915_EXEC_SECURE;
>>>> -
>>>> -	memset(obj, 0, sizeof(obj));
>>>> -	obj[SCRATCH].handle = target;
>>>> -
>>>> -	obj[BATCH].handle = gem_create(fd, 4096);
>>>> -	obj[BATCH].relocs_ptr = to_user_pointer(&reloc);
>>>> -	obj[BATCH].relocation_count = !ahnd ? 1 : 0;
>>>> -	bb_offset = get_offset(ahnd, obj[BATCH].handle, 4096, 0);
>>>> -	memset(&reloc, 0, sizeof(reloc));
>>>> -
>>>> -	i = 0;
>>>> -	delta = sizeof(uint32_t) * offset_value;
>>>> -	if (!ahnd) {
>>>> -		reloc.target_handle = obj[SCRATCH].handle;
>>>> -		reloc.presumed_offset = -1;
>>>> -		reloc.offset = sizeof(uint32_t) * (i + 1);
>>>> -		reloc.delta = delta;
>>>> -		reloc.read_domains = I915_GEM_DOMAIN_INSTRUCTION;
>>>> -		reloc.write_domain = I915_GEM_DOMAIN_INSTRUCTION;
>>>> -	} else {
>>>> -		obj[SCRATCH].offset = target_offset;
>>>> -		obj[SCRATCH].flags |= EXEC_OBJECT_PINNED | EXEC_OBJECT_WRITE;
>>>> -		obj[BATCH].offset = bb_offset;
>>>> -		obj[BATCH].flags |= EXEC_OBJECT_PINNED;
>>>> -	}
>>>> -	batch[i] = MI_STORE_DWORD_IMM | (gen < 6 ? 1 << 22 : 0);
>>>> -	if (gen >= 8) {
>>>> -		batch[++i] = target_offset + delta;
>>>> -		batch[++i] = target_offset >> 32;
>>>> -	} else if (gen >= 4) {
>>>> -		batch[++i] = 0;
>>>> -		batch[++i] = delta;
>>>> -		reloc.offset += sizeof(uint32_t);
>>>> -	} else {
>>>> -		batch[i]--;
>>>> -		batch[++i] = delta;
>>>> -	}
>>>> -	batch[++i] = offset_value;
>>>> -	batch[++i] = MI_BATCH_BUFFER_END;
>>>> -	gem_write(fd, obj[BATCH].handle, 0, batch, sizeof(batch));
>>>> -	gem_execbuf(fd, &execbuf);
>>>> -	gem_close(fd, obj[BATCH].handle);
>>>> -	put_offset(ahnd, obj[BATCH].handle);
>>>> -}
>>>> -
>>>>    static bool fence_busy(int fence)
>>>>    {
>>>>    	return poll(&(struct pollfd){fence, POLLIN}, 1, 0) == 0;
>>>> @@ -400,13 +333,13 @@ static void test_fence_await(int fd, const intel_ctx_t *ctx,
>>>>    			continue;
>>>>    		if (flags & NONBLOCK) {
>>>> -			store(fd, ahnd, ctx, e2, spin->out_fence,
>>>> -			      scratch, scratch_offset, i);
>>>> +			igt_store_word(fd, ahnd, ctx, e2, spin->out_fence,
>>>> +				       scratch, scratch_offset, i);
>>>>    		} else {
>>>>    			igt_fork(child, 1) {
>>>>    				ahnd = get_reloc_ahnd(fd, ctx->id);
>>>> -				store(fd, ahnd, ctx, e2, spin->out_fence,
>>>> -				      scratch, scratch_offset, i);
>>>> +				igt_store_word(fd, ahnd, ctx, e2, spin->out_fence,
>>>> +					       scratch, scratch_offset, i);
>>>>    				put_ahnd(ahnd);
>>>>    			}
>>>>    		}
>>>> diff --git a/tests/i915/i915_hangman.c b/tests/i915/i915_hangman.c
>>>> index 20653b479..4cb9b8b85 100644
>>>> --- a/tests/i915/i915_hangman.c
>>>> +++ b/tests/i915/i915_hangman.c
>>>> @@ -36,6 +36,7 @@
>>>>    #include "i915/gem.h"
>>>>    #include "i915/gem_create.h"
>>>>    #include "igt.h"
>>>> +#include "igt_store.h"
>>>>    #include "igt_sysfs.h"
>>>>    #include "igt_debugfs.h"
>>>>    #include "sw_sync.h"
>>>> @@ -51,64 +52,6 @@ static int sysfs = -1;
>>>>    IGT_TEST_DESCRIPTION("Tests for hang detection and recovery");
>>>> -/* Requires master for STORE_DWORD on gen4/5 */
>>>> -static void store(int fd, const struct intel_execution_engine2 *e,
>>>> -		  int fence, uint32_t target, unsigned offset_value)
>>>> -{
>>>> -	const int SCRATCH = 0;
>>>> -	const int BATCH = 1;
>>>> -	const int gen = intel_gen(intel_get_drm_devid(fd));
>>>> -	struct drm_i915_gem_exec_object2 obj[2];
>>>> -	struct drm_i915_gem_relocation_entry reloc;
>>>> -	struct drm_i915_gem_execbuffer2 execbuf;
>>>> -	uint32_t batch[16];
>>>> -	int i;
>>>> -
>>>> -	memset(&execbuf, 0, sizeof(execbuf));
>>>> -	execbuf.buffers_ptr = to_user_pointer(obj);
>>>> -	execbuf.buffer_count = ARRAY_SIZE(obj);
>>>> -	execbuf.flags = e->flags;
>>>> -	if (fence != -1) {
>>>> -		execbuf.flags |= I915_EXEC_FENCE_IN;
>>>> -		execbuf.rsvd2 = fence;
>>>> -	}
>>>> -	if (gen < 6)
>>>> -		execbuf.flags |= I915_EXEC_SECURE;
>>>> -
>>>> -	memset(obj, 0, sizeof(obj));
>>>> -	obj[SCRATCH].handle = target;
>>>> -
>>>> -	obj[BATCH].handle = gem_create(fd, 4096);
>>>> -	obj[BATCH].relocs_ptr = to_user_pointer(&reloc);
>>>> -	obj[BATCH].relocation_count = 1;
>>>> -	memset(&reloc, 0, sizeof(reloc));
>>>> -
>>>> -	i = 0;
>>>> -	reloc.target_handle = obj[SCRATCH].handle;
>>>> -	reloc.presumed_offset = -1;
>>>> -	reloc.offset = sizeof(uint32_t) * (i + 1);
>>>> -	reloc.delta = sizeof(uint32_t) * offset_value;
>>>> -	reloc.read_domains = I915_GEM_DOMAIN_INSTRUCTION;
>>>> -	reloc.write_domain = I915_GEM_DOMAIN_INSTRUCTION;
>>>> -	batch[i] = MI_STORE_DWORD_IMM | (gen < 6 ? 1 << 22 : 0);
>>>> -	if (gen >= 8) {
>>>> -		batch[++i] = reloc.delta;
>>>> -		batch[++i] = 0;
>>>> -	} else if (gen >= 4) {
>>>> -		batch[++i] = 0;
>>>> -		batch[++i] = reloc.delta;
>>>> -		reloc.offset += sizeof(uint32_t);
>>>> -	} else {
>>>> -		batch[i]--;
>>>> -		batch[++i] = reloc.delta;
>>>> -	}
>>>> -	batch[++i] = offset_value;
>>>> -	batch[++i] = MI_BATCH_BUFFER_END;
>>>> -	gem_write(fd, obj[BATCH].handle, 0, batch, sizeof(batch));
>>>> -	gem_execbuf(fd, &execbuf);
>>>> -	gem_close(fd, obj[BATCH].handle);
>>>> -}
>>>> -
>>>>    static void check_alive(void)
>>>>    {
>>>>    	const struct intel_execution_engine2 *engine;
>>>> @@ -138,7 +81,7 @@ static void check_alive(void)
>>>>    			continue;
>>>>    		/* +OFFSET_ALIVE to ensure engine zero doesn't get a false negative */
>>>> -		store(fd, engine, -1, scratch, i + OFFSET_ALIVE);
>>>> +		igt_store_word(fd, ahnd, ctx, engine, -1, scratch, i + OFFSET_ALIVE, i + OFFSET_ALIVE);
>>>>    		i++;
>>>>    	}
>>>> -- 
>>>> 2.25.1
>>>>

Re: [Intel-gfx] [igt-dev] [PATCH i-g-t 08/11] lib/store: Refactor common store code into helper function

[Zbigniew Kempczyński]

On Tue, Dec 21, 2021 at 06:22:22PM -0800, John Harrison wrote:
> On 12/20/2021 10:13, Zbigniew Kempczyński wrote:
> > On Thu, Dec 16, 2021 at 02:40:21PM -0800, John Harrison wrote:
> > > On 12/15/2021 23:46, Zbigniew Kempczyński wrote:
> > > > On Mon, Dec 13, 2021 at 03:29:11PM -0800, John.C.Harrison@Intel.com wrote:
> > > > > From: John Harrison <John.C.Harrison@Intel.com>
> > > > > 
> > > > > A lot of tests use almost identical code for creating a batch buffer
> > > > > which does a single write to memory. This patch collects two such
> > > > > instances into a common helper function. Unfortunately, the other
> > > > > instances are all subtly different enough to make it not so trivial to
> > > > > try to use the helper. It could be done but it is unclear if it is
> > > > > worth the effort at this point. This patch proves the concept, if
> > > > > people like it enough then it can be extended.
> > > > > 
> > > > > Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
> > > > > ---
> > > > >    lib/igt_store.c             | 114 ++++++++++++++++++++++++++++++++++++
> > > > >    lib/igt_store.h             |  30 ++++++++++
> > > > >    lib/meson.build             |   1 +
> > > > >    tests/i915/gem_exec_fence.c |  77 ++----------------------
> > > > >    tests/i915/i915_hangman.c   |  61 +------------------
> > > > >    5 files changed, 152 insertions(+), 131 deletions(-)
> > > > >    create mode 100644 lib/igt_store.c
> > > > >    create mode 100644 lib/igt_store.h
> > > > > 
> > > > > diff --git a/lib/igt_store.c b/lib/igt_store.c
> > > > > new file mode 100644
> > > > > index 000000000..6d9869b58
> > > > > --- /dev/null
> > > > > +++ b/lib/igt_store.c
> > > > > @@ -0,0 +1,114 @@
> > > > > +/*
> > > > > + * Copyright © 2020 Intel Corporation
> > > > > + *
> > > > > + * Permission is hereby granted, free of charge, to any person obtaining a
> > > > > + * copy of this software and associated documentation files (the "Software"),
> > > > > + * to deal in the Software without restriction, including without limitation
> > > > > + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> > > > > + * and/or sell copies of the Software, and to permit persons to whom the
> > > > > + * Software is furnished to do so, subject to the following conditions:
> > > > > + *
> > > > > + * The above copyright notice and this permission notice (including the next
> > > > > + * paragraph) shall be included in all copies or substantial portions of the
> > > > > + * Software.
> > > > > + *
> > > > > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> > > > > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> > > > > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> > > > > + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> > > > > + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> > > > > + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
> > > > > + * IN THE SOFTWARE.
> > > > > + *
> > > > > + */
> > > > Use SPDX. I like idea of extracting this.
> > > > 
> > > > > +
> > > > > +#include "i915/gem_create.h"
> > > > > +#include "igt_core.h"
> > > > > +#include "drmtest.h"
> > > > > +#include "igt_store.h"
> > > > > +#include "intel_chipset.h"
> > > > > +#include "intel_reg.h"
> > > > > +#include "ioctl_wrappers.h"
> > > > > +#include "lib/intel_allocator.h"
> > > > > +
> > > > > +/**
> > > > > + * SECTION:igt_store_word
> > > > > + * @short_description: Library for writing a value to memory
> > > > > + * @title: StoreWord
> > > > > + * @include: igt.h
> > > > > + *
> > > > > + * A lot of igt testcases need some mechanism for writing a value to memory
> > > > > + * as a test that a batch buffer has executed.
> > > > > + *
> > > > > + * NB: Requires master for STORE_DWORD on gen4/5.
> > > > > + */
> > > > > +void igt_store_word(int fd, uint64_t ahnd, const intel_ctx_t *ctx,
> > > > > +		    const struct intel_execution_engine2 *e,
> > > > > +		    int fence, uint32_t target_handle,
> > > > > +		    uint64_t target_offset, uint32_t target_value)
> > > > > +{
> > > > > +	const int SCRATCH = 0;
> > > > > +	const int BATCH = 1;
> > > > > +	const unsigned int gen = intel_gen(intel_get_drm_devid(fd));
> > > > > +	struct drm_i915_gem_exec_object2 obj[2];
> > > > > +	struct drm_i915_gem_relocation_entry reloc;
> > > > > +	struct drm_i915_gem_execbuffer2 execbuf;
> > > > > +	uint32_t batch[16], delta;
> > > > > +	uint64_t bb_offset;
> > > > > +	int i;
> > > > > +
> > > > > +	memset(&execbuf, 0, sizeof(execbuf));
> > > > > +	execbuf.buffers_ptr = to_user_pointer(obj);
> > > > > +	execbuf.buffer_count = ARRAY_SIZE(obj);
> > > > > +	execbuf.flags = e->flags;
> > > > > +	execbuf.rsvd1 = ctx->id;
> > > > > +	if (fence != -1) {
> > > > > +		execbuf.flags |= I915_EXEC_FENCE_IN;
> > > > > +		execbuf.rsvd2 = fence;
> > > > > +	}
> > > > > +	if (gen < 6)
> > > > > +		execbuf.flags |= I915_EXEC_SECURE;
> > > > > +
> > > > > +	memset(obj, 0, sizeof(obj));
> > > > > +	obj[SCRATCH].handle = target_handle;
> > > > > +
> > > > > +	obj[BATCH].handle = gem_create(fd, 4096);
> > > > > +	obj[BATCH].relocs_ptr = to_user_pointer(&reloc);
> > > > > +	obj[BATCH].relocation_count = !ahnd ? 1 : 0;
> > > > > +	bb_offset = get_offset(ahnd, obj[BATCH].handle, 4096, 0);
> > > > > +	memset(&reloc, 0, sizeof(reloc));
> > > > > +
> > > > > +	i = 0;
> > > > > +	delta = sizeof(uint32_t) * target_value;	/* why value not offset??? */
> > > > I guess I know why there's problem here. target_offset is address in vm
> > > > passed by the caller. This is regarding to some limitations of allocator
> > > > infrastructure - for "reloc" pseudo-allocator you would get new offset
> > > > (internally it returns offset and then add size for new "allocation").
> > > > With this we don't need to wait for rebind offset for new execbuf.
> > > > With "simple" allocator put will release offset so new allocation will
> > > > reuse same offset. Ashutosh proposed how to join both functionalities
> > > > (stepping as with reloc, stateful like in simple) but I got no time to
> > > > code this.
> > > > 
> > > > Regarding issue here, target_offset passed from the caller is to avoid
> > > > rebind if get_offset() would be called for "reloc" allocator.
> > > > So there's not real value offset within bo. I would add separate
> > > > value_offset (shift) to allow caller to put place where it wants to
> > > > write the value.
> > > If you understand what is going on here and how to improve it then feel free
> > > to either send me an updated version or post an extra patch after this is
> > > merged. I don't get how any of the new reloc (or anti-reloc?) code is meant
> > > to work. These patches were all written as part of the GuC support a long
> > > time ago - before there was any such thing as an AHND (what does that stand
> > > for?) or intel_ctx_t. All I'm doing in this patch is moving the existing
> > > code to a helper and trying to make it generic enough to be used by another
> > > test. And right now, the two tests are passing on both GuC and execlist
> > > platforms for me. So the code can't be all that broken.
> > I've added some missing parts to your code:
> > 
> > https://patchwork.freedesktop.org/series/98242/
> > 
> > If you think something is missing please add or fix.
> > 
> > Previously value was used both for value and offset within bo
> > used for example in gem_exec_fence@basic-await. I think adding
> > separate arg for offset for value within bo makes this code
> > more universal.
> I don't follow. The purpose of the offset is the to say where the value is
> written within the buffer. As in 'target_offset' is 'offset into target
> buffer to write value'. You have added a 'value_offset' which surely would
> be defined as 'the offset at which to write the value in the target buffer'.
> I.e. exactly the same thing. What is the intention behind having two
> separate offset variables?

No, there're not the same thing.

 target_offset
 ──────────────►┌────────────┐
 0x201000       │ size = 8K  │
                │            │
value_offset    │            │
(relative to    │            │
target_offset)  │            │
───────────────►│            │
0x1100          │            │
                │            │
                │            │
                │            │
                │            │
                │            │
                └────────────┘

Target_offset is vma start address where object will be bind.
value_offset is delta from that vma.

In execobj.offset you need to put 0x201000, but in bb final offset 
is calculated as target_offset + value_offset.

--
Zbigniew

> 
> John.
> 
> 
> > 
> > NB: ahnd is short version of allocator_handle
> > 
> > --
> > Zbigniew
> > 
> > > 
> > > > 
> > > > > +	if (!ahnd) {
> > > > > +		reloc.target_handle = obj[SCRATCH].handle;
> > > > > +		reloc.presumed_offset = -1;
> > > > > +		reloc.offset = sizeof(uint32_t) * (i + 1);
> > > > > +		reloc.delta = delta;
> > > > > +		reloc.read_domains = I915_GEM_DOMAIN_INSTRUCTION;
> > > > > +		reloc.write_domain = I915_GEM_DOMAIN_INSTRUCTION;
> > > > > +	} else {
> > > > > +		obj[SCRATCH].offset = target_offset;
> > > > > +		obj[SCRATCH].flags |= EXEC_OBJECT_PINNED | EXEC_OBJECT_WRITE;
> > > > > +		obj[BATCH].offset = bb_offset;
> > > > > +		obj[BATCH].flags |= EXEC_OBJECT_PINNED;
> > > > > +	}
> > > > > +	batch[i] = MI_STORE_DWORD_IMM | (gen < 6 ? 1 << 22 : 0);
> > > > > +	if (gen >= 8) {
> > > > > +		batch[++i] = target_offset + delta;
> > > > > +		batch[++i] = target_offset >> 32;
> > > > Probably I've added this in previous code, for being safe I would
> > > > add (target_offset + delta) >> 32 for avoid risk passing invalid higher
> > > > offset part on 32b boundary.
> > > Pretty sure we don't have any addresses larger than 32 bits yet, but yes,
> > > delta should be added in.
> > > 
> > > Thanks,
> > > John.
> > > 
> > > > > +	} else if (gen >= 4) {
> > > > > +		batch[++i] = 0;
> > > > > +		batch[++i] = delta;
> > > > > +		reloc.offset += sizeof(uint32_t);
> > > > > +	} else {
> > > > > +		batch[i]--;
> > > > > +		batch[++i] = delta;
> > > > > +	}
> > > > > +	batch[++i] = target_value;
> > > > > +	batch[++i] = MI_BATCH_BUFFER_END;
> > > > > +	gem_write(fd, obj[BATCH].handle, 0, batch, sizeof(batch));
> > > > > +	gem_execbuf(fd, &execbuf);
> > > > > +	gem_close(fd, obj[BATCH].handle);
> > > > > +	put_offset(ahnd, obj[BATCH].handle);
> > > > > +}
> > > > > diff --git a/lib/igt_store.h b/lib/igt_store.h
> > > > > new file mode 100644
> > > > > index 000000000..4d5979e07
> > > > > --- /dev/null
> > > > > +++ b/lib/igt_store.h
> > > > > @@ -0,0 +1,30 @@
> > > > > +/*
> > > > > + * Copyright © 2020 Intel Corporation
> > > > > + *
> > > > > + * Permission is hereby granted, free of charge, to any person obtaining a
> > > > > + * copy of this software and associated documentation files (the "Software"),
> > > > > + * to deal in the Software without restriction, including without limitation
> > > > > + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> > > > > + * and/or sell copies of the Software, and to permit persons to whom the
> > > > > + * Software is furnished to do so, subject to the following conditions:
> > > > > + *
> > > > > + * The above copyright notice and this permission notice (including the next
> > > > > + * paragraph) shall be included in all copies or substantial portions of the
> > > > > + * Software.
> > > > > + *
> > > > > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> > > > > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> > > > > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> > > > > + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> > > > > + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> > > > > + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
> > > > > + * IN THE SOFTWARE.
> > > > > + *
> > > > > + */
> > > > Use SPDX and 2021.
> > > > 
> > > > --
> > > > Zbigniew
> > > > 
> > > > > +
> > > > > +#include "igt_gt.h"
> > > > > +
> > > > > +void igt_store_word(int fd, uint64_t ahnd, const intel_ctx_t *ctx,
> > > > > +		    const struct intel_execution_engine2 *e,
> > > > > +		    int fence, uint32_t target_handle,
> > > > > +		    uint64_t target_offset, uint32_t target_value);
> > > > > diff --git a/lib/meson.build b/lib/meson.build
> > > > > index b9568a71b..3e43316d1 100644
> > > > > --- a/lib/meson.build
> > > > > +++ b/lib/meson.build
> > > > > @@ -72,6 +72,7 @@ lib_sources = [
> > > > >    	'igt_map.c',
> > > > >    	'igt_pm.c',
> > > > >    	'igt_dummyload.c',
> > > > > +	'igt_store.c',
> > > > >    	'uwildmat/uwildmat.c',
> > > > >    	'igt_kmod.c',
> > > > >    	'igt_panfrost.c',
> > > > > diff --git a/tests/i915/gem_exec_fence.c b/tests/i915/gem_exec_fence.c
> > > > > index 9a6336ce9..c4091a454 100644
> > > > > --- a/tests/i915/gem_exec_fence.c
> > > > > +++ b/tests/i915/gem_exec_fence.c
> > > > > @@ -28,6 +28,7 @@
> > > > >    #include "i915/gem.h"
> > > > >    #include "i915/gem_create.h"
> > > > >    #include "igt.h"
> > > > > +#include "igt_store.h"
> > > > >    #include "igt_syncobj.h"
> > > > >    #include "igt_sysfs.h"
> > > > >    #include "igt_vgem.h"
> > > > > @@ -57,74 +58,6 @@ struct sync_merge_data {
> > > > >    #define   MI_SEMAPHORE_SAD_EQ_SDD       (4 << 12)
> > > > >    #define   MI_SEMAPHORE_SAD_NEQ_SDD      (5 << 12)
> > > > > -static void store(int fd, uint64_t ahnd, const intel_ctx_t *ctx,
> > > > > -		  const struct intel_execution_engine2 *e,
> > > > > -		  int fence, uint32_t target, uint64_t target_offset,
> > > > > -		  unsigned offset_value)
> > > > > -{
> > > > > -	const int SCRATCH = 0;
> > > > > -	const int BATCH = 1;
> > > > > -	const unsigned int gen = intel_gen(intel_get_drm_devid(fd));
> > > > > -	struct drm_i915_gem_exec_object2 obj[2];
> > > > > -	struct drm_i915_gem_relocation_entry reloc;
> > > > > -	struct drm_i915_gem_execbuffer2 execbuf;
> > > > > -	uint32_t batch[16], delta;
> > > > > -	uint64_t bb_offset;
> > > > > -	int i;
> > > > > -
> > > > > -	memset(&execbuf, 0, sizeof(execbuf));
> > > > > -	execbuf.buffers_ptr = to_user_pointer(obj);
> > > > > -	execbuf.buffer_count = 2;
> > > > > -	execbuf.flags = e->flags | I915_EXEC_FENCE_IN;
> > > > > -	execbuf.rsvd1 = ctx->id;
> > > > > -	execbuf.rsvd2 = fence;
> > > > > -	if (gen < 6)
> > > > > -		execbuf.flags |= I915_EXEC_SECURE;
> > > > > -
> > > > > -	memset(obj, 0, sizeof(obj));
> > > > > -	obj[SCRATCH].handle = target;
> > > > > -
> > > > > -	obj[BATCH].handle = gem_create(fd, 4096);
> > > > > -	obj[BATCH].relocs_ptr = to_user_pointer(&reloc);
> > > > > -	obj[BATCH].relocation_count = !ahnd ? 1 : 0;
> > > > > -	bb_offset = get_offset(ahnd, obj[BATCH].handle, 4096, 0);
> > > > > -	memset(&reloc, 0, sizeof(reloc));
> > > > > -
> > > > > -	i = 0;
> > > > > -	delta = sizeof(uint32_t) * offset_value;
> > > > > -	if (!ahnd) {
> > > > > -		reloc.target_handle = obj[SCRATCH].handle;
> > > > > -		reloc.presumed_offset = -1;
> > > > > -		reloc.offset = sizeof(uint32_t) * (i + 1);
> > > > > -		reloc.delta = delta;
> > > > > -		reloc.read_domains = I915_GEM_DOMAIN_INSTRUCTION;
> > > > > -		reloc.write_domain = I915_GEM_DOMAIN_INSTRUCTION;
> > > > > -	} else {
> > > > > -		obj[SCRATCH].offset = target_offset;
> > > > > -		obj[SCRATCH].flags |= EXEC_OBJECT_PINNED | EXEC_OBJECT_WRITE;
> > > > > -		obj[BATCH].offset = bb_offset;
> > > > > -		obj[BATCH].flags |= EXEC_OBJECT_PINNED;
> > > > > -	}
> > > > > -	batch[i] = MI_STORE_DWORD_IMM | (gen < 6 ? 1 << 22 : 0);
> > > > > -	if (gen >= 8) {
> > > > > -		batch[++i] = target_offset + delta;
> > > > > -		batch[++i] = target_offset >> 32;
> > > > > -	} else if (gen >= 4) {
> > > > > -		batch[++i] = 0;
> > > > > -		batch[++i] = delta;
> > > > > -		reloc.offset += sizeof(uint32_t);
> > > > > -	} else {
> > > > > -		batch[i]--;
> > > > > -		batch[++i] = delta;
> > > > > -	}
> > > > > -	batch[++i] = offset_value;
> > > > > -	batch[++i] = MI_BATCH_BUFFER_END;
> > > > > -	gem_write(fd, obj[BATCH].handle, 0, batch, sizeof(batch));
> > > > > -	gem_execbuf(fd, &execbuf);
> > > > > -	gem_close(fd, obj[BATCH].handle);
> > > > > -	put_offset(ahnd, obj[BATCH].handle);
> > > > > -}
> > > > > -
> > > > >    static bool fence_busy(int fence)
> > > > >    {
> > > > >    	return poll(&(struct pollfd){fence, POLLIN}, 1, 0) == 0;
> > > > > @@ -400,13 +333,13 @@ static void test_fence_await(int fd, const intel_ctx_t *ctx,
> > > > >    			continue;
> > > > >    		if (flags & NONBLOCK) {
> > > > > -			store(fd, ahnd, ctx, e2, spin->out_fence,
> > > > > -			      scratch, scratch_offset, i);
> > > > > +			igt_store_word(fd, ahnd, ctx, e2, spin->out_fence,
> > > > > +				       scratch, scratch_offset, i);
> > > > >    		} else {
> > > > >    			igt_fork(child, 1) {
> > > > >    				ahnd = get_reloc_ahnd(fd, ctx->id);
> > > > > -				store(fd, ahnd, ctx, e2, spin->out_fence,
> > > > > -				      scratch, scratch_offset, i);
> > > > > +				igt_store_word(fd, ahnd, ctx, e2, spin->out_fence,
> > > > > +					       scratch, scratch_offset, i);
> > > > >    				put_ahnd(ahnd);
> > > > >    			}
> > > > >    		}
> > > > > diff --git a/tests/i915/i915_hangman.c b/tests/i915/i915_hangman.c
> > > > > index 20653b479..4cb9b8b85 100644
> > > > > --- a/tests/i915/i915_hangman.c
> > > > > +++ b/tests/i915/i915_hangman.c
> > > > > @@ -36,6 +36,7 @@
> > > > >    #include "i915/gem.h"
> > > > >    #include "i915/gem_create.h"
> > > > >    #include "igt.h"
> > > > > +#include "igt_store.h"
> > > > >    #include "igt_sysfs.h"
> > > > >    #include "igt_debugfs.h"
> > > > >    #include "sw_sync.h"
> > > > > @@ -51,64 +52,6 @@ static int sysfs = -1;
> > > > >    IGT_TEST_DESCRIPTION("Tests for hang detection and recovery");
> > > > > -/* Requires master for STORE_DWORD on gen4/5 */
> > > > > -static void store(int fd, const struct intel_execution_engine2 *e,
> > > > > -		  int fence, uint32_t target, unsigned offset_value)
> > > > > -{
> > > > > -	const int SCRATCH = 0;
> > > > > -	const int BATCH = 1;
> > > > > -	const int gen = intel_gen(intel_get_drm_devid(fd));
> > > > > -	struct drm_i915_gem_exec_object2 obj[2];
> > > > > -	struct drm_i915_gem_relocation_entry reloc;
> > > > > -	struct drm_i915_gem_execbuffer2 execbuf;
> > > > > -	uint32_t batch[16];
> > > > > -	int i;
> > > > > -
> > > > > -	memset(&execbuf, 0, sizeof(execbuf));
> > > > > -	execbuf.buffers_ptr = to_user_pointer(obj);
> > > > > -	execbuf.buffer_count = ARRAY_SIZE(obj);
> > > > > -	execbuf.flags = e->flags;
> > > > > -	if (fence != -1) {
> > > > > -		execbuf.flags |= I915_EXEC_FENCE_IN;
> > > > > -		execbuf.rsvd2 = fence;
> > > > > -	}
> > > > > -	if (gen < 6)
> > > > > -		execbuf.flags |= I915_EXEC_SECURE;
> > > > > -
> > > > > -	memset(obj, 0, sizeof(obj));
> > > > > -	obj[SCRATCH].handle = target;
> > > > > -
> > > > > -	obj[BATCH].handle = gem_create(fd, 4096);
> > > > > -	obj[BATCH].relocs_ptr = to_user_pointer(&reloc);
> > > > > -	obj[BATCH].relocation_count = 1;
> > > > > -	memset(&reloc, 0, sizeof(reloc));
> > > > > -
> > > > > -	i = 0;
> > > > > -	reloc.target_handle = obj[SCRATCH].handle;
> > > > > -	reloc.presumed_offset = -1;
> > > > > -	reloc.offset = sizeof(uint32_t) * (i + 1);
> > > > > -	reloc.delta = sizeof(uint32_t) * offset_value;
> > > > > -	reloc.read_domains = I915_GEM_DOMAIN_INSTRUCTION;
> > > > > -	reloc.write_domain = I915_GEM_DOMAIN_INSTRUCTION;
> > > > > -	batch[i] = MI_STORE_DWORD_IMM | (gen < 6 ? 1 << 22 : 0);
> > > > > -	if (gen >= 8) {
> > > > > -		batch[++i] = reloc.delta;
> > > > > -		batch[++i] = 0;
> > > > > -	} else if (gen >= 4) {
> > > > > -		batch[++i] = 0;
> > > > > -		batch[++i] = reloc.delta;
> > > > > -		reloc.offset += sizeof(uint32_t);
> > > > > -	} else {
> > > > > -		batch[i]--;
> > > > > -		batch[++i] = reloc.delta;
> > > > > -	}
> > > > > -	batch[++i] = offset_value;
> > > > > -	batch[++i] = MI_BATCH_BUFFER_END;
> > > > > -	gem_write(fd, obj[BATCH].handle, 0, batch, sizeof(batch));
> > > > > -	gem_execbuf(fd, &execbuf);
> > > > > -	gem_close(fd, obj[BATCH].handle);
> > > > > -}
> > > > > -
> > > > >    static void check_alive(void)
> > > > >    {
> > > > >    	const struct intel_execution_engine2 *engine;
> > > > > @@ -138,7 +81,7 @@ static void check_alive(void)
> > > > >    			continue;
> > > > >    		/* +OFFSET_ALIVE to ensure engine zero doesn't get a false negative */
> > > > > -		store(fd, engine, -1, scratch, i + OFFSET_ALIVE);
> > > > > +		igt_store_word(fd, ahnd, ctx, engine, -1, scratch, i + OFFSET_ALIVE, i + OFFSET_ALIVE);
> > > > >    		i++;
> > > > >    	}
> > > > > -- 
> > > > > 2.25.1
> > > > > 
> 

Re: [igt-dev] [PATCH i-g-t 08/11] lib/store: Refactor common store code into helper function

[Zbigniew Kempczyński]

On Tue, Dec 21, 2021 at 06:22:22PM -0800, John Harrison wrote:
> On 12/20/2021 10:13, Zbigniew Kempczyński wrote:
> > On Thu, Dec 16, 2021 at 02:40:21PM -0800, John Harrison wrote:
> > > On 12/15/2021 23:46, Zbigniew Kempczyński wrote:
> > > > On Mon, Dec 13, 2021 at 03:29:11PM -0800, John.C.Harrison@Intel.com wrote:
> > > > > From: John Harrison <John.C.Harrison@Intel.com>
> > > > > 
> > > > > A lot of tests use almost identical code for creating a batch buffer
> > > > > which does a single write to memory. This patch collects two such
> > > > > instances into a common helper function. Unfortunately, the other
> > > > > instances are all subtly different enough to make it not so trivial to
> > > > > try to use the helper. It could be done but it is unclear if it is
> > > > > worth the effort at this point. This patch proves the concept, if
> > > > > people like it enough then it can be extended.
> > > > > 
> > > > > Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
> > > > > ---
> > > > >    lib/igt_store.c             | 114 ++++++++++++++++++++++++++++++++++++
> > > > >    lib/igt_store.h             |  30 ++++++++++
> > > > >    lib/meson.build             |   1 +
> > > > >    tests/i915/gem_exec_fence.c |  77 ++----------------------
> > > > >    tests/i915/i915_hangman.c   |  61 +------------------
> > > > >    5 files changed, 152 insertions(+), 131 deletions(-)
> > > > >    create mode 100644 lib/igt_store.c
> > > > >    create mode 100644 lib/igt_store.h
> > > > > 
> > > > > diff --git a/lib/igt_store.c b/lib/igt_store.c
> > > > > new file mode 100644
> > > > > index 000000000..6d9869b58
> > > > > --- /dev/null
> > > > > +++ b/lib/igt_store.c
> > > > > @@ -0,0 +1,114 @@
> > > > > +/*
> > > > > + * Copyright © 2020 Intel Corporation
> > > > > + *
> > > > > + * Permission is hereby granted, free of charge, to any person obtaining a
> > > > > + * copy of this software and associated documentation files (the "Software"),
> > > > > + * to deal in the Software without restriction, including without limitation
> > > > > + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> > > > > + * and/or sell copies of the Software, and to permit persons to whom the
> > > > > + * Software is furnished to do so, subject to the following conditions:
> > > > > + *
> > > > > + * The above copyright notice and this permission notice (including the next
> > > > > + * paragraph) shall be included in all copies or substantial portions of the
> > > > > + * Software.
> > > > > + *
> > > > > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> > > > > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> > > > > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> > > > > + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> > > > > + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> > > > > + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
> > > > > + * IN THE SOFTWARE.
> > > > > + *
> > > > > + */
> > > > Use SPDX. I like idea of extracting this.
> > > > 
> > > > > +
> > > > > +#include "i915/gem_create.h"
> > > > > +#include "igt_core.h"
> > > > > +#include "drmtest.h"
> > > > > +#include "igt_store.h"
> > > > > +#include "intel_chipset.h"
> > > > > +#include "intel_reg.h"
> > > > > +#include "ioctl_wrappers.h"
> > > > > +#include "lib/intel_allocator.h"
> > > > > +
> > > > > +/**
> > > > > + * SECTION:igt_store_word
> > > > > + * @short_description: Library for writing a value to memory
> > > > > + * @title: StoreWord
> > > > > + * @include: igt.h
> > > > > + *
> > > > > + * A lot of igt testcases need some mechanism for writing a value to memory
> > > > > + * as a test that a batch buffer has executed.
> > > > > + *
> > > > > + * NB: Requires master for STORE_DWORD on gen4/5.
> > > > > + */
> > > > > +void igt_store_word(int fd, uint64_t ahnd, const intel_ctx_t *ctx,
> > > > > +		    const struct intel_execution_engine2 *e,
> > > > > +		    int fence, uint32_t target_handle,
> > > > > +		    uint64_t target_offset, uint32_t target_value)
> > > > > +{
> > > > > +	const int SCRATCH = 0;
> > > > > +	const int BATCH = 1;
> > > > > +	const unsigned int gen = intel_gen(intel_get_drm_devid(fd));
> > > > > +	struct drm_i915_gem_exec_object2 obj[2];
> > > > > +	struct drm_i915_gem_relocation_entry reloc;
> > > > > +	struct drm_i915_gem_execbuffer2 execbuf;
> > > > > +	uint32_t batch[16], delta;
> > > > > +	uint64_t bb_offset;
> > > > > +	int i;
> > > > > +
> > > > > +	memset(&execbuf, 0, sizeof(execbuf));
> > > > > +	execbuf.buffers_ptr = to_user_pointer(obj);
> > > > > +	execbuf.buffer_count = ARRAY_SIZE(obj);
> > > > > +	execbuf.flags = e->flags;
> > > > > +	execbuf.rsvd1 = ctx->id;
> > > > > +	if (fence != -1) {
> > > > > +		execbuf.flags |= I915_EXEC_FENCE_IN;
> > > > > +		execbuf.rsvd2 = fence;
> > > > > +	}
> > > > > +	if (gen < 6)
> > > > > +		execbuf.flags |= I915_EXEC_SECURE;
> > > > > +
> > > > > +	memset(obj, 0, sizeof(obj));
> > > > > +	obj[SCRATCH].handle = target_handle;
> > > > > +
> > > > > +	obj[BATCH].handle = gem_create(fd, 4096);
> > > > > +	obj[BATCH].relocs_ptr = to_user_pointer(&reloc);
> > > > > +	obj[BATCH].relocation_count = !ahnd ? 1 : 0;
> > > > > +	bb_offset = get_offset(ahnd, obj[BATCH].handle, 4096, 0);
> > > > > +	memset(&reloc, 0, sizeof(reloc));
> > > > > +
> > > > > +	i = 0;
> > > > > +	delta = sizeof(uint32_t) * target_value;	/* why value not offset??? */
> > > > I guess I know why there's problem here. target_offset is address in vm
> > > > passed by the caller. This is regarding to some limitations of allocator
> > > > infrastructure - for "reloc" pseudo-allocator you would get new offset
> > > > (internally it returns offset and then add size for new "allocation").
> > > > With this we don't need to wait for rebind offset for new execbuf.
> > > > With "simple" allocator put will release offset so new allocation will
> > > > reuse same offset. Ashutosh proposed how to join both functionalities
> > > > (stepping as with reloc, stateful like in simple) but I got no time to
> > > > code this.
> > > > 
> > > > Regarding issue here, target_offset passed from the caller is to avoid
> > > > rebind if get_offset() would be called for "reloc" allocator.
> > > > So there's not real value offset within bo. I would add separate
> > > > value_offset (shift) to allow caller to put place where it wants to
> > > > write the value.
> > > If you understand what is going on here and how to improve it then feel free
> > > to either send me an updated version or post an extra patch after this is
> > > merged. I don't get how any of the new reloc (or anti-reloc?) code is meant
> > > to work. These patches were all written as part of the GuC support a long
> > > time ago - before there was any such thing as an AHND (what does that stand
> > > for?) or intel_ctx_t. All I'm doing in this patch is moving the existing
> > > code to a helper and trying to make it generic enough to be used by another
> > > test. And right now, the two tests are passing on both GuC and execlist
> > > platforms for me. So the code can't be all that broken.
> > I've added some missing parts to your code:
> > 
> > https://patchwork.freedesktop.org/series/98242/
> > 
> > If you think something is missing please add or fix.
> > 
> > Previously value was used both for value and offset within bo
> > used for example in gem_exec_fence@basic-await. I think adding
> > separate arg for offset for value within bo makes this code
> > more universal.
> I don't follow. The purpose of the offset is the to say where the value is
> written within the buffer. As in 'target_offset' is 'offset into target
> buffer to write value'. You have added a 'value_offset' which surely would
> be defined as 'the offset at which to write the value in the target buffer'.
> I.e. exactly the same thing. What is the intention behind having two
> separate offset variables?

No, there're not the same thing.

 target_offset
 ──────────────►┌────────────┐
 0x201000       │ size = 8K  │
                │            │
value_offset    │            │
(relative to    │            │
target_offset)  │            │
───────────────►│            │
0x1100          │            │
                │            │
                │            │
                │            │
                │            │
                │            │
                └────────────┘

Target_offset is vma start address where object will be bind.
value_offset is delta from that vma.

In execobj.offset you need to put 0x201000, but in bb final offset 
is calculated as target_offset + value_offset.

--
Zbigniew

> 
> John.
> 
> 
> > 
> > NB: ahnd is short version of allocator_handle
> > 
> > --
> > Zbigniew
> > 
> > > 
> > > > 
> > > > > +	if (!ahnd) {
> > > > > +		reloc.target_handle = obj[SCRATCH].handle;
> > > > > +		reloc.presumed_offset = -1;
> > > > > +		reloc.offset = sizeof(uint32_t) * (i + 1);
> > > > > +		reloc.delta = delta;
> > > > > +		reloc.read_domains = I915_GEM_DOMAIN_INSTRUCTION;
> > > > > +		reloc.write_domain = I915_GEM_DOMAIN_INSTRUCTION;
> > > > > +	} else {
> > > > > +		obj[SCRATCH].offset = target_offset;
> > > > > +		obj[SCRATCH].flags |= EXEC_OBJECT_PINNED | EXEC_OBJECT_WRITE;
> > > > > +		obj[BATCH].offset = bb_offset;
> > > > > +		obj[BATCH].flags |= EXEC_OBJECT_PINNED;
> > > > > +	}
> > > > > +	batch[i] = MI_STORE_DWORD_IMM | (gen < 6 ? 1 << 22 : 0);
> > > > > +	if (gen >= 8) {
> > > > > +		batch[++i] = target_offset + delta;
> > > > > +		batch[++i] = target_offset >> 32;
> > > > Probably I've added this in previous code, for being safe I would
> > > > add (target_offset + delta) >> 32 for avoid risk passing invalid higher
> > > > offset part on 32b boundary.
> > > Pretty sure we don't have any addresses larger than 32 bits yet, but yes,
> > > delta should be added in.
> > > 
> > > Thanks,
> > > John.
> > > 
> > > > > +	} else if (gen >= 4) {
> > > > > +		batch[++i] = 0;
> > > > > +		batch[++i] = delta;
> > > > > +		reloc.offset += sizeof(uint32_t);
> > > > > +	} else {
> > > > > +		batch[i]--;
> > > > > +		batch[++i] = delta;
> > > > > +	}
> > > > > +	batch[++i] = target_value;
> > > > > +	batch[++i] = MI_BATCH_BUFFER_END;
> > > > > +	gem_write(fd, obj[BATCH].handle, 0, batch, sizeof(batch));
> > > > > +	gem_execbuf(fd, &execbuf);
> > > > > +	gem_close(fd, obj[BATCH].handle);
> > > > > +	put_offset(ahnd, obj[BATCH].handle);
> > > > > +}
> > > > > diff --git a/lib/igt_store.h b/lib/igt_store.h
> > > > > new file mode 100644
> > > > > index 000000000..4d5979e07
> > > > > --- /dev/null
> > > > > +++ b/lib/igt_store.h
> > > > > @@ -0,0 +1,30 @@
> > > > > +/*
> > > > > + * Copyright © 2020 Intel Corporation
> > > > > + *
> > > > > + * Permission is hereby granted, free of charge, to any person obtaining a
> > > > > + * copy of this software and associated documentation files (the "Software"),
> > > > > + * to deal in the Software without restriction, including without limitation
> > > > > + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> > > > > + * and/or sell copies of the Software, and to permit persons to whom the
> > > > > + * Software is furnished to do so, subject to the following conditions:
> > > > > + *
> > > > > + * The above copyright notice and this permission notice (including the next
> > > > > + * paragraph) shall be included in all copies or substantial portions of the
> > > > > + * Software.
> > > > > + *
> > > > > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> > > > > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> > > > > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> > > > > + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> > > > > + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> > > > > + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
> > > > > + * IN THE SOFTWARE.
> > > > > + *
> > > > > + */
> > > > Use SPDX and 2021.
> > > > 
> > > > --
> > > > Zbigniew
> > > > 
> > > > > +
> > > > > +#include "igt_gt.h"
> > > > > +
> > > > > +void igt_store_word(int fd, uint64_t ahnd, const intel_ctx_t *ctx,
> > > > > +		    const struct intel_execution_engine2 *e,
> > > > > +		    int fence, uint32_t target_handle,
> > > > > +		    uint64_t target_offset, uint32_t target_value);
> > > > > diff --git a/lib/meson.build b/lib/meson.build
> > > > > index b9568a71b..3e43316d1 100644
> > > > > --- a/lib/meson.build
> > > > > +++ b/lib/meson.build
> > > > > @@ -72,6 +72,7 @@ lib_sources = [
> > > > >    	'igt_map.c',
> > > > >    	'igt_pm.c',
> > > > >    	'igt_dummyload.c',
> > > > > +	'igt_store.c',
> > > > >    	'uwildmat/uwildmat.c',
> > > > >    	'igt_kmod.c',
> > > > >    	'igt_panfrost.c',
> > > > > diff --git a/tests/i915/gem_exec_fence.c b/tests/i915/gem_exec_fence.c
> > > > > index 9a6336ce9..c4091a454 100644
> > > > > --- a/tests/i915/gem_exec_fence.c
> > > > > +++ b/tests/i915/gem_exec_fence.c
> > > > > @@ -28,6 +28,7 @@
> > > > >    #include "i915/gem.h"
> > > > >    #include "i915/gem_create.h"
> > > > >    #include "igt.h"
> > > > > +#include "igt_store.h"
> > > > >    #include "igt_syncobj.h"
> > > > >    #include "igt_sysfs.h"
> > > > >    #include "igt_vgem.h"
> > > > > @@ -57,74 +58,6 @@ struct sync_merge_data {
> > > > >    #define   MI_SEMAPHORE_SAD_EQ_SDD       (4 << 12)
> > > > >    #define   MI_SEMAPHORE_SAD_NEQ_SDD      (5 << 12)
> > > > > -static void store(int fd, uint64_t ahnd, const intel_ctx_t *ctx,
> > > > > -		  const struct intel_execution_engine2 *e,
> > > > > -		  int fence, uint32_t target, uint64_t target_offset,
> > > > > -		  unsigned offset_value)
> > > > > -{
> > > > > -	const int SCRATCH = 0;
> > > > > -	const int BATCH = 1;
> > > > > -	const unsigned int gen = intel_gen(intel_get_drm_devid(fd));
> > > > > -	struct drm_i915_gem_exec_object2 obj[2];
> > > > > -	struct drm_i915_gem_relocation_entry reloc;
> > > > > -	struct drm_i915_gem_execbuffer2 execbuf;
> > > > > -	uint32_t batch[16], delta;
> > > > > -	uint64_t bb_offset;
> > > > > -	int i;
> > > > > -
> > > > > -	memset(&execbuf, 0, sizeof(execbuf));
> > > > > -	execbuf.buffers_ptr = to_user_pointer(obj);
> > > > > -	execbuf.buffer_count = 2;
> > > > > -	execbuf.flags = e->flags | I915_EXEC_FENCE_IN;
> > > > > -	execbuf.rsvd1 = ctx->id;
> > > > > -	execbuf.rsvd2 = fence;
> > > > > -	if (gen < 6)
> > > > > -		execbuf.flags |= I915_EXEC_SECURE;
> > > > > -
> > > > > -	memset(obj, 0, sizeof(obj));
> > > > > -	obj[SCRATCH].handle = target;
> > > > > -
> > > > > -	obj[BATCH].handle = gem_create(fd, 4096);
> > > > > -	obj[BATCH].relocs_ptr = to_user_pointer(&reloc);
> > > > > -	obj[BATCH].relocation_count = !ahnd ? 1 : 0;
> > > > > -	bb_offset = get_offset(ahnd, obj[BATCH].handle, 4096, 0);
> > > > > -	memset(&reloc, 0, sizeof(reloc));
> > > > > -
> > > > > -	i = 0;
> > > > > -	delta = sizeof(uint32_t) * offset_value;
> > > > > -	if (!ahnd) {
> > > > > -		reloc.target_handle = obj[SCRATCH].handle;
> > > > > -		reloc.presumed_offset = -1;
> > > > > -		reloc.offset = sizeof(uint32_t) * (i + 1);
> > > > > -		reloc.delta = delta;
> > > > > -		reloc.read_domains = I915_GEM_DOMAIN_INSTRUCTION;
> > > > > -		reloc.write_domain = I915_GEM_DOMAIN_INSTRUCTION;
> > > > > -	} else {
> > > > > -		obj[SCRATCH].offset = target_offset;
> > > > > -		obj[SCRATCH].flags |= EXEC_OBJECT_PINNED | EXEC_OBJECT_WRITE;
> > > > > -		obj[BATCH].offset = bb_offset;
> > > > > -		obj[BATCH].flags |= EXEC_OBJECT_PINNED;
> > > > > -	}
> > > > > -	batch[i] = MI_STORE_DWORD_IMM | (gen < 6 ? 1 << 22 : 0);
> > > > > -	if (gen >= 8) {
> > > > > -		batch[++i] = target_offset + delta;
> > > > > -		batch[++i] = target_offset >> 32;
> > > > > -	} else if (gen >= 4) {
> > > > > -		batch[++i] = 0;
> > > > > -		batch[++i] = delta;
> > > > > -		reloc.offset += sizeof(uint32_t);
> > > > > -	} else {
> > > > > -		batch[i]--;
> > > > > -		batch[++i] = delta;
> > > > > -	}
> > > > > -	batch[++i] = offset_value;
> > > > > -	batch[++i] = MI_BATCH_BUFFER_END;
> > > > > -	gem_write(fd, obj[BATCH].handle, 0, batch, sizeof(batch));
> > > > > -	gem_execbuf(fd, &execbuf);
> > > > > -	gem_close(fd, obj[BATCH].handle);
> > > > > -	put_offset(ahnd, obj[BATCH].handle);
> > > > > -}
> > > > > -
> > > > >    static bool fence_busy(int fence)
> > > > >    {
> > > > >    	return poll(&(struct pollfd){fence, POLLIN}, 1, 0) == 0;
> > > > > @@ -400,13 +333,13 @@ static void test_fence_await(int fd, const intel_ctx_t *ctx,
> > > > >    			continue;
> > > > >    		if (flags & NONBLOCK) {
> > > > > -			store(fd, ahnd, ctx, e2, spin->out_fence,
> > > > > -			      scratch, scratch_offset, i);
> > > > > +			igt_store_word(fd, ahnd, ctx, e2, spin->out_fence,
> > > > > +				       scratch, scratch_offset, i);
> > > > >    		} else {
> > > > >    			igt_fork(child, 1) {
> > > > >    				ahnd = get_reloc_ahnd(fd, ctx->id);
> > > > > -				store(fd, ahnd, ctx, e2, spin->out_fence,
> > > > > -				      scratch, scratch_offset, i);
> > > > > +				igt_store_word(fd, ahnd, ctx, e2, spin->out_fence,
> > > > > +					       scratch, scratch_offset, i);
> > > > >    				put_ahnd(ahnd);
> > > > >    			}
> > > > >    		}
> > > > > diff --git a/tests/i915/i915_hangman.c b/tests/i915/i915_hangman.c
> > > > > index 20653b479..4cb9b8b85 100644
> > > > > --- a/tests/i915/i915_hangman.c
> > > > > +++ b/tests/i915/i915_hangman.c
> > > > > @@ -36,6 +36,7 @@
> > > > >    #include "i915/gem.h"
> > > > >    #include "i915/gem_create.h"
> > > > >    #include "igt.h"
> > > > > +#include "igt_store.h"
> > > > >    #include "igt_sysfs.h"
> > > > >    #include "igt_debugfs.h"
> > > > >    #include "sw_sync.h"
> > > > > @@ -51,64 +52,6 @@ static int sysfs = -1;
> > > > >    IGT_TEST_DESCRIPTION("Tests for hang detection and recovery");
> > > > > -/* Requires master for STORE_DWORD on gen4/5 */
> > > > > -static void store(int fd, const struct intel_execution_engine2 *e,
> > > > > -		  int fence, uint32_t target, unsigned offset_value)
> > > > > -{
> > > > > -	const int SCRATCH = 0;
> > > > > -	const int BATCH = 1;
> > > > > -	const int gen = intel_gen(intel_get_drm_devid(fd));
> > > > > -	struct drm_i915_gem_exec_object2 obj[2];
> > > > > -	struct drm_i915_gem_relocation_entry reloc;
> > > > > -	struct drm_i915_gem_execbuffer2 execbuf;
> > > > > -	uint32_t batch[16];
> > > > > -	int i;
> > > > > -
> > > > > -	memset(&execbuf, 0, sizeof(execbuf));
> > > > > -	execbuf.buffers_ptr = to_user_pointer(obj);
> > > > > -	execbuf.buffer_count = ARRAY_SIZE(obj);
> > > > > -	execbuf.flags = e->flags;
> > > > > -	if (fence != -1) {
> > > > > -		execbuf.flags |= I915_EXEC_FENCE_IN;
> > > > > -		execbuf.rsvd2 = fence;
> > > > > -	}
> > > > > -	if (gen < 6)
> > > > > -		execbuf.flags |= I915_EXEC_SECURE;
> > > > > -
> > > > > -	memset(obj, 0, sizeof(obj));
> > > > > -	obj[SCRATCH].handle = target;
> > > > > -
> > > > > -	obj[BATCH].handle = gem_create(fd, 4096);
> > > > > -	obj[BATCH].relocs_ptr = to_user_pointer(&reloc);
> > > > > -	obj[BATCH].relocation_count = 1;
> > > > > -	memset(&reloc, 0, sizeof(reloc));
> > > > > -
> > > > > -	i = 0;
> > > > > -	reloc.target_handle = obj[SCRATCH].handle;
> > > > > -	reloc.presumed_offset = -1;
> > > > > -	reloc.offset = sizeof(uint32_t) * (i + 1);
> > > > > -	reloc.delta = sizeof(uint32_t) * offset_value;
> > > > > -	reloc.read_domains = I915_GEM_DOMAIN_INSTRUCTION;
> > > > > -	reloc.write_domain = I915_GEM_DOMAIN_INSTRUCTION;
> > > > > -	batch[i] = MI_STORE_DWORD_IMM | (gen < 6 ? 1 << 22 : 0);
> > > > > -	if (gen >= 8) {
> > > > > -		batch[++i] = reloc.delta;
> > > > > -		batch[++i] = 0;
> > > > > -	} else if (gen >= 4) {
> > > > > -		batch[++i] = 0;
> > > > > -		batch[++i] = reloc.delta;
> > > > > -		reloc.offset += sizeof(uint32_t);
> > > > > -	} else {
> > > > > -		batch[i]--;
> > > > > -		batch[++i] = reloc.delta;
> > > > > -	}
> > > > > -	batch[++i] = offset_value;
> > > > > -	batch[++i] = MI_BATCH_BUFFER_END;
> > > > > -	gem_write(fd, obj[BATCH].handle, 0, batch, sizeof(batch));
> > > > > -	gem_execbuf(fd, &execbuf);
> > > > > -	gem_close(fd, obj[BATCH].handle);
> > > > > -}
> > > > > -
> > > > >    static void check_alive(void)
> > > > >    {
> > > > >    	const struct intel_execution_engine2 *engine;
> > > > > @@ -138,7 +81,7 @@ static void check_alive(void)
> > > > >    			continue;
> > > > >    		/* +OFFSET_ALIVE to ensure engine zero doesn't get a false negative */
> > > > > -		store(fd, engine, -1, scratch, i + OFFSET_ALIVE);
> > > > > +		igt_store_word(fd, ahnd, ctx, engine, -1, scratch, i + OFFSET_ALIVE, i + OFFSET_ALIVE);
> > > > >    		i++;
> > > > >    	}
> > > > > -- 
> > > > > 2.25.1
> > > > > 
> 

Re: [Intel-gfx] [igt-dev] [PATCH i-g-t 08/11] lib/store: Refactor common store code into helper function

[John Harrison]

On 12/26/2021 22:02, Zbigniew Kempczyński wrote:
> On Tue, Dec 21, 2021 at 06:22:22PM -0800, John Harrison wrote:
>> On 12/20/2021 10:13, Zbigniew Kempczyński wrote:
>>> On Thu, Dec 16, 2021 at 02:40:21PM -0800, John Harrison wrote:
>>>> On 12/15/2021 23:46, Zbigniew Kempczyński wrote:
>>>>> On Mon, Dec 13, 2021 at 03:29:11PM -0800, John.C.Harrison@Intel.com wrote:
>>>>>> From: John Harrison <John.C.Harrison@Intel.com>
>>>>>>
>>>>>> A lot of tests use almost identical code for creating a batch buffer
>>>>>> which does a single write to memory. This patch collects two such
>>>>>> instances into a common helper function. Unfortunately, the other
>>>>>> instances are all subtly different enough to make it not so trivial to
>>>>>> try to use the helper. It could be done but it is unclear if it is
>>>>>> worth the effort at this point. This patch proves the concept, if
>>>>>> people like it enough then it can be extended.
>>>>>>
>>>>>> Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
>>>>>> ---
>>>>>>     lib/igt_store.c             | 114 ++++++++++++++++++++++++++++++++++++
>>>>>>     lib/igt_store.h             |  30 ++++++++++
>>>>>>     lib/meson.build             |   1 +
>>>>>>     tests/i915/gem_exec_fence.c |  77 ++----------------------
>>>>>>     tests/i915/i915_hangman.c   |  61 +------------------
>>>>>>     5 files changed, 152 insertions(+), 131 deletions(-)
>>>>>>     create mode 100644 lib/igt_store.c
>>>>>>     create mode 100644 lib/igt_store.h
>>>>>>
>>>>>> diff --git a/lib/igt_store.c b/lib/igt_store.c
>>>>>> new file mode 100644
>>>>>> index 000000000..6d9869b58
>>>>>> --- /dev/null
>>>>>> +++ b/lib/igt_store.c
>>>>>> @@ -0,0 +1,114 @@
>>>>>> +/*
>>>>>> + * Copyright © 2020 Intel Corporation
>>>>>> + *
>>>>>> + * Permission is hereby granted, free of charge, to any person obtaining a
>>>>>> + * copy of this software and associated documentation files (the "Software"),
>>>>>> + * to deal in the Software without restriction, including without limitation
>>>>>> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>>>>>> + * and/or sell copies of the Software, and to permit persons to whom the
>>>>>> + * Software is furnished to do so, subject to the following conditions:
>>>>>> + *
>>>>>> + * The above copyright notice and this permission notice (including the next
>>>>>> + * paragraph) shall be included in all copies or substantial portions of the
>>>>>> + * Software.
>>>>>> + *
>>>>>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>>>>>> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>>>>>> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>>>>>> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
>>>>>> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>>>>>> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
>>>>>> + * IN THE SOFTWARE.
>>>>>> + *
>>>>>> + */
>>>>> Use SPDX. I like idea of extracting this.
>>>>>
>>>>>> +
>>>>>> +#include "i915/gem_create.h"
>>>>>> +#include "igt_core.h"
>>>>>> +#include "drmtest.h"
>>>>>> +#include "igt_store.h"
>>>>>> +#include "intel_chipset.h"
>>>>>> +#include "intel_reg.h"
>>>>>> +#include "ioctl_wrappers.h"
>>>>>> +#include "lib/intel_allocator.h"
>>>>>> +
>>>>>> +/**
>>>>>> + * SECTION:igt_store_word
>>>>>> + * @short_description: Library for writing a value to memory
>>>>>> + * @title: StoreWord
>>>>>> + * @include: igt.h
>>>>>> + *
>>>>>> + * A lot of igt testcases need some mechanism for writing a value to memory
>>>>>> + * as a test that a batch buffer has executed.
>>>>>> + *
>>>>>> + * NB: Requires master for STORE_DWORD on gen4/5.
>>>>>> + */
>>>>>> +void igt_store_word(int fd, uint64_t ahnd, const intel_ctx_t *ctx,
>>>>>> +		    const struct intel_execution_engine2 *e,
>>>>>> +		    int fence, uint32_t target_handle,
>>>>>> +		    uint64_t target_offset, uint32_t target_value)
>>>>>> +{
>>>>>> +	const int SCRATCH = 0;
>>>>>> +	const int BATCH = 1;
>>>>>> +	const unsigned int gen = intel_gen(intel_get_drm_devid(fd));
>>>>>> +	struct drm_i915_gem_exec_object2 obj[2];
>>>>>> +	struct drm_i915_gem_relocation_entry reloc;
>>>>>> +	struct drm_i915_gem_execbuffer2 execbuf;
>>>>>> +	uint32_t batch[16], delta;
>>>>>> +	uint64_t bb_offset;
>>>>>> +	int i;
>>>>>> +
>>>>>> +	memset(&execbuf, 0, sizeof(execbuf));
>>>>>> +	execbuf.buffers_ptr = to_user_pointer(obj);
>>>>>> +	execbuf.buffer_count = ARRAY_SIZE(obj);
>>>>>> +	execbuf.flags = e->flags;
>>>>>> +	execbuf.rsvd1 = ctx->id;
>>>>>> +	if (fence != -1) {
>>>>>> +		execbuf.flags |= I915_EXEC_FENCE_IN;
>>>>>> +		execbuf.rsvd2 = fence;
>>>>>> +	}
>>>>>> +	if (gen < 6)
>>>>>> +		execbuf.flags |= I915_EXEC_SECURE;
>>>>>> +
>>>>>> +	memset(obj, 0, sizeof(obj));
>>>>>> +	obj[SCRATCH].handle = target_handle;
>>>>>> +
>>>>>> +	obj[BATCH].handle = gem_create(fd, 4096);
>>>>>> +	obj[BATCH].relocs_ptr = to_user_pointer(&reloc);
>>>>>> +	obj[BATCH].relocation_count = !ahnd ? 1 : 0;
>>>>>> +	bb_offset = get_offset(ahnd, obj[BATCH].handle, 4096, 0);
>>>>>> +	memset(&reloc, 0, sizeof(reloc));
>>>>>> +
>>>>>> +	i = 0;
>>>>>> +	delta = sizeof(uint32_t) * target_value;	/* why value not offset??? */
>>>>> I guess I know why there's problem here. target_offset is address in vm
>>>>> passed by the caller. This is regarding to some limitations of allocator
>>>>> infrastructure - for "reloc" pseudo-allocator you would get new offset
>>>>> (internally it returns offset and then add size for new "allocation").
>>>>> With this we don't need to wait for rebind offset for new execbuf.
>>>>> With "simple" allocator put will release offset so new allocation will
>>>>> reuse same offset. Ashutosh proposed how to join both functionalities
>>>>> (stepping as with reloc, stateful like in simple) but I got no time to
>>>>> code this.
>>>>>
>>>>> Regarding issue here, target_offset passed from the caller is to avoid
>>>>> rebind if get_offset() would be called for "reloc" allocator.
>>>>> So there's not real value offset within bo. I would add separate
>>>>> value_offset (shift) to allow caller to put place where it wants to
>>>>> write the value.
>>>> If you understand what is going on here and how to improve it then feel free
>>>> to either send me an updated version or post an extra patch after this is
>>>> merged. I don't get how any of the new reloc (or anti-reloc?) code is meant
>>>> to work. These patches were all written as part of the GuC support a long
>>>> time ago - before there was any such thing as an AHND (what does that stand
>>>> for?) or intel_ctx_t. All I'm doing in this patch is moving the existing
>>>> code to a helper and trying to make it generic enough to be used by another
>>>> test. And right now, the two tests are passing on both GuC and execlist
>>>> platforms for me. So the code can't be all that broken.
>>> I've added some missing parts to your code:
>>>
>>> https://patchwork.freedesktop.org/series/98242/
>>>
>>> If you think something is missing please add or fix.
>>>
>>> Previously value was used both for value and offset within bo
>>> used for example in gem_exec_fence@basic-await. I think adding
>>> separate arg for offset for value within bo makes this code
>>> more universal.
>> I don't follow. The purpose of the offset is the to say where the value is
>> written within the buffer. As in 'target_offset' is 'offset into target
>> buffer to write value'. You have added a 'value_offset' which surely would
>> be defined as 'the offset at which to write the value in the target buffer'.
>> I.e. exactly the same thing. What is the intention behind having two
>> separate offset variables?
> No, there're not the same thing.
>
>   target_offset
>   ──────────────►┌────────────┐
>   0x201000       │ size = 8K  │
>                  │            │
> value_offset    │            │
> (relative to    │            │
> target_offset)  │            │
> ───────────────►│            │
> 0x1100          │            │
>                  │            │
>                  │            │
>                  │            │
>                  │            │
>                  │            │
>                  └────────────┘
>
> Target_offset is vma start address where object will be bind.
> value_offset is delta from that vma.
Meaning the graphics address? As in, the offset from the start of the 
PPGTT or some such? Surely that should be a part of the object structure 
and specified when the object is created. What is the point of the 
object's handle if it does not specify what object to access? I mean, 
what is an 'object' other than a start address and size / end address? 
The memory mapping details really should not be a parameter to a helper 
function whose purpose is to write a single word to a specific location 
within a pre-existing object. At the very least, it should be called 
obj_gpu_addr or similar. Calling two very different concepts 'offset' is 
totally confusing.

Or am I still completely confused as to what the purpose is?

John.


>
> In execobj.offset you need to put 0x201000, but in bb final offset
> is calculated as target_offset + value_offset.
>
> --
> Zbigniew
>
>> John.
>>
>>
>>> NB: ahnd is short version of allocator_handle
>>>
>>> --
>>> Zbigniew
>>>
>>>>>> +	if (!ahnd) {
>>>>>> +		reloc.target_handle = obj[SCRATCH].handle;
>>>>>> +		reloc.presumed_offset = -1;
>>>>>> +		reloc.offset = sizeof(uint32_t) * (i + 1);
>>>>>> +		reloc.delta = delta;
>>>>>> +		reloc.read_domains = I915_GEM_DOMAIN_INSTRUCTION;
>>>>>> +		reloc.write_domain = I915_GEM_DOMAIN_INSTRUCTION;
>>>>>> +	} else {
>>>>>> +		obj[SCRATCH].offset = target_offset;
>>>>>> +		obj[SCRATCH].flags |= EXEC_OBJECT_PINNED | EXEC_OBJECT_WRITE;
>>>>>> +		obj[BATCH].offset = bb_offset;
>>>>>> +		obj[BATCH].flags |= EXEC_OBJECT_PINNED;
>>>>>> +	}
>>>>>> +	batch[i] = MI_STORE_DWORD_IMM | (gen < 6 ? 1 << 22 : 0);
>>>>>> +	if (gen >= 8) {
>>>>>> +		batch[++i] = target_offset + delta;
>>>>>> +		batch[++i] = target_offset >> 32;
>>>>> Probably I've added this in previous code, for being safe I would
>>>>> add (target_offset + delta) >> 32 for avoid risk passing invalid higher
>>>>> offset part on 32b boundary.
>>>> Pretty sure we don't have any addresses larger than 32 bits yet, but yes,
>>>> delta should be added in.
>>>>
>>>> Thanks,
>>>> John.
>>>>
>>>>>> +	} else if (gen >= 4) {
>>>>>> +		batch[++i] = 0;
>>>>>> +		batch[++i] = delta;
>>>>>> +		reloc.offset += sizeof(uint32_t);
>>>>>> +	} else {
>>>>>> +		batch[i]--;
>>>>>> +		batch[++i] = delta;
>>>>>> +	}
>>>>>> +	batch[++i] = target_value;
>>>>>> +	batch[++i] = MI_BATCH_BUFFER_END;
>>>>>> +	gem_write(fd, obj[BATCH].handle, 0, batch, sizeof(batch));
>>>>>> +	gem_execbuf(fd, &execbuf);
>>>>>> +	gem_close(fd, obj[BATCH].handle);
>>>>>> +	put_offset(ahnd, obj[BATCH].handle);
>>>>>> +}
>>>>>> diff --git a/lib/igt_store.h b/lib/igt_store.h
>>>>>> new file mode 100644
>>>>>> index 000000000..4d5979e07
>>>>>> --- /dev/null
>>>>>> +++ b/lib/igt_store.h
>>>>>> @@ -0,0 +1,30 @@
>>>>>> +/*
>>>>>> + * Copyright © 2020 Intel Corporation
>>>>>> + *
>>>>>> + * Permission is hereby granted, free of charge, to any person obtaining a
>>>>>> + * copy of this software and associated documentation files (the "Software"),
>>>>>> + * to deal in the Software without restriction, including without limitation
>>>>>> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>>>>>> + * and/or sell copies of the Software, and to permit persons to whom the
>>>>>> + * Software is furnished to do so, subject to the following conditions:
>>>>>> + *
>>>>>> + * The above copyright notice and this permission notice (including the next
>>>>>> + * paragraph) shall be included in all copies or substantial portions of the
>>>>>> + * Software.
>>>>>> + *
>>>>>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>>>>>> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>>>>>> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>>>>>> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
>>>>>> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>>>>>> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
>>>>>> + * IN THE SOFTWARE.
>>>>>> + *
>>>>>> + */
>>>>> Use SPDX and 2021.
>>>>>
>>>>> --
>>>>> Zbigniew
>>>>>
>>>>>> +
>>>>>> +#include "igt_gt.h"
>>>>>> +
>>>>>> +void igt_store_word(int fd, uint64_t ahnd, const intel_ctx_t *ctx,
>>>>>> +		    const struct intel_execution_engine2 *e,
>>>>>> +		    int fence, uint32_t target_handle,
>>>>>> +		    uint64_t target_offset, uint32_t target_value);
>>>>>> diff --git a/lib/meson.build b/lib/meson.build
>>>>>> index b9568a71b..3e43316d1 100644
>>>>>> --- a/lib/meson.build
>>>>>> +++ b/lib/meson.build
>>>>>> @@ -72,6 +72,7 @@ lib_sources = [
>>>>>>     	'igt_map.c',
>>>>>>     	'igt_pm.c',
>>>>>>     	'igt_dummyload.c',
>>>>>> +	'igt_store.c',
>>>>>>     	'uwildmat/uwildmat.c',
>>>>>>     	'igt_kmod.c',
>>>>>>     	'igt_panfrost.c',
>>>>>> diff --git a/tests/i915/gem_exec_fence.c b/tests/i915/gem_exec_fence.c
>>>>>> index 9a6336ce9..c4091a454 100644
>>>>>> --- a/tests/i915/gem_exec_fence.c
>>>>>> +++ b/tests/i915/gem_exec_fence.c
>>>>>> @@ -28,6 +28,7 @@
>>>>>>     #include "i915/gem.h"
>>>>>>     #include "i915/gem_create.h"
>>>>>>     #include "igt.h"
>>>>>> +#include "igt_store.h"
>>>>>>     #include "igt_syncobj.h"
>>>>>>     #include "igt_sysfs.h"
>>>>>>     #include "igt_vgem.h"
>>>>>> @@ -57,74 +58,6 @@ struct sync_merge_data {
>>>>>>     #define   MI_SEMAPHORE_SAD_EQ_SDD       (4 << 12)
>>>>>>     #define   MI_SEMAPHORE_SAD_NEQ_SDD      (5 << 12)
>>>>>> -static void store(int fd, uint64_t ahnd, const intel_ctx_t *ctx,
>>>>>> -		  const struct intel_execution_engine2 *e,
>>>>>> -		  int fence, uint32_t target, uint64_t target_offset,
>>>>>> -		  unsigned offset_value)
>>>>>> -{
>>>>>> -	const int SCRATCH = 0;
>>>>>> -	const int BATCH = 1;
>>>>>> -	const unsigned int gen = intel_gen(intel_get_drm_devid(fd));
>>>>>> -	struct drm_i915_gem_exec_object2 obj[2];
>>>>>> -	struct drm_i915_gem_relocation_entry reloc;
>>>>>> -	struct drm_i915_gem_execbuffer2 execbuf;
>>>>>> -	uint32_t batch[16], delta;
>>>>>> -	uint64_t bb_offset;
>>>>>> -	int i;
>>>>>> -
>>>>>> -	memset(&execbuf, 0, sizeof(execbuf));
>>>>>> -	execbuf.buffers_ptr = to_user_pointer(obj);
>>>>>> -	execbuf.buffer_count = 2;
>>>>>> -	execbuf.flags = e->flags | I915_EXEC_FENCE_IN;
>>>>>> -	execbuf.rsvd1 = ctx->id;
>>>>>> -	execbuf.rsvd2 = fence;
>>>>>> -	if (gen < 6)
>>>>>> -		execbuf.flags |= I915_EXEC_SECURE;
>>>>>> -
>>>>>> -	memset(obj, 0, sizeof(obj));
>>>>>> -	obj[SCRATCH].handle = target;
>>>>>> -
>>>>>> -	obj[BATCH].handle = gem_create(fd, 4096);
>>>>>> -	obj[BATCH].relocs_ptr = to_user_pointer(&reloc);
>>>>>> -	obj[BATCH].relocation_count = !ahnd ? 1 : 0;
>>>>>> -	bb_offset = get_offset(ahnd, obj[BATCH].handle, 4096, 0);
>>>>>> -	memset(&reloc, 0, sizeof(reloc));
>>>>>> -
>>>>>> -	i = 0;
>>>>>> -	delta = sizeof(uint32_t) * offset_value;
>>>>>> -	if (!ahnd) {
>>>>>> -		reloc.target_handle = obj[SCRATCH].handle;
>>>>>> -		reloc.presumed_offset = -1;
>>>>>> -		reloc.offset = sizeof(uint32_t) * (i + 1);
>>>>>> -		reloc.delta = delta;
>>>>>> -		reloc.read_domains = I915_GEM_DOMAIN_INSTRUCTION;
>>>>>> -		reloc.write_domain = I915_GEM_DOMAIN_INSTRUCTION;
>>>>>> -	} else {
>>>>>> -		obj[SCRATCH].offset = target_offset;
>>>>>> -		obj[SCRATCH].flags |= EXEC_OBJECT_PINNED | EXEC_OBJECT_WRITE;
>>>>>> -		obj[BATCH].offset = bb_offset;
>>>>>> -		obj[BATCH].flags |= EXEC_OBJECT_PINNED;
>>>>>> -	}
>>>>>> -	batch[i] = MI_STORE_DWORD_IMM | (gen < 6 ? 1 << 22 : 0);
>>>>>> -	if (gen >= 8) {
>>>>>> -		batch[++i] = target_offset + delta;
>>>>>> -		batch[++i] = target_offset >> 32;
>>>>>> -	} else if (gen >= 4) {
>>>>>> -		batch[++i] = 0;
>>>>>> -		batch[++i] = delta;
>>>>>> -		reloc.offset += sizeof(uint32_t);
>>>>>> -	} else {
>>>>>> -		batch[i]--;
>>>>>> -		batch[++i] = delta;
>>>>>> -	}
>>>>>> -	batch[++i] = offset_value;
>>>>>> -	batch[++i] = MI_BATCH_BUFFER_END;
>>>>>> -	gem_write(fd, obj[BATCH].handle, 0, batch, sizeof(batch));
>>>>>> -	gem_execbuf(fd, &execbuf);
>>>>>> -	gem_close(fd, obj[BATCH].handle);
>>>>>> -	put_offset(ahnd, obj[BATCH].handle);
>>>>>> -}
>>>>>> -
>>>>>>     static bool fence_busy(int fence)
>>>>>>     {
>>>>>>     	return poll(&(struct pollfd){fence, POLLIN}, 1, 0) == 0;
>>>>>> @@ -400,13 +333,13 @@ static void test_fence_await(int fd, const intel_ctx_t *ctx,
>>>>>>     			continue;
>>>>>>     		if (flags & NONBLOCK) {
>>>>>> -			store(fd, ahnd, ctx, e2, spin->out_fence,
>>>>>> -			      scratch, scratch_offset, i);
>>>>>> +			igt_store_word(fd, ahnd, ctx, e2, spin->out_fence,
>>>>>> +				       scratch, scratch_offset, i);
>>>>>>     		} else {
>>>>>>     			igt_fork(child, 1) {
>>>>>>     				ahnd = get_reloc_ahnd(fd, ctx->id);
>>>>>> -				store(fd, ahnd, ctx, e2, spin->out_fence,
>>>>>> -				      scratch, scratch_offset, i);
>>>>>> +				igt_store_word(fd, ahnd, ctx, e2, spin->out_fence,
>>>>>> +					       scratch, scratch_offset, i);
>>>>>>     				put_ahnd(ahnd);
>>>>>>     			}
>>>>>>     		}
>>>>>> diff --git a/tests/i915/i915_hangman.c b/tests/i915/i915_hangman.c
>>>>>> index 20653b479..4cb9b8b85 100644
>>>>>> --- a/tests/i915/i915_hangman.c
>>>>>> +++ b/tests/i915/i915_hangman.c
>>>>>> @@ -36,6 +36,7 @@
>>>>>>     #include "i915/gem.h"
>>>>>>     #include "i915/gem_create.h"
>>>>>>     #include "igt.h"
>>>>>> +#include "igt_store.h"
>>>>>>     #include "igt_sysfs.h"
>>>>>>     #include "igt_debugfs.h"
>>>>>>     #include "sw_sync.h"
>>>>>> @@ -51,64 +52,6 @@ static int sysfs = -1;
>>>>>>     IGT_TEST_DESCRIPTION("Tests for hang detection and recovery");
>>>>>> -/* Requires master for STORE_DWORD on gen4/5 */
>>>>>> -static void store(int fd, const struct intel_execution_engine2 *e,
>>>>>> -		  int fence, uint32_t target, unsigned offset_value)
>>>>>> -{
>>>>>> -	const int SCRATCH = 0;
>>>>>> -	const int BATCH = 1;
>>>>>> -	const int gen = intel_gen(intel_get_drm_devid(fd));
>>>>>> -	struct drm_i915_gem_exec_object2 obj[2];
>>>>>> -	struct drm_i915_gem_relocation_entry reloc;
>>>>>> -	struct drm_i915_gem_execbuffer2 execbuf;
>>>>>> -	uint32_t batch[16];
>>>>>> -	int i;
>>>>>> -
>>>>>> -	memset(&execbuf, 0, sizeof(execbuf));
>>>>>> -	execbuf.buffers_ptr = to_user_pointer(obj);
>>>>>> -	execbuf.buffer_count = ARRAY_SIZE(obj);
>>>>>> -	execbuf.flags = e->flags;
>>>>>> -	if (fence != -1) {
>>>>>> -		execbuf.flags |= I915_EXEC_FENCE_IN;
>>>>>> -		execbuf.rsvd2 = fence;
>>>>>> -	}
>>>>>> -	if (gen < 6)
>>>>>> -		execbuf.flags |= I915_EXEC_SECURE;
>>>>>> -
>>>>>> -	memset(obj, 0, sizeof(obj));
>>>>>> -	obj[SCRATCH].handle = target;
>>>>>> -
>>>>>> -	obj[BATCH].handle = gem_create(fd, 4096);
>>>>>> -	obj[BATCH].relocs_ptr = to_user_pointer(&reloc);
>>>>>> -	obj[BATCH].relocation_count = 1;
>>>>>> -	memset(&reloc, 0, sizeof(reloc));
>>>>>> -
>>>>>> -	i = 0;
>>>>>> -	reloc.target_handle = obj[SCRATCH].handle;
>>>>>> -	reloc.presumed_offset = -1;
>>>>>> -	reloc.offset = sizeof(uint32_t) * (i + 1);
>>>>>> -	reloc.delta = sizeof(uint32_t) * offset_value;
>>>>>> -	reloc.read_domains = I915_GEM_DOMAIN_INSTRUCTION;
>>>>>> -	reloc.write_domain = I915_GEM_DOMAIN_INSTRUCTION;
>>>>>> -	batch[i] = MI_STORE_DWORD_IMM | (gen < 6 ? 1 << 22 : 0);
>>>>>> -	if (gen >= 8) {
>>>>>> -		batch[++i] = reloc.delta;
>>>>>> -		batch[++i] = 0;
>>>>>> -	} else if (gen >= 4) {
>>>>>> -		batch[++i] = 0;
>>>>>> -		batch[++i] = reloc.delta;
>>>>>> -		reloc.offset += sizeof(uint32_t);
>>>>>> -	} else {
>>>>>> -		batch[i]--;
>>>>>> -		batch[++i] = reloc.delta;
>>>>>> -	}
>>>>>> -	batch[++i] = offset_value;
>>>>>> -	batch[++i] = MI_BATCH_BUFFER_END;
>>>>>> -	gem_write(fd, obj[BATCH].handle, 0, batch, sizeof(batch));
>>>>>> -	gem_execbuf(fd, &execbuf);
>>>>>> -	gem_close(fd, obj[BATCH].handle);
>>>>>> -}
>>>>>> -
>>>>>>     static void check_alive(void)
>>>>>>     {
>>>>>>     	const struct intel_execution_engine2 *engine;
>>>>>> @@ -138,7 +81,7 @@ static void check_alive(void)
>>>>>>     			continue;
>>>>>>     		/* +OFFSET_ALIVE to ensure engine zero doesn't get a false negative */
>>>>>> -		store(fd, engine, -1, scratch, i + OFFSET_ALIVE);
>>>>>> +		igt_store_word(fd, ahnd, ctx, engine, -1, scratch, i + OFFSET_ALIVE, i + OFFSET_ALIVE);
>>>>>>     		i++;
>>>>>>     	}
>>>>>> -- 
>>>>>> 2.25.1
>>>>>>

Re: [igt-dev] [PATCH i-g-t 08/11] lib/store: Refactor common store code into helper function

[John Harrison]

On 12/26/2021 22:02, Zbigniew Kempczyński wrote:
> On Tue, Dec 21, 2021 at 06:22:22PM -0800, John Harrison wrote:
>> On 12/20/2021 10:13, Zbigniew Kempczyński wrote:
>>> On Thu, Dec 16, 2021 at 02:40:21PM -0800, John Harrison wrote:
>>>> On 12/15/2021 23:46, Zbigniew Kempczyński wrote:
>>>>> On Mon, Dec 13, 2021 at 03:29:11PM -0800, John.C.Harrison@Intel.com wrote:
>>>>>> From: John Harrison <John.C.Harrison@Intel.com>
>>>>>>
>>>>>> A lot of tests use almost identical code for creating a batch buffer
>>>>>> which does a single write to memory. This patch collects two such
>>>>>> instances into a common helper function. Unfortunately, the other
>>>>>> instances are all subtly different enough to make it not so trivial to
>>>>>> try to use the helper. It could be done but it is unclear if it is
>>>>>> worth the effort at this point. This patch proves the concept, if
>>>>>> people like it enough then it can be extended.
>>>>>>
>>>>>> Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
>>>>>> ---
>>>>>>     lib/igt_store.c             | 114 ++++++++++++++++++++++++++++++++++++
>>>>>>     lib/igt_store.h             |  30 ++++++++++
>>>>>>     lib/meson.build             |   1 +
>>>>>>     tests/i915/gem_exec_fence.c |  77 ++----------------------
>>>>>>     tests/i915/i915_hangman.c   |  61 +------------------
>>>>>>     5 files changed, 152 insertions(+), 131 deletions(-)
>>>>>>     create mode 100644 lib/igt_store.c
>>>>>>     create mode 100644 lib/igt_store.h
>>>>>>
>>>>>> diff --git a/lib/igt_store.c b/lib/igt_store.c
>>>>>> new file mode 100644
>>>>>> index 000000000..6d9869b58
>>>>>> --- /dev/null
>>>>>> +++ b/lib/igt_store.c
>>>>>> @@ -0,0 +1,114 @@
>>>>>> +/*
>>>>>> + * Copyright © 2020 Intel Corporation
>>>>>> + *
>>>>>> + * Permission is hereby granted, free of charge, to any person obtaining a
>>>>>> + * copy of this software and associated documentation files (the "Software"),
>>>>>> + * to deal in the Software without restriction, including without limitation
>>>>>> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>>>>>> + * and/or sell copies of the Software, and to permit persons to whom the
>>>>>> + * Software is furnished to do so, subject to the following conditions:
>>>>>> + *
>>>>>> + * The above copyright notice and this permission notice (including the next
>>>>>> + * paragraph) shall be included in all copies or substantial portions of the
>>>>>> + * Software.
>>>>>> + *
>>>>>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>>>>>> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>>>>>> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>>>>>> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
>>>>>> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>>>>>> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
>>>>>> + * IN THE SOFTWARE.
>>>>>> + *
>>>>>> + */
>>>>> Use SPDX. I like idea of extracting this.
>>>>>
>>>>>> +
>>>>>> +#include "i915/gem_create.h"
>>>>>> +#include "igt_core.h"
>>>>>> +#include "drmtest.h"
>>>>>> +#include "igt_store.h"
>>>>>> +#include "intel_chipset.h"
>>>>>> +#include "intel_reg.h"
>>>>>> +#include "ioctl_wrappers.h"
>>>>>> +#include "lib/intel_allocator.h"
>>>>>> +
>>>>>> +/**
>>>>>> + * SECTION:igt_store_word
>>>>>> + * @short_description: Library for writing a value to memory
>>>>>> + * @title: StoreWord
>>>>>> + * @include: igt.h
>>>>>> + *
>>>>>> + * A lot of igt testcases need some mechanism for writing a value to memory
>>>>>> + * as a test that a batch buffer has executed.
>>>>>> + *
>>>>>> + * NB: Requires master for STORE_DWORD on gen4/5.
>>>>>> + */
>>>>>> +void igt_store_word(int fd, uint64_t ahnd, const intel_ctx_t *ctx,
>>>>>> +		    const struct intel_execution_engine2 *e,
>>>>>> +		    int fence, uint32_t target_handle,
>>>>>> +		    uint64_t target_offset, uint32_t target_value)
>>>>>> +{
>>>>>> +	const int SCRATCH = 0;
>>>>>> +	const int BATCH = 1;
>>>>>> +	const unsigned int gen = intel_gen(intel_get_drm_devid(fd));
>>>>>> +	struct drm_i915_gem_exec_object2 obj[2];
>>>>>> +	struct drm_i915_gem_relocation_entry reloc;
>>>>>> +	struct drm_i915_gem_execbuffer2 execbuf;
>>>>>> +	uint32_t batch[16], delta;
>>>>>> +	uint64_t bb_offset;
>>>>>> +	int i;
>>>>>> +
>>>>>> +	memset(&execbuf, 0, sizeof(execbuf));
>>>>>> +	execbuf.buffers_ptr = to_user_pointer(obj);
>>>>>> +	execbuf.buffer_count = ARRAY_SIZE(obj);
>>>>>> +	execbuf.flags = e->flags;
>>>>>> +	execbuf.rsvd1 = ctx->id;
>>>>>> +	if (fence != -1) {
>>>>>> +		execbuf.flags |= I915_EXEC_FENCE_IN;
>>>>>> +		execbuf.rsvd2 = fence;
>>>>>> +	}
>>>>>> +	if (gen < 6)
>>>>>> +		execbuf.flags |= I915_EXEC_SECURE;
>>>>>> +
>>>>>> +	memset(obj, 0, sizeof(obj));
>>>>>> +	obj[SCRATCH].handle = target_handle;
>>>>>> +
>>>>>> +	obj[BATCH].handle = gem_create(fd, 4096);
>>>>>> +	obj[BATCH].relocs_ptr = to_user_pointer(&reloc);
>>>>>> +	obj[BATCH].relocation_count = !ahnd ? 1 : 0;
>>>>>> +	bb_offset = get_offset(ahnd, obj[BATCH].handle, 4096, 0);
>>>>>> +	memset(&reloc, 0, sizeof(reloc));
>>>>>> +
>>>>>> +	i = 0;
>>>>>> +	delta = sizeof(uint32_t) * target_value;	/* why value not offset??? */
>>>>> I guess I know why there's problem here. target_offset is address in vm
>>>>> passed by the caller. This is regarding to some limitations of allocator
>>>>> infrastructure - for "reloc" pseudo-allocator you would get new offset
>>>>> (internally it returns offset and then add size for new "allocation").
>>>>> With this we don't need to wait for rebind offset for new execbuf.
>>>>> With "simple" allocator put will release offset so new allocation will
>>>>> reuse same offset. Ashutosh proposed how to join both functionalities
>>>>> (stepping as with reloc, stateful like in simple) but I got no time to
>>>>> code this.
>>>>>
>>>>> Regarding issue here, target_offset passed from the caller is to avoid
>>>>> rebind if get_offset() would be called for "reloc" allocator.
>>>>> So there's not real value offset within bo. I would add separate
>>>>> value_offset (shift) to allow caller to put place where it wants to
>>>>> write the value.
>>>> If you understand what is going on here and how to improve it then feel free
>>>> to either send me an updated version or post an extra patch after this is
>>>> merged. I don't get how any of the new reloc (or anti-reloc?) code is meant
>>>> to work. These patches were all written as part of the GuC support a long
>>>> time ago - before there was any such thing as an AHND (what does that stand
>>>> for?) or intel_ctx_t. All I'm doing in this patch is moving the existing
>>>> code to a helper and trying to make it generic enough to be used by another
>>>> test. And right now, the two tests are passing on both GuC and execlist
>>>> platforms for me. So the code can't be all that broken.
>>> I've added some missing parts to your code:
>>>
>>> https://patchwork.freedesktop.org/series/98242/
>>>
>>> If you think something is missing please add or fix.
>>>
>>> Previously value was used both for value and offset within bo
>>> used for example in gem_exec_fence@basic-await. I think adding
>>> separate arg for offset for value within bo makes this code
>>> more universal.
>> I don't follow. The purpose of the offset is the to say where the value is
>> written within the buffer. As in 'target_offset' is 'offset into target
>> buffer to write value'. You have added a 'value_offset' which surely would
>> be defined as 'the offset at which to write the value in the target buffer'.
>> I.e. exactly the same thing. What is the intention behind having two
>> separate offset variables?
> No, there're not the same thing.
>
>   target_offset
>   ──────────────►┌────────────┐
>   0x201000       │ size = 8K  │
>                  │            │
> value_offset    │            │
> (relative to    │            │
> target_offset)  │            │
> ───────────────►│            │
> 0x1100          │            │
>                  │            │
>                  │            │
>                  │            │
>                  │            │
>                  │            │
>                  └────────────┘
>
> Target_offset is vma start address where object will be bind.
> value_offset is delta from that vma.
Meaning the graphics address? As in, the offset from the start of the 
PPGTT or some such? Surely that should be a part of the object structure 
and specified when the object is created. What is the point of the 
object's handle if it does not specify what object to access? I mean, 
what is an 'object' other than a start address and size / end address? 
The memory mapping details really should not be a parameter to a helper 
function whose purpose is to write a single word to a specific location 
within a pre-existing object. At the very least, it should be called 
obj_gpu_addr or similar. Calling two very different concepts 'offset' is 
totally confusing.

Or am I still completely confused as to what the purpose is?

John.


>
> In execobj.offset you need to put 0x201000, but in bb final offset
> is calculated as target_offset + value_offset.
>
> --
> Zbigniew
>
>> John.
>>
>>
>>> NB: ahnd is short version of allocator_handle
>>>
>>> --
>>> Zbigniew
>>>
>>>>>> +	if (!ahnd) {
>>>>>> +		reloc.target_handle = obj[SCRATCH].handle;
>>>>>> +		reloc.presumed_offset = -1;
>>>>>> +		reloc.offset = sizeof(uint32_t) * (i + 1);
>>>>>> +		reloc.delta = delta;
>>>>>> +		reloc.read_domains = I915_GEM_DOMAIN_INSTRUCTION;
>>>>>> +		reloc.write_domain = I915_GEM_DOMAIN_INSTRUCTION;
>>>>>> +	} else {
>>>>>> +		obj[SCRATCH].offset = target_offset;
>>>>>> +		obj[SCRATCH].flags |= EXEC_OBJECT_PINNED | EXEC_OBJECT_WRITE;
>>>>>> +		obj[BATCH].offset = bb_offset;
>>>>>> +		obj[BATCH].flags |= EXEC_OBJECT_PINNED;
>>>>>> +	}
>>>>>> +	batch[i] = MI_STORE_DWORD_IMM | (gen < 6 ? 1 << 22 : 0);
>>>>>> +	if (gen >= 8) {
>>>>>> +		batch[++i] = target_offset + delta;
>>>>>> +		batch[++i] = target_offset >> 32;
>>>>> Probably I've added this in previous code, for being safe I would
>>>>> add (target_offset + delta) >> 32 for avoid risk passing invalid higher
>>>>> offset part on 32b boundary.
>>>> Pretty sure we don't have any addresses larger than 32 bits yet, but yes,
>>>> delta should be added in.
>>>>
>>>> Thanks,
>>>> John.
>>>>
>>>>>> +	} else if (gen >= 4) {
>>>>>> +		batch[++i] = 0;
>>>>>> +		batch[++i] = delta;
>>>>>> +		reloc.offset += sizeof(uint32_t);
>>>>>> +	} else {
>>>>>> +		batch[i]--;
>>>>>> +		batch[++i] = delta;
>>>>>> +	}
>>>>>> +	batch[++i] = target_value;
>>>>>> +	batch[++i] = MI_BATCH_BUFFER_END;
>>>>>> +	gem_write(fd, obj[BATCH].handle, 0, batch, sizeof(batch));
>>>>>> +	gem_execbuf(fd, &execbuf);
>>>>>> +	gem_close(fd, obj[BATCH].handle);
>>>>>> +	put_offset(ahnd, obj[BATCH].handle);
>>>>>> +}
>>>>>> diff --git a/lib/igt_store.h b/lib/igt_store.h
>>>>>> new file mode 100644
>>>>>> index 000000000..4d5979e07
>>>>>> --- /dev/null
>>>>>> +++ b/lib/igt_store.h
>>>>>> @@ -0,0 +1,30 @@
>>>>>> +/*
>>>>>> + * Copyright © 2020 Intel Corporation
>>>>>> + *
>>>>>> + * Permission is hereby granted, free of charge, to any person obtaining a
>>>>>> + * copy of this software and associated documentation files (the "Software"),
>>>>>> + * to deal in the Software without restriction, including without limitation
>>>>>> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>>>>>> + * and/or sell copies of the Software, and to permit persons to whom the
>>>>>> + * Software is furnished to do so, subject to the following conditions:
>>>>>> + *
>>>>>> + * The above copyright notice and this permission notice (including the next
>>>>>> + * paragraph) shall be included in all copies or substantial portions of the
>>>>>> + * Software.
>>>>>> + *
>>>>>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>>>>>> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>>>>>> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>>>>>> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
>>>>>> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>>>>>> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
>>>>>> + * IN THE SOFTWARE.
>>>>>> + *
>>>>>> + */
>>>>> Use SPDX and 2021.
>>>>>
>>>>> --
>>>>> Zbigniew
>>>>>
>>>>>> +
>>>>>> +#include "igt_gt.h"
>>>>>> +
>>>>>> +void igt_store_word(int fd, uint64_t ahnd, const intel_ctx_t *ctx,
>>>>>> +		    const struct intel_execution_engine2 *e,
>>>>>> +		    int fence, uint32_t target_handle,
>>>>>> +		    uint64_t target_offset, uint32_t target_value);
>>>>>> diff --git a/lib/meson.build b/lib/meson.build
>>>>>> index b9568a71b..3e43316d1 100644
>>>>>> --- a/lib/meson.build
>>>>>> +++ b/lib/meson.build
>>>>>> @@ -72,6 +72,7 @@ lib_sources = [
>>>>>>     	'igt_map.c',
>>>>>>     	'igt_pm.c',
>>>>>>     	'igt_dummyload.c',
>>>>>> +	'igt_store.c',
>>>>>>     	'uwildmat/uwildmat.c',
>>>>>>     	'igt_kmod.c',
>>>>>>     	'igt_panfrost.c',
>>>>>> diff --git a/tests/i915/gem_exec_fence.c b/tests/i915/gem_exec_fence.c
>>>>>> index 9a6336ce9..c4091a454 100644
>>>>>> --- a/tests/i915/gem_exec_fence.c
>>>>>> +++ b/tests/i915/gem_exec_fence.c
>>>>>> @@ -28,6 +28,7 @@
>>>>>>     #include "i915/gem.h"
>>>>>>     #include "i915/gem_create.h"
>>>>>>     #include "igt.h"
>>>>>> +#include "igt_store.h"
>>>>>>     #include "igt_syncobj.h"
>>>>>>     #include "igt_sysfs.h"
>>>>>>     #include "igt_vgem.h"
>>>>>> @@ -57,74 +58,6 @@ struct sync_merge_data {
>>>>>>     #define   MI_SEMAPHORE_SAD_EQ_SDD       (4 << 12)
>>>>>>     #define   MI_SEMAPHORE_SAD_NEQ_SDD      (5 << 12)
>>>>>> -static void store(int fd, uint64_t ahnd, const intel_ctx_t *ctx,
>>>>>> -		  const struct intel_execution_engine2 *e,
>>>>>> -		  int fence, uint32_t target, uint64_t target_offset,
>>>>>> -		  unsigned offset_value)
>>>>>> -{
>>>>>> -	const int SCRATCH = 0;
>>>>>> -	const int BATCH = 1;
>>>>>> -	const unsigned int gen = intel_gen(intel_get_drm_devid(fd));
>>>>>> -	struct drm_i915_gem_exec_object2 obj[2];
>>>>>> -	struct drm_i915_gem_relocation_entry reloc;
>>>>>> -	struct drm_i915_gem_execbuffer2 execbuf;
>>>>>> -	uint32_t batch[16], delta;
>>>>>> -	uint64_t bb_offset;
>>>>>> -	int i;
>>>>>> -
>>>>>> -	memset(&execbuf, 0, sizeof(execbuf));
>>>>>> -	execbuf.buffers_ptr = to_user_pointer(obj);
>>>>>> -	execbuf.buffer_count = 2;
>>>>>> -	execbuf.flags = e->flags | I915_EXEC_FENCE_IN;
>>>>>> -	execbuf.rsvd1 = ctx->id;
>>>>>> -	execbuf.rsvd2 = fence;
>>>>>> -	if (gen < 6)
>>>>>> -		execbuf.flags |= I915_EXEC_SECURE;
>>>>>> -
>>>>>> -	memset(obj, 0, sizeof(obj));
>>>>>> -	obj[SCRATCH].handle = target;
>>>>>> -
>>>>>> -	obj[BATCH].handle = gem_create(fd, 4096);
>>>>>> -	obj[BATCH].relocs_ptr = to_user_pointer(&reloc);
>>>>>> -	obj[BATCH].relocation_count = !ahnd ? 1 : 0;
>>>>>> -	bb_offset = get_offset(ahnd, obj[BATCH].handle, 4096, 0);
>>>>>> -	memset(&reloc, 0, sizeof(reloc));
>>>>>> -
>>>>>> -	i = 0;
>>>>>> -	delta = sizeof(uint32_t) * offset_value;
>>>>>> -	if (!ahnd) {
>>>>>> -		reloc.target_handle = obj[SCRATCH].handle;
>>>>>> -		reloc.presumed_offset = -1;
>>>>>> -		reloc.offset = sizeof(uint32_t) * (i + 1);
>>>>>> -		reloc.delta = delta;
>>>>>> -		reloc.read_domains = I915_GEM_DOMAIN_INSTRUCTION;
>>>>>> -		reloc.write_domain = I915_GEM_DOMAIN_INSTRUCTION;
>>>>>> -	} else {
>>>>>> -		obj[SCRATCH].offset = target_offset;
>>>>>> -		obj[SCRATCH].flags |= EXEC_OBJECT_PINNED | EXEC_OBJECT_WRITE;
>>>>>> -		obj[BATCH].offset = bb_offset;
>>>>>> -		obj[BATCH].flags |= EXEC_OBJECT_PINNED;
>>>>>> -	}
>>>>>> -	batch[i] = MI_STORE_DWORD_IMM | (gen < 6 ? 1 << 22 : 0);
>>>>>> -	if (gen >= 8) {
>>>>>> -		batch[++i] = target_offset + delta;
>>>>>> -		batch[++i] = target_offset >> 32;
>>>>>> -	} else if (gen >= 4) {
>>>>>> -		batch[++i] = 0;
>>>>>> -		batch[++i] = delta;
>>>>>> -		reloc.offset += sizeof(uint32_t);
>>>>>> -	} else {
>>>>>> -		batch[i]--;
>>>>>> -		batch[++i] = delta;
>>>>>> -	}
>>>>>> -	batch[++i] = offset_value;
>>>>>> -	batch[++i] = MI_BATCH_BUFFER_END;
>>>>>> -	gem_write(fd, obj[BATCH].handle, 0, batch, sizeof(batch));
>>>>>> -	gem_execbuf(fd, &execbuf);
>>>>>> -	gem_close(fd, obj[BATCH].handle);
>>>>>> -	put_offset(ahnd, obj[BATCH].handle);
>>>>>> -}
>>>>>> -
>>>>>>     static bool fence_busy(int fence)
>>>>>>     {
>>>>>>     	return poll(&(struct pollfd){fence, POLLIN}, 1, 0) == 0;
>>>>>> @@ -400,13 +333,13 @@ static void test_fence_await(int fd, const intel_ctx_t *ctx,
>>>>>>     			continue;
>>>>>>     		if (flags & NONBLOCK) {
>>>>>> -			store(fd, ahnd, ctx, e2, spin->out_fence,
>>>>>> -			      scratch, scratch_offset, i);
>>>>>> +			igt_store_word(fd, ahnd, ctx, e2, spin->out_fence,
>>>>>> +				       scratch, scratch_offset, i);
>>>>>>     		} else {
>>>>>>     			igt_fork(child, 1) {
>>>>>>     				ahnd = get_reloc_ahnd(fd, ctx->id);
>>>>>> -				store(fd, ahnd, ctx, e2, spin->out_fence,
>>>>>> -				      scratch, scratch_offset, i);
>>>>>> +				igt_store_word(fd, ahnd, ctx, e2, spin->out_fence,
>>>>>> +					       scratch, scratch_offset, i);
>>>>>>     				put_ahnd(ahnd);
>>>>>>     			}
>>>>>>     		}
>>>>>> diff --git a/tests/i915/i915_hangman.c b/tests/i915/i915_hangman.c
>>>>>> index 20653b479..4cb9b8b85 100644
>>>>>> --- a/tests/i915/i915_hangman.c
>>>>>> +++ b/tests/i915/i915_hangman.c
>>>>>> @@ -36,6 +36,7 @@
>>>>>>     #include "i915/gem.h"
>>>>>>     #include "i915/gem_create.h"
>>>>>>     #include "igt.h"
>>>>>> +#include "igt_store.h"
>>>>>>     #include "igt_sysfs.h"
>>>>>>     #include "igt_debugfs.h"
>>>>>>     #include "sw_sync.h"
>>>>>> @@ -51,64 +52,6 @@ static int sysfs = -1;
>>>>>>     IGT_TEST_DESCRIPTION("Tests for hang detection and recovery");
>>>>>> -/* Requires master for STORE_DWORD on gen4/5 */
>>>>>> -static void store(int fd, const struct intel_execution_engine2 *e,
>>>>>> -		  int fence, uint32_t target, unsigned offset_value)
>>>>>> -{
>>>>>> -	const int SCRATCH = 0;
>>>>>> -	const int BATCH = 1;
>>>>>> -	const int gen = intel_gen(intel_get_drm_devid(fd));
>>>>>> -	struct drm_i915_gem_exec_object2 obj[2];
>>>>>> -	struct drm_i915_gem_relocation_entry reloc;
>>>>>> -	struct drm_i915_gem_execbuffer2 execbuf;
>>>>>> -	uint32_t batch[16];
>>>>>> -	int i;
>>>>>> -
>>>>>> -	memset(&execbuf, 0, sizeof(execbuf));
>>>>>> -	execbuf.buffers_ptr = to_user_pointer(obj);
>>>>>> -	execbuf.buffer_count = ARRAY_SIZE(obj);
>>>>>> -	execbuf.flags = e->flags;
>>>>>> -	if (fence != -1) {
>>>>>> -		execbuf.flags |= I915_EXEC_FENCE_IN;
>>>>>> -		execbuf.rsvd2 = fence;
>>>>>> -	}
>>>>>> -	if (gen < 6)
>>>>>> -		execbuf.flags |= I915_EXEC_SECURE;
>>>>>> -
>>>>>> -	memset(obj, 0, sizeof(obj));
>>>>>> -	obj[SCRATCH].handle = target;
>>>>>> -
>>>>>> -	obj[BATCH].handle = gem_create(fd, 4096);
>>>>>> -	obj[BATCH].relocs_ptr = to_user_pointer(&reloc);
>>>>>> -	obj[BATCH].relocation_count = 1;
>>>>>> -	memset(&reloc, 0, sizeof(reloc));
>>>>>> -
>>>>>> -	i = 0;
>>>>>> -	reloc.target_handle = obj[SCRATCH].handle;
>>>>>> -	reloc.presumed_offset = -1;
>>>>>> -	reloc.offset = sizeof(uint32_t) * (i + 1);
>>>>>> -	reloc.delta = sizeof(uint32_t) * offset_value;
>>>>>> -	reloc.read_domains = I915_GEM_DOMAIN_INSTRUCTION;
>>>>>> -	reloc.write_domain = I915_GEM_DOMAIN_INSTRUCTION;
>>>>>> -	batch[i] = MI_STORE_DWORD_IMM | (gen < 6 ? 1 << 22 : 0);
>>>>>> -	if (gen >= 8) {
>>>>>> -		batch[++i] = reloc.delta;
>>>>>> -		batch[++i] = 0;
>>>>>> -	} else if (gen >= 4) {
>>>>>> -		batch[++i] = 0;
>>>>>> -		batch[++i] = reloc.delta;
>>>>>> -		reloc.offset += sizeof(uint32_t);
>>>>>> -	} else {
>>>>>> -		batch[i]--;
>>>>>> -		batch[++i] = reloc.delta;
>>>>>> -	}
>>>>>> -	batch[++i] = offset_value;
>>>>>> -	batch[++i] = MI_BATCH_BUFFER_END;
>>>>>> -	gem_write(fd, obj[BATCH].handle, 0, batch, sizeof(batch));
>>>>>> -	gem_execbuf(fd, &execbuf);
>>>>>> -	gem_close(fd, obj[BATCH].handle);
>>>>>> -}
>>>>>> -
>>>>>>     static void check_alive(void)
>>>>>>     {
>>>>>>     	const struct intel_execution_engine2 *engine;
>>>>>> @@ -138,7 +81,7 @@ static void check_alive(void)
>>>>>>     			continue;
>>>>>>     		/* +OFFSET_ALIVE to ensure engine zero doesn't get a false negative */
>>>>>> -		store(fd, engine, -1, scratch, i + OFFSET_ALIVE);
>>>>>> +		igt_store_word(fd, ahnd, ctx, engine, -1, scratch, i + OFFSET_ALIVE, i + OFFSET_ALIVE);
>>>>>>     		i++;
>>>>>>     	}
>>>>>> -- 
>>>>>> 2.25.1
>>>>>>