From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-0.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4D5FDC3A59C for ; Fri, 16 Aug 2019 06:30:16 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id EEB8D2077C for ; Fri, 16 Aug 2019 06:30:15 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org EEB8D2077C Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=bt.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:49722 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1hyVkd-0000vc-2j for qemu-devel@archiver.kernel.org; Fri, 16 Aug 2019 02:30:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:57625) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1hyVjK-0008BT-DL for qemu-devel@nongnu.org; Fri, 16 Aug 2019 02:28:57 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hyVjH-0002Ib-7q for qemu-devel@nongnu.org; Fri, 16 Aug 2019 02:28:54 -0400 Received: from smtpe1.intersmtp.com ([213.121.35.74]:5202) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hyVjG-0002HU-S8; Fri, 16 Aug 2019 02:28:51 -0400 Received: from tpw09926dag18g.domain1.systemhost.net (10.9.212.34) by BWP09926079.bt.com (10.36.82.110) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.1713.5; Fri, 16 Aug 2019 07:28:25 +0100 Received: from tpw09926dag18e.domain1.systemhost.net (10.9.212.18) by tpw09926dag18g.domain1.systemhost.net (10.9.212.34) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Fri, 16 Aug 2019 07:28:47 +0100 Received: from tpw09926dag18e.domain1.systemhost.net ([fe80::a946:6348:ccf4:fa6c]) by tpw09926dag18e.domain1.systemhost.net ([fe80::a946:6348:ccf4:fa6c%12]) with mapi id 15.00.1395.000; Fri, 16 Aug 2019 07:28:47 +0100 From: To: Thread-Topic: [Qemu-devel] [PATCH v7 00/42] Invert Endian bit in SPARCv9 MMU TTE Thread-Index: AQHVU/vc8DdfhK3ulkmWv148s0Uozg== Date: Fri, 16 Aug 2019 06:28:47 +0000 Message-ID: <43bc5e07ac614d0e8e740bf6007ff77b@tpw09926dag18e.domain1.systemhost.net> Accept-Language: en-AU, en-GB, en-US Content-Language: en-AU X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-exchange-messagesentrepresentingtype: 1 x-ms-exchange-transport-fromentityheader: Hosted x-originating-ip: [10.187.101.40] Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Windows 7 or 8 [fuzzy] X-Received-From: 213.121.35.74 Subject: [Qemu-devel] [PATCH v7 00/42] Invert Endian bit in SPARCv9 MMU TTE X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: frederic.konrad@adacore.com, berto@igalia.com, qemu-block@nongnu.org, arikalo@wavecomp.com, pasic@linux.ibm.com, hpoussin@reactos.org, anthony.perard@citrix.com, xen-devel@lists.xenproject.org, lersek@redhat.com, jasowang@redhat.com, jiri@resnulli.us, ehabkost@redhat.com, b.galvani@gmail.com, eric.auger@redhat.com, alex.williamson@redhat.com, stefanha@redhat.com, jsnow@redhat.com, rth@twiddle.net, kwolf@redhat.com, andrew@aj.id.au, claudio.fontana@suse.com, crwulff@gmail.com, laurent@vivier.eu, sundeep.lkml@gmail.com, michael@walle.cc, qemu-ppc@nongnu.org, kbastian@mail.uni-paderborn.de, imammedo@redhat.com, fam@euphon.net, peter.maydell@linaro.org, david@redhat.com, palmer@sifive.com, keith.busch@intel.com, jcmvbkbc@gmail.com, hare@suse.com, sstabellini@kernel.org, andrew.smirnov@gmail.com, deller@gmx.de, magnus.damm@gmail.com, atar4qemu@gmail.com, minyard@acm.org, sw@weilnetz.de, yuval.shaia@oracle.com, qemu-s390x@nongnu.org, qemu-arm@nongnu.org, jan.kiszka@web.de, clg@kaod.org, shorne@gmail.com, qemu-riscv@nongnu.org, i.mitsyanko@gmail.com, cohuck@redhat.com, philmd@redhat.com, amarkovic@wavecomp.com, peter.chubb@nicta.com.au, aurelien@aurel32.net, pburton@wavecomp.com, sagark@eecs.berkeley.edu, green@moxielogic.com, kraxel@redhat.com, edgar.iglesias@gmail.com, gxt@mprc.pku.edu.cn, robh@kernel.org, borntraeger@de.ibm.com, joel@jms.id.au, antonynpavlov@gmail.com, chouteau@adacore.com, Andrew.Baumann@microsoft.com, mreitz@redhat.com, walling@linux.ibm.com, dmitry.fleytman@gmail.com, mst@redhat.com, mark.cave-ayland@ilande.co.uk, jslaby@suse.cz, marex@denx.de, proljc@gmail.com, marcandre.lureau@redhat.com, alistair@alistair23.me, paul.durrant@citrix.com, david@gibson.dropbear.id.au, xiaoguangrong.eric@gmail.com, huth@tuxfamily.org, jcd@tribudubois.net, pbonzini@redhat.com, stefanb@linux.ibm.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" This patchset implements the IE (Invert Endian) bit in SPARCv9 MMU TTE.=0A= =0A= It is an attempt of the instructions outlined by Richard Henderson to Mark= =0A= Cave-Ayland.=0A= =0A= Tested with OpenBSD on sun4u. Solaris 10 is my actual goal, but unfortunate= ly a=0A= separate keyboard issue remains in the way.=0A= =0A= On 01/11/17 19:15, Mark Cave-Ayland wrote:=0A= =0A= >On 15/08/17 19:10, Richard Henderson wrote:=0A= >=0A= >> [CC Peter re MemTxAttrs below]=0A= >>=0A= >> On 08/15/2017 09:38 AM, Mark Cave-Ayland wrote:=0A= >>> Working through an incorrect endian issue on qemu-system-sparc64, it ha= s=0A= >>> become apparent that at least one OS makes use of the IE (Invert Endian= )=0A= >>> bit in the SPARCv9 MMU TTE to map PCI memory space without the=0A= >>> programmer having to manually endian-swap accesses.=0A= >>>=0A= >>> In other words, to quote the UltraSPARC specification: "if this bit is= =0A= >>> set, accesses to the associated page are processed with inverse=0A= >>> endianness from what is specified by the instruction (big-for-little an= d=0A= >>> little-for-big)".=0A= =0A= A good explanation by Mark why the IE bit is required.=0A= =0A= >>>=0A= >>> Looking through various bits of code, I'm trying to get a feel for the= =0A= >>> best way to implement this in an efficient manner. From what I can see= =0A= >>> this could be solved using an additional MMU index, however I'm not=0A= >>> overly familiar with the memory and softmmu subsystems.=0A= >>=0A= >> No, it can't be solved with an MMU index.=0A= >>=0A= >>> Can anyone point me in the right direction as to what would be the best= =0A= >>> way to implement this feature within QEMU?=0A= >>=0A= >> It's definitely tricky.=0A= >>=0A= >> We definitely need some TLB_FLAGS_MASK bit set so that we're forced thro= ugh=0A= >> the=0A= >> memory slow path. There is no other way to bypass the endianness that w= e've=0A= >> already encoded from the target instruction.=0A= >>=0A= >> Given the tlb_set_page_with_attrs interface, I would think that we need = a new=0A= >> bit in MemTxAttrs, so that the target/sparc tlb_fill (and subroutines) c= an=0A= >> pass=0A= >> along the TTE bit for the given page.=0A= >>=0A= >> We have an existing problem in softmmu_template.h,=0A= >>=0A= >> /* ??? Note that the io helpers always read data in the target=0A= >> byte ordering. We should push the LE/BE request down into io. *= /=0A= >> res =3D glue(io_read, SUFFIX)(env, mmu_idx, index, addr, retaddr);= =0A= >> res =3D TGT_BE(res);=0A= >>=0A= >> We do not want to add a third(!) byte swap along the i/o path. We need = to=0A= >> collapse the two that we have already before considering this one.=0A= >>=0A= >> This probably takes the form of:=0A= >>=0A= >> (1) Replacing the "int size" argument with "TCGMemOp memop" for=0A= >> a) io_{read,write}x in accel/tcg/cputlb.c,=0A= >> b) memory_region_dispatch_{read,write} in memory.c,=0A= >> c) adjust_endianness in memory.c.=0A= >> This carries size+sign+endianness down to the next level.=0A= >>=0A= >> (2) In memory.c, adjust_endianness,=0A= >>=0A= >> if (memory_region_wrong_endianness(mr)) {=0A= >> - switch (size) {=0A= >> + memop ^=3D MO_BSWAP;=0A= >> + }=0A= >> + if (memop & MO_BSWAP) {=0A= >>=0A= >> For extra credit, re-arrange memory_region_wrong_endianness=0A= >> to something more explicit -- "wrong" isn't helpful.=0A= >=0A= >Finally I've had a bit of spare time to experiment with this approach,=0A= >and from what I can see there are currently 2 issues:=0A= >=0A= >=0A= >1) Using TCGMemOp in memory.c means it is no longer accelerator agnostic= =0A= >=0A= >For the moment I've defined a separate MemOp in memory.h and provided a=0A= >mapping function in io_{read,write}x to map from TCGMemOp to MemOp and=0A= >then pass that into memory_region_dispatch_{read,write}.=0A= >=0A= >Other than not referencing TCGMemOp in the memory API, another reason=0A= >for doing this was that I wasn't convinced that all the MO_ attributes=0A= >were valid outside of TCG. I do, of course, strongly defer to other=0A= >people's knowledge in this area though.=0A= >=0A= >=0A= >2) The above changes to adjust_endianness() fail when=0A= >memory_region_dispatch_{read,write} are called recursively=0A= >=0A= >Whilst booting qemu-system-sparc64 I see that=0A= >memory_region_dispatch_{read,write} get called recursively - once via=0A= >io_{read,write}x and then again via flatview_read_continue() in exec.c.=0A= >=0A= >The net effect of this is that we perform the bswap correctly at the=0A= >tail of the recursion, but then as we travel back up the stack we hit=0A= >memory_region_dispatch_{read,write} once again causing a second bswap=0A= >which means the value is returned with the incorrect endian again.=0A= >=0A= >=0A= >My understanding from your softmmu_template.h comment above is that the=0A= >memory API should do the endian swapping internally allowing the removal= =0A= >of the final TGT_BE/TGT_LE applied to the result, or did I get this wrong?= =0A= >=0A= >> (3) In tlb_set_page_with_attrs, notice attrs.byte_swap and set=0A= >> a new TLB_FORCE_SLOW bit within TLB_FLAGS_MASK.=0A= >>=0A= >> (4) In io_{read,write}x, if iotlbentry->attrs.byte_swap is set,=0A= >> then memop ^=3D MO_BSWAP.=0A= =0A= Thanks all for the feedback. Learnt a lot =3D)=0A= =0A= v2:=0A= - Moved size+sign+endianness attributes from TCGMemOp into MemOp.=0A= In v1 TCGMemOp was re-purposed entirely into MemOp.=0A= - Replaced MemOp MO_{8|16|32|64} with TCGMemOp MO_{UB|UW|UL|UQ} alias.=0A= This is to avoid warnings on comparing and coercing different enums.=0A= - Renamed get_memop to get_tcgmemop for clarity.=0A= - MEMOP is now SIZE_MEMOP, which is just ctzl(size).=0A= - Split patch 3/4 so one memory_region_dispatch_{read|write} interface=0A= is converted per patch.=0A= - Do not reuse TLB_RECHECK, use new TLB_FORCE_SLOW instead.=0A= - Split patch 4/4 so adding the MemTxAddrs parameters and converting=0A= tlb_set_page() to tlb_set_page_with_attrs() is separate from usage.=0A= - CC'd maintainers.=0A= =0A= v3:=0A= - Like v1, the entire TCGMemOp enum is now MemOp.=0A= - MemOp target dependant attributes are conditional upon NEED_CPU_H=0A= =0A= v4:=0A= - Added Paolo Bonzini as include/exec/memop.h maintainer=0A= =0A= v5:=0A= - Improved commit messages to clarify how interface to access=0A= MemoryRegion will be converted from "unsigned size" to "MemOp op".=0A= - Moved cpu_transaction_failed() MemOp conversion from patch #11 to #9=0A= to make review easier.=0A= =0A= v6:=0A= - Improved commit messages.=0A= - Include as patch #1 an earlier posted TARGET_ALIGNED_ONLY configure patch= .=0A= - Typeless macro SIZE_MEMOP is now inline.=0A= - size_memop now includes CONFIG_DEBUG_TCG code.=0A= - size_memop now also encodes endianness via MO_TE.=0A= - Reverted size_memop operand "unsigned long" back to "unsigned".=0A= - Second pass of size_memop to replace no-op place holder with MO_{8|16|32|= 64}.=0A= - Delay memory_region_dispatch_{read,write} operand conversion until no-op= =0A= size_memop is implemented so we have proper typing at all points in betwe= en.=0A= - Fixed bug where not all memory_region_dispatch_{read,write} callers where= =0A= encoding endianness into the MemOp operand, see patch #20.=0A= - Fixed bug where not all memory_region_dispatch_{read,write} callers were= =0A= collapsing their byte swap into adjust_endianness, see patch #20 and #22.= =0A= - Split byte swap collapsing patch (v5 #11) into #21 and #22.=0A= - Corrected non-common *-common-obj to *-obj.=0A= - Replaced enum device_endian with MemOp to simplify endianness checks. A= =0A= straight forward sed but touched *alot* of files. See patch #16 and #17.= =0A= - Deleted enum device_endian.=0A= - Deleted DEVICE_HOST_ENDIAN definition.=0A= - Generalized the description of introduced MemTxAttrs attribute byte_swap.= =0A= =0A= v7:=0A= - Fixed bug where size_memop was implicitly encoding MO_TE. Endianness,=0A= {MO_TE|MO_BE|MO_LE}, is now explicitly encoded by MemoryRegion accessors.= =0A= - While a no-op, size_memop return type remains an unsigned.=0A= - Use '=3D 0' short hand instead of macro logic to declare host endianness.= =0A= - With a new set of constant arguments, sanity checked the compiler is stil= l=0A= folding away tests in cputlb.c=0A= - Re-declared many native endian devices as little or big endian. This is w= hy=0A= v7 has +16 patches.=0A= =0A= Tony Nguyen (42):=0A= configure: Define TARGET_ALIGNED_ONLY in configure=0A= tcg: TCGMemOp is now accelerator independent MemOp=0A= memory: Introduce size_memop=0A= target/mips: Access MemoryRegion with MemOp=0A= hw/s390x: Access MemoryRegion with MemOp=0A= hw/intc/armv7m_nic: Access MemoryRegion with MemOp=0A= hw/virtio: Access MemoryRegion with MemOp=0A= hw/vfio: Access MemoryRegion with MemOp=0A= exec: Access MemoryRegion with MemOp=0A= cputlb: Access MemoryRegion with MemOp=0A= memory: Access MemoryRegion with MemOp=0A= hw/s390x: Hard code size with MO_{8|16|32|64}=0A= target/mips: Hard code size with MO_{8|16|32|64}=0A= exec: Hard code size with MO_{8|16|32|64}=0A= hw/audio: Declare device little or big endian=0A= hw/block: Declare device little or big endian=0A= hw/char: Declare device little or big endian=0A= hw/display: Declare device little or big endian=0A= hw/dma: Declare device little or big endian=0A= hw/gpio: Declare device little or big endian=0A= hw/i2c: Declare device little or big endian=0A= hw/input: Declare device little or big endian=0A= hw/intc: Declare device little or big endian=0A= hw/isa: Declare device little or big endian=0A= hw/misc: Declare device little or big endian=0A= hw/net: Declare device little or big endian=0A= hw/pci-host: Declare device little or big endian=0A= hw/sd: Declare device little or big endian=0A= hw/ssi: Declare device little or big endian=0A= hw/timer: Declare device little or big endian=0A= build: Correct non-common common-obj-* to obj-*=0A= exec: Map device_endian onto MemOp=0A= exec: Replace device_endian with MemOp=0A= exec: Delete device_endian=0A= exec: Delete DEVICE_HOST_ENDIAN=0A= memory: Access MemoryRegion with endianness=0A= cputlb: Replace size and endian operands for MemOp=0A= memory: Single byte swap along the I/O path=0A= cpu: TLB_FLAGS_MASK bit to force memory slow path=0A= cputlb: Byte swap memory transaction attribute=0A= target/sparc: Add TLB entry with attributes=0A= target/sparc: sun4u Invert Endian TTE bit=0A= =0A= MAINTAINERS | 1 +=0A= accel/tcg/cputlb.c | 197 ++++++++++++++--------------= ----=0A= configure | 10 +-=0A= exec.c | 15 ++-=0A= hw/acpi/core.c | 6 +-=0A= hw/acpi/cpu.c | 2 +-=0A= hw/acpi/cpu_hotplug.c | 2 +-=0A= hw/acpi/ich9.c | 4 +-=0A= hw/acpi/memory_hotplug.c | 2 +-=0A= hw/acpi/nvdimm.c | 2 +-=0A= hw/acpi/pcihp.c | 2 +-=0A= hw/acpi/piix4.c | 2 +-=0A= hw/acpi/tco.c | 2 +-=0A= hw/adc/stm32f2xx_adc.c | 2 +-=0A= hw/alpha/pci.c | 6 +-=0A= hw/alpha/typhoon.c | 6 +-=0A= hw/arm/allwinner-a10.c | 2 +-=0A= hw/arm/armv7m.c | 2 +-=0A= hw/arm/aspeed.c | 2 +-=0A= hw/arm/aspeed_soc.c | 2 +-=0A= hw/arm/exynos4210.c | 2 +-=0A= hw/arm/highbank.c | 2 +-=0A= hw/arm/integratorcp.c | 6 +-=0A= hw/arm/kzm.c | 2 +-=0A= hw/arm/msf2-soc.c | 2 +-=0A= hw/arm/musicpal.c | 20 ++--=0A= hw/arm/omap1.c | 40 +++----=0A= hw/arm/omap2.c | 10 +-=0A= hw/arm/omap_sx1.c | 2 +-=0A= hw/arm/palm.c | 2 +-=0A= hw/arm/pxa2xx.c | 20 ++--=0A= hw/arm/pxa2xx_gpio.c | 2 +-=0A= hw/arm/pxa2xx_pic.c | 2 +-=0A= hw/arm/smmuv3.c | 2 +-=0A= hw/arm/spitz.c | 2 +-=0A= hw/arm/stellaris.c | 8 +-=0A= hw/arm/strongarm.c | 12 +-=0A= hw/arm/versatilepb.c | 2 +-=0A= hw/audio/Makefile.objs | 3 +-=0A= hw/audio/ac97.c | 4 +-=0A= hw/audio/cs4231.c | 2 +-=0A= hw/audio/es1370.c | 2 +-=0A= hw/audio/intel-hda.c | 2 +-=0A= hw/audio/marvell_88w8618.c | 2 +-=0A= hw/audio/milkymist-ac97.c | 2 +-=0A= hw/audio/pl041.c | 2 +-=0A= hw/block/Makefile.objs | 6 +-=0A= hw/block/fdc.c | 4 +-=0A= hw/block/nvme.c | 4 +-=0A= hw/block/onenand.c | 2 +-=0A= hw/block/pflash_cfi01.c | 2 +-=0A= hw/block/pflash_cfi02.c | 2 +-=0A= hw/char/Makefile.objs | 4 +-=0A= hw/char/bcm2835_aux.c | 2 +-=0A= hw/char/cadence_uart.c | 2 +-=0A= hw/char/cmsdk-apb-uart.c | 2 +-=0A= hw/char/debugcon.c | 2 +-=0A= hw/char/digic-uart.c | 2 +-=0A= hw/char/escc.c | 2 +-=0A= hw/char/etraxfs_ser.c | 2 +-=0A= hw/char/exynos4210_uart.c | 2 +-=0A= hw/char/grlib_apbuart.c | 2 +-=0A= hw/char/imx_serial.c | 2 +-=0A= hw/char/lm32_uart.c | 2 +-=0A= hw/char/mcf_uart.c | 2 +-=0A= hw/char/milkymist-uart.c | 2 +-=0A= hw/char/nrf51_uart.c | 2 +-=0A= hw/char/omap_uart.c | 6 +-=0A= hw/char/parallel.c | 2 +-=0A= hw/char/pl011.c | 2 +-=0A= hw/char/serial.c | 26 ++---=0A= hw/char/sh_serial.c | 2 +-=0A= hw/char/stm32f2xx_usart.c | 2 +-=0A= hw/char/xilinx_uartlite.c | 2 +-=0A= hw/core/Makefile.objs | 2 +-=0A= hw/core/empty_slot.c | 2 +-=0A= hw/cris/axis_dev88.c | 4 +-=0A= hw/display/Makefile.objs | 6 +-=0A= hw/display/ati.c | 2 +-=0A= hw/display/bcm2835_fb.c | 2 +-=0A= hw/display/bochs-display.c | 4 +-=0A= hw/display/cg3.c | 2 +-=0A= hw/display/cirrus_vga.c | 10 +-=0A= hw/display/edid-region.c | 2 +-=0A= hw/display/exynos4210_fimd.c | 2 +-=0A= hw/display/g364fb.c | 2 +-=0A= hw/display/jazz_led.c | 2 +-=0A= hw/display/milkymist-tmu2.c | 2 +-=0A= hw/display/milkymist-vgafb.c | 2 +-=0A= hw/display/omap_dss.c | 10 +-=0A= hw/display/omap_lcdc.c | 2 +-=0A= hw/display/pl110.c | 2 +-=0A= hw/display/pxa2xx_lcd.c | 2 +-=0A= hw/display/sm501.c | 10 +-=0A= hw/display/tc6393xb.c | 2 +-=0A= hw/display/tcx.c | 14 +--=0A= hw/display/vga-isa-mm.c | 2 +-=0A= hw/display/vga-pci.c | 6 +-=0A= hw/display/vga.c | 2 +-=0A= hw/display/vmware_vga.c | 2 +-=0A= hw/display/xlnx_dp.c | 8 +-=0A= hw/dma/Makefile.objs | 6 +-=0A= hw/dma/bcm2835_dma.c | 4 +-=0A= hw/dma/etraxfs_dma.c | 2 +-=0A= hw/dma/i8257.c | 4 +-=0A= hw/dma/omap_dma.c | 4 +-=0A= hw/dma/pl080.c | 2 +-=0A= hw/dma/pl330.c | 2 +-=0A= hw/dma/puv3_dma.c | 2 +-=0A= hw/dma/pxa2xx_dma.c | 2 +-=0A= hw/dma/rc4030.c | 4 +-=0A= hw/dma/sparc32_dma.c | 2 +-=0A= hw/dma/xilinx_axidma.c | 2 +-=0A= hw/dma/xlnx-zdma.c | 2 +-=0A= hw/dma/xlnx-zynq-devcfg.c | 2 +-=0A= hw/dma/xlnx_dpdma.c | 2 +-=0A= hw/gpio/Makefile.objs | 2 +-=0A= hw/gpio/bcm2835_gpio.c | 2 +-=0A= hw/gpio/imx_gpio.c | 2 +-=0A= hw/gpio/mpc8xxx.c | 2 +-=0A= hw/gpio/nrf51_gpio.c | 2 +-=0A= hw/gpio/omap_gpio.c | 6 +-=0A= hw/gpio/pl061.c | 2 +-=0A= hw/gpio/puv3_gpio.c | 2 +-=0A= hw/gpio/zaurus.c | 2 +-=0A= hw/hppa/dino.c | 6 +-=0A= hw/hppa/machine.c | 2 +-=0A= hw/hppa/pci.c | 6 +-=0A= hw/hyperv/hyperv_testdev.c | 2 +-=0A= hw/i2c/Makefile.objs | 2 +-=0A= hw/i2c/aspeed_i2c.c | 4 +-=0A= hw/i2c/exynos4210_i2c.c | 2 +-=0A= hw/i2c/imx_i2c.c | 2 +-=0A= hw/i2c/microbit_i2c.c | 2 +-=0A= hw/i2c/mpc_i2c.c | 2 +-=0A= hw/i2c/omap_i2c.c | 2 +-=0A= hw/i2c/pm_smbus.c | 2 +-=0A= hw/i2c/ppc4xx_i2c.c | 2 +-=0A= hw/i2c/versatile_i2c.c | 2 +-=0A= hw/i386/amd_iommu.c | 4 +-=0A= hw/i386/intel_iommu.c | 4 +-=0A= hw/i386/kvm/apic.c | 2 +-=0A= hw/i386/kvmvapic.c | 2 +-=0A= hw/i386/pc.c | 6 +-=0A= hw/i386/vmport.c | 2 +-=0A= hw/i386/xen/xen_apic.c | 2 +-=0A= hw/i386/xen/xen_platform.c | 4 +-=0A= hw/i386/xen/xen_pvdevice.c | 2 +-=0A= hw/ide/ahci-allwinner.c | 2 +-=0A= hw/ide/ahci.c | 4 +-=0A= hw/ide/macio.c | 2 +-=0A= hw/ide/mmio.c | 4 +-=0A= hw/ide/pci.c | 6 +-=0A= hw/ide/sii3112.c | 2 +-=0A= hw/input/Makefile.objs | 2 +-=0A= hw/input/milkymist-softusb.c | 2 +-=0A= hw/input/pckbd.c | 6 +-=0A= hw/input/pl050.c | 2 +-=0A= hw/input/pxa2xx_keypad.c | 2 +-=0A= hw/intc/Makefile.objs | 6 +-=0A= hw/intc/allwinner-a10-pic.c | 2 +-=0A= hw/intc/apic.c | 2 +-=0A= hw/intc/arm_gic.c | 12 +-=0A= hw/intc/arm_gicv2m.c | 2 +-=0A= hw/intc/arm_gicv3.c | 4 +-=0A= hw/intc/arm_gicv3_its_common.c | 2 +-=0A= hw/intc/armv7m_nvic.c | 19 +--=0A= hw/intc/aspeed_vic.c | 2 +-=0A= hw/intc/bcm2835_ic.c | 2 +-=0A= hw/intc/bcm2836_control.c | 2 +-=0A= hw/intc/etraxfs_pic.c | 2 +-=0A= hw/intc/exynos4210_combiner.c | 2 +-=0A= hw/intc/grlib_irqmp.c | 2 +-=0A= hw/intc/heathrow_pic.c | 2 +-=0A= hw/intc/imx_avic.c | 2 +-=0A= hw/intc/imx_gpcv2.c | 2 +-=0A= hw/intc/ioapic.c | 2 +-=0A= hw/intc/mips_gic.c | 2 +-=0A= hw/intc/omap_intc.c | 4 +-=0A= hw/intc/ompic.c | 2 +-=0A= hw/intc/openpic.c | 20 ++--=0A= hw/intc/openpic_kvm.c | 2 +-=0A= hw/intc/pl190.c | 2 +-=0A= hw/intc/pnv_xive.c | 14 +--=0A= hw/intc/puv3_intc.c | 2 +-=0A= hw/intc/sh_intc.c | 2 +-=0A= hw/intc/slavio_intctl.c | 4 +-=0A= hw/intc/xics_pnv.c | 2 +-=0A= hw/intc/xilinx_intc.c | 2 +-=0A= hw/intc/xive.c | 6 +-=0A= hw/intc/xlnx-pmu-iomod-intc.c | 2 +-=0A= hw/intc/xlnx-zynqmp-ipi.c | 2 +-=0A= hw/ipack/Makefile.objs | 2 +-=0A= hw/ipack/tpci200.c | 10 +-=0A= hw/ipmi/isa_ipmi_bt.c | 2 +-=0A= hw/ipmi/isa_ipmi_kcs.c | 2 +-=0A= hw/isa/lpc_ich9.c | 4 +-=0A= hw/isa/pc87312.c | 2 +-=0A= hw/isa/vt82c686.c | 2 +-=0A= hw/m68k/mcf5206.c | 2 +-=0A= hw/m68k/mcf5208.c | 4 +-=0A= hw/m68k/mcf_intc.c | 2 +-=0A= hw/microblaze/petalogix_ml605_mmu.c | 2 +-=0A= hw/mips/boston.c | 6 +-=0A= hw/mips/gt64xxx_pci.c | 2 +-=0A= hw/mips/mips_jazz.c | 8 +-=0A= hw/mips/mips_malta.c | 4 +-=0A= hw/mips/mips_r4k.c | 2 +-=0A= hw/misc/Makefile.objs | 10 +-=0A= hw/misc/a9scu.c | 2 +-=0A= hw/misc/applesmc.c | 6 +-=0A= hw/misc/arm11scu.c | 2 +-=0A= hw/misc/arm_integrator_debug.c | 2 +-=0A= hw/misc/arm_l2x0.c | 2 +-=0A= hw/misc/arm_sysctl.c | 2 +-=0A= hw/misc/armsse-cpuid.c | 2 +-=0A= hw/misc/armsse-mhu.c | 2 +-=0A= hw/misc/aspeed_scu.c | 2 +-=0A= hw/misc/aspeed_sdmc.c | 2 +-=0A= hw/misc/aspeed_xdma.c | 2 +-=0A= hw/misc/bcm2835_mbox.c | 2 +-=0A= hw/misc/bcm2835_property.c | 2 +-=0A= hw/misc/bcm2835_rng.c | 2 +-=0A= hw/misc/debugexit.c | 2 +-=0A= hw/misc/eccmemctl.c | 4 +-=0A= hw/misc/edu.c | 2 +-=0A= hw/misc/exynos4210_clk.c | 2 +-=0A= hw/misc/exynos4210_pmu.c | 2 +-=0A= hw/misc/exynos4210_rng.c | 2 +-=0A= hw/misc/grlib_ahb_apb_pnp.c | 4 +-=0A= hw/misc/imx25_ccm.c | 2 +-=0A= hw/misc/imx2_wdt.c | 2 +-=0A= hw/misc/imx31_ccm.c | 2 +-=0A= hw/misc/imx6_ccm.c | 4 +-=0A= hw/misc/imx6_src.c | 2 +-=0A= hw/misc/imx6ul_ccm.c | 4 +-=0A= hw/misc/imx7_ccm.c | 4 +-=0A= hw/misc/imx7_gpr.c | 2 +-=0A= hw/misc/imx7_snvs.c | 2 +-=0A= hw/misc/iotkit-secctl.c | 4 +-=0A= hw/misc/iotkit-sysctl.c | 2 +-=0A= hw/misc/iotkit-sysinfo.c | 2 +-=0A= hw/misc/ivshmem.c | 2 +-=0A= hw/misc/macio/cuda.c | 2 +-=0A= hw/misc/macio/gpio.c | 2 +-=0A= hw/misc/macio/mac_dbdma.c | 2 +-=0A= hw/misc/macio/macio.c | 2 +-=0A= hw/misc/macio/pmu.c | 2 +-=0A= hw/misc/milkymist-hpdmc.c | 2 +-=0A= hw/misc/milkymist-pfpu.c | 2 +-=0A= hw/misc/mips_cmgcr.c | 2 +-=0A= hw/misc/mips_cpc.c | 2 +-=0A= hw/misc/mips_itu.c | 4 +-=0A= hw/misc/mos6522.c | 2 +-=0A= hw/misc/mps2-fpgaio.c | 2 +-=0A= hw/misc/mps2-scc.c | 2 +-=0A= hw/misc/msf2-sysreg.c | 2 +-=0A= hw/misc/mst_fpga.c | 2 +-=0A= hw/misc/nrf51_rng.c | 2 +-=0A= hw/misc/omap_gpmc.c | 6 +-=0A= hw/misc/omap_l4.c | 2 +-=0A= hw/misc/omap_sdrc.c | 2 +-=0A= hw/misc/omap_tap.c | 2 +-=0A= hw/misc/pc-testdev.c | 10 +-=0A= hw/misc/pci-testdev.c | 4 +-=0A= hw/misc/puv3_pm.c | 2 +-=0A= hw/misc/slavio_misc.c | 16 +--=0A= hw/misc/stm32f2xx_syscfg.c | 2 +-=0A= hw/misc/tz-mpc.c | 4 +-=0A= hw/misc/tz-msc.c | 2 +-=0A= hw/misc/tz-ppc.c | 2 +-=0A= hw/misc/unimp.c | 2 +-=0A= hw/misc/zynq-xadc.c | 2 +-=0A= hw/misc/zynq_slcr.c | 2 +-=0A= hw/moxie/moxiesim.c | 2 +-=0A= hw/net/Makefile.objs | 2 +-=0A= hw/net/allwinner_emac.c | 2 +-=0A= hw/net/cadence_gem.c | 2 +-=0A= hw/net/can/can_kvaser_pci.c | 6 +-=0A= hw/net/can/can_mioe3680_pci.c | 4 +-=0A= hw/net/can/can_pcm3680_pci.c | 4 +-=0A= hw/net/dp8393x.c | 2 +-=0A= hw/net/e1000.c | 4 +-=0A= hw/net/e1000e.c | 4 +-=0A= hw/net/eepro100.c | 2 +-=0A= hw/net/etraxfs_eth.c | 2 +-=0A= hw/net/fsl_etsec/etsec.c | 2 +-=0A= hw/net/ftgmac100.c | 2 +-=0A= hw/net/imx_fec.c | 2 +-=0A= hw/net/lan9118.c | 4 +-=0A= hw/net/lance.c | 2 +-=0A= hw/net/mcf_fec.c | 2 +-=0A= hw/net/milkymist-minimac2.c | 2 +-=0A= hw/net/ne2000.c | 2 +-=0A= hw/net/pcnet-pci.c | 4 +-=0A= hw/net/rocker/rocker.c | 2 +-=0A= hw/net/rtl8139.c | 2 +-=0A= hw/net/smc91c111.c | 2 +-=0A= hw/net/stellaris_enet.c | 2 +-=0A= hw/net/sungem.c | 12 +-=0A= hw/net/sunhme.c | 10 +-=0A= hw/net/vmxnet3.c | 4 +-=0A= hw/net/xgmac.c | 2 +-=0A= hw/net/xilinx_axienet.c | 2 +-=0A= hw/net/xilinx_ethlite.c | 2 +-=0A= hw/nios2/10m50_devboard.c | 2 +-=0A= hw/nvram/ds1225y.c | 2 +-=0A= hw/nvram/fw_cfg.c | 8 +-=0A= hw/nvram/mac_nvram.c | 2 +-=0A= hw/nvram/nrf51_nvm.c | 8 +-=0A= hw/openrisc/openrisc_sim.c | 2 +-=0A= hw/pci-host/Makefile.objs | 2 +-=0A= hw/pci-host/bonito.c | 10 +-=0A= hw/pci-host/designware.c | 6 +-=0A= hw/pci-host/piix.c | 2 +-=0A= hw/pci-host/ppce500.c | 2 +-=0A= hw/pci-host/prep.c | 4 +-=0A= hw/pci-host/q35.c | 4 +-=0A= hw/pci-host/sabre.c | 4 +-=0A= hw/pci-host/uninorth.c | 4 +-=0A= hw/pci-host/versatile.c | 4 +-=0A= hw/pci/msix.c | 4 +-=0A= hw/pci/pci_host.c | 8 +-=0A= hw/pci/pcie_host.c | 2 +-=0A= hw/pci/shpc.c | 2 +-=0A= hw/pcmcia/pxa2xx.c | 6 +-=0A= hw/ppc/e500.c | 4 +-=0A= hw/ppc/mpc8544_guts.c | 2 +-=0A= hw/ppc/pnv_core.c | 6 +-=0A= hw/ppc/pnv_lpc.c | 8 +-=0A= hw/ppc/pnv_occ.c | 4 +-=0A= hw/ppc/pnv_psi.c | 8 +-=0A= hw/ppc/pnv_xscom.c | 2 +-=0A= hw/ppc/ppc405_boards.c | 4 +-=0A= hw/ppc/ppc405_uc.c | 14 +--=0A= hw/ppc/ppc440_bamboo.c | 4 +-=0A= hw/ppc/ppc440_pcix.c | 4 +-=0A= hw/ppc/ppc4xx_pci.c | 2 +-=0A= hw/ppc/ppce500_spin.c | 2 +-=0A= hw/ppc/sam460ex.c | 4 +-=0A= hw/ppc/spapr_pci.c | 2 +-=0A= hw/ppc/virtex_ml507.c | 2 +-=0A= hw/rdma/vmw/pvrdma_main.c | 4 +-=0A= hw/riscv/sifive_clint.c | 2 +-=0A= hw/riscv/sifive_gpio.c | 2 +-=0A= hw/riscv/sifive_plic.c | 2 +-=0A= hw/riscv/sifive_prci.c | 2 +-=0A= hw/riscv/sifive_test.c | 2 +-=0A= hw/riscv/sifive_uart.c | 2 +-=0A= hw/riscv/virt.c | 2 +-=0A= hw/s390x/s390-pci-bus.c | 2 +-=0A= hw/s390x/s390-pci-inst.c | 11 +-=0A= hw/scsi/Makefile.objs | 2 +-=0A= hw/scsi/esp-pci.c | 2 +-=0A= hw/scsi/esp.c | 2 +-=0A= hw/scsi/lsi53c895a.c | 6 +-=0A= hw/scsi/megasas.c | 6 +-=0A= hw/scsi/mptsas.c | 6 +-=0A= hw/scsi/vmw_pvscsi.c | 2 +-=0A= hw/sd/bcm2835_sdhost.c | 2 +-=0A= hw/sd/milkymist-memcard.c | 2 +-=0A= hw/sd/omap_mmc.c | 2 +-=0A= hw/sd/pl181.c | 2 +-=0A= hw/sd/pxa2xx_mmci.c | 2 +-=0A= hw/sd/sdhci.c | 4 +-=0A= hw/sh4/r2d.c | 2 +-=0A= hw/sh4/sh7750.c | 4 +-=0A= hw/sh4/sh_pci.c | 2 +-=0A= hw/sparc/sun4m_iommu.c | 2 +-=0A= hw/sparc64/niagara.c | 2 +-=0A= hw/sparc64/sun4u.c | 4 +-=0A= hw/sparc64/sun4u_iommu.c | 2 +-=0A= hw/ssi/Makefile.objs | 2 +-=0A= hw/ssi/aspeed_smc.c | 6 +-=0A= hw/ssi/imx_spi.c | 2 +-=0A= hw/ssi/mss-spi.c | 2 +-=0A= hw/ssi/omap_spi.c | 2 +-=0A= hw/ssi/pl022.c | 2 +-=0A= hw/ssi/stm32f2xx_spi.c | 2 +-=0A= hw/ssi/xilinx_spi.c | 2 +-=0A= hw/ssi/xilinx_spips.c | 8 +-=0A= hw/timer/Makefile.objs | 6 +-=0A= hw/timer/a9gtimer.c | 4 +-=0A= hw/timer/allwinner-a10-pit.c | 2 +-=0A= hw/timer/altera_timer.c | 2 +-=0A= hw/timer/arm_mptimer.c | 4 +-=0A= hw/timer/arm_timer.c | 4 +-=0A= hw/timer/armv7m_systick.c | 2 +-=0A= hw/timer/aspeed_rtc.c | 2 +-=0A= hw/timer/aspeed_timer.c | 2 +-=0A= hw/timer/cadence_ttc.c | 2 +-=0A= hw/timer/cmsdk-apb-dualtimer.c | 2 +-=0A= hw/timer/cmsdk-apb-timer.c | 2 +-=0A= hw/timer/digic-timer.c | 2 +-=0A= hw/timer/etraxfs_timer.c | 2 +-=0A= hw/timer/exynos4210_mct.c | 2 +-=0A= hw/timer/exynos4210_pwm.c | 2 +-=0A= hw/timer/exynos4210_rtc.c | 2 +-=0A= hw/timer/grlib_gptimer.c | 2 +-=0A= hw/timer/hpet.c | 2 +-=0A= hw/timer/i8254.c | 2 +-=0A= hw/timer/imx_epit.c | 2 +-=0A= hw/timer/imx_gpt.c | 2 +-=0A= hw/timer/lm32_timer.c | 2 +-=0A= hw/timer/m48t59.c | 4 +-=0A= hw/timer/mc146818rtc.c | 2 +-=0A= hw/timer/milkymist-sysctl.c | 2 +-=0A= hw/timer/mss-timer.c | 2 +-=0A= hw/timer/nrf51_timer.c | 2 +-=0A= hw/timer/omap_gptimer.c | 2 +-=0A= hw/timer/omap_synctimer.c | 2 +-=0A= hw/timer/pl031.c | 2 +-=0A= hw/timer/puv3_ost.c | 2 +-=0A= hw/timer/pxa2xx_timer.c | 2 +-=0A= hw/timer/sh_timer.c | 2 +-=0A= hw/timer/slavio_timer.c | 2 +-=0A= hw/timer/stm32f2xx_timer.c | 2 +-=0A= hw/timer/sun4v-rtc.c | 2 +-=0A= hw/timer/xilinx_timer.c | 2 +-=0A= hw/timer/xlnx-zynqmp-rtc.c | 2 +-=0A= hw/tpm/tpm_crb.c | 2 +-=0A= hw/tpm/tpm_tis.c | 2 +-=0A= hw/usb/chipidea.c | 4 +-=0A= hw/usb/hcd-ehci-sysbus.c | 2 +-=0A= hw/usb/hcd-ehci.c | 6 +-=0A= hw/usb/hcd-ohci.c | 2 +-=0A= hw/usb/hcd-uhci.c | 2 +-=0A= hw/usb/hcd-xhci.c | 10 +-=0A= hw/usb/tusb6010.c | 2 +-=0A= hw/vfio/common.c | 2 +-=0A= hw/vfio/pci-quirks.c | 33 +++---=0A= hw/vfio/pci.c | 4 +-=0A= hw/virtio/Makefile.objs | 2 +-=0A= hw/virtio/virtio-mmio.c | 2 +-=0A= hw/virtio/virtio-pci.c | 27 +++--=0A= hw/watchdog/cmsdk-apb-watchdog.c | 2 +-=0A= hw/watchdog/wdt_aspeed.c | 2 +-=0A= hw/watchdog/wdt_i6300esb.c | 2 +-=0A= hw/xen/xen_pt.c | 2 +-=0A= hw/xen/xen_pt_msi.c | 2 +-=0A= hw/xtensa/mx_pic.c | 2 +-=0A= hw/xtensa/xtfpga.c | 6 +-=0A= include/exec/cpu-all.h | 10 +-=0A= include/exec/cpu-common.h | 12 --=0A= include/exec/memattrs.h | 2 +=0A= include/exec/memop.h | 134 ++++++++++++++++++++++=0A= include/exec/memory.h | 11 +-=0A= include/exec/poison.h | 1 +=0A= include/hw/char/serial.h | 2 +-=0A= include/qom/cpu.h | 2 +-=0A= ioport.c | 4 +-=0A= memory.c | 55 ++++-----=0A= memory_ldst.inc.c | 153 ++++++++-----------------=0A= target/alpha/cpu.h | 2 -=0A= target/alpha/translate.c | 2 +-=0A= target/arm/translate-a64.c | 48 ++++----=0A= target/arm/translate-a64.h | 2 +-=0A= target/arm/translate-sve.c | 2 +-=0A= target/arm/translate.c | 32 +++---=0A= target/arm/translate.h | 2 +-=0A= target/hppa/cpu.h | 1 -=0A= target/hppa/translate.c | 14 +--=0A= target/i386/translate.c | 132 ++++++++++-----------=0A= target/m68k/translate.c | 2 +-=0A= target/microblaze/translate.c | 4 +-=0A= target/mips/cpu.h | 2 -=0A= target/mips/op_helper.c | 5 +-=0A= target/mips/translate.c | 8 +-=0A= target/openrisc/translate.c | 4 +-=0A= target/ppc/translate.c | 12 +-=0A= target/riscv/insn_trans/trans_rva.inc.c | 8 +-=0A= target/riscv/insn_trans/trans_rvi.inc.c | 4 +-=0A= target/s390x/translate.c | 6 +-=0A= target/s390x/translate_vx.inc.c | 10 +-=0A= target/sh4/cpu.h | 2 -=0A= target/sparc/cpu.h | 4 +-=0A= target/sparc/mmu_helper.c | 40 ++++---=0A= target/sparc/translate.c | 14 +--=0A= target/tilegx/translate.c | 10 +-=0A= target/tricore/translate.c | 8 +-=0A= target/xtensa/cpu.h | 2 -=0A= tcg/README | 2 +-=0A= tcg/aarch64/tcg-target.inc.c | 26 ++---=0A= tcg/arm/tcg-target.inc.c | 26 ++---=0A= tcg/i386/tcg-target.inc.c | 24 ++--=0A= tcg/mips/tcg-target.inc.c | 16 +--=0A= tcg/optimize.c | 2 +-=0A= tcg/ppc/tcg-target.inc.c | 12 +-=0A= tcg/riscv/tcg-target.inc.c | 20 ++--=0A= tcg/s390/tcg-target.inc.c | 14 +--=0A= tcg/sparc/tcg-target.inc.c | 6 +-=0A= tcg/tcg-op.c | 38 +++---=0A= tcg/tcg-op.h | 86 +++++++-------=0A= tcg/tcg.c | 4 +-=0A= tcg/tcg.h | 99 +---------------=0A= trace/mem-internal.h | 4 +-=0A= trace/mem.h | 4 +-=0A= 497 files changed, 1436 insertions(+), 1473 deletions(-)=0A= create mode 100644 include/exec/memop.h=0A= =0A= -- =0A= 1.8.3.1=0A= From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-0.7 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BB553C3A59C for ; Fri, 16 Aug 2019 06:29:35 +0000 (UTC) Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 831722171F for ; Fri, 16 Aug 2019 06:29:34 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 831722171F Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=bt.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hyVjN-0005Pj-6L; Fri, 16 Aug 2019 06:28:57 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57] helo=us1-amaz-eas2.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1hyVjL-0005Pe-Ad for xen-devel@lists.xenproject.org; Fri, 16 Aug 2019 06:28:55 +0000 X-Inumbo-ID: 1b742114-bfef-11e9-8bb0-12813bfff9fa Received: from smtpe1.intersmtp.com (unknown [213.121.35.74]) by us1-amaz-eas2.inumbo.com (Halon) with ESMTPS id 1b742114-bfef-11e9-8bb0-12813bfff9fa; Fri, 16 Aug 2019 06:28:49 +0000 (UTC) Received: from tpw09926dag18g.domain1.systemhost.net (10.9.212.34) by BWP09926079.bt.com (10.36.82.110) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.1713.5; Fri, 16 Aug 2019 07:28:25 +0100 Received: from tpw09926dag18e.domain1.systemhost.net (10.9.212.18) by tpw09926dag18g.domain1.systemhost.net (10.9.212.34) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Fri, 16 Aug 2019 07:28:47 +0100 Received: from tpw09926dag18e.domain1.systemhost.net ([fe80::a946:6348:ccf4:fa6c]) by tpw09926dag18e.domain1.systemhost.net ([fe80::a946:6348:ccf4:fa6c%12]) with mapi id 15.00.1395.000; Fri, 16 Aug 2019 07:28:47 +0100 From: To: Thread-Topic: [Qemu-devel] [PATCH v7 00/42] Invert Endian bit in SPARCv9 MMU TTE Thread-Index: AQHVU/vc8DdfhK3ulkmWv148s0Uozg== Date: Fri, 16 Aug 2019 06:28:47 +0000 Message-ID: <43bc5e07ac614d0e8e740bf6007ff77b@tpw09926dag18e.domain1.systemhost.net> Accept-Language: en-AU, en-GB, en-US Content-Language: en-AU X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-exchange-messagesentrepresentingtype: 1 x-ms-exchange-transport-fromentityheader: Hosted x-originating-ip: [10.187.101.40] MIME-Version: 1.0 Subject: [Xen-devel] [Qemu-devel] [PATCH v7 00/42] Invert Endian bit in SPARCv9 MMU TTE X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: frederic.konrad@adacore.com, berto@igalia.com, qemu-block@nongnu.org, arikalo@wavecomp.com, pasic@linux.ibm.com, hpoussin@reactos.org, anthony.perard@citrix.com, xen-devel@lists.xenproject.org, lersek@redhat.com, jasowang@redhat.com, jiri@resnulli.us, ehabkost@redhat.com, b.galvani@gmail.com, eric.auger@redhat.com, alex.williamson@redhat.com, stefanha@redhat.com, jsnow@redhat.com, rth@twiddle.net, kwolf@redhat.com, andrew@aj.id.au, claudio.fontana@suse.com, crwulff@gmail.com, laurent@vivier.eu, sundeep.lkml@gmail.com, michael@walle.cc, qemu-ppc@nongnu.org, kbastian@mail.uni-paderborn.de, imammedo@redhat.com, fam@euphon.net, peter.maydell@linaro.org, david@redhat.com, palmer@sifive.com, balaton@eik.bme.hu, keith.busch@intel.com, jcmvbkbc@gmail.com, hare@suse.com, sstabellini@kernel.org, andrew.smirnov@gmail.com, deller@gmx.de, magnus.damm@gmail.com, marcel.apfelbaum@gmail.com, atar4qemu@gmail.com, minyard@acm.org, sw@weilnetz.de, yuval.shaia@oracle.com, qemu-s390x@nongnu.org, qemu-arm@nongnu.org, jan.kiszka@web.de, clg@kaod.org, shorne@gmail.com, qemu-riscv@nongnu.org, i.mitsyanko@gmail.com, cohuck@redhat.com, philmd@redhat.com, amarkovic@wavecomp.com, peter.chubb@nicta.com.au, aurelien@aurel32.net, pburton@wavecomp.com, sagark@eecs.berkeley.edu, green@moxielogic.com, kraxel@redhat.com, edgar.iglesias@gmail.com, gxt@mprc.pku.edu.cn, robh@kernel.org, borntraeger@de.ibm.com, joel@jms.id.au, antonynpavlov@gmail.com, chouteau@adacore.com, balrogg@gmail.com, Andrew.Baumann@microsoft.com, mreitz@redhat.com, walling@linux.ibm.com, dmitry.fleytman@gmail.com, mst@redhat.com, mark.cave-ayland@ilande.co.uk, jslaby@suse.cz, marex@denx.de, proljc@gmail.com, marcandre.lureau@redhat.com, alistair@alistair23.me, paul.durrant@citrix.com, david@gibson.dropbear.id.au, xiaoguangrong.eric@gmail.com, huth@tuxfamily.org, jcd@tribudubois.net, pbonzini@redhat.com, stefanb@linux.ibm.com Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" VGhpcyBwYXRjaHNldCBpbXBsZW1lbnRzIHRoZSBJRSAoSW52ZXJ0IEVuZGlhbikgYml0IGluIFNQ QVJDdjkgTU1VIFRURS4KCkl0IGlzIGFuIGF0dGVtcHQgb2YgdGhlIGluc3RydWN0aW9ucyBvdXRs aW5lZCBieSBSaWNoYXJkIEhlbmRlcnNvbiB0byBNYXJrCkNhdmUtQXlsYW5kLgoKVGVzdGVkIHdp dGggT3BlbkJTRCBvbiBzdW40dS4gU29sYXJpcyAxMCBpcyBteSBhY3R1YWwgZ29hbCwgYnV0IHVu Zm9ydHVuYXRlbHkgYQpzZXBhcmF0ZSBrZXlib2FyZCBpc3N1ZSByZW1haW5zIGluIHRoZSB3YXku CgpPbiAwMS8xMS8xNyAxOToxNSwgTWFyayBDYXZlLUF5bGFuZCB3cm90ZToKCj5PbiAxNS8wOC8x NyAxOToxMCwgUmljaGFyZCBIZW5kZXJzb24gd3JvdGU6Cj4KPj4gW0NDIFBldGVyIHJlIE1lbVR4 QXR0cnMgYmVsb3ddCj4+Cj4+IE9uIDA4LzE1LzIwMTcgMDk6MzggQU0sIE1hcmsgQ2F2ZS1BeWxh bmQgd3JvdGU6Cj4+PiBXb3JraW5nIHRocm91Z2ggYW4gaW5jb3JyZWN0IGVuZGlhbiBpc3N1ZSBv biBxZW11LXN5c3RlbS1zcGFyYzY0LCBpdCBoYXMKPj4+IGJlY29tZSBhcHBhcmVudCB0aGF0IGF0 IGxlYXN0IG9uZSBPUyBtYWtlcyB1c2Ugb2YgdGhlIElFIChJbnZlcnQgRW5kaWFuKQo+Pj4gYml0 IGluIHRoZSBTUEFSQ3Y5IE1NVSBUVEUgdG8gbWFwIFBDSSBtZW1vcnkgc3BhY2Ugd2l0aG91dCB0 aGUKPj4+IHByb2dyYW1tZXIgaGF2aW5nIHRvIG1hbnVhbGx5IGVuZGlhbi1zd2FwIGFjY2Vzc2Vz Lgo+Pj4KPj4+IEluIG90aGVyIHdvcmRzLCB0byBxdW90ZSB0aGUgVWx0cmFTUEFSQyBzcGVjaWZp Y2F0aW9uOiAiaWYgdGhpcyBiaXQgaXMKPj4+IHNldCwgYWNjZXNzZXMgdG8gdGhlIGFzc29jaWF0 ZWQgcGFnZSBhcmUgcHJvY2Vzc2VkIHdpdGggaW52ZXJzZQo+Pj4gZW5kaWFubmVzcyBmcm9tIHdo YXQgaXMgc3BlY2lmaWVkIGJ5IHRoZSBpbnN0cnVjdGlvbiAoYmlnLWZvci1saXR0bGUgYW5kCj4+ PiBsaXR0bGUtZm9yLWJpZykiLgoKQSBnb29kIGV4cGxhbmF0aW9uIGJ5IE1hcmsgd2h5IHRoZSBJ RSBiaXQgaXMgcmVxdWlyZWQuCgo+Pj4KPj4+IExvb2tpbmcgdGhyb3VnaCB2YXJpb3VzIGJpdHMg b2YgY29kZSwgSSdtIHRyeWluZyB0byBnZXQgYSBmZWVsIGZvciB0aGUKPj4+IGJlc3Qgd2F5IHRv IGltcGxlbWVudCB0aGlzIGluIGFuIGVmZmljaWVudCBtYW5uZXIuIEZyb20gd2hhdCBJIGNhbiBz ZWUKPj4+IHRoaXMgY291bGQgYmUgc29sdmVkIHVzaW5nIGFuIGFkZGl0aW9uYWwgTU1VIGluZGV4 LCBob3dldmVyIEknbSBub3QKPj4+IG92ZXJseSBmYW1pbGlhciB3aXRoIHRoZSBtZW1vcnkgYW5k IHNvZnRtbXUgc3Vic3lzdGVtcy4KPj4KPj4gTm8sIGl0IGNhbid0IGJlIHNvbHZlZCB3aXRoIGFu IE1NVSBpbmRleC4KPj4KPj4+IENhbiBhbnlvbmUgcG9pbnQgbWUgaW4gdGhlIHJpZ2h0IGRpcmVj dGlvbiBhcyB0byB3aGF0IHdvdWxkIGJlIHRoZSBiZXN0Cj4+PiB3YXkgdG8gaW1wbGVtZW50IHRo aXMgZmVhdHVyZSB3aXRoaW4gUUVNVT8KPj4KPj4gSXQncyBkZWZpbml0ZWx5IHRyaWNreS4KPj4K Pj4gV2UgZGVmaW5pdGVseSBuZWVkIHNvbWUgVExCX0ZMQUdTX01BU0sgYml0IHNldCBzbyB0aGF0 IHdlJ3JlIGZvcmNlZCB0aHJvdWdoCj4+IHRoZQo+PiBtZW1vcnkgc2xvdyBwYXRoLiAgVGhlcmUg aXMgbm8gb3RoZXIgd2F5IHRvIGJ5cGFzcyB0aGUgZW5kaWFubmVzcyB0aGF0IHdlJ3ZlCj4+IGFs cmVhZHkgZW5jb2RlZCBmcm9tIHRoZSB0YXJnZXQgaW5zdHJ1Y3Rpb24uCj4+Cj4+IEdpdmVuIHRo ZSB0bGJfc2V0X3BhZ2Vfd2l0aF9hdHRycyBpbnRlcmZhY2UsIEkgd291bGQgdGhpbmsgdGhhdCB3 ZSBuZWVkIGEgbmV3Cj4+IGJpdCBpbiBNZW1UeEF0dHJzLCBzbyB0aGF0IHRoZSB0YXJnZXQvc3Bh cmMgdGxiX2ZpbGwgKGFuZCBzdWJyb3V0aW5lcykgY2FuCj4+IHBhc3MKPj4gYWxvbmcgdGhlIFRU RSBiaXQgZm9yIHRoZSBnaXZlbiBwYWdlLgo+Pgo+PiBXZSBoYXZlIGFuIGV4aXN0aW5nIHByb2Js ZW0gaW4gc29mdG1tdV90ZW1wbGF0ZS5oLAo+Pgo+PiAgICAgLyogPz8/IE5vdGUgdGhhdCB0aGUg aW8gaGVscGVycyBhbHdheXMgcmVhZCBkYXRhIGluIHRoZSB0YXJnZXQKPj4gICAgICAgIGJ5dGUg b3JkZXJpbmcuICBXZSBzaG91bGQgcHVzaCB0aGUgTEUvQkUgcmVxdWVzdCBkb3duIGludG8gaW8u ICAqLwo+PiAgICAgcmVzID0gZ2x1ZShpb19yZWFkLCBTVUZGSVgpKGVudiwgbW11X2lkeCwgaW5k ZXgsIGFkZHIsIHJldGFkZHIpOwo+PiAgICAgcmVzID0gVEdUX0JFKHJlcyk7Cj4+Cj4+IFdlIGRv IG5vdCB3YW50IHRvIGFkZCBhIHRoaXJkKCEpIGJ5dGUgc3dhcCBhbG9uZyB0aGUgaS9vIHBhdGgu ICBXZSBuZWVkIHRvCj4+IGNvbGxhcHNlIHRoZSB0d28gdGhhdCB3ZSBoYXZlIGFscmVhZHkgYmVm b3JlIGNvbnNpZGVyaW5nIHRoaXMgb25lLgo+Pgo+PiBUaGlzIHByb2JhYmx5IHRha2VzIHRoZSBm b3JtIG9mOgo+Pgo+PiAoMSkgUmVwbGFjaW5nIHRoZSAiaW50IHNpemUiIGFyZ3VtZW50IHdpdGgg IlRDR01lbU9wIG1lbW9wIiBmb3IKPj4gICAgICAgYSkgaW9fe3JlYWQsd3JpdGV9eCBpbiBhY2Nl bC90Y2cvY3B1dGxiLmMsCj4+ICAgICAgIGIpIG1lbW9yeV9yZWdpb25fZGlzcGF0Y2hfe3JlYWQs d3JpdGV9IGluIG1lbW9yeS5jLAo+PiAgICAgICBjKSBhZGp1c3RfZW5kaWFubmVzcyBpbiBtZW1v cnkuYy4KPj4gICAgIFRoaXMgY2FycmllcyBzaXplK3NpZ24rZW5kaWFubmVzcyBkb3duIHRvIHRo ZSBuZXh0IGxldmVsLgo+Pgo+PiAoMikgSW4gbWVtb3J5LmMsIGFkanVzdF9lbmRpYW5uZXNzLAo+ Pgo+PiAgICAgIGlmIChtZW1vcnlfcmVnaW9uX3dyb25nX2VuZGlhbm5lc3MobXIpKSB7Cj4+IC0g ICAgICAgIHN3aXRjaCAoc2l6ZSkgewo+PiArICAgICAgICBtZW1vcCBePSBNT19CU1dBUDsKPj4g KyAgICB9Cj4+ICsgICAgaWYgKG1lbW9wICYgTU9fQlNXQVApIHsKPj4KPj4gICAgIEZvciBleHRy YSBjcmVkaXQsIHJlLWFycmFuZ2UgbWVtb3J5X3JlZ2lvbl93cm9uZ19lbmRpYW5uZXNzCj4+ICAg ICB0byBzb21ldGhpbmcgbW9yZSBleHBsaWNpdCAtLSAid3JvbmciIGlzbid0IGhlbHBmdWwuCj4K PkZpbmFsbHkgSSd2ZSBoYWQgYSBiaXQgb2Ygc3BhcmUgdGltZSB0byBleHBlcmltZW50IHdpdGgg dGhpcyBhcHByb2FjaCwKPmFuZCBmcm9tIHdoYXQgSSBjYW4gc2VlIHRoZXJlIGFyZSBjdXJyZW50 bHkgMiBpc3N1ZXM6Cj4KPgo+MSkgVXNpbmcgVENHTWVtT3AgaW4gbWVtb3J5LmMgbWVhbnMgaXQg aXMgbm8gbG9uZ2VyIGFjY2VsZXJhdG9yIGFnbm9zdGljCj4KPkZvciB0aGUgbW9tZW50IEkndmUg ZGVmaW5lZCBhIHNlcGFyYXRlIE1lbU9wIGluIG1lbW9yeS5oIGFuZCBwcm92aWRlZCBhCj5tYXBw aW5nIGZ1bmN0aW9uIGluIGlvX3tyZWFkLHdyaXRlfXggdG8gbWFwIGZyb20gVENHTWVtT3AgdG8g TWVtT3AgYW5kCj50aGVuIHBhc3MgdGhhdCBpbnRvIG1lbW9yeV9yZWdpb25fZGlzcGF0Y2hfe3Jl YWQsd3JpdGV9Lgo+Cj5PdGhlciB0aGFuIG5vdCByZWZlcmVuY2luZyBUQ0dNZW1PcCBpbiB0aGUg bWVtb3J5IEFQSSwgYW5vdGhlciByZWFzb24KPmZvciBkb2luZyB0aGlzIHdhcyB0aGF0IEkgd2Fz bid0IGNvbnZpbmNlZCB0aGF0IGFsbCB0aGUgTU9fIGF0dHJpYnV0ZXMKPndlcmUgdmFsaWQgb3V0 c2lkZSBvZiBUQ0cuIEkgZG8sIG9mIGNvdXJzZSwgc3Ryb25nbHkgZGVmZXIgdG8gb3RoZXIKPnBl b3BsZSdzIGtub3dsZWRnZSBpbiB0aGlzIGFyZWEgdGhvdWdoLgo+Cj4KPjIpIFRoZSBhYm92ZSBj aGFuZ2VzIHRvIGFkanVzdF9lbmRpYW5uZXNzKCkgZmFpbCB3aGVuCj5tZW1vcnlfcmVnaW9uX2Rp c3BhdGNoX3tyZWFkLHdyaXRlfSBhcmUgY2FsbGVkIHJlY3Vyc2l2ZWx5Cj4KPldoaWxzdCBib290 aW5nIHFlbXUtc3lzdGVtLXNwYXJjNjQgSSBzZWUgdGhhdAo+bWVtb3J5X3JlZ2lvbl9kaXNwYXRj aF97cmVhZCx3cml0ZX0gZ2V0IGNhbGxlZCByZWN1cnNpdmVseSAtIG9uY2UgdmlhCj5pb197cmVh ZCx3cml0ZX14IGFuZCB0aGVuIGFnYWluIHZpYSBmbGF0dmlld19yZWFkX2NvbnRpbnVlKCkgaW4g ZXhlYy5jLgo+Cj5UaGUgbmV0IGVmZmVjdCBvZiB0aGlzIGlzIHRoYXQgd2UgcGVyZm9ybSB0aGUg YnN3YXAgY29ycmVjdGx5IGF0IHRoZQo+dGFpbCBvZiB0aGUgcmVjdXJzaW9uLCBidXQgdGhlbiBh cyB3ZSB0cmF2ZWwgYmFjayB1cCB0aGUgc3RhY2sgd2UgaGl0Cj5tZW1vcnlfcmVnaW9uX2Rpc3Bh dGNoX3tyZWFkLHdyaXRlfSBvbmNlIGFnYWluIGNhdXNpbmcgYSBzZWNvbmQgYnN3YXAKPndoaWNo IG1lYW5zIHRoZSB2YWx1ZSBpcyByZXR1cm5lZCB3aXRoIHRoZSBpbmNvcnJlY3QgZW5kaWFuIGFn YWluLgo+Cj4KPk15IHVuZGVyc3RhbmRpbmcgZnJvbSB5b3VyIHNvZnRtbXVfdGVtcGxhdGUuaCBj b21tZW50IGFib3ZlIGlzIHRoYXQgdGhlCj5tZW1vcnkgQVBJIHNob3VsZCBkbyB0aGUgZW5kaWFu IHN3YXBwaW5nIGludGVybmFsbHkgYWxsb3dpbmcgdGhlIHJlbW92YWwKPm9mIHRoZSBmaW5hbCBU R1RfQkUvVEdUX0xFIGFwcGxpZWQgdG8gdGhlIHJlc3VsdCwgb3IgZGlkIEkgZ2V0IHRoaXMgd3Jv bmc/Cj4KPj4gKDMpIEluIHRsYl9zZXRfcGFnZV93aXRoX2F0dHJzLCBub3RpY2UgYXR0cnMuYnl0 ZV9zd2FwIGFuZCBzZXQKPj4gICAgIGEgbmV3IFRMQl9GT1JDRV9TTE9XIGJpdCB3aXRoaW4gVExC X0ZMQUdTX01BU0suCj4+Cj4+ICg0KSBJbiBpb197cmVhZCx3cml0ZX14LCBpZiBpb3RsYmVudHJ5 LT5hdHRycy5ieXRlX3N3YXAgaXMgc2V0LAo+PiAgICAgdGhlbiBtZW1vcCBePSBNT19CU1dBUC4K ClRoYW5rcyBhbGwgZm9yIHRoZSBmZWVkYmFjay4gTGVhcm50IGEgbG90ID0pCgp2MjoKLSBNb3Zl ZCBzaXplK3NpZ24rZW5kaWFubmVzcyBhdHRyaWJ1dGVzIGZyb20gVENHTWVtT3AgaW50byBNZW1P cC4KICBJbiB2MSBUQ0dNZW1PcCB3YXMgcmUtcHVycG9zZWQgZW50aXJlbHkgaW50byBNZW1PcC4K LSBSZXBsYWNlZCBNZW1PcCBNT197OHwxNnwzMnw2NH0gd2l0aCBUQ0dNZW1PcCBNT197VUJ8VVd8 VUx8VVF9IGFsaWFzLgogIFRoaXMgaXMgdG8gYXZvaWQgd2FybmluZ3Mgb24gY29tcGFyaW5nIGFu ZCBjb2VyY2luZyBkaWZmZXJlbnQgZW51bXMuCi0gUmVuYW1lZCBnZXRfbWVtb3AgdG8gZ2V0X3Rj Z21lbW9wIGZvciBjbGFyaXR5LgotIE1FTU9QIGlzIG5vdyBTSVpFX01FTU9QLCB3aGljaCBpcyBq dXN0IGN0emwoc2l6ZSkuCi0gU3BsaXQgcGF0Y2ggMy80IHNvIG9uZSBtZW1vcnlfcmVnaW9uX2Rp c3BhdGNoX3tyZWFkfHdyaXRlfSBpbnRlcmZhY2UKICBpcyBjb252ZXJ0ZWQgcGVyIHBhdGNoLgot IERvIG5vdCByZXVzZSBUTEJfUkVDSEVDSywgdXNlIG5ldyBUTEJfRk9SQ0VfU0xPVyBpbnN0ZWFk LgotIFNwbGl0IHBhdGNoIDQvNCBzbyBhZGRpbmcgdGhlIE1lbVR4QWRkcnMgcGFyYW1ldGVycyBh bmQgY29udmVydGluZwogIHRsYl9zZXRfcGFnZSgpIHRvIHRsYl9zZXRfcGFnZV93aXRoX2F0dHJz KCkgaXMgc2VwYXJhdGUgZnJvbSB1c2FnZS4KLSBDQydkIG1haW50YWluZXJzLgoKdjM6Ci0gTGlr ZSB2MSwgdGhlIGVudGlyZSBUQ0dNZW1PcCBlbnVtIGlzIG5vdyBNZW1PcC4KLSBNZW1PcCB0YXJn ZXQgZGVwZW5kYW50IGF0dHJpYnV0ZXMgYXJlIGNvbmRpdGlvbmFsIHVwb24gTkVFRF9DUFVfSAoK djQ6Ci0gQWRkZWQgUGFvbG8gQm9uemluaSBhcyBpbmNsdWRlL2V4ZWMvbWVtb3AuaCBtYWludGFp bmVyCgp2NToKLSBJbXByb3ZlZCBjb21taXQgbWVzc2FnZXMgdG8gY2xhcmlmeSBob3cgaW50ZXJm YWNlIHRvIGFjY2VzcwogIE1lbW9yeVJlZ2lvbiB3aWxsIGJlIGNvbnZlcnRlZCBmcm9tICJ1bnNp Z25lZCBzaXplIiB0byAiTWVtT3Agb3AiLgotIE1vdmVkIGNwdV90cmFuc2FjdGlvbl9mYWlsZWQo KSBNZW1PcCBjb252ZXJzaW9uIGZyb20gcGF0Y2ggIzExIHRvICM5CiAgdG8gbWFrZSByZXZpZXcg ZWFzaWVyLgoKdjY6Ci0gSW1wcm92ZWQgY29tbWl0IG1lc3NhZ2VzLgotIEluY2x1ZGUgYXMgcGF0 Y2ggIzEgYW4gZWFybGllciBwb3N0ZWQgVEFSR0VUX0FMSUdORURfT05MWSBjb25maWd1cmUgcGF0 Y2guCi0gVHlwZWxlc3MgbWFjcm8gU0laRV9NRU1PUCBpcyBub3cgaW5saW5lLgotIHNpemVfbWVt b3Agbm93IGluY2x1ZGVzIENPTkZJR19ERUJVR19UQ0cgY29kZS4KLSBzaXplX21lbW9wIG5vdyBh bHNvIGVuY29kZXMgZW5kaWFubmVzcyB2aWEgTU9fVEUuCi0gUmV2ZXJ0ZWQgc2l6ZV9tZW1vcCBv cGVyYW5kICJ1bnNpZ25lZCBsb25nIiBiYWNrIHRvICJ1bnNpZ25lZCIuCi0gU2Vjb25kIHBhc3Mg b2Ygc2l6ZV9tZW1vcCB0byByZXBsYWNlIG5vLW9wIHBsYWNlIGhvbGRlciB3aXRoIE1PX3s4fDE2 fDMyfDY0fS4KLSBEZWxheSBtZW1vcnlfcmVnaW9uX2Rpc3BhdGNoX3tyZWFkLHdyaXRlfSBvcGVy YW5kIGNvbnZlcnNpb24gdW50aWwgbm8tb3AKICBzaXplX21lbW9wIGlzIGltcGxlbWVudGVkIHNv IHdlIGhhdmUgcHJvcGVyIHR5cGluZyBhdCBhbGwgcG9pbnRzIGluIGJldHdlZW4uCi0gRml4ZWQg YnVnIHdoZXJlIG5vdCBhbGwgbWVtb3J5X3JlZ2lvbl9kaXNwYXRjaF97cmVhZCx3cml0ZX0gY2Fs bGVycyB3aGVyZQogIGVuY29kaW5nIGVuZGlhbm5lc3MgaW50byB0aGUgTWVtT3Agb3BlcmFuZCwg c2VlIHBhdGNoICMyMC4KLSBGaXhlZCBidWcgd2hlcmUgbm90IGFsbCBtZW1vcnlfcmVnaW9uX2Rp c3BhdGNoX3tyZWFkLHdyaXRlfSBjYWxsZXJzIHdlcmUKICBjb2xsYXBzaW5nIHRoZWlyIGJ5dGUg c3dhcCBpbnRvIGFkanVzdF9lbmRpYW5uZXNzLCBzZWUgcGF0Y2ggIzIwIGFuZCAjMjIuCi0gU3Bs aXQgYnl0ZSBzd2FwIGNvbGxhcHNpbmcgcGF0Y2ggKHY1ICMxMSkgaW50byAjMjEgYW5kICMyMi4K LSBDb3JyZWN0ZWQgbm9uLWNvbW1vbiAqLWNvbW1vbi1vYmogdG8gKi1vYmouCi0gUmVwbGFjZWQg ZW51bSBkZXZpY2VfZW5kaWFuIHdpdGggTWVtT3AgdG8gc2ltcGxpZnkgZW5kaWFubmVzcyBjaGVj a3MuIEEKICBzdHJhaWdodCBmb3J3YXJkIHNlZCBidXQgdG91Y2hlZCAqYWxvdCogb2YgZmlsZXMu IFNlZSBwYXRjaCAjMTYgYW5kICMxNy4KLSBEZWxldGVkIGVudW0gZGV2aWNlX2VuZGlhbi4KLSBE ZWxldGVkIERFVklDRV9IT1NUX0VORElBTiBkZWZpbml0aW9uLgotIEdlbmVyYWxpemVkIHRoZSBk ZXNjcmlwdGlvbiBvZiBpbnRyb2R1Y2VkIE1lbVR4QXR0cnMgYXR0cmlidXRlIGJ5dGVfc3dhcC4K CnY3OgotIEZpeGVkIGJ1ZyB3aGVyZSBzaXplX21lbW9wIHdhcyBpbXBsaWNpdGx5IGVuY29kaW5n IE1PX1RFLiBFbmRpYW5uZXNzLAogIHtNT19URXxNT19CRXxNT19MRX0sIGlzIG5vdyBleHBsaWNp dGx5IGVuY29kZWQgYnkgTWVtb3J5UmVnaW9uIGFjY2Vzc29ycy4KLSBXaGlsZSBhIG5vLW9wLCBz aXplX21lbW9wIHJldHVybiB0eXBlIHJlbWFpbnMgYW4gdW5zaWduZWQuCi0gVXNlICc9IDAnIHNo b3J0IGhhbmQgaW5zdGVhZCBvZiBtYWNybyBsb2dpYyB0byBkZWNsYXJlIGhvc3QgZW5kaWFubmVz cy4KLSBXaXRoIGEgbmV3IHNldCBvZiBjb25zdGFudCBhcmd1bWVudHMsIHNhbml0eSBjaGVja2Vk IHRoZSBjb21waWxlciBpcyBzdGlsbAogIGZvbGRpbmcgYXdheSB0ZXN0cyBpbiBjcHV0bGIuYwot IFJlLWRlY2xhcmVkIG1hbnkgbmF0aXZlIGVuZGlhbiBkZXZpY2VzIGFzIGxpdHRsZSBvciBiaWcg ZW5kaWFuLiBUaGlzIGlzIHdoeQogIHY3IGhhcyArMTYgcGF0Y2hlcy4KClRvbnkgTmd1eWVuICg0 Mik6CiAgY29uZmlndXJlOiBEZWZpbmUgVEFSR0VUX0FMSUdORURfT05MWSBpbiBjb25maWd1cmUK ICB0Y2c6IFRDR01lbU9wIGlzIG5vdyBhY2NlbGVyYXRvciBpbmRlcGVuZGVudCBNZW1PcAogIG1l bW9yeTogSW50cm9kdWNlIHNpemVfbWVtb3AKICB0YXJnZXQvbWlwczogQWNjZXNzIE1lbW9yeVJl Z2lvbiB3aXRoIE1lbU9wCiAgaHcvczM5MHg6IEFjY2VzcyBNZW1vcnlSZWdpb24gd2l0aCBNZW1P cAogIGh3L2ludGMvYXJtdjdtX25pYzogQWNjZXNzIE1lbW9yeVJlZ2lvbiB3aXRoIE1lbU9wCiAg aHcvdmlydGlvOiBBY2Nlc3MgTWVtb3J5UmVnaW9uIHdpdGggTWVtT3AKICBody92ZmlvOiBBY2Nl c3MgTWVtb3J5UmVnaW9uIHdpdGggTWVtT3AKICBleGVjOiBBY2Nlc3MgTWVtb3J5UmVnaW9uIHdp dGggTWVtT3AKICBjcHV0bGI6IEFjY2VzcyBNZW1vcnlSZWdpb24gd2l0aCBNZW1PcAogIG1lbW9y eTogQWNjZXNzIE1lbW9yeVJlZ2lvbiB3aXRoIE1lbU9wCiAgaHcvczM5MHg6IEhhcmQgY29kZSBz aXplIHdpdGggTU9fezh8MTZ8MzJ8NjR9CiAgdGFyZ2V0L21pcHM6IEhhcmQgY29kZSBzaXplIHdp dGggTU9fezh8MTZ8MzJ8NjR9CiAgZXhlYzogSGFyZCBjb2RlIHNpemUgd2l0aCBNT197OHwxNnwz Mnw2NH0KICBody9hdWRpbzogRGVjbGFyZSBkZXZpY2UgbGl0dGxlIG9yIGJpZyBlbmRpYW4KICBo dy9ibG9jazogRGVjbGFyZSBkZXZpY2UgbGl0dGxlIG9yIGJpZyBlbmRpYW4KICBody9jaGFyOiBE ZWNsYXJlIGRldmljZSBsaXR0bGUgb3IgYmlnIGVuZGlhbgogIGh3L2Rpc3BsYXk6IERlY2xhcmUg ZGV2aWNlIGxpdHRsZSBvciBiaWcgZW5kaWFuCiAgaHcvZG1hOiBEZWNsYXJlIGRldmljZSBsaXR0 bGUgb3IgYmlnIGVuZGlhbgogIGh3L2dwaW86IERlY2xhcmUgZGV2aWNlIGxpdHRsZSBvciBiaWcg ZW5kaWFuCiAgaHcvaTJjOiBEZWNsYXJlIGRldmljZSBsaXR0bGUgb3IgYmlnIGVuZGlhbgogIGh3 L2lucHV0OiBEZWNsYXJlIGRldmljZSBsaXR0bGUgb3IgYmlnIGVuZGlhbgogIGh3L2ludGM6IERl Y2xhcmUgZGV2aWNlIGxpdHRsZSBvciBiaWcgZW5kaWFuCiAgaHcvaXNhOiBEZWNsYXJlIGRldmlj ZSBsaXR0bGUgb3IgYmlnIGVuZGlhbgogIGh3L21pc2M6IERlY2xhcmUgZGV2aWNlIGxpdHRsZSBv ciBiaWcgZW5kaWFuCiAgaHcvbmV0OiBEZWNsYXJlIGRldmljZSBsaXR0bGUgb3IgYmlnIGVuZGlh bgogIGh3L3BjaS1ob3N0OiBEZWNsYXJlIGRldmljZSBsaXR0bGUgb3IgYmlnIGVuZGlhbgogIGh3 L3NkOiBEZWNsYXJlIGRldmljZSBsaXR0bGUgb3IgYmlnIGVuZGlhbgogIGh3L3NzaTogRGVjbGFy ZSBkZXZpY2UgbGl0dGxlIG9yIGJpZyBlbmRpYW4KICBody90aW1lcjogRGVjbGFyZSBkZXZpY2Ug bGl0dGxlIG9yIGJpZyBlbmRpYW4KICBidWlsZDogQ29ycmVjdCBub24tY29tbW9uIGNvbW1vbi1v YmotKiB0byBvYmotKgogIGV4ZWM6IE1hcCBkZXZpY2VfZW5kaWFuIG9udG8gTWVtT3AKICBleGVj OiBSZXBsYWNlIGRldmljZV9lbmRpYW4gd2l0aCBNZW1PcAogIGV4ZWM6IERlbGV0ZSBkZXZpY2Vf ZW5kaWFuCiAgZXhlYzogRGVsZXRlIERFVklDRV9IT1NUX0VORElBTgogIG1lbW9yeTogQWNjZXNz IE1lbW9yeVJlZ2lvbiB3aXRoIGVuZGlhbm5lc3MKICBjcHV0bGI6IFJlcGxhY2Ugc2l6ZSBhbmQg ZW5kaWFuIG9wZXJhbmRzIGZvciBNZW1PcAogIG1lbW9yeTogU2luZ2xlIGJ5dGUgc3dhcCBhbG9u ZyB0aGUgSS9PIHBhdGgKICBjcHU6IFRMQl9GTEFHU19NQVNLIGJpdCB0byBmb3JjZSBtZW1vcnkg c2xvdyBwYXRoCiAgY3B1dGxiOiBCeXRlIHN3YXAgbWVtb3J5IHRyYW5zYWN0aW9uIGF0dHJpYnV0 ZQogIHRhcmdldC9zcGFyYzogQWRkIFRMQiBlbnRyeSB3aXRoIGF0dHJpYnV0ZXMKICB0YXJnZXQv c3BhcmM6IHN1bjR1IEludmVydCBFbmRpYW4gVFRFIGJpdAoKIE1BSU5UQUlORVJTICAgICAgICAg ICAgICAgICAgICAgICAgICAgICB8ICAgMSArCiBhY2NlbC90Y2cvY3B1dGxiLmMgICAgICAgICAg ICAgICAgICAgICAgfCAxOTcgKysrKysrKysrKysrKystLS0tLS0tLS0tLS0tLS0tLS0KIGNvbmZp Z3VyZSAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICB8ICAxMCArLQogZXhlYy5jICAgICAg ICAgICAgICAgICAgICAgICAgICAgICAgICAgIHwgIDE1ICsrLQogaHcvYWNwaS9jb3JlLmMgICAg ICAgICAgICAgICAgICAgICAgICAgIHwgICA2ICstCiBody9hY3BpL2NwdS5jICAgICAgICAgICAg ICAgICAgICAgICAgICAgfCAgIDIgKy0KIGh3L2FjcGkvY3B1X2hvdHBsdWcuYyAgICAgICAgICAg ICAgICAgICB8ICAgMiArLQogaHcvYWNwaS9pY2g5LmMgICAgICAgICAgICAgICAgICAgICAgICAg IHwgICA0ICstCiBody9hY3BpL21lbW9yeV9ob3RwbHVnLmMgICAgICAgICAgICAgICAgfCAgIDIg Ky0KIGh3L2FjcGkvbnZkaW1tLmMgICAgICAgICAgICAgICAgICAgICAgICB8ICAgMiArLQogaHcv YWNwaS9wY2locC5jICAgICAgICAgICAgICAgICAgICAgICAgIHwgICAyICstCiBody9hY3BpL3Bp aXg0LmMgICAgICAgICAgICAgICAgICAgICAgICAgfCAgIDIgKy0KIGh3L2FjcGkvdGNvLmMgICAg ICAgICAgICAgICAgICAgICAgICAgICB8ICAgMiArLQogaHcvYWRjL3N0bTMyZjJ4eF9hZGMuYyAg ICAgICAgICAgICAgICAgIHwgICAyICstCiBody9hbHBoYS9wY2kuYyAgICAgICAgICAgICAgICAg ICAgICAgICAgfCAgIDYgKy0KIGh3L2FscGhhL3R5cGhvb24uYyAgICAgICAgICAgICAgICAgICAg ICB8ICAgNiArLQogaHcvYXJtL2FsbHdpbm5lci1hMTAuYyAgICAgICAgICAgICAgICAgIHwgICAy ICstCiBody9hcm0vYXJtdjdtLmMgICAgICAgICAgICAgICAgICAgICAgICAgfCAgIDIgKy0KIGh3 L2FybS9hc3BlZWQuYyAgICAgICAgICAgICAgICAgICAgICAgICB8ICAgMiArLQogaHcvYXJtL2Fz cGVlZF9zb2MuYyAgICAgICAgICAgICAgICAgICAgIHwgICAyICstCiBody9hcm0vZXh5bm9zNDIx MC5jICAgICAgICAgICAgICAgICAgICAgfCAgIDIgKy0KIGh3L2FybS9oaWdoYmFuay5jICAgICAg ICAgICAgICAgICAgICAgICB8ICAgMiArLQogaHcvYXJtL2ludGVncmF0b3JjcC5jICAgICAgICAg ICAgICAgICAgIHwgICA2ICstCiBody9hcm0va3ptLmMgICAgICAgICAgICAgICAgICAgICAgICAg ICAgfCAgIDIgKy0KIGh3L2FybS9tc2YyLXNvYy5jICAgICAgICAgICAgICAgICAgICAgICB8ICAg MiArLQogaHcvYXJtL211c2ljcGFsLmMgICAgICAgICAgICAgICAgICAgICAgIHwgIDIwICsrLS0K IGh3L2FybS9vbWFwMS5jICAgICAgICAgICAgICAgICAgICAgICAgICB8ICA0MCArKystLS0tCiBo dy9hcm0vb21hcDIuYyAgICAgICAgICAgICAgICAgICAgICAgICAgfCAgMTAgKy0KIGh3L2FybS9v bWFwX3N4MS5jICAgICAgICAgICAgICAgICAgICAgICB8ICAgMiArLQogaHcvYXJtL3BhbG0uYyAg ICAgICAgICAgICAgICAgICAgICAgICAgIHwgICAyICstCiBody9hcm0vcHhhMnh4LmMgICAgICAg ICAgICAgICAgICAgICAgICAgfCAgMjAgKystLQogaHcvYXJtL3B4YTJ4eF9ncGlvLmMgICAgICAg ICAgICAgICAgICAgIHwgICAyICstCiBody9hcm0vcHhhMnh4X3BpYy5jICAgICAgICAgICAgICAg ICAgICAgfCAgIDIgKy0KIGh3L2FybS9zbW11djMuYyAgICAgICAgICAgICAgICAgICAgICAgICB8 ICAgMiArLQogaHcvYXJtL3NwaXR6LmMgICAgICAgICAgICAgICAgICAgICAgICAgIHwgICAyICst CiBody9hcm0vc3RlbGxhcmlzLmMgICAgICAgICAgICAgICAgICAgICAgfCAgIDggKy0KIGh3L2Fy bS9zdHJvbmdhcm0uYyAgICAgICAgICAgICAgICAgICAgICB8ICAxMiArLQogaHcvYXJtL3ZlcnNh dGlsZXBiLmMgICAgICAgICAgICAgICAgICAgIHwgICAyICstCiBody9hdWRpby9NYWtlZmlsZS5v YmpzICAgICAgICAgICAgICAgICAgfCAgIDMgKy0KIGh3L2F1ZGlvL2FjOTcuYyAgICAgICAgICAg ICAgICAgICAgICAgICB8ICAgNCArLQogaHcvYXVkaW8vY3M0MjMxLmMgICAgICAgICAgICAgICAg ICAgICAgIHwgICAyICstCiBody9hdWRpby9lczEzNzAuYyAgICAgICAgICAgICAgICAgICAgICAg fCAgIDIgKy0KIGh3L2F1ZGlvL2ludGVsLWhkYS5jICAgICAgICAgICAgICAgICAgICB8ICAgMiAr LQogaHcvYXVkaW8vbWFydmVsbF84OHc4NjE4LmMgICAgICAgICAgICAgIHwgICAyICstCiBody9h dWRpby9taWxreW1pc3QtYWM5Ny5jICAgICAgICAgICAgICAgfCAgIDIgKy0KIGh3L2F1ZGlvL3Bs MDQxLmMgICAgICAgICAgICAgICAgICAgICAgICB8ICAgMiArLQogaHcvYmxvY2svTWFrZWZpbGUu b2JqcyAgICAgICAgICAgICAgICAgIHwgICA2ICstCiBody9ibG9jay9mZGMuYyAgICAgICAgICAg ICAgICAgICAgICAgICAgfCAgIDQgKy0KIGh3L2Jsb2NrL252bWUuYyAgICAgICAgICAgICAgICAg ICAgICAgICB8ICAgNCArLQogaHcvYmxvY2svb25lbmFuZC5jICAgICAgICAgICAgICAgICAgICAg IHwgICAyICstCiBody9ibG9jay9wZmxhc2hfY2ZpMDEuYyAgICAgICAgICAgICAgICAgfCAgIDIg Ky0KIGh3L2Jsb2NrL3BmbGFzaF9jZmkwMi5jICAgICAgICAgICAgICAgICB8ICAgMiArLQogaHcv Y2hhci9NYWtlZmlsZS5vYmpzICAgICAgICAgICAgICAgICAgIHwgICA0ICstCiBody9jaGFyL2Jj bTI4MzVfYXV4LmMgICAgICAgICAgICAgICAgICAgfCAgIDIgKy0KIGh3L2NoYXIvY2FkZW5jZV91 YXJ0LmMgICAgICAgICAgICAgICAgICB8ICAgMiArLQogaHcvY2hhci9jbXNkay1hcGItdWFydC5j ICAgICAgICAgICAgICAgIHwgICAyICstCiBody9jaGFyL2RlYnVnY29uLmMgICAgICAgICAgICAg ICAgICAgICAgfCAgIDIgKy0KIGh3L2NoYXIvZGlnaWMtdWFydC5jICAgICAgICAgICAgICAgICAg ICB8ICAgMiArLQogaHcvY2hhci9lc2NjLmMgICAgICAgICAgICAgICAgICAgICAgICAgIHwgICAy ICstCiBody9jaGFyL2V0cmF4ZnNfc2VyLmMgICAgICAgICAgICAgICAgICAgfCAgIDIgKy0KIGh3 L2NoYXIvZXh5bm9zNDIxMF91YXJ0LmMgICAgICAgICAgICAgICB8ICAgMiArLQogaHcvY2hhci9n cmxpYl9hcGJ1YXJ0LmMgICAgICAgICAgICAgICAgIHwgICAyICstCiBody9jaGFyL2lteF9zZXJp YWwuYyAgICAgICAgICAgICAgICAgICAgfCAgIDIgKy0KIGh3L2NoYXIvbG0zMl91YXJ0LmMgICAg ICAgICAgICAgICAgICAgICB8ICAgMiArLQogaHcvY2hhci9tY2ZfdWFydC5jICAgICAgICAgICAg ICAgICAgICAgIHwgICAyICstCiBody9jaGFyL21pbGt5bWlzdC11YXJ0LmMgICAgICAgICAgICAg ICAgfCAgIDIgKy0KIGh3L2NoYXIvbnJmNTFfdWFydC5jICAgICAgICAgICAgICAgICAgICB8ICAg MiArLQogaHcvY2hhci9vbWFwX3VhcnQuYyAgICAgICAgICAgICAgICAgICAgIHwgICA2ICstCiBo dy9jaGFyL3BhcmFsbGVsLmMgICAgICAgICAgICAgICAgICAgICAgfCAgIDIgKy0KIGh3L2NoYXIv cGwwMTEuYyAgICAgICAgICAgICAgICAgICAgICAgICB8ICAgMiArLQogaHcvY2hhci9zZXJpYWwu YyAgICAgICAgICAgICAgICAgICAgICAgIHwgIDI2ICsrLS0tCiBody9jaGFyL3NoX3NlcmlhbC5j ICAgICAgICAgICAgICAgICAgICAgfCAgIDIgKy0KIGh3L2NoYXIvc3RtMzJmMnh4X3VzYXJ0LmMg ICAgICAgICAgICAgICB8ICAgMiArLQogaHcvY2hhci94aWxpbnhfdWFydGxpdGUuYyAgICAgICAg ICAgICAgIHwgICAyICstCiBody9jb3JlL01ha2VmaWxlLm9ianMgICAgICAgICAgICAgICAgICAg fCAgIDIgKy0KIGh3L2NvcmUvZW1wdHlfc2xvdC5jICAgICAgICAgICAgICAgICAgICB8ICAgMiAr LQogaHcvY3Jpcy9heGlzX2Rldjg4LmMgICAgICAgICAgICAgICAgICAgIHwgICA0ICstCiBody9k aXNwbGF5L01ha2VmaWxlLm9ianMgICAgICAgICAgICAgICAgfCAgIDYgKy0KIGh3L2Rpc3BsYXkv YXRpLmMgICAgICAgICAgICAgICAgICAgICAgICB8ICAgMiArLQogaHcvZGlzcGxheS9iY20yODM1 X2ZiLmMgICAgICAgICAgICAgICAgIHwgICAyICstCiBody9kaXNwbGF5L2JvY2hzLWRpc3BsYXku YyAgICAgICAgICAgICAgfCAgIDQgKy0KIGh3L2Rpc3BsYXkvY2czLmMgICAgICAgICAgICAgICAg ICAgICAgICB8ICAgMiArLQogaHcvZGlzcGxheS9jaXJydXNfdmdhLmMgICAgICAgICAgICAgICAg IHwgIDEwICstCiBody9kaXNwbGF5L2VkaWQtcmVnaW9uLmMgICAgICAgICAgICAgICAgfCAgIDIg Ky0KIGh3L2Rpc3BsYXkvZXh5bm9zNDIxMF9maW1kLmMgICAgICAgICAgICB8ICAgMiArLQogaHcv ZGlzcGxheS9nMzY0ZmIuYyAgICAgICAgICAgICAgICAgICAgIHwgICAyICstCiBody9kaXNwbGF5 L2phenpfbGVkLmMgICAgICAgICAgICAgICAgICAgfCAgIDIgKy0KIGh3L2Rpc3BsYXkvbWlsa3lt aXN0LXRtdTIuYyAgICAgICAgICAgICB8ICAgMiArLQogaHcvZGlzcGxheS9taWxreW1pc3Qtdmdh ZmIuYyAgICAgICAgICAgIHwgICAyICstCiBody9kaXNwbGF5L29tYXBfZHNzLmMgICAgICAgICAg ICAgICAgICAgfCAgMTAgKy0KIGh3L2Rpc3BsYXkvb21hcF9sY2RjLmMgICAgICAgICAgICAgICAg ICB8ICAgMiArLQogaHcvZGlzcGxheS9wbDExMC5jICAgICAgICAgICAgICAgICAgICAgIHwgICAy ICstCiBody9kaXNwbGF5L3B4YTJ4eF9sY2QuYyAgICAgICAgICAgICAgICAgfCAgIDIgKy0KIGh3 L2Rpc3BsYXkvc201MDEuYyAgICAgICAgICAgICAgICAgICAgICB8ICAxMCArLQogaHcvZGlzcGxh eS90YzYzOTN4Yi5jICAgICAgICAgICAgICAgICAgIHwgICAyICstCiBody9kaXNwbGF5L3RjeC5j ICAgICAgICAgICAgICAgICAgICAgICAgfCAgMTQgKy0tCiBody9kaXNwbGF5L3ZnYS1pc2EtbW0u YyAgICAgICAgICAgICAgICAgfCAgIDIgKy0KIGh3L2Rpc3BsYXkvdmdhLXBjaS5jICAgICAgICAg ICAgICAgICAgICB8ICAgNiArLQogaHcvZGlzcGxheS92Z2EuYyAgICAgICAgICAgICAgICAgICAg ICAgIHwgICAyICstCiBody9kaXNwbGF5L3Ztd2FyZV92Z2EuYyAgICAgICAgICAgICAgICAgfCAg IDIgKy0KIGh3L2Rpc3BsYXkveGxueF9kcC5jICAgICAgICAgICAgICAgICAgICB8ICAgOCArLQog aHcvZG1hL01ha2VmaWxlLm9ianMgICAgICAgICAgICAgICAgICAgIHwgICA2ICstCiBody9kbWEv YmNtMjgzNV9kbWEuYyAgICAgICAgICAgICAgICAgICAgfCAgIDQgKy0KIGh3L2RtYS9ldHJheGZz X2RtYS5jICAgICAgICAgICAgICAgICAgICB8ICAgMiArLQogaHcvZG1hL2k4MjU3LmMgICAgICAg ICAgICAgICAgICAgICAgICAgIHwgICA0ICstCiBody9kbWEvb21hcF9kbWEuYyAgICAgICAgICAg ICAgICAgICAgICAgfCAgIDQgKy0KIGh3L2RtYS9wbDA4MC5jICAgICAgICAgICAgICAgICAgICAg ICAgICB8ICAgMiArLQogaHcvZG1hL3BsMzMwLmMgICAgICAgICAgICAgICAgICAgICAgICAgIHwg ICAyICstCiBody9kbWEvcHV2M19kbWEuYyAgICAgICAgICAgICAgICAgICAgICAgfCAgIDIgKy0K IGh3L2RtYS9weGEyeHhfZG1hLmMgICAgICAgICAgICAgICAgICAgICB8ICAgMiArLQogaHcvZG1h L3JjNDAzMC5jICAgICAgICAgICAgICAgICAgICAgICAgIHwgICA0ICstCiBody9kbWEvc3BhcmMz Ml9kbWEuYyAgICAgICAgICAgICAgICAgICAgfCAgIDIgKy0KIGh3L2RtYS94aWxpbnhfYXhpZG1h LmMgICAgICAgICAgICAgICAgICB8ICAgMiArLQogaHcvZG1hL3hsbngtemRtYS5jICAgICAgICAg ICAgICAgICAgICAgIHwgICAyICstCiBody9kbWEveGxueC16eW5xLWRldmNmZy5jICAgICAgICAg ICAgICAgfCAgIDIgKy0KIGh3L2RtYS94bG54X2RwZG1hLmMgICAgICAgICAgICAgICAgICAgICB8 ICAgMiArLQogaHcvZ3Bpby9NYWtlZmlsZS5vYmpzICAgICAgICAgICAgICAgICAgIHwgICAyICst CiBody9ncGlvL2JjbTI4MzVfZ3Bpby5jICAgICAgICAgICAgICAgICAgfCAgIDIgKy0KIGh3L2dw aW8vaW14X2dwaW8uYyAgICAgICAgICAgICAgICAgICAgICB8ICAgMiArLQogaHcvZ3Bpby9tcGM4 eHh4LmMgICAgICAgICAgICAgICAgICAgICAgIHwgICAyICstCiBody9ncGlvL25yZjUxX2dwaW8u YyAgICAgICAgICAgICAgICAgICAgfCAgIDIgKy0KIGh3L2dwaW8vb21hcF9ncGlvLmMgICAgICAg ICAgICAgICAgICAgICB8ICAgNiArLQogaHcvZ3Bpby9wbDA2MS5jICAgICAgICAgICAgICAgICAg ICAgICAgIHwgICAyICstCiBody9ncGlvL3B1djNfZ3Bpby5jICAgICAgICAgICAgICAgICAgICAg fCAgIDIgKy0KIGh3L2dwaW8vemF1cnVzLmMgICAgICAgICAgICAgICAgICAgICAgICB8ICAgMiAr LQogaHcvaHBwYS9kaW5vLmMgICAgICAgICAgICAgICAgICAgICAgICAgIHwgICA2ICstCiBody9o cHBhL21hY2hpbmUuYyAgICAgICAgICAgICAgICAgICAgICAgfCAgIDIgKy0KIGh3L2hwcGEvcGNp LmMgICAgICAgICAgICAgICAgICAgICAgICAgICB8ICAgNiArLQogaHcvaHlwZXJ2L2h5cGVydl90 ZXN0ZGV2LmMgICAgICAgICAgICAgIHwgICAyICstCiBody9pMmMvTWFrZWZpbGUub2JqcyAgICAg ICAgICAgICAgICAgICAgfCAgIDIgKy0KIGh3L2kyYy9hc3BlZWRfaTJjLmMgICAgICAgICAgICAg ICAgICAgICB8ICAgNCArLQogaHcvaTJjL2V4eW5vczQyMTBfaTJjLmMgICAgICAgICAgICAgICAg IHwgICAyICstCiBody9pMmMvaW14X2kyYy5jICAgICAgICAgICAgICAgICAgICAgICAgfCAgIDIg Ky0KIGh3L2kyYy9taWNyb2JpdF9pMmMuYyAgICAgICAgICAgICAgICAgICB8ICAgMiArLQogaHcv aTJjL21wY19pMmMuYyAgICAgICAgICAgICAgICAgICAgICAgIHwgICAyICstCiBody9pMmMvb21h cF9pMmMuYyAgICAgICAgICAgICAgICAgICAgICAgfCAgIDIgKy0KIGh3L2kyYy9wbV9zbWJ1cy5j ICAgICAgICAgICAgICAgICAgICAgICB8ICAgMiArLQogaHcvaTJjL3BwYzR4eF9pMmMuYyAgICAg ICAgICAgICAgICAgICAgIHwgICAyICstCiBody9pMmMvdmVyc2F0aWxlX2kyYy5jICAgICAgICAg ICAgICAgICAgfCAgIDIgKy0KIGh3L2kzODYvYW1kX2lvbW11LmMgICAgICAgICAgICAgICAgICAg ICB8ICAgNCArLQogaHcvaTM4Ni9pbnRlbF9pb21tdS5jICAgICAgICAgICAgICAgICAgIHwgICA0 ICstCiBody9pMzg2L2t2bS9hcGljLmMgICAgICAgICAgICAgICAgICAgICAgfCAgIDIgKy0KIGh3 L2kzODYva3ZtdmFwaWMuYyAgICAgICAgICAgICAgICAgICAgICB8ICAgMiArLQogaHcvaTM4Ni9w Yy5jICAgICAgICAgICAgICAgICAgICAgICAgICAgIHwgICA2ICstCiBody9pMzg2L3ZtcG9ydC5j ICAgICAgICAgICAgICAgICAgICAgICAgfCAgIDIgKy0KIGh3L2kzODYveGVuL3hlbl9hcGljLmMg ICAgICAgICAgICAgICAgICB8ICAgMiArLQogaHcvaTM4Ni94ZW4veGVuX3BsYXRmb3JtLmMgICAg ICAgICAgICAgIHwgICA0ICstCiBody9pMzg2L3hlbi94ZW5fcHZkZXZpY2UuYyAgICAgICAgICAg ICAgfCAgIDIgKy0KIGh3L2lkZS9haGNpLWFsbHdpbm5lci5jICAgICAgICAgICAgICAgICB8ICAg MiArLQogaHcvaWRlL2FoY2kuYyAgICAgICAgICAgICAgICAgICAgICAgICAgIHwgICA0ICstCiBo dy9pZGUvbWFjaW8uYyAgICAgICAgICAgICAgICAgICAgICAgICAgfCAgIDIgKy0KIGh3L2lkZS9t bWlvLmMgICAgICAgICAgICAgICAgICAgICAgICAgICB8ICAgNCArLQogaHcvaWRlL3BjaS5jICAg ICAgICAgICAgICAgICAgICAgICAgICAgIHwgICA2ICstCiBody9pZGUvc2lpMzExMi5jICAgICAg ICAgICAgICAgICAgICAgICAgfCAgIDIgKy0KIGh3L2lucHV0L01ha2VmaWxlLm9ianMgICAgICAg ICAgICAgICAgICB8ICAgMiArLQogaHcvaW5wdXQvbWlsa3ltaXN0LXNvZnR1c2IuYyAgICAgICAg ICAgIHwgICAyICstCiBody9pbnB1dC9wY2tiZC5jICAgICAgICAgICAgICAgICAgICAgICAgfCAg IDYgKy0KIGh3L2lucHV0L3BsMDUwLmMgICAgICAgICAgICAgICAgICAgICAgICB8ICAgMiArLQog aHcvaW5wdXQvcHhhMnh4X2tleXBhZC5jICAgICAgICAgICAgICAgIHwgICAyICstCiBody9pbnRj L01ha2VmaWxlLm9ianMgICAgICAgICAgICAgICAgICAgfCAgIDYgKy0KIGh3L2ludGMvYWxsd2lu bmVyLWExMC1waWMuYyAgICAgICAgICAgICB8ICAgMiArLQogaHcvaW50Yy9hcGljLmMgICAgICAg ICAgICAgICAgICAgICAgICAgIHwgICAyICstCiBody9pbnRjL2FybV9naWMuYyAgICAgICAgICAg ICAgICAgICAgICAgfCAgMTIgKy0KIGh3L2ludGMvYXJtX2dpY3YybS5jICAgICAgICAgICAgICAg ICAgICB8ICAgMiArLQogaHcvaW50Yy9hcm1fZ2ljdjMuYyAgICAgICAgICAgICAgICAgICAgIHwg ICA0ICstCiBody9pbnRjL2FybV9naWN2M19pdHNfY29tbW9uLmMgICAgICAgICAgfCAgIDIgKy0K IGh3L2ludGMvYXJtdjdtX252aWMuYyAgICAgICAgICAgICAgICAgICB8ICAxOSArLS0KIGh3L2lu dGMvYXNwZWVkX3ZpYy5jICAgICAgICAgICAgICAgICAgICB8ICAgMiArLQogaHcvaW50Yy9iY20y ODM1X2ljLmMgICAgICAgICAgICAgICAgICAgIHwgICAyICstCiBody9pbnRjL2JjbTI4MzZfY29u dHJvbC5jICAgICAgICAgICAgICAgfCAgIDIgKy0KIGh3L2ludGMvZXRyYXhmc19waWMuYyAgICAg ICAgICAgICAgICAgICB8ICAgMiArLQogaHcvaW50Yy9leHlub3M0MjEwX2NvbWJpbmVyLmMgICAg ICAgICAgIHwgICAyICstCiBody9pbnRjL2dybGliX2lycW1wLmMgICAgICAgICAgICAgICAgICAg fCAgIDIgKy0KIGh3L2ludGMvaGVhdGhyb3dfcGljLmMgICAgICAgICAgICAgICAgICB8ICAgMiAr LQogaHcvaW50Yy9pbXhfYXZpYy5jICAgICAgICAgICAgICAgICAgICAgIHwgICAyICstCiBody9p bnRjL2lteF9ncGN2Mi5jICAgICAgICAgICAgICAgICAgICAgfCAgIDIgKy0KIGh3L2ludGMvaW9h cGljLmMgICAgICAgICAgICAgICAgICAgICAgICB8ICAgMiArLQogaHcvaW50Yy9taXBzX2dpYy5j ICAgICAgICAgICAgICAgICAgICAgIHwgICAyICstCiBody9pbnRjL29tYXBfaW50Yy5jICAgICAg ICAgICAgICAgICAgICAgfCAgIDQgKy0KIGh3L2ludGMvb21waWMuYyAgICAgICAgICAgICAgICAg ICAgICAgICB8ICAgMiArLQogaHcvaW50Yy9vcGVucGljLmMgICAgICAgICAgICAgICAgICAgICAg IHwgIDIwICsrLS0KIGh3L2ludGMvb3BlbnBpY19rdm0uYyAgICAgICAgICAgICAgICAgICB8ICAg MiArLQogaHcvaW50Yy9wbDE5MC5jICAgICAgICAgICAgICAgICAgICAgICAgIHwgICAyICstCiBo dy9pbnRjL3Budl94aXZlLmMgICAgICAgICAgICAgICAgICAgICAgfCAgMTQgKy0tCiBody9pbnRj L3B1djNfaW50Yy5jICAgICAgICAgICAgICAgICAgICAgfCAgIDIgKy0KIGh3L2ludGMvc2hfaW50 Yy5jICAgICAgICAgICAgICAgICAgICAgICB8ICAgMiArLQogaHcvaW50Yy9zbGF2aW9faW50Y3Rs LmMgICAgICAgICAgICAgICAgIHwgICA0ICstCiBody9pbnRjL3hpY3NfcG52LmMgICAgICAgICAg ICAgICAgICAgICAgfCAgIDIgKy0KIGh3L2ludGMveGlsaW54X2ludGMuYyAgICAgICAgICAgICAg ICAgICB8ICAgMiArLQogaHcvaW50Yy94aXZlLmMgICAgICAgICAgICAgICAgICAgICAgICAgIHwg ICA2ICstCiBody9pbnRjL3hsbngtcG11LWlvbW9kLWludGMuYyAgICAgICAgICAgfCAgIDIgKy0K IGh3L2ludGMveGxueC16eW5xbXAtaXBpLmMgICAgICAgICAgICAgICB8ICAgMiArLQogaHcvaXBh Y2svTWFrZWZpbGUub2JqcyAgICAgICAgICAgICAgICAgIHwgICAyICstCiBody9pcGFjay90cGNp MjAwLmMgICAgICAgICAgICAgICAgICAgICAgfCAgMTAgKy0KIGh3L2lwbWkvaXNhX2lwbWlfYnQu YyAgICAgICAgICAgICAgICAgICB8ICAgMiArLQogaHcvaXBtaS9pc2FfaXBtaV9rY3MuYyAgICAg ICAgICAgICAgICAgIHwgICAyICstCiBody9pc2EvbHBjX2ljaDkuYyAgICAgICAgICAgICAgICAg ICAgICAgfCAgIDQgKy0KIGh3L2lzYS9wYzg3MzEyLmMgICAgICAgICAgICAgICAgICAgICAgICB8 ICAgMiArLQogaHcvaXNhL3Z0ODJjNjg2LmMgICAgICAgICAgICAgICAgICAgICAgIHwgICAyICst CiBody9tNjhrL21jZjUyMDYuYyAgICAgICAgICAgICAgICAgICAgICAgfCAgIDIgKy0KIGh3L202 OGsvbWNmNTIwOC5jICAgICAgICAgICAgICAgICAgICAgICB8ICAgNCArLQogaHcvbTY4ay9tY2Zf aW50Yy5jICAgICAgICAgICAgICAgICAgICAgIHwgICAyICstCiBody9taWNyb2JsYXplL3BldGFs b2dpeF9tbDYwNV9tbXUuYyAgICAgfCAgIDIgKy0KIGh3L21pcHMvYm9zdG9uLmMgICAgICAgICAg ICAgICAgICAgICAgICB8ICAgNiArLQogaHcvbWlwcy9ndDY0eHh4X3BjaS5jICAgICAgICAgICAg ICAgICAgIHwgICAyICstCiBody9taXBzL21pcHNfamF6ei5jICAgICAgICAgICAgICAgICAgICAg fCAgIDggKy0KIGh3L21pcHMvbWlwc19tYWx0YS5jICAgICAgICAgICAgICAgICAgICB8ICAgNCAr LQogaHcvbWlwcy9taXBzX3I0ay5jICAgICAgICAgICAgICAgICAgICAgIHwgICAyICstCiBody9t aXNjL01ha2VmaWxlLm9ianMgICAgICAgICAgICAgICAgICAgfCAgMTAgKy0KIGh3L21pc2MvYTlz Y3UuYyAgICAgICAgICAgICAgICAgICAgICAgICB8ICAgMiArLQogaHcvbWlzYy9hcHBsZXNtYy5j ICAgICAgICAgICAgICAgICAgICAgIHwgICA2ICstCiBody9taXNjL2FybTExc2N1LmMgICAgICAg ICAgICAgICAgICAgICAgfCAgIDIgKy0KIGh3L21pc2MvYXJtX2ludGVncmF0b3JfZGVidWcuYyAg ICAgICAgICB8ICAgMiArLQogaHcvbWlzYy9hcm1fbDJ4MC5jICAgICAgICAgICAgICAgICAgICAg IHwgICAyICstCiBody9taXNjL2FybV9zeXNjdGwuYyAgICAgICAgICAgICAgICAgICAgfCAgIDIg Ky0KIGh3L21pc2MvYXJtc3NlLWNwdWlkLmMgICAgICAgICAgICAgICAgICB8ICAgMiArLQogaHcv bWlzYy9hcm1zc2UtbWh1LmMgICAgICAgICAgICAgICAgICAgIHwgICAyICstCiBody9taXNjL2Fz cGVlZF9zY3UuYyAgICAgICAgICAgICAgICAgICAgfCAgIDIgKy0KIGh3L21pc2MvYXNwZWVkX3Nk bWMuYyAgICAgICAgICAgICAgICAgICB8ICAgMiArLQogaHcvbWlzYy9hc3BlZWRfeGRtYS5jICAg ICAgICAgICAgICAgICAgIHwgICAyICstCiBody9taXNjL2JjbTI4MzVfbWJveC5jICAgICAgICAg ICAgICAgICAgfCAgIDIgKy0KIGh3L21pc2MvYmNtMjgzNV9wcm9wZXJ0eS5jICAgICAgICAgICAg ICB8ICAgMiArLQogaHcvbWlzYy9iY20yODM1X3JuZy5jICAgICAgICAgICAgICAgICAgIHwgICAy ICstCiBody9taXNjL2RlYnVnZXhpdC5jICAgICAgICAgICAgICAgICAgICAgfCAgIDIgKy0KIGh3 L21pc2MvZWNjbWVtY3RsLmMgICAgICAgICAgICAgICAgICAgICB8ICAgNCArLQogaHcvbWlzYy9l ZHUuYyAgICAgICAgICAgICAgICAgICAgICAgICAgIHwgICAyICstCiBody9taXNjL2V4eW5vczQy MTBfY2xrLmMgICAgICAgICAgICAgICAgfCAgIDIgKy0KIGh3L21pc2MvZXh5bm9zNDIxMF9wbXUu YyAgICAgICAgICAgICAgICB8ICAgMiArLQogaHcvbWlzYy9leHlub3M0MjEwX3JuZy5jICAgICAg ICAgICAgICAgIHwgICAyICstCiBody9taXNjL2dybGliX2FoYl9hcGJfcG5wLmMgICAgICAgICAg ICAgfCAgIDQgKy0KIGh3L21pc2MvaW14MjVfY2NtLmMgICAgICAgICAgICAgICAgICAgICB8ICAg MiArLQogaHcvbWlzYy9pbXgyX3dkdC5jICAgICAgICAgICAgICAgICAgICAgIHwgICAyICstCiBo dy9taXNjL2lteDMxX2NjbS5jICAgICAgICAgICAgICAgICAgICAgfCAgIDIgKy0KIGh3L21pc2Mv aW14Nl9jY20uYyAgICAgICAgICAgICAgICAgICAgICB8ICAgNCArLQogaHcvbWlzYy9pbXg2X3Ny Yy5jICAgICAgICAgICAgICAgICAgICAgIHwgICAyICstCiBody9taXNjL2lteDZ1bF9jY20uYyAg ICAgICAgICAgICAgICAgICAgfCAgIDQgKy0KIGh3L21pc2MvaW14N19jY20uYyAgICAgICAgICAg ICAgICAgICAgICB8ICAgNCArLQogaHcvbWlzYy9pbXg3X2dwci5jICAgICAgICAgICAgICAgICAg ICAgIHwgICAyICstCiBody9taXNjL2lteDdfc252cy5jICAgICAgICAgICAgICAgICAgICAgfCAg IDIgKy0KIGh3L21pc2MvaW90a2l0LXNlY2N0bC5jICAgICAgICAgICAgICAgICB8ICAgNCArLQog aHcvbWlzYy9pb3RraXQtc3lzY3RsLmMgICAgICAgICAgICAgICAgIHwgICAyICstCiBody9taXNj L2lvdGtpdC1zeXNpbmZvLmMgICAgICAgICAgICAgICAgfCAgIDIgKy0KIGh3L21pc2MvaXZzaG1l bS5jICAgICAgICAgICAgICAgICAgICAgICB8ICAgMiArLQogaHcvbWlzYy9tYWNpby9jdWRhLmMg ICAgICAgICAgICAgICAgICAgIHwgICAyICstCiBody9taXNjL21hY2lvL2dwaW8uYyAgICAgICAg ICAgICAgICAgICAgfCAgIDIgKy0KIGh3L21pc2MvbWFjaW8vbWFjX2RiZG1hLmMgICAgICAgICAg ICAgICB8ICAgMiArLQogaHcvbWlzYy9tYWNpby9tYWNpby5jICAgICAgICAgICAgICAgICAgIHwg ICAyICstCiBody9taXNjL21hY2lvL3BtdS5jICAgICAgICAgICAgICAgICAgICAgfCAgIDIgKy0K IGh3L21pc2MvbWlsa3ltaXN0LWhwZG1jLmMgICAgICAgICAgICAgICB8ICAgMiArLQogaHcvbWlz Yy9taWxreW1pc3QtcGZwdS5jICAgICAgICAgICAgICAgIHwgICAyICstCiBody9taXNjL21pcHNf Y21nY3IuYyAgICAgICAgICAgICAgICAgICAgfCAgIDIgKy0KIGh3L21pc2MvbWlwc19jcGMuYyAg ICAgICAgICAgICAgICAgICAgICB8ICAgMiArLQogaHcvbWlzYy9taXBzX2l0dS5jICAgICAgICAg ICAgICAgICAgICAgIHwgICA0ICstCiBody9taXNjL21vczY1MjIuYyAgICAgICAgICAgICAgICAg ICAgICAgfCAgIDIgKy0KIGh3L21pc2MvbXBzMi1mcGdhaW8uYyAgICAgICAgICAgICAgICAgICB8 ICAgMiArLQogaHcvbWlzYy9tcHMyLXNjYy5jICAgICAgICAgICAgICAgICAgICAgIHwgICAyICst CiBody9taXNjL21zZjItc3lzcmVnLmMgICAgICAgICAgICAgICAgICAgfCAgIDIgKy0KIGh3L21p c2MvbXN0X2ZwZ2EuYyAgICAgICAgICAgICAgICAgICAgICB8ICAgMiArLQogaHcvbWlzYy9ucmY1 MV9ybmcuYyAgICAgICAgICAgICAgICAgICAgIHwgICAyICstCiBody9taXNjL29tYXBfZ3BtYy5j ICAgICAgICAgICAgICAgICAgICAgfCAgIDYgKy0KIGh3L21pc2Mvb21hcF9sNC5jICAgICAgICAg ICAgICAgICAgICAgICB8ICAgMiArLQogaHcvbWlzYy9vbWFwX3NkcmMuYyAgICAgICAgICAgICAg ICAgICAgIHwgICAyICstCiBody9taXNjL29tYXBfdGFwLmMgICAgICAgICAgICAgICAgICAgICAg fCAgIDIgKy0KIGh3L21pc2MvcGMtdGVzdGRldi5jICAgICAgICAgICAgICAgICAgICB8ICAxMCAr LQogaHcvbWlzYy9wY2ktdGVzdGRldi5jICAgICAgICAgICAgICAgICAgIHwgICA0ICstCiBody9t aXNjL3B1djNfcG0uYyAgICAgICAgICAgICAgICAgICAgICAgfCAgIDIgKy0KIGh3L21pc2Mvc2xh dmlvX21pc2MuYyAgICAgICAgICAgICAgICAgICB8ICAxNiArLS0KIGh3L21pc2Mvc3RtMzJmMnh4 X3N5c2NmZy5jICAgICAgICAgICAgICB8ICAgMiArLQogaHcvbWlzYy90ei1tcGMuYyAgICAgICAg ICAgICAgICAgICAgICAgIHwgICA0ICstCiBody9taXNjL3R6LW1zYy5jICAgICAgICAgICAgICAg ICAgICAgICAgfCAgIDIgKy0KIGh3L21pc2MvdHotcHBjLmMgICAgICAgICAgICAgICAgICAgICAg ICB8ICAgMiArLQogaHcvbWlzYy91bmltcC5jICAgICAgICAgICAgICAgICAgICAgICAgIHwgICAy ICstCiBody9taXNjL3p5bnEteGFkYy5jICAgICAgICAgICAgICAgICAgICAgfCAgIDIgKy0KIGh3 L21pc2MvenlucV9zbGNyLmMgICAgICAgICAgICAgICAgICAgICB8ICAgMiArLQogaHcvbW94aWUv bW94aWVzaW0uYyAgICAgICAgICAgICAgICAgICAgIHwgICAyICstCiBody9uZXQvTWFrZWZpbGUu b2JqcyAgICAgICAgICAgICAgICAgICAgfCAgIDIgKy0KIGh3L25ldC9hbGx3aW5uZXJfZW1hYy5j ICAgICAgICAgICAgICAgICB8ICAgMiArLQogaHcvbmV0L2NhZGVuY2VfZ2VtLmMgICAgICAgICAg ICAgICAgICAgIHwgICAyICstCiBody9uZXQvY2FuL2Nhbl9rdmFzZXJfcGNpLmMgICAgICAgICAg ICAgfCAgIDYgKy0KIGh3L25ldC9jYW4vY2FuX21pb2UzNjgwX3BjaS5jICAgICAgICAgICB8ICAg NCArLQogaHcvbmV0L2Nhbi9jYW5fcGNtMzY4MF9wY2kuYyAgICAgICAgICAgIHwgICA0ICstCiBo dy9uZXQvZHA4MzkzeC5jICAgICAgICAgICAgICAgICAgICAgICAgfCAgIDIgKy0KIGh3L25ldC9l MTAwMC5jICAgICAgICAgICAgICAgICAgICAgICAgICB8ICAgNCArLQogaHcvbmV0L2UxMDAwZS5j ICAgICAgICAgICAgICAgICAgICAgICAgIHwgICA0ICstCiBody9uZXQvZWVwcm8xMDAuYyAgICAg ICAgICAgICAgICAgICAgICAgfCAgIDIgKy0KIGh3L25ldC9ldHJheGZzX2V0aC5jICAgICAgICAg ICAgICAgICAgICB8ICAgMiArLQogaHcvbmV0L2ZzbF9ldHNlYy9ldHNlYy5jICAgICAgICAgICAg ICAgIHwgICAyICstCiBody9uZXQvZnRnbWFjMTAwLmMgICAgICAgICAgICAgICAgICAgICAgfCAg IDIgKy0KIGh3L25ldC9pbXhfZmVjLmMgICAgICAgICAgICAgICAgICAgICAgICB8ICAgMiArLQog aHcvbmV0L2xhbjkxMTguYyAgICAgICAgICAgICAgICAgICAgICAgIHwgICA0ICstCiBody9uZXQv bGFuY2UuYyAgICAgICAgICAgICAgICAgICAgICAgICAgfCAgIDIgKy0KIGh3L25ldC9tY2ZfZmVj LmMgICAgICAgICAgICAgICAgICAgICAgICB8ICAgMiArLQogaHcvbmV0L21pbGt5bWlzdC1taW5p bWFjMi5jICAgICAgICAgICAgIHwgICAyICstCiBody9uZXQvbmUyMDAwLmMgICAgICAgICAgICAg ICAgICAgICAgICAgfCAgIDIgKy0KIGh3L25ldC9wY25ldC1wY2kuYyAgICAgICAgICAgICAgICAg ICAgICB8ICAgNCArLQogaHcvbmV0L3JvY2tlci9yb2NrZXIuYyAgICAgICAgICAgICAgICAgIHwg ICAyICstCiBody9uZXQvcnRsODEzOS5jICAgICAgICAgICAgICAgICAgICAgICAgfCAgIDIgKy0K IGh3L25ldC9zbWM5MWMxMTEuYyAgICAgICAgICAgICAgICAgICAgICB8ICAgMiArLQogaHcvbmV0 L3N0ZWxsYXJpc19lbmV0LmMgICAgICAgICAgICAgICAgIHwgICAyICstCiBody9uZXQvc3VuZ2Vt LmMgICAgICAgICAgICAgICAgICAgICAgICAgfCAgMTIgKy0KIGh3L25ldC9zdW5obWUuYyAgICAg ICAgICAgICAgICAgICAgICAgICB8ICAxMCArLQogaHcvbmV0L3ZteG5ldDMuYyAgICAgICAgICAg ICAgICAgICAgICAgIHwgICA0ICstCiBody9uZXQveGdtYWMuYyAgICAgICAgICAgICAgICAgICAg ICAgICAgfCAgIDIgKy0KIGh3L25ldC94aWxpbnhfYXhpZW5ldC5jICAgICAgICAgICAgICAgICB8 ICAgMiArLQogaHcvbmV0L3hpbGlueF9ldGhsaXRlLmMgICAgICAgICAgICAgICAgIHwgICAyICst CiBody9uaW9zMi8xMG01MF9kZXZib2FyZC5jICAgICAgICAgICAgICAgfCAgIDIgKy0KIGh3L252 cmFtL2RzMTIyNXkuYyAgICAgICAgICAgICAgICAgICAgICB8ICAgMiArLQogaHcvbnZyYW0vZndf Y2ZnLmMgICAgICAgICAgICAgICAgICAgICAgIHwgICA4ICstCiBody9udnJhbS9tYWNfbnZyYW0u YyAgICAgICAgICAgICAgICAgICAgfCAgIDIgKy0KIGh3L252cmFtL25yZjUxX252bS5jICAgICAg ICAgICAgICAgICAgICB8ICAgOCArLQogaHcvb3BlbnJpc2Mvb3BlbnJpc2Nfc2ltLmMgICAgICAg ICAgICAgIHwgICAyICstCiBody9wY2ktaG9zdC9NYWtlZmlsZS5vYmpzICAgICAgICAgICAgICAg fCAgIDIgKy0KIGh3L3BjaS1ob3N0L2Jvbml0by5jICAgICAgICAgICAgICAgICAgICB8ICAxMCAr LQogaHcvcGNpLWhvc3QvZGVzaWdud2FyZS5jICAgICAgICAgICAgICAgIHwgICA2ICstCiBody9w Y2ktaG9zdC9waWl4LmMgICAgICAgICAgICAgICAgICAgICAgfCAgIDIgKy0KIGh3L3BjaS1ob3N0 L3BwY2U1MDAuYyAgICAgICAgICAgICAgICAgICB8ICAgMiArLQogaHcvcGNpLWhvc3QvcHJlcC5j ICAgICAgICAgICAgICAgICAgICAgIHwgICA0ICstCiBody9wY2ktaG9zdC9xMzUuYyAgICAgICAg ICAgICAgICAgICAgICAgfCAgIDQgKy0KIGh3L3BjaS1ob3N0L3NhYnJlLmMgICAgICAgICAgICAg ICAgICAgICB8ICAgNCArLQogaHcvcGNpLWhvc3QvdW5pbm9ydGguYyAgICAgICAgICAgICAgICAg IHwgICA0ICstCiBody9wY2ktaG9zdC92ZXJzYXRpbGUuYyAgICAgICAgICAgICAgICAgfCAgIDQg Ky0KIGh3L3BjaS9tc2l4LmMgICAgICAgICAgICAgICAgICAgICAgICAgICB8ICAgNCArLQogaHcv cGNpL3BjaV9ob3N0LmMgICAgICAgICAgICAgICAgICAgICAgIHwgICA4ICstCiBody9wY2kvcGNp ZV9ob3N0LmMgICAgICAgICAgICAgICAgICAgICAgfCAgIDIgKy0KIGh3L3BjaS9zaHBjLmMgICAg ICAgICAgICAgICAgICAgICAgICAgICB8ICAgMiArLQogaHcvcGNtY2lhL3B4YTJ4eC5jICAgICAg ICAgICAgICAgICAgICAgIHwgICA2ICstCiBody9wcGMvZTUwMC5jICAgICAgICAgICAgICAgICAg ICAgICAgICAgfCAgIDQgKy0KIGh3L3BwYy9tcGM4NTQ0X2d1dHMuYyAgICAgICAgICAgICAgICAg ICB8ICAgMiArLQogaHcvcHBjL3Budl9jb3JlLmMgICAgICAgICAgICAgICAgICAgICAgIHwgICA2 ICstCiBody9wcGMvcG52X2xwYy5jICAgICAgICAgICAgICAgICAgICAgICAgfCAgIDggKy0KIGh3 L3BwYy9wbnZfb2NjLmMgICAgICAgICAgICAgICAgICAgICAgICB8ICAgNCArLQogaHcvcHBjL3Bu dl9wc2kuYyAgICAgICAgICAgICAgICAgICAgICAgIHwgICA4ICstCiBody9wcGMvcG52X3hzY29t LmMgICAgICAgICAgICAgICAgICAgICAgfCAgIDIgKy0KIGh3L3BwYy9wcGM0MDVfYm9hcmRzLmMg ICAgICAgICAgICAgICAgICB8ICAgNCArLQogaHcvcHBjL3BwYzQwNV91Yy5jICAgICAgICAgICAg ICAgICAgICAgIHwgIDE0ICstLQogaHcvcHBjL3BwYzQ0MF9iYW1ib28uYyAgICAgICAgICAgICAg ICAgIHwgICA0ICstCiBody9wcGMvcHBjNDQwX3BjaXguYyAgICAgICAgICAgICAgICAgICAgfCAg IDQgKy0KIGh3L3BwYy9wcGM0eHhfcGNpLmMgICAgICAgICAgICAgICAgICAgICB8ICAgMiArLQog aHcvcHBjL3BwY2U1MDBfc3Bpbi5jICAgICAgICAgICAgICAgICAgIHwgICAyICstCiBody9wcGMv c2FtNDYwZXguYyAgICAgICAgICAgICAgICAgICAgICAgfCAgIDQgKy0KIGh3L3BwYy9zcGFwcl9w Y2kuYyAgICAgICAgICAgICAgICAgICAgICB8ICAgMiArLQogaHcvcHBjL3ZpcnRleF9tbDUwNy5j ICAgICAgICAgICAgICAgICAgIHwgICAyICstCiBody9yZG1hL3Ztdy9wdnJkbWFfbWFpbi5jICAg ICAgICAgICAgICAgfCAgIDQgKy0KIGh3L3Jpc2N2L3NpZml2ZV9jbGludC5jICAgICAgICAgICAg ICAgICB8ICAgMiArLQogaHcvcmlzY3Yvc2lmaXZlX2dwaW8uYyAgICAgICAgICAgICAgICAgIHwg ICAyICstCiBody9yaXNjdi9zaWZpdmVfcGxpYy5jICAgICAgICAgICAgICAgICAgfCAgIDIgKy0K IGh3L3Jpc2N2L3NpZml2ZV9wcmNpLmMgICAgICAgICAgICAgICAgICB8ICAgMiArLQogaHcvcmlz Y3Yvc2lmaXZlX3Rlc3QuYyAgICAgICAgICAgICAgICAgIHwgICAyICstCiBody9yaXNjdi9zaWZp dmVfdWFydC5jICAgICAgICAgICAgICAgICAgfCAgIDIgKy0KIGh3L3Jpc2N2L3ZpcnQuYyAgICAg ICAgICAgICAgICAgICAgICAgICB8ICAgMiArLQogaHcvczM5MHgvczM5MC1wY2ktYnVzLmMgICAg ICAgICAgICAgICAgIHwgICAyICstCiBody9zMzkweC9zMzkwLXBjaS1pbnN0LmMgICAgICAgICAg ICAgICAgfCAgMTEgKy0KIGh3L3Njc2kvTWFrZWZpbGUub2JqcyAgICAgICAgICAgICAgICAgICB8 ICAgMiArLQogaHcvc2NzaS9lc3AtcGNpLmMgICAgICAgICAgICAgICAgICAgICAgIHwgICAyICst CiBody9zY3NpL2VzcC5jICAgICAgICAgICAgICAgICAgICAgICAgICAgfCAgIDIgKy0KIGh3L3Nj c2kvbHNpNTNjODk1YS5jICAgICAgICAgICAgICAgICAgICB8ICAgNiArLQogaHcvc2NzaS9tZWdh c2FzLmMgICAgICAgICAgICAgICAgICAgICAgIHwgICA2ICstCiBody9zY3NpL21wdHNhcy5jICAg ICAgICAgICAgICAgICAgICAgICAgfCAgIDYgKy0KIGh3L3Njc2kvdm13X3B2c2NzaS5jICAgICAg ICAgICAgICAgICAgICB8ICAgMiArLQogaHcvc2QvYmNtMjgzNV9zZGhvc3QuYyAgICAgICAgICAg ICAgICAgIHwgICAyICstCiBody9zZC9taWxreW1pc3QtbWVtY2FyZC5jICAgICAgICAgICAgICAg fCAgIDIgKy0KIGh3L3NkL29tYXBfbW1jLmMgICAgICAgICAgICAgICAgICAgICAgICB8ICAgMiAr LQogaHcvc2QvcGwxODEuYyAgICAgICAgICAgICAgICAgICAgICAgICAgIHwgICAyICstCiBody9z ZC9weGEyeHhfbW1jaS5jICAgICAgICAgICAgICAgICAgICAgfCAgIDIgKy0KIGh3L3NkL3NkaGNp LmMgICAgICAgICAgICAgICAgICAgICAgICAgICB8ICAgNCArLQogaHcvc2g0L3IyZC5jICAgICAg ICAgICAgICAgICAgICAgICAgICAgIHwgICAyICstCiBody9zaDQvc2g3NzUwLmMgICAgICAgICAg ICAgICAgICAgICAgICAgfCAgIDQgKy0KIGh3L3NoNC9zaF9wY2kuYyAgICAgICAgICAgICAgICAg ICAgICAgICB8ICAgMiArLQogaHcvc3BhcmMvc3VuNG1faW9tbXUuYyAgICAgICAgICAgICAgICAg IHwgICAyICstCiBody9zcGFyYzY0L25pYWdhcmEuYyAgICAgICAgICAgICAgICAgICAgfCAgIDIg Ky0KIGh3L3NwYXJjNjQvc3VuNHUuYyAgICAgICAgICAgICAgICAgICAgICB8ICAgNCArLQogaHcv c3BhcmM2NC9zdW40dV9pb21tdS5jICAgICAgICAgICAgICAgIHwgICAyICstCiBody9zc2kvTWFr ZWZpbGUub2JqcyAgICAgICAgICAgICAgICAgICAgfCAgIDIgKy0KIGh3L3NzaS9hc3BlZWRfc21j LmMgICAgICAgICAgICAgICAgICAgICB8ICAgNiArLQogaHcvc3NpL2lteF9zcGkuYyAgICAgICAg ICAgICAgICAgICAgICAgIHwgICAyICstCiBody9zc2kvbXNzLXNwaS5jICAgICAgICAgICAgICAg ICAgICAgICAgfCAgIDIgKy0KIGh3L3NzaS9vbWFwX3NwaS5jICAgICAgICAgICAgICAgICAgICAg ICB8ICAgMiArLQogaHcvc3NpL3BsMDIyLmMgICAgICAgICAgICAgICAgICAgICAgICAgIHwgICAy ICstCiBody9zc2kvc3RtMzJmMnh4X3NwaS5jICAgICAgICAgICAgICAgICAgfCAgIDIgKy0KIGh3 L3NzaS94aWxpbnhfc3BpLmMgICAgICAgICAgICAgICAgICAgICB8ICAgMiArLQogaHcvc3NpL3hp bGlueF9zcGlwcy5jICAgICAgICAgICAgICAgICAgIHwgICA4ICstCiBody90aW1lci9NYWtlZmls ZS5vYmpzICAgICAgICAgICAgICAgICAgfCAgIDYgKy0KIGh3L3RpbWVyL2E5Z3RpbWVyLmMgICAg ICAgICAgICAgICAgICAgICB8ICAgNCArLQogaHcvdGltZXIvYWxsd2lubmVyLWExMC1waXQuYyAg ICAgICAgICAgIHwgICAyICstCiBody90aW1lci9hbHRlcmFfdGltZXIuYyAgICAgICAgICAgICAg ICAgfCAgIDIgKy0KIGh3L3RpbWVyL2FybV9tcHRpbWVyLmMgICAgICAgICAgICAgICAgICB8ICAg NCArLQogaHcvdGltZXIvYXJtX3RpbWVyLmMgICAgICAgICAgICAgICAgICAgIHwgICA0ICstCiBo dy90aW1lci9hcm12N21fc3lzdGljay5jICAgICAgICAgICAgICAgfCAgIDIgKy0KIGh3L3RpbWVy L2FzcGVlZF9ydGMuYyAgICAgICAgICAgICAgICAgICB8ICAgMiArLQogaHcvdGltZXIvYXNwZWVk X3RpbWVyLmMgICAgICAgICAgICAgICAgIHwgICAyICstCiBody90aW1lci9jYWRlbmNlX3R0Yy5j ICAgICAgICAgICAgICAgICAgfCAgIDIgKy0KIGh3L3RpbWVyL2Ntc2RrLWFwYi1kdWFsdGltZXIu YyAgICAgICAgICB8ICAgMiArLQogaHcvdGltZXIvY21zZGstYXBiLXRpbWVyLmMgICAgICAgICAg ICAgIHwgICAyICstCiBody90aW1lci9kaWdpYy10aW1lci5jICAgICAgICAgICAgICAgICAgfCAg IDIgKy0KIGh3L3RpbWVyL2V0cmF4ZnNfdGltZXIuYyAgICAgICAgICAgICAgICB8ICAgMiArLQog aHcvdGltZXIvZXh5bm9zNDIxMF9tY3QuYyAgICAgICAgICAgICAgIHwgICAyICstCiBody90aW1l ci9leHlub3M0MjEwX3B3bS5jICAgICAgICAgICAgICAgfCAgIDIgKy0KIGh3L3RpbWVyL2V4eW5v czQyMTBfcnRjLmMgICAgICAgICAgICAgICB8ICAgMiArLQogaHcvdGltZXIvZ3JsaWJfZ3B0aW1l ci5jICAgICAgICAgICAgICAgIHwgICAyICstCiBody90aW1lci9ocGV0LmMgICAgICAgICAgICAg ICAgICAgICAgICAgfCAgIDIgKy0KIGh3L3RpbWVyL2k4MjU0LmMgICAgICAgICAgICAgICAgICAg ICAgICB8ICAgMiArLQogaHcvdGltZXIvaW14X2VwaXQuYyAgICAgICAgICAgICAgICAgICAgIHwg ICAyICstCiBody90aW1lci9pbXhfZ3B0LmMgICAgICAgICAgICAgICAgICAgICAgfCAgIDIgKy0K IGh3L3RpbWVyL2xtMzJfdGltZXIuYyAgICAgICAgICAgICAgICAgICB8ICAgMiArLQogaHcvdGlt ZXIvbTQ4dDU5LmMgICAgICAgICAgICAgICAgICAgICAgIHwgICA0ICstCiBody90aW1lci9tYzE0 NjgxOHJ0Yy5jICAgICAgICAgICAgICAgICAgfCAgIDIgKy0KIGh3L3RpbWVyL21pbGt5bWlzdC1z eXNjdGwuYyAgICAgICAgICAgICB8ICAgMiArLQogaHcvdGltZXIvbXNzLXRpbWVyLmMgICAgICAg ICAgICAgICAgICAgIHwgICAyICstCiBody90aW1lci9ucmY1MV90aW1lci5jICAgICAgICAgICAg ICAgICAgfCAgIDIgKy0KIGh3L3RpbWVyL29tYXBfZ3B0aW1lci5jICAgICAgICAgICAgICAgICB8 ICAgMiArLQogaHcvdGltZXIvb21hcF9zeW5jdGltZXIuYyAgICAgICAgICAgICAgIHwgICAyICst CiBody90aW1lci9wbDAzMS5jICAgICAgICAgICAgICAgICAgICAgICAgfCAgIDIgKy0KIGh3L3Rp bWVyL3B1djNfb3N0LmMgICAgICAgICAgICAgICAgICAgICB8ICAgMiArLQogaHcvdGltZXIvcHhh Mnh4X3RpbWVyLmMgICAgICAgICAgICAgICAgIHwgICAyICstCiBody90aW1lci9zaF90aW1lci5j ICAgICAgICAgICAgICAgICAgICAgfCAgIDIgKy0KIGh3L3RpbWVyL3NsYXZpb190aW1lci5jICAg ICAgICAgICAgICAgICB8ICAgMiArLQogaHcvdGltZXIvc3RtMzJmMnh4X3RpbWVyLmMgICAgICAg ICAgICAgIHwgICAyICstCiBody90aW1lci9zdW40di1ydGMuYyAgICAgICAgICAgICAgICAgICAg fCAgIDIgKy0KIGh3L3RpbWVyL3hpbGlueF90aW1lci5jICAgICAgICAgICAgICAgICB8ICAgMiAr LQogaHcvdGltZXIveGxueC16eW5xbXAtcnRjLmMgICAgICAgICAgICAgIHwgICAyICstCiBody90 cG0vdHBtX2NyYi5jICAgICAgICAgICAgICAgICAgICAgICAgfCAgIDIgKy0KIGh3L3RwbS90cG1f dGlzLmMgICAgICAgICAgICAgICAgICAgICAgICB8ICAgMiArLQogaHcvdXNiL2NoaXBpZGVhLmMg ICAgICAgICAgICAgICAgICAgICAgIHwgICA0ICstCiBody91c2IvaGNkLWVoY2ktc3lzYnVzLmMg ICAgICAgICAgICAgICAgfCAgIDIgKy0KIGh3L3VzYi9oY2QtZWhjaS5jICAgICAgICAgICAgICAg ICAgICAgICB8ICAgNiArLQogaHcvdXNiL2hjZC1vaGNpLmMgICAgICAgICAgICAgICAgICAgICAg IHwgICAyICstCiBody91c2IvaGNkLXVoY2kuYyAgICAgICAgICAgICAgICAgICAgICAgfCAgIDIg Ky0KIGh3L3VzYi9oY2QteGhjaS5jICAgICAgICAgICAgICAgICAgICAgICB8ICAxMCArLQogaHcv dXNiL3R1c2I2MDEwLmMgICAgICAgICAgICAgICAgICAgICAgIHwgICAyICstCiBody92ZmlvL2Nv bW1vbi5jICAgICAgICAgICAgICAgICAgICAgICAgfCAgIDIgKy0KIGh3L3ZmaW8vcGNpLXF1aXJr cy5jICAgICAgICAgICAgICAgICAgICB8ICAzMyArKystLS0KIGh3L3ZmaW8vcGNpLmMgICAgICAg ICAgICAgICAgICAgICAgICAgICB8ICAgNCArLQogaHcvdmlydGlvL01ha2VmaWxlLm9ianMgICAg ICAgICAgICAgICAgIHwgICAyICstCiBody92aXJ0aW8vdmlydGlvLW1taW8uYyAgICAgICAgICAg ICAgICAgfCAgIDIgKy0KIGh3L3ZpcnRpby92aXJ0aW8tcGNpLmMgICAgICAgICAgICAgICAgICB8 ICAyNyArKystLQogaHcvd2F0Y2hkb2cvY21zZGstYXBiLXdhdGNoZG9nLmMgICAgICAgIHwgICAy ICstCiBody93YXRjaGRvZy93ZHRfYXNwZWVkLmMgICAgICAgICAgICAgICAgfCAgIDIgKy0KIGh3 L3dhdGNoZG9nL3dkdF9pNjMwMGVzYi5jICAgICAgICAgICAgICB8ICAgMiArLQogaHcveGVuL3hl bl9wdC5jICAgICAgICAgICAgICAgICAgICAgICAgIHwgICAyICstCiBody94ZW4veGVuX3B0X21z aS5jICAgICAgICAgICAgICAgICAgICAgfCAgIDIgKy0KIGh3L3h0ZW5zYS9teF9waWMuYyAgICAg ICAgICAgICAgICAgICAgICB8ICAgMiArLQogaHcveHRlbnNhL3h0ZnBnYS5jICAgICAgICAgICAg ICAgICAgICAgIHwgICA2ICstCiBpbmNsdWRlL2V4ZWMvY3B1LWFsbC5oICAgICAgICAgICAgICAg ICAgfCAgMTAgKy0KIGluY2x1ZGUvZXhlYy9jcHUtY29tbW9uLmggICAgICAgICAgICAgICB8ICAx MiAtLQogaW5jbHVkZS9leGVjL21lbWF0dHJzLmggICAgICAgICAgICAgICAgIHwgICAyICsKIGlu Y2x1ZGUvZXhlYy9tZW1vcC5oICAgICAgICAgICAgICAgICAgICB8IDEzNCArKysrKysrKysrKysr KysrKysrKysrCiBpbmNsdWRlL2V4ZWMvbWVtb3J5LmggICAgICAgICAgICAgICAgICAgfCAgMTEg Ky0KIGluY2x1ZGUvZXhlYy9wb2lzb24uaCAgICAgICAgICAgICAgICAgICB8ICAgMSArCiBpbmNs dWRlL2h3L2NoYXIvc2VyaWFsLmggICAgICAgICAgICAgICAgfCAgIDIgKy0KIGluY2x1ZGUvcW9t L2NwdS5oICAgICAgICAgICAgICAgICAgICAgICB8ICAgMiArLQogaW9wb3J0LmMgICAgICAgICAg ICAgICAgICAgICAgICAgICAgICAgIHwgICA0ICstCiBtZW1vcnkuYyAgICAgICAgICAgICAgICAg ICAgICAgICAgICAgICAgfCAgNTUgKysrKy0tLS0tCiBtZW1vcnlfbGRzdC5pbmMuYyAgICAgICAg ICAgICAgICAgICAgICAgfCAxNTMgKysrKysrKystLS0tLS0tLS0tLS0tLS0tLQogdGFyZ2V0L2Fs cGhhL2NwdS5oICAgICAgICAgICAgICAgICAgICAgIHwgICAyIC0KIHRhcmdldC9hbHBoYS90cmFu c2xhdGUuYyAgICAgICAgICAgICAgICB8ICAgMiArLQogdGFyZ2V0L2FybS90cmFuc2xhdGUtYTY0 LmMgICAgICAgICAgICAgIHwgIDQ4ICsrKystLS0tCiB0YXJnZXQvYXJtL3RyYW5zbGF0ZS1hNjQu aCAgICAgICAgICAgICAgfCAgIDIgKy0KIHRhcmdldC9hcm0vdHJhbnNsYXRlLXN2ZS5jICAgICAg ICAgICAgICB8ICAgMiArLQogdGFyZ2V0L2FybS90cmFuc2xhdGUuYyAgICAgICAgICAgICAgICAg IHwgIDMyICsrKy0tLQogdGFyZ2V0L2FybS90cmFuc2xhdGUuaCAgICAgICAgICAgICAgICAgIHwg ICAyICstCiB0YXJnZXQvaHBwYS9jcHUuaCAgICAgICAgICAgICAgICAgICAgICAgfCAgIDEgLQog dGFyZ2V0L2hwcGEvdHJhbnNsYXRlLmMgICAgICAgICAgICAgICAgIHwgIDE0ICstLQogdGFyZ2V0 L2kzODYvdHJhbnNsYXRlLmMgICAgICAgICAgICAgICAgIHwgMTMyICsrKysrKysrKystLS0tLS0t LS0tLQogdGFyZ2V0L202OGsvdHJhbnNsYXRlLmMgICAgICAgICAgICAgICAgIHwgICAyICstCiB0 YXJnZXQvbWljcm9ibGF6ZS90cmFuc2xhdGUuYyAgICAgICAgICAgfCAgIDQgKy0KIHRhcmdldC9t aXBzL2NwdS5oICAgICAgICAgICAgICAgICAgICAgICB8ICAgMiAtCiB0YXJnZXQvbWlwcy9vcF9o ZWxwZXIuYyAgICAgICAgICAgICAgICAgfCAgIDUgKy0KIHRhcmdldC9taXBzL3RyYW5zbGF0ZS5j ICAgICAgICAgICAgICAgICB8ICAgOCArLQogdGFyZ2V0L29wZW5yaXNjL3RyYW5zbGF0ZS5jICAg ICAgICAgICAgIHwgICA0ICstCiB0YXJnZXQvcHBjL3RyYW5zbGF0ZS5jICAgICAgICAgICAgICAg ICAgfCAgMTIgKy0KIHRhcmdldC9yaXNjdi9pbnNuX3RyYW5zL3RyYW5zX3J2YS5pbmMuYyB8ICAg OCArLQogdGFyZ2V0L3Jpc2N2L2luc25fdHJhbnMvdHJhbnNfcnZpLmluYy5jIHwgICA0ICstCiB0 YXJnZXQvczM5MHgvdHJhbnNsYXRlLmMgICAgICAgICAgICAgICAgfCAgIDYgKy0KIHRhcmdldC9z MzkweC90cmFuc2xhdGVfdnguaW5jLmMgICAgICAgICB8ICAxMCArLQogdGFyZ2V0L3NoNC9jcHUu aCAgICAgICAgICAgICAgICAgICAgICAgIHwgICAyIC0KIHRhcmdldC9zcGFyYy9jcHUuaCAgICAg ICAgICAgICAgICAgICAgICB8ICAgNCArLQogdGFyZ2V0L3NwYXJjL21tdV9oZWxwZXIuYyAgICAg ICAgICAgICAgIHwgIDQwICsrKystLS0KIHRhcmdldC9zcGFyYy90cmFuc2xhdGUuYyAgICAgICAg ICAgICAgICB8ICAxNCArLS0KIHRhcmdldC90aWxlZ3gvdHJhbnNsYXRlLmMgICAgICAgICAgICAg ICB8ICAxMCArLQogdGFyZ2V0L3RyaWNvcmUvdHJhbnNsYXRlLmMgICAgICAgICAgICAgIHwgICA4 ICstCiB0YXJnZXQveHRlbnNhL2NwdS5oICAgICAgICAgICAgICAgICAgICAgfCAgIDIgLQogdGNn L1JFQURNRSAgICAgICAgICAgICAgICAgICAgICAgICAgICAgIHwgICAyICstCiB0Y2cvYWFyY2g2 NC90Y2ctdGFyZ2V0LmluYy5jICAgICAgICAgICAgfCAgMjYgKystLS0KIHRjZy9hcm0vdGNnLXRh cmdldC5pbmMuYyAgICAgICAgICAgICAgICB8ICAyNiArKy0tLQogdGNnL2kzODYvdGNnLXRhcmdl dC5pbmMuYyAgICAgICAgICAgICAgIHwgIDI0ICsrLS0KIHRjZy9taXBzL3RjZy10YXJnZXQuaW5j LmMgICAgICAgICAgICAgICB8ICAxNiArLS0KIHRjZy9vcHRpbWl6ZS5jICAgICAgICAgICAgICAg ICAgICAgICAgICB8ICAgMiArLQogdGNnL3BwYy90Y2ctdGFyZ2V0LmluYy5jICAgICAgICAgICAg ICAgIHwgIDEyICstCiB0Y2cvcmlzY3YvdGNnLXRhcmdldC5pbmMuYyAgICAgICAgICAgICAgfCAg MjAgKystLQogdGNnL3MzOTAvdGNnLXRhcmdldC5pbmMuYyAgICAgICAgICAgICAgIHwgIDE0ICst LQogdGNnL3NwYXJjL3RjZy10YXJnZXQuaW5jLmMgICAgICAgICAgICAgIHwgICA2ICstCiB0Y2cv dGNnLW9wLmMgICAgICAgICAgICAgICAgICAgICAgICAgICAgfCAgMzggKysrLS0tCiB0Y2cvdGNn LW9wLmggICAgICAgICAgICAgICAgICAgICAgICAgICAgfCAgODYgKysrKysrKy0tLS0tLS0KIHRj Zy90Y2cuYyAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICB8ICAgNCArLQogdGNnL3RjZy5o ICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgIHwgIDk5ICstLS0tLS0tLS0tLS0tLS0KIHRy YWNlL21lbS1pbnRlcm5hbC5oICAgICAgICAgICAgICAgICAgICB8ICAgNCArLQogdHJhY2UvbWVt LmggICAgICAgICAgICAgICAgICAgICAgICAgICAgIHwgICA0ICstCiA0OTcgZmlsZXMgY2hhbmdl ZCwgMTQzNiBpbnNlcnRpb25zKCspLCAxNDczIGRlbGV0aW9ucygtKQogY3JlYXRlIG1vZGUgMTAw NjQ0IGluY2x1ZGUvZXhlYy9tZW1vcC5oCgotLSAKMS44LjMuMQoKX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX18KWGVuLWRldmVsIG1haWxpbmcgbGlzdApYZW4t ZGV2ZWxAbGlzdHMueGVucHJvamVjdC5vcmcKaHR0cHM6Ly9saXN0cy54ZW5wcm9qZWN0Lm9yZy9t YWlsbWFuL2xpc3RpbmZvL3hlbi1kZXZlbA== From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1hyVjt-0000ZL-9H for mharc-qemu-riscv@gnu.org; Fri, 16 Aug 2019 02:29:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:57736) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1hyVjk-0000To-8C for qemu-riscv@nongnu.org; Fri, 16 Aug 2019 02:29:23 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hyVjh-0002Y9-2K for qemu-riscv@nongnu.org; Fri, 16 Aug 2019 02:29:20 -0400 Received: from smtpe1.intersmtp.com ([213.121.35.74]:5202) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hyVjG-0002HU-S8; Fri, 16 Aug 2019 02:28:51 -0400 Received: from tpw09926dag18g.domain1.systemhost.net (10.9.212.34) by BWP09926079.bt.com (10.36.82.110) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.1713.5; Fri, 16 Aug 2019 07:28:25 +0100 Received: from tpw09926dag18e.domain1.systemhost.net (10.9.212.18) by tpw09926dag18g.domain1.systemhost.net (10.9.212.34) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Fri, 16 Aug 2019 07:28:47 +0100 Received: from tpw09926dag18e.domain1.systemhost.net ([fe80::a946:6348:ccf4:fa6c]) by tpw09926dag18e.domain1.systemhost.net ([fe80::a946:6348:ccf4:fa6c%12]) with mapi id 15.00.1395.000; Fri, 16 Aug 2019 07:28:47 +0100 From: To: CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Thread-Topic: [Qemu-devel] [PATCH v7 00/42] Invert Endian bit in SPARCv9 MMU TTE Thread-Index: AQHVU/vc8DdfhK3ulkmWv148s0Uozg== Date: Fri, 16 Aug 2019 06:28:47 +0000 Message-ID: <43bc5e07ac614d0e8e740bf6007ff77b@tpw09926dag18e.domain1.systemhost.net> Accept-Language: en-AU, en-GB, en-US Content-Language: en-AU X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-exchange-messagesentrepresentingtype: 1 x-ms-exchange-transport-fromentityheader: Hosted x-originating-ip: [10.187.101.40] Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Windows 7 or 8 [fuzzy] X-Received-From: 213.121.35.74 Subject: [Qemu-riscv] [Qemu-devel] [PATCH v7 00/42] Invert Endian bit in SPARCv9 MMU TTE X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 16 Aug 2019 06:29:23 -0000 This patchset implements the IE (Invert Endian) bit in SPARCv9 MMU TTE.=0A= =0A= It is an attempt of the instructions outlined by Richard Henderson to Mark= =0A= Cave-Ayland.=0A= =0A= Tested with OpenBSD on sun4u. Solaris 10 is my actual goal, but unfortunate= ly a=0A= separate keyboard issue remains in the way.=0A= =0A= On 01/11/17 19:15, Mark Cave-Ayland wrote:=0A= =0A= >On 15/08/17 19:10, Richard Henderson wrote:=0A= >=0A= >> [CC Peter re MemTxAttrs below]=0A= >>=0A= >> On 08/15/2017 09:38 AM, Mark Cave-Ayland wrote:=0A= >>> Working through an incorrect endian issue on qemu-system-sparc64, it ha= s=0A= >>> become apparent that at least one OS makes use of the IE (Invert Endian= )=0A= >>> bit in the SPARCv9 MMU TTE to map PCI memory space without the=0A= >>> programmer having to manually endian-swap accesses.=0A= >>>=0A= >>> In other words, to quote the UltraSPARC specification: "if this bit is= =0A= >>> set, accesses to the associated page are processed with inverse=0A= >>> endianness from what is specified by the instruction (big-for-little an= d=0A= >>> little-for-big)".=0A= =0A= A good explanation by Mark why the IE bit is required.=0A= =0A= >>>=0A= >>> Looking through various bits of code, I'm trying to get a feel for the= =0A= >>> best way to implement this in an efficient manner. From what I can see= =0A= >>> this could be solved using an additional MMU index, however I'm not=0A= >>> overly familiar with the memory and softmmu subsystems.=0A= >>=0A= >> No, it can't be solved with an MMU index.=0A= >>=0A= >>> Can anyone point me in the right direction as to what would be the best= =0A= >>> way to implement this feature within QEMU?=0A= >>=0A= >> It's definitely tricky.=0A= >>=0A= >> We definitely need some TLB_FLAGS_MASK bit set so that we're forced thro= ugh=0A= >> the=0A= >> memory slow path. There is no other way to bypass the endianness that w= e've=0A= >> already encoded from the target instruction.=0A= >>=0A= >> Given the tlb_set_page_with_attrs interface, I would think that we need = a new=0A= >> bit in MemTxAttrs, so that the target/sparc tlb_fill (and subroutines) c= an=0A= >> pass=0A= >> along the TTE bit for the given page.=0A= >>=0A= >> We have an existing problem in softmmu_template.h,=0A= >>=0A= >> /* ??? Note that the io helpers always read data in the target=0A= >> byte ordering. We should push the LE/BE request down into io. *= /=0A= >> res =3D glue(io_read, SUFFIX)(env, mmu_idx, index, addr, retaddr);= =0A= >> res =3D TGT_BE(res);=0A= >>=0A= >> We do not want to add a third(!) byte swap along the i/o path. We need = to=0A= >> collapse the two that we have already before considering this one.=0A= >>=0A= >> This probably takes the form of:=0A= >>=0A= >> (1) Replacing the "int size" argument with "TCGMemOp memop" for=0A= >> a) io_{read,write}x in accel/tcg/cputlb.c,=0A= >> b) memory_region_dispatch_{read,write} in memory.c,=0A= >> c) adjust_endianness in memory.c.=0A= >> This carries size+sign+endianness down to the next level.=0A= >>=0A= >> (2) In memory.c, adjust_endianness,=0A= >>=0A= >> if (memory_region_wrong_endianness(mr)) {=0A= >> - switch (size) {=0A= >> + memop ^=3D MO_BSWAP;=0A= >> + }=0A= >> + if (memop & MO_BSWAP) {=0A= >>=0A= >> For extra credit, re-arrange memory_region_wrong_endianness=0A= >> to something more explicit -- "wrong" isn't helpful.=0A= >=0A= >Finally I've had a bit of spare time to experiment with this approach,=0A= >and from what I can see there are currently 2 issues:=0A= >=0A= >=0A= >1) Using TCGMemOp in memory.c means it is no longer accelerator agnostic= =0A= >=0A= >For the moment I've defined a separate MemOp in memory.h and provided a=0A= >mapping function in io_{read,write}x to map from TCGMemOp to MemOp and=0A= >then pass that into memory_region_dispatch_{read,write}.=0A= >=0A= >Other than not referencing TCGMemOp in the memory API, another reason=0A= >for doing this was that I wasn't convinced that all the MO_ attributes=0A= >were valid outside of TCG. I do, of course, strongly defer to other=0A= >people's knowledge in this area though.=0A= >=0A= >=0A= >2) The above changes to adjust_endianness() fail when=0A= >memory_region_dispatch_{read,write} are called recursively=0A= >=0A= >Whilst booting qemu-system-sparc64 I see that=0A= >memory_region_dispatch_{read,write} get called recursively - once via=0A= >io_{read,write}x and then again via flatview_read_continue() in exec.c.=0A= >=0A= >The net effect of this is that we perform the bswap correctly at the=0A= >tail of the recursion, but then as we travel back up the stack we hit=0A= >memory_region_dispatch_{read,write} once again causing a second bswap=0A= >which means the value is returned with the incorrect endian again.=0A= >=0A= >=0A= >My understanding from your softmmu_template.h comment above is that the=0A= >memory API should do the endian swapping internally allowing the removal= =0A= >of the final TGT_BE/TGT_LE applied to the result, or did I get this wrong?= =0A= >=0A= >> (3) In tlb_set_page_with_attrs, notice attrs.byte_swap and set=0A= >> a new TLB_FORCE_SLOW bit within TLB_FLAGS_MASK.=0A= >>=0A= >> (4) In io_{read,write}x, if iotlbentry->attrs.byte_swap is set,=0A= >> then memop ^=3D MO_BSWAP.=0A= =0A= Thanks all for the feedback. Learnt a lot =3D)=0A= =0A= v2:=0A= - Moved size+sign+endianness attributes from TCGMemOp into MemOp.=0A= In v1 TCGMemOp was re-purposed entirely into MemOp.=0A= - Replaced MemOp MO_{8|16|32|64} with TCGMemOp MO_{UB|UW|UL|UQ} alias.=0A= This is to avoid warnings on comparing and coercing different enums.=0A= - Renamed get_memop to get_tcgmemop for clarity.=0A= - MEMOP is now SIZE_MEMOP, which is just ctzl(size).=0A= - Split patch 3/4 so one memory_region_dispatch_{read|write} interface=0A= is converted per patch.=0A= - Do not reuse TLB_RECHECK, use new TLB_FORCE_SLOW instead.=0A= - Split patch 4/4 so adding the MemTxAddrs parameters and converting=0A= tlb_set_page() to tlb_set_page_with_attrs() is separate from usage.=0A= - CC'd maintainers.=0A= =0A= v3:=0A= - Like v1, the entire TCGMemOp enum is now MemOp.=0A= - MemOp target dependant attributes are conditional upon NEED_CPU_H=0A= =0A= v4:=0A= - Added Paolo Bonzini as include/exec/memop.h maintainer=0A= =0A= v5:=0A= - Improved commit messages to clarify how interface to access=0A= MemoryRegion will be converted from "unsigned size" to "MemOp op".=0A= - Moved cpu_transaction_failed() MemOp conversion from patch #11 to #9=0A= to make review easier.=0A= =0A= v6:=0A= - Improved commit messages.=0A= - Include as patch #1 an earlier posted TARGET_ALIGNED_ONLY configure patch= .=0A= - Typeless macro SIZE_MEMOP is now inline.=0A= - size_memop now includes CONFIG_DEBUG_TCG code.=0A= - size_memop now also encodes endianness via MO_TE.=0A= - Reverted size_memop operand "unsigned long" back to "unsigned".=0A= - Second pass of size_memop to replace no-op place holder with MO_{8|16|32|= 64}.=0A= - Delay memory_region_dispatch_{read,write} operand conversion until no-op= =0A= size_memop is implemented so we have proper typing at all points in betwe= en.=0A= - Fixed bug where not all memory_region_dispatch_{read,write} callers where= =0A= encoding endianness into the MemOp operand, see patch #20.=0A= - Fixed bug where not all memory_region_dispatch_{read,write} callers were= =0A= collapsing their byte swap into adjust_endianness, see patch #20 and #22.= =0A= - Split byte swap collapsing patch (v5 #11) into #21 and #22.=0A= - Corrected non-common *-common-obj to *-obj.=0A= - Replaced enum device_endian with MemOp to simplify endianness checks. A= =0A= straight forward sed but touched *alot* of files. See patch #16 and #17.= =0A= - Deleted enum device_endian.=0A= - Deleted DEVICE_HOST_ENDIAN definition.=0A= - Generalized the description of introduced MemTxAttrs attribute byte_swap.= =0A= =0A= v7:=0A= - Fixed bug where size_memop was implicitly encoding MO_TE. Endianness,=0A= {MO_TE|MO_BE|MO_LE}, is now explicitly encoded by MemoryRegion accessors.= =0A= - While a no-op, size_memop return type remains an unsigned.=0A= - Use '=3D 0' short hand instead of macro logic to declare host endianness.= =0A= - With a new set of constant arguments, sanity checked the compiler is stil= l=0A= folding away tests in cputlb.c=0A= - Re-declared many native endian devices as little or big endian. This is w= hy=0A= v7 has +16 patches.=0A= =0A= Tony Nguyen (42):=0A= configure: Define TARGET_ALIGNED_ONLY in configure=0A= tcg: TCGMemOp is now accelerator independent MemOp=0A= memory: Introduce size_memop=0A= target/mips: Access MemoryRegion with MemOp=0A= hw/s390x: Access MemoryRegion with MemOp=0A= hw/intc/armv7m_nic: Access MemoryRegion with MemOp=0A= hw/virtio: Access MemoryRegion with MemOp=0A= hw/vfio: Access MemoryRegion with MemOp=0A= exec: Access MemoryRegion with MemOp=0A= cputlb: Access MemoryRegion with MemOp=0A= memory: Access MemoryRegion with MemOp=0A= hw/s390x: Hard code size with MO_{8|16|32|64}=0A= target/mips: Hard code size with MO_{8|16|32|64}=0A= exec: Hard code size with MO_{8|16|32|64}=0A= hw/audio: Declare device little or big endian=0A= hw/block: Declare device little or big endian=0A= hw/char: Declare device little or big endian=0A= hw/display: Declare device little or big endian=0A= hw/dma: Declare device little or big endian=0A= hw/gpio: Declare device little or big endian=0A= hw/i2c: Declare device little or big endian=0A= hw/input: Declare device little or big endian=0A= hw/intc: Declare device little or big endian=0A= hw/isa: Declare device little or big endian=0A= hw/misc: Declare device little or big endian=0A= hw/net: Declare device little or big endian=0A= hw/pci-host: Declare device little or big endian=0A= hw/sd: Declare device little or big endian=0A= hw/ssi: Declare device little or big endian=0A= hw/timer: Declare device little or big endian=0A= build: Correct non-common common-obj-* to obj-*=0A= exec: Map device_endian onto MemOp=0A= exec: Replace device_endian with MemOp=0A= exec: Delete device_endian=0A= exec: Delete DEVICE_HOST_ENDIAN=0A= memory: Access MemoryRegion with endianness=0A= cputlb: Replace size and endian operands for MemOp=0A= memory: Single byte swap along the I/O path=0A= cpu: TLB_FLAGS_MASK bit to force memory slow path=0A= cputlb: Byte swap memory transaction attribute=0A= target/sparc: Add TLB entry with attributes=0A= target/sparc: sun4u Invert Endian TTE bit=0A= =0A= MAINTAINERS | 1 +=0A= accel/tcg/cputlb.c | 197 ++++++++++++++--------------= ----=0A= configure | 10 +-=0A= exec.c | 15 ++-=0A= hw/acpi/core.c | 6 +-=0A= hw/acpi/cpu.c | 2 +-=0A= hw/acpi/cpu_hotplug.c | 2 +-=0A= hw/acpi/ich9.c | 4 +-=0A= hw/acpi/memory_hotplug.c | 2 +-=0A= hw/acpi/nvdimm.c | 2 +-=0A= hw/acpi/pcihp.c | 2 +-=0A= hw/acpi/piix4.c | 2 +-=0A= hw/acpi/tco.c | 2 +-=0A= hw/adc/stm32f2xx_adc.c | 2 +-=0A= hw/alpha/pci.c | 6 +-=0A= hw/alpha/typhoon.c | 6 +-=0A= hw/arm/allwinner-a10.c | 2 +-=0A= hw/arm/armv7m.c | 2 +-=0A= hw/arm/aspeed.c | 2 +-=0A= hw/arm/aspeed_soc.c | 2 +-=0A= hw/arm/exynos4210.c | 2 +-=0A= hw/arm/highbank.c | 2 +-=0A= hw/arm/integratorcp.c | 6 +-=0A= hw/arm/kzm.c | 2 +-=0A= hw/arm/msf2-soc.c | 2 +-=0A= hw/arm/musicpal.c | 20 ++--=0A= hw/arm/omap1.c | 40 +++----=0A= hw/arm/omap2.c | 10 +-=0A= hw/arm/omap_sx1.c | 2 +-=0A= hw/arm/palm.c | 2 +-=0A= hw/arm/pxa2xx.c | 20 ++--=0A= hw/arm/pxa2xx_gpio.c | 2 +-=0A= hw/arm/pxa2xx_pic.c | 2 +-=0A= hw/arm/smmuv3.c | 2 +-=0A= hw/arm/spitz.c | 2 +-=0A= hw/arm/stellaris.c | 8 +-=0A= hw/arm/strongarm.c | 12 +-=0A= hw/arm/versatilepb.c | 2 +-=0A= hw/audio/Makefile.objs | 3 +-=0A= hw/audio/ac97.c | 4 +-=0A= hw/audio/cs4231.c | 2 +-=0A= hw/audio/es1370.c | 2 +-=0A= hw/audio/intel-hda.c | 2 +-=0A= hw/audio/marvell_88w8618.c | 2 +-=0A= hw/audio/milkymist-ac97.c | 2 +-=0A= hw/audio/pl041.c | 2 +-=0A= hw/block/Makefile.objs | 6 +-=0A= hw/block/fdc.c | 4 +-=0A= hw/block/nvme.c | 4 +-=0A= hw/block/onenand.c | 2 +-=0A= hw/block/pflash_cfi01.c | 2 +-=0A= hw/block/pflash_cfi02.c | 2 +-=0A= hw/char/Makefile.objs | 4 +-=0A= hw/char/bcm2835_aux.c | 2 +-=0A= hw/char/cadence_uart.c | 2 +-=0A= hw/char/cmsdk-apb-uart.c | 2 +-=0A= hw/char/debugcon.c | 2 +-=0A= hw/char/digic-uart.c | 2 +-=0A= hw/char/escc.c | 2 +-=0A= hw/char/etraxfs_ser.c | 2 +-=0A= hw/char/exynos4210_uart.c | 2 +-=0A= hw/char/grlib_apbuart.c | 2 +-=0A= hw/char/imx_serial.c | 2 +-=0A= hw/char/lm32_uart.c | 2 +-=0A= hw/char/mcf_uart.c | 2 +-=0A= hw/char/milkymist-uart.c | 2 +-=0A= hw/char/nrf51_uart.c | 2 +-=0A= hw/char/omap_uart.c | 6 +-=0A= hw/char/parallel.c | 2 +-=0A= hw/char/pl011.c | 2 +-=0A= hw/char/serial.c | 26 ++---=0A= hw/char/sh_serial.c | 2 +-=0A= hw/char/stm32f2xx_usart.c | 2 +-=0A= hw/char/xilinx_uartlite.c | 2 +-=0A= hw/core/Makefile.objs | 2 +-=0A= hw/core/empty_slot.c | 2 +-=0A= hw/cris/axis_dev88.c | 4 +-=0A= hw/display/Makefile.objs | 6 +-=0A= hw/display/ati.c | 2 +-=0A= hw/display/bcm2835_fb.c | 2 +-=0A= hw/display/bochs-display.c | 4 +-=0A= hw/display/cg3.c | 2 +-=0A= hw/display/cirrus_vga.c | 10 +-=0A= hw/display/edid-region.c | 2 +-=0A= hw/display/exynos4210_fimd.c | 2 +-=0A= hw/display/g364fb.c | 2 +-=0A= hw/display/jazz_led.c | 2 +-=0A= hw/display/milkymist-tmu2.c | 2 +-=0A= hw/display/milkymist-vgafb.c | 2 +-=0A= hw/display/omap_dss.c | 10 +-=0A= hw/display/omap_lcdc.c | 2 +-=0A= hw/display/pl110.c | 2 +-=0A= hw/display/pxa2xx_lcd.c | 2 +-=0A= hw/display/sm501.c | 10 +-=0A= hw/display/tc6393xb.c | 2 +-=0A= hw/display/tcx.c | 14 +--=0A= hw/display/vga-isa-mm.c | 2 +-=0A= hw/display/vga-pci.c | 6 +-=0A= hw/display/vga.c | 2 +-=0A= hw/display/vmware_vga.c | 2 +-=0A= hw/display/xlnx_dp.c | 8 +-=0A= hw/dma/Makefile.objs | 6 +-=0A= hw/dma/bcm2835_dma.c | 4 +-=0A= hw/dma/etraxfs_dma.c | 2 +-=0A= hw/dma/i8257.c | 4 +-=0A= hw/dma/omap_dma.c | 4 +-=0A= hw/dma/pl080.c | 2 +-=0A= hw/dma/pl330.c | 2 +-=0A= hw/dma/puv3_dma.c | 2 +-=0A= hw/dma/pxa2xx_dma.c | 2 +-=0A= hw/dma/rc4030.c | 4 +-=0A= hw/dma/sparc32_dma.c | 2 +-=0A= hw/dma/xilinx_axidma.c | 2 +-=0A= hw/dma/xlnx-zdma.c | 2 +-=0A= hw/dma/xlnx-zynq-devcfg.c | 2 +-=0A= hw/dma/xlnx_dpdma.c | 2 +-=0A= hw/gpio/Makefile.objs | 2 +-=0A= hw/gpio/bcm2835_gpio.c | 2 +-=0A= hw/gpio/imx_gpio.c | 2 +-=0A= hw/gpio/mpc8xxx.c | 2 +-=0A= hw/gpio/nrf51_gpio.c | 2 +-=0A= hw/gpio/omap_gpio.c | 6 +-=0A= hw/gpio/pl061.c | 2 +-=0A= hw/gpio/puv3_gpio.c | 2 +-=0A= hw/gpio/zaurus.c | 2 +-=0A= hw/hppa/dino.c | 6 +-=0A= hw/hppa/machine.c | 2 +-=0A= hw/hppa/pci.c | 6 +-=0A= hw/hyperv/hyperv_testdev.c | 2 +-=0A= hw/i2c/Makefile.objs | 2 +-=0A= hw/i2c/aspeed_i2c.c | 4 +-=0A= hw/i2c/exynos4210_i2c.c | 2 +-=0A= hw/i2c/imx_i2c.c | 2 +-=0A= hw/i2c/microbit_i2c.c | 2 +-=0A= hw/i2c/mpc_i2c.c | 2 +-=0A= hw/i2c/omap_i2c.c | 2 +-=0A= hw/i2c/pm_smbus.c | 2 +-=0A= hw/i2c/ppc4xx_i2c.c | 2 +-=0A= hw/i2c/versatile_i2c.c | 2 +-=0A= hw/i386/amd_iommu.c | 4 +-=0A= hw/i386/intel_iommu.c | 4 +-=0A= hw/i386/kvm/apic.c | 2 +-=0A= hw/i386/kvmvapic.c | 2 +-=0A= hw/i386/pc.c | 6 +-=0A= hw/i386/vmport.c | 2 +-=0A= hw/i386/xen/xen_apic.c | 2 +-=0A= hw/i386/xen/xen_platform.c | 4 +-=0A= hw/i386/xen/xen_pvdevice.c | 2 +-=0A= hw/ide/ahci-allwinner.c | 2 +-=0A= hw/ide/ahci.c | 4 +-=0A= hw/ide/macio.c | 2 +-=0A= hw/ide/mmio.c | 4 +-=0A= hw/ide/pci.c | 6 +-=0A= hw/ide/sii3112.c | 2 +-=0A= hw/input/Makefile.objs | 2 +-=0A= hw/input/milkymist-softusb.c | 2 +-=0A= hw/input/pckbd.c | 6 +-=0A= hw/input/pl050.c | 2 +-=0A= hw/input/pxa2xx_keypad.c | 2 +-=0A= hw/intc/Makefile.objs | 6 +-=0A= hw/intc/allwinner-a10-pic.c | 2 +-=0A= hw/intc/apic.c | 2 +-=0A= hw/intc/arm_gic.c | 12 +-=0A= hw/intc/arm_gicv2m.c | 2 +-=0A= hw/intc/arm_gicv3.c | 4 +-=0A= hw/intc/arm_gicv3_its_common.c | 2 +-=0A= hw/intc/armv7m_nvic.c | 19 +--=0A= hw/intc/aspeed_vic.c | 2 +-=0A= hw/intc/bcm2835_ic.c | 2 +-=0A= hw/intc/bcm2836_control.c | 2 +-=0A= hw/intc/etraxfs_pic.c | 2 +-=0A= hw/intc/exynos4210_combiner.c | 2 +-=0A= hw/intc/grlib_irqmp.c | 2 +-=0A= hw/intc/heathrow_pic.c | 2 +-=0A= hw/intc/imx_avic.c | 2 +-=0A= hw/intc/imx_gpcv2.c | 2 +-=0A= hw/intc/ioapic.c | 2 +-=0A= hw/intc/mips_gic.c | 2 +-=0A= hw/intc/omap_intc.c | 4 +-=0A= hw/intc/ompic.c | 2 +-=0A= hw/intc/openpic.c | 20 ++--=0A= hw/intc/openpic_kvm.c | 2 +-=0A= hw/intc/pl190.c | 2 +-=0A= hw/intc/pnv_xive.c | 14 +--=0A= hw/intc/puv3_intc.c | 2 +-=0A= hw/intc/sh_intc.c | 2 +-=0A= hw/intc/slavio_intctl.c | 4 +-=0A= hw/intc/xics_pnv.c | 2 +-=0A= hw/intc/xilinx_intc.c | 2 +-=0A= hw/intc/xive.c | 6 +-=0A= hw/intc/xlnx-pmu-iomod-intc.c | 2 +-=0A= hw/intc/xlnx-zynqmp-ipi.c | 2 +-=0A= hw/ipack/Makefile.objs | 2 +-=0A= hw/ipack/tpci200.c | 10 +-=0A= hw/ipmi/isa_ipmi_bt.c | 2 +-=0A= hw/ipmi/isa_ipmi_kcs.c | 2 +-=0A= hw/isa/lpc_ich9.c | 4 +-=0A= hw/isa/pc87312.c | 2 +-=0A= hw/isa/vt82c686.c | 2 +-=0A= hw/m68k/mcf5206.c | 2 +-=0A= hw/m68k/mcf5208.c | 4 +-=0A= hw/m68k/mcf_intc.c | 2 +-=0A= hw/microblaze/petalogix_ml605_mmu.c | 2 +-=0A= hw/mips/boston.c | 6 +-=0A= hw/mips/gt64xxx_pci.c | 2 +-=0A= hw/mips/mips_jazz.c | 8 +-=0A= hw/mips/mips_malta.c | 4 +-=0A= hw/mips/mips_r4k.c | 2 +-=0A= hw/misc/Makefile.objs | 10 +-=0A= hw/misc/a9scu.c | 2 +-=0A= hw/misc/applesmc.c | 6 +-=0A= hw/misc/arm11scu.c | 2 +-=0A= hw/misc/arm_integrator_debug.c | 2 +-=0A= hw/misc/arm_l2x0.c | 2 +-=0A= hw/misc/arm_sysctl.c | 2 +-=0A= hw/misc/armsse-cpuid.c | 2 +-=0A= hw/misc/armsse-mhu.c | 2 +-=0A= hw/misc/aspeed_scu.c | 2 +-=0A= hw/misc/aspeed_sdmc.c | 2 +-=0A= hw/misc/aspeed_xdma.c | 2 +-=0A= hw/misc/bcm2835_mbox.c | 2 +-=0A= hw/misc/bcm2835_property.c | 2 +-=0A= hw/misc/bcm2835_rng.c | 2 +-=0A= hw/misc/debugexit.c | 2 +-=0A= hw/misc/eccmemctl.c | 4 +-=0A= hw/misc/edu.c | 2 +-=0A= hw/misc/exynos4210_clk.c | 2 +-=0A= hw/misc/exynos4210_pmu.c | 2 +-=0A= hw/misc/exynos4210_rng.c | 2 +-=0A= hw/misc/grlib_ahb_apb_pnp.c | 4 +-=0A= hw/misc/imx25_ccm.c | 2 +-=0A= hw/misc/imx2_wdt.c | 2 +-=0A= hw/misc/imx31_ccm.c | 2 +-=0A= hw/misc/imx6_ccm.c | 4 +-=0A= hw/misc/imx6_src.c | 2 +-=0A= hw/misc/imx6ul_ccm.c | 4 +-=0A= hw/misc/imx7_ccm.c | 4 +-=0A= hw/misc/imx7_gpr.c | 2 +-=0A= hw/misc/imx7_snvs.c | 2 +-=0A= hw/misc/iotkit-secctl.c | 4 +-=0A= hw/misc/iotkit-sysctl.c | 2 +-=0A= hw/misc/iotkit-sysinfo.c | 2 +-=0A= hw/misc/ivshmem.c | 2 +-=0A= hw/misc/macio/cuda.c | 2 +-=0A= hw/misc/macio/gpio.c | 2 +-=0A= hw/misc/macio/mac_dbdma.c | 2 +-=0A= hw/misc/macio/macio.c | 2 +-=0A= hw/misc/macio/pmu.c | 2 +-=0A= hw/misc/milkymist-hpdmc.c | 2 +-=0A= hw/misc/milkymist-pfpu.c | 2 +-=0A= hw/misc/mips_cmgcr.c | 2 +-=0A= hw/misc/mips_cpc.c | 2 +-=0A= hw/misc/mips_itu.c | 4 +-=0A= hw/misc/mos6522.c | 2 +-=0A= hw/misc/mps2-fpgaio.c | 2 +-=0A= hw/misc/mps2-scc.c | 2 +-=0A= hw/misc/msf2-sysreg.c | 2 +-=0A= hw/misc/mst_fpga.c | 2 +-=0A= hw/misc/nrf51_rng.c | 2 +-=0A= hw/misc/omap_gpmc.c | 6 +-=0A= hw/misc/omap_l4.c | 2 +-=0A= hw/misc/omap_sdrc.c | 2 +-=0A= hw/misc/omap_tap.c | 2 +-=0A= hw/misc/pc-testdev.c | 10 +-=0A= hw/misc/pci-testdev.c | 4 +-=0A= hw/misc/puv3_pm.c | 2 +-=0A= hw/misc/slavio_misc.c | 16 +--=0A= hw/misc/stm32f2xx_syscfg.c | 2 +-=0A= hw/misc/tz-mpc.c | 4 +-=0A= hw/misc/tz-msc.c | 2 +-=0A= hw/misc/tz-ppc.c | 2 +-=0A= hw/misc/unimp.c | 2 +-=0A= hw/misc/zynq-xadc.c | 2 +-=0A= hw/misc/zynq_slcr.c | 2 +-=0A= hw/moxie/moxiesim.c | 2 +-=0A= hw/net/Makefile.objs | 2 +-=0A= hw/net/allwinner_emac.c | 2 +-=0A= hw/net/cadence_gem.c | 2 +-=0A= hw/net/can/can_kvaser_pci.c | 6 +-=0A= hw/net/can/can_mioe3680_pci.c | 4 +-=0A= hw/net/can/can_pcm3680_pci.c | 4 +-=0A= hw/net/dp8393x.c | 2 +-=0A= hw/net/e1000.c | 4 +-=0A= hw/net/e1000e.c | 4 +-=0A= hw/net/eepro100.c | 2 +-=0A= hw/net/etraxfs_eth.c | 2 +-=0A= hw/net/fsl_etsec/etsec.c | 2 +-=0A= hw/net/ftgmac100.c | 2 +-=0A= hw/net/imx_fec.c | 2 +-=0A= hw/net/lan9118.c | 4 +-=0A= hw/net/lance.c | 2 +-=0A= hw/net/mcf_fec.c | 2 +-=0A= hw/net/milkymist-minimac2.c | 2 +-=0A= hw/net/ne2000.c | 2 +-=0A= hw/net/pcnet-pci.c | 4 +-=0A= hw/net/rocker/rocker.c | 2 +-=0A= hw/net/rtl8139.c | 2 +-=0A= hw/net/smc91c111.c | 2 +-=0A= hw/net/stellaris_enet.c | 2 +-=0A= hw/net/sungem.c | 12 +-=0A= hw/net/sunhme.c | 10 +-=0A= hw/net/vmxnet3.c | 4 +-=0A= hw/net/xgmac.c | 2 +-=0A= hw/net/xilinx_axienet.c | 2 +-=0A= hw/net/xilinx_ethlite.c | 2 +-=0A= hw/nios2/10m50_devboard.c | 2 +-=0A= hw/nvram/ds1225y.c | 2 +-=0A= hw/nvram/fw_cfg.c | 8 +-=0A= hw/nvram/mac_nvram.c | 2 +-=0A= hw/nvram/nrf51_nvm.c | 8 +-=0A= hw/openrisc/openrisc_sim.c | 2 +-=0A= hw/pci-host/Makefile.objs | 2 +-=0A= hw/pci-host/bonito.c | 10 +-=0A= hw/pci-host/designware.c | 6 +-=0A= hw/pci-host/piix.c | 2 +-=0A= hw/pci-host/ppce500.c | 2 +-=0A= hw/pci-host/prep.c | 4 +-=0A= hw/pci-host/q35.c | 4 +-=0A= hw/pci-host/sabre.c | 4 +-=0A= hw/pci-host/uninorth.c | 4 +-=0A= hw/pci-host/versatile.c | 4 +-=0A= hw/pci/msix.c | 4 +-=0A= hw/pci/pci_host.c | 8 +-=0A= hw/pci/pcie_host.c | 2 +-=0A= hw/pci/shpc.c | 2 +-=0A= hw/pcmcia/pxa2xx.c | 6 +-=0A= hw/ppc/e500.c | 4 +-=0A= hw/ppc/mpc8544_guts.c | 2 +-=0A= hw/ppc/pnv_core.c | 6 +-=0A= hw/ppc/pnv_lpc.c | 8 +-=0A= hw/ppc/pnv_occ.c | 4 +-=0A= hw/ppc/pnv_psi.c | 8 +-=0A= hw/ppc/pnv_xscom.c | 2 +-=0A= hw/ppc/ppc405_boards.c | 4 +-=0A= hw/ppc/ppc405_uc.c | 14 +--=0A= hw/ppc/ppc440_bamboo.c | 4 +-=0A= hw/ppc/ppc440_pcix.c | 4 +-=0A= hw/ppc/ppc4xx_pci.c | 2 +-=0A= hw/ppc/ppce500_spin.c | 2 +-=0A= hw/ppc/sam460ex.c | 4 +-=0A= hw/ppc/spapr_pci.c | 2 +-=0A= hw/ppc/virtex_ml507.c | 2 +-=0A= hw/rdma/vmw/pvrdma_main.c | 4 +-=0A= hw/riscv/sifive_clint.c | 2 +-=0A= hw/riscv/sifive_gpio.c | 2 +-=0A= hw/riscv/sifive_plic.c | 2 +-=0A= hw/riscv/sifive_prci.c | 2 +-=0A= hw/riscv/sifive_test.c | 2 +-=0A= hw/riscv/sifive_uart.c | 2 +-=0A= hw/riscv/virt.c | 2 +-=0A= hw/s390x/s390-pci-bus.c | 2 +-=0A= hw/s390x/s390-pci-inst.c | 11 +-=0A= hw/scsi/Makefile.objs | 2 +-=0A= hw/scsi/esp-pci.c | 2 +-=0A= hw/scsi/esp.c | 2 +-=0A= hw/scsi/lsi53c895a.c | 6 +-=0A= hw/scsi/megasas.c | 6 +-=0A= hw/scsi/mptsas.c | 6 +-=0A= hw/scsi/vmw_pvscsi.c | 2 +-=0A= hw/sd/bcm2835_sdhost.c | 2 +-=0A= hw/sd/milkymist-memcard.c | 2 +-=0A= hw/sd/omap_mmc.c | 2 +-=0A= hw/sd/pl181.c | 2 +-=0A= hw/sd/pxa2xx_mmci.c | 2 +-=0A= hw/sd/sdhci.c | 4 +-=0A= hw/sh4/r2d.c | 2 +-=0A= hw/sh4/sh7750.c | 4 +-=0A= hw/sh4/sh_pci.c | 2 +-=0A= hw/sparc/sun4m_iommu.c | 2 +-=0A= hw/sparc64/niagara.c | 2 +-=0A= hw/sparc64/sun4u.c | 4 +-=0A= hw/sparc64/sun4u_iommu.c | 2 +-=0A= hw/ssi/Makefile.objs | 2 +-=0A= hw/ssi/aspeed_smc.c | 6 +-=0A= hw/ssi/imx_spi.c | 2 +-=0A= hw/ssi/mss-spi.c | 2 +-=0A= hw/ssi/omap_spi.c | 2 +-=0A= hw/ssi/pl022.c | 2 +-=0A= hw/ssi/stm32f2xx_spi.c | 2 +-=0A= hw/ssi/xilinx_spi.c | 2 +-=0A= hw/ssi/xilinx_spips.c | 8 +-=0A= hw/timer/Makefile.objs | 6 +-=0A= hw/timer/a9gtimer.c | 4 +-=0A= hw/timer/allwinner-a10-pit.c | 2 +-=0A= hw/timer/altera_timer.c | 2 +-=0A= hw/timer/arm_mptimer.c | 4 +-=0A= hw/timer/arm_timer.c | 4 +-=0A= hw/timer/armv7m_systick.c | 2 +-=0A= hw/timer/aspeed_rtc.c | 2 +-=0A= hw/timer/aspeed_timer.c | 2 +-=0A= hw/timer/cadence_ttc.c | 2 +-=0A= hw/timer/cmsdk-apb-dualtimer.c | 2 +-=0A= hw/timer/cmsdk-apb-timer.c | 2 +-=0A= hw/timer/digic-timer.c | 2 +-=0A= hw/timer/etraxfs_timer.c | 2 +-=0A= hw/timer/exynos4210_mct.c | 2 +-=0A= hw/timer/exynos4210_pwm.c | 2 +-=0A= hw/timer/exynos4210_rtc.c | 2 +-=0A= hw/timer/grlib_gptimer.c | 2 +-=0A= hw/timer/hpet.c | 2 +-=0A= hw/timer/i8254.c | 2 +-=0A= hw/timer/imx_epit.c | 2 +-=0A= hw/timer/imx_gpt.c | 2 +-=0A= hw/timer/lm32_timer.c | 2 +-=0A= hw/timer/m48t59.c | 4 +-=0A= hw/timer/mc146818rtc.c | 2 +-=0A= hw/timer/milkymist-sysctl.c | 2 +-=0A= hw/timer/mss-timer.c | 2 +-=0A= hw/timer/nrf51_timer.c | 2 +-=0A= hw/timer/omap_gptimer.c | 2 +-=0A= hw/timer/omap_synctimer.c | 2 +-=0A= hw/timer/pl031.c | 2 +-=0A= hw/timer/puv3_ost.c | 2 +-=0A= hw/timer/pxa2xx_timer.c | 2 +-=0A= hw/timer/sh_timer.c | 2 +-=0A= hw/timer/slavio_timer.c | 2 +-=0A= hw/timer/stm32f2xx_timer.c | 2 +-=0A= hw/timer/sun4v-rtc.c | 2 +-=0A= hw/timer/xilinx_timer.c | 2 +-=0A= hw/timer/xlnx-zynqmp-rtc.c | 2 +-=0A= hw/tpm/tpm_crb.c | 2 +-=0A= hw/tpm/tpm_tis.c | 2 +-=0A= hw/usb/chipidea.c | 4 +-=0A= hw/usb/hcd-ehci-sysbus.c | 2 +-=0A= hw/usb/hcd-ehci.c | 6 +-=0A= hw/usb/hcd-ohci.c | 2 +-=0A= hw/usb/hcd-uhci.c | 2 +-=0A= hw/usb/hcd-xhci.c | 10 +-=0A= hw/usb/tusb6010.c | 2 +-=0A= hw/vfio/common.c | 2 +-=0A= hw/vfio/pci-quirks.c | 33 +++---=0A= hw/vfio/pci.c | 4 +-=0A= hw/virtio/Makefile.objs | 2 +-=0A= hw/virtio/virtio-mmio.c | 2 +-=0A= hw/virtio/virtio-pci.c | 27 +++--=0A= hw/watchdog/cmsdk-apb-watchdog.c | 2 +-=0A= hw/watchdog/wdt_aspeed.c | 2 +-=0A= hw/watchdog/wdt_i6300esb.c | 2 +-=0A= hw/xen/xen_pt.c | 2 +-=0A= hw/xen/xen_pt_msi.c | 2 +-=0A= hw/xtensa/mx_pic.c | 2 +-=0A= hw/xtensa/xtfpga.c | 6 +-=0A= include/exec/cpu-all.h | 10 +-=0A= include/exec/cpu-common.h | 12 --=0A= include/exec/memattrs.h | 2 +=0A= include/exec/memop.h | 134 ++++++++++++++++++++++=0A= include/exec/memory.h | 11 +-=0A= include/exec/poison.h | 1 +=0A= include/hw/char/serial.h | 2 +-=0A= include/qom/cpu.h | 2 +-=0A= ioport.c | 4 +-=0A= memory.c | 55 ++++-----=0A= memory_ldst.inc.c | 153 ++++++++-----------------=0A= target/alpha/cpu.h | 2 -=0A= target/alpha/translate.c | 2 +-=0A= target/arm/translate-a64.c | 48 ++++----=0A= target/arm/translate-a64.h | 2 +-=0A= target/arm/translate-sve.c | 2 +-=0A= target/arm/translate.c | 32 +++---=0A= target/arm/translate.h | 2 +-=0A= target/hppa/cpu.h | 1 -=0A= target/hppa/translate.c | 14 +--=0A= target/i386/translate.c | 132 ++++++++++-----------=0A= target/m68k/translate.c | 2 +-=0A= target/microblaze/translate.c | 4 +-=0A= target/mips/cpu.h | 2 -=0A= target/mips/op_helper.c | 5 +-=0A= target/mips/translate.c | 8 +-=0A= target/openrisc/translate.c | 4 +-=0A= target/ppc/translate.c | 12 +-=0A= target/riscv/insn_trans/trans_rva.inc.c | 8 +-=0A= target/riscv/insn_trans/trans_rvi.inc.c | 4 +-=0A= target/s390x/translate.c | 6 +-=0A= target/s390x/translate_vx.inc.c | 10 +-=0A= target/sh4/cpu.h | 2 -=0A= target/sparc/cpu.h | 4 +-=0A= target/sparc/mmu_helper.c | 40 ++++---=0A= target/sparc/translate.c | 14 +--=0A= target/tilegx/translate.c | 10 +-=0A= target/tricore/translate.c | 8 +-=0A= target/xtensa/cpu.h | 2 -=0A= tcg/README | 2 +-=0A= tcg/aarch64/tcg-target.inc.c | 26 ++---=0A= tcg/arm/tcg-target.inc.c | 26 ++---=0A= tcg/i386/tcg-target.inc.c | 24 ++--=0A= tcg/mips/tcg-target.inc.c | 16 +--=0A= tcg/optimize.c | 2 +-=0A= tcg/ppc/tcg-target.inc.c | 12 +-=0A= tcg/riscv/tcg-target.inc.c | 20 ++--=0A= tcg/s390/tcg-target.inc.c | 14 +--=0A= tcg/sparc/tcg-target.inc.c | 6 +-=0A= tcg/tcg-op.c | 38 +++---=0A= tcg/tcg-op.h | 86 +++++++-------=0A= tcg/tcg.c | 4 +-=0A= tcg/tcg.h | 99 +---------------=0A= trace/mem-internal.h | 4 +-=0A= trace/mem.h | 4 +-=0A= 497 files changed, 1436 insertions(+), 1473 deletions(-)=0A= create mode 100644 include/exec/memop.h=0A= =0A= -- =0A= 1.8.3.1=0A=